ia64/xen-unstable

changeset 16928:7aa2149a3b0e

ioemu: Add support for e100 nic save/restore.
Signed-off-by: Yosuke Iwamatsu <y-iwamatsu@ab.jp.nec.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Jan 29 11:45:15 2008 +0000 (2008-01-29)
parents a4bd1371196e
children 128f7bc0a277
files tools/ioemu/hw/e100.c
line diff
     1.1 --- a/tools/ioemu/hw/e100.c	Tue Jan 29 11:19:04 2008 +0000
     1.2 +++ b/tools/ioemu/hw/e100.c	Tue Jan 29 11:45:15 2008 +0000
     1.3 @@ -851,13 +851,154 @@ static void e100_reset(void *opaque)
     1.4  
     1.5  static void e100_save(QEMUFile * f, void *opaque)
     1.6  {
     1.7 -    //TODO
     1.8 -    return;
     1.9 +    E100State *s = (E100State *)opaque;
    1.10 +    int i;
    1.11 +
    1.12 +    pci_device_save(s->pci_dev, f);
    1.13 +
    1.14 +    qemu_put_be32s(f, &s->mmio_index);
    1.15 +    qemu_put_8s(f, &s->scb_stat);
    1.16 +    for(i = 0; i < REGION_NUM; i++) {
    1.17 +        qemu_put_be32s(f, &s->region_base_addr[i]);
    1.18 +    }
    1.19 +    qemu_put_buffer(f, s->macaddr, 6);
    1.20 +    for(i = 0; i < 32; i++) {
    1.21 +        qemu_put_be16s(f, &s->mdimem[i]);
    1.22 +    }
    1.23 +
    1.24 +    /* Save eeprom. */
    1.25 +    qemu_put_8s(f, &s->eeprom.start_bit);
    1.26 +    qemu_put_8s(f, &s->eeprom.opcode);
    1.27 +    qemu_put_8s(f, &s->eeprom.address);
    1.28 +    qemu_put_be16s(f, &s->eeprom.data);
    1.29 +    qemu_put_be32s(f, &s->eeprom.val);
    1.30 +    qemu_put_be32s(f, &s->eeprom.val);
    1.31 +    qemu_put_be32s(f, &s->eeprom.val_len);
    1.32 +    qemu_put_be32s(f, &s->eeprom.val_type);
    1.33 +    qemu_put_8s(f, &s->eeprom.cs);
    1.34 +    qemu_put_8s(f, &s->eeprom.sk);
    1.35 +    qemu_put_be16s(f, &s->eeprom.addr_len);
    1.36 +    for(i = 0; i < 256; i++) {
    1.37 +        qemu_put_be16s(f, &s->eeprom.contents[i]);
    1.38 +    }
    1.39 +
    1.40 +    qemu_put_be32s(f, &s->device);
    1.41 +
    1.42 +    qemu_put_buffer(f, s->mult_list, 8);
    1.43 +    qemu_put_be32s(f, &s->is_multcast_enable);
    1.44 +
    1.45 +    qemu_put_be32s(f, &s->cu_base);
    1.46 +    qemu_put_be32s(f, &s->cu_offset);
    1.47 +    qemu_put_be32s(f, &s->cu_next);
    1.48 +
    1.49 +    qemu_put_be32s(f, &s->ru_base);
    1.50 +    qemu_put_be32s(f, &s->ru_offset);
    1.51 +
    1.52 +    qemu_put_be32s(f, &s->statsaddr);
    1.53 +
    1.54 +    /* Save statistics. */
    1.55 +    qemu_put_be32s(f, &s->statistics.tx_good_frames);
    1.56 +    qemu_put_be32s(f, &s->statistics.tx_max_collisions);
    1.57 +    qemu_put_be32s(f, &s->statistics.tx_late_collisions);
    1.58 +    qemu_put_be32s(f, &s->statistics.tx_underruns);
    1.59 +    qemu_put_be32s(f, &s->statistics.tx_lost_crs);
    1.60 +    qemu_put_be32s(f, &s->statistics.tx_deferred);
    1.61 +    qemu_put_be32s(f, &s->statistics.tx_single_collisions);
    1.62 +    qemu_put_be32s(f, &s->statistics.tx_multiple_collisions);
    1.63 +    qemu_put_be32s(f, &s->statistics.tx_total_collisions);
    1.64 +    qemu_put_be32s(f, &s->statistics.rx_good_frames);
    1.65 +    qemu_put_be32s(f, &s->statistics.rx_crc_errors);
    1.66 +    qemu_put_be32s(f, &s->statistics.rx_alignment_errors);
    1.67 +    qemu_put_be32s(f, &s->statistics.rx_resource_errors);
    1.68 +    qemu_put_be32s(f, &s->statistics.rx_overrun_errors);
    1.69 +    qemu_put_be32s(f, &s->statistics.rx_short_frame_errors);
    1.70 +    qemu_put_be32s(f, &s->statistics.complete_word);
    1.71 +
    1.72 +    qemu_put_buffer(f, (uint8*)(&s->config), sizeof(s->config));
    1.73 +
    1.74 +    qemu_put_buffer(f, s->pkt_buf, MAX_ETH_FRAME_SIZE+4);
    1.75 +    qemu_put_be32s(f, &s->pkt_buf_len);
    1.76 +
    1.77 +    qemu_put_buffer(f, (uint8_t*)(&s->pci_mem), sizeof(s->pci_mem));
    1.78  }
    1.79  
    1.80  static int e100_load(QEMUFile * f, void *opaque, int version_id)
    1.81  {
    1.82 -    //TODO
    1.83 +    E100State *s = (E100State *)opaque;
    1.84 +    int i, ret;
    1.85 +
    1.86 +    if (version_id > 3)
    1.87 +        return -EINVAL;
    1.88 +
    1.89 +    ret = pci_device_load(s->pci_dev, f);
    1.90 +    if (ret < 0)
    1.91 +        return ret;
    1.92 +
    1.93 +    qemu_get_be32s(f, &s->mmio_index);
    1.94 +    qemu_get_8s(f, &s->scb_stat);
    1.95 +    for(i = 0; i < REGION_NUM; i++) {
    1.96 +        qemu_get_be32s(f, &s->region_base_addr[i]);
    1.97 +    }
    1.98 +    qemu_get_buffer(f, s->macaddr, 6);
    1.99 +    for(i = 0; i < 32; i++) {
   1.100 +        qemu_get_be16s(f, &s->mdimem[i]);
   1.101 +    }
   1.102 +
   1.103 +    /* Load eeprom. */
   1.104 +    qemu_get_8s(f, &s->eeprom.start_bit);
   1.105 +    qemu_get_8s(f, &s->eeprom.opcode);
   1.106 +    qemu_get_8s(f, &s->eeprom.address);
   1.107 +    qemu_get_be16s(f, &s->eeprom.data);
   1.108 +    qemu_get_be32s(f, &s->eeprom.val);
   1.109 +    qemu_get_be32s(f, &s->eeprom.val);
   1.110 +    qemu_get_be32s(f, &s->eeprom.val_len);
   1.111 +    qemu_get_be32s(f, &s->eeprom.val_type);
   1.112 +    qemu_get_8s(f, &s->eeprom.cs);
   1.113 +    qemu_get_8s(f, &s->eeprom.sk);
   1.114 +    qemu_get_be16s(f, &s->eeprom.addr_len);
   1.115 +    for(i = 0; i < 256; i++) {
   1.116 +        qemu_get_be16s(f, &s->eeprom.contents[i]);
   1.117 +    }
   1.118 +
   1.119 +    qemu_get_be32s(f, &s->device);
   1.120 +
   1.121 +    qemu_get_buffer(f, s->mult_list, 8);
   1.122 +    qemu_get_be32s(f, &s->is_multcast_enable);
   1.123 +
   1.124 +    qemu_get_be32s(f, &s->cu_base);
   1.125 +    qemu_get_be32s(f, &s->cu_offset);
   1.126 +    qemu_get_be32s(f, &s->cu_next);
   1.127 +
   1.128 +    qemu_get_be32s(f, &s->ru_base);
   1.129 +    qemu_get_be32s(f, &s->ru_offset);
   1.130 +
   1.131 +    qemu_get_be32s(f, &s->statsaddr);
   1.132 +
   1.133 +    /* Load statistics. */
   1.134 +    qemu_get_be32s(f, &s->statistics.tx_good_frames);
   1.135 +    qemu_get_be32s(f, &s->statistics.tx_max_collisions);
   1.136 +    qemu_get_be32s(f, &s->statistics.tx_late_collisions);
   1.137 +    qemu_get_be32s(f, &s->statistics.tx_underruns);
   1.138 +    qemu_get_be32s(f, &s->statistics.tx_lost_crs);
   1.139 +    qemu_get_be32s(f, &s->statistics.tx_deferred);
   1.140 +    qemu_get_be32s(f, &s->statistics.tx_single_collisions);
   1.141 +    qemu_get_be32s(f, &s->statistics.tx_multiple_collisions);
   1.142 +    qemu_get_be32s(f, &s->statistics.tx_total_collisions);
   1.143 +    qemu_get_be32s(f, &s->statistics.rx_good_frames);
   1.144 +    qemu_get_be32s(f, &s->statistics.rx_crc_errors);
   1.145 +    qemu_get_be32s(f, &s->statistics.rx_alignment_errors);
   1.146 +    qemu_get_be32s(f, &s->statistics.rx_resource_errors);
   1.147 +    qemu_get_be32s(f, &s->statistics.rx_overrun_errors);
   1.148 +    qemu_get_be32s(f, &s->statistics.rx_short_frame_errors);
   1.149 +    qemu_get_be32s(f, &s->statistics.complete_word);
   1.150 +
   1.151 +    qemu_put_buffer(f, (uint8*)(&s->config), sizeof(s->config));
   1.152 +
   1.153 +    qemu_get_buffer(f, s->pkt_buf, MAX_ETH_FRAME_SIZE+4);
   1.154 +    qemu_get_be32s(f, &s->pkt_buf_len);
   1.155 +
   1.156 +    qemu_get_buffer(f, (uint8_t*)(&s->pci_mem), sizeof(s->pci_mem));
   1.157 +
   1.158      return 0;
   1.159  }
   1.160