1.1 --- a/xen/arch/x86/cpu/centaur.c	Wed Aug 29 11:34:01 2007 +0100
     1.2 +++ b/xen/arch/x86/cpu/centaur.c	Wed Aug 29 14:40:00 2007 +0100
     1.3 @@ -7,248 +7,6 @@
     1.4  #include <asm/e820.h>
     1.5  #include "cpu.h"
     1.6  
     1.7 -#ifdef CONFIG_X86_OOSTORE
     1.8 -
     1.9 -static u32 __init power2(u32 x)
    1.10 -{
    1.11 -	u32 s=1;
    1.12 -	while(s<=x)
    1.13 -		s<<=1;
    1.14 -	return s>>=1;
    1.15 -}
    1.16 -
    1.17 -
    1.18 -/*
    1.19 - *	Set up an actual MCR
    1.20 - */
    1.21 - 
    1.22 -static void __init centaur_mcr_insert(int reg, u32 base, u32 size, int key)
    1.23 -{
    1.24 -	u32 lo, hi;
    1.25 -	
    1.26 -	hi = base & ~0xFFF;
    1.27 -	lo = ~(size-1);		/* Size is a power of 2 so this makes a mask */
    1.28 -	lo &= ~0xFFF;		/* Remove the ctrl value bits */
    1.29 -	lo |= key;		/* Attribute we wish to set */
    1.30 -	wrmsr(reg+MSR_IDT_MCR0, lo, hi);
    1.31 -	mtrr_centaur_report_mcr(reg, lo, hi);	/* Tell the mtrr driver */
    1.32 -}
    1.33 -
    1.34 -/*
    1.35 - *	Figure what we can cover with MCR's
    1.36 - *
    1.37 - *	Shortcut: We know you can't put 4Gig of RAM on a winchip
    1.38 - */
    1.39 -
    1.40 -static u32 __init ramtop(void)		/* 16388 */
    1.41 -{
    1.42 -	int i;
    1.43 -	u32 top = 0;
    1.44 -	u32 clip = 0xFFFFFFFFUL;
    1.45 -	
    1.46 -	for (i = 0; i < e820.nr_map; i++) {
    1.47 -		unsigned long start, end;
    1.48 -
    1.49 -		if (e820.map[i].addr > 0xFFFFFFFFUL)
    1.50 -			continue;
    1.51 -		/*
    1.52 -		 *	Don't MCR over reserved space. Ignore the ISA hole
    1.53 -		 *	we frob around that catastrophy already
    1.54 -		 */
    1.55 -		 			
    1.56 -		if (e820.map[i].type == E820_RESERVED)
    1.57 -		{
    1.58 -			if(e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip)
    1.59 -				clip = e820.map[i].addr;
    1.60 -			continue;
    1.61 -		}
    1.62 -		start = e820.map[i].addr;
    1.63 -		end = e820.map[i].addr + e820.map[i].size;
    1.64 -		if (start >= end)
    1.65 -			continue;
    1.66 -		if (end > top)
    1.67 -			top = end;
    1.68 -	}
    1.69 -	/* Everything below 'top' should be RAM except for the ISA hole.
    1.70 -	   Because of the limited MCR's we want to map NV/ACPI into our
    1.71 -	   MCR range for gunk in RAM 
    1.72 -	   
    1.73 -	   Clip might cause us to MCR insufficient RAM but that is an
    1.74 -	   acceptable failure mode and should only bite obscure boxes with
    1.75 -	   a VESA hole at 15Mb
    1.76 -	   
    1.77 -	   The second case Clip sometimes kicks in is when the EBDA is marked
    1.78 -	   as reserved. Again we fail safe with reasonable results
    1.79 -	*/
    1.80 -	
    1.81 -	if(top>clip)
    1.82 -		top=clip;
    1.83 -		
    1.84 -	return top;
    1.85 -}
    1.86 -
    1.87 -/*
    1.88 - *	Compute a set of MCR's to give maximum coverage
    1.89 - */
    1.90 -
    1.91 -static int __init centaur_mcr_compute(int nr, int key)
    1.92 -{
    1.93 -	u32 mem = ramtop();
    1.94 -	u32 root = power2(mem);
    1.95 -	u32 base = root;
    1.96 -	u32 top = root;
    1.97 -	u32 floor = 0;
    1.98 -	int ct = 0;
    1.99 -	
   1.100 -	while(ct<nr)
   1.101 -	{
   1.102 -		u32 fspace = 0;
   1.103 -
   1.104 -		/*
   1.105 -		 *	Find the largest block we will fill going upwards
   1.106 -		 */
   1.107 -
   1.108 -		u32 high = power2(mem-top);	
   1.109 -
   1.110 -		/*
   1.111 -		 *	Find the largest block we will fill going downwards
   1.112 -		 */
   1.113 -
   1.114 -		u32 low = base/2;
   1.115 -
   1.116 -		/*
   1.117 -		 *	Don't fill below 1Mb going downwards as there
   1.118 -		 *	is an ISA hole in the way.
   1.119 -		 */		
   1.120 -		 
   1.121 -		if(base <= 1024*1024)
   1.122 -			low = 0;
   1.123 -			
   1.124 -		/*
   1.125 -		 *	See how much space we could cover by filling below
   1.126 -		 *	the ISA hole
   1.127 -		 */
   1.128 -		 
   1.129 -		if(floor == 0)
   1.130 -			fspace = 512*1024;
   1.131 -		else if(floor ==512*1024)
   1.132 -			fspace = 128*1024;
   1.133 -
   1.134 -		/* And forget ROM space */
   1.135 -		
   1.136 -		/*
   1.137 -		 *	Now install the largest coverage we get
   1.138 -		 */
   1.139 -		 
   1.140 -		if(fspace > high && fspace > low)
   1.141 -		{
   1.142 -			centaur_mcr_insert(ct, floor, fspace, key);
   1.143 -			floor += fspace;
   1.144 -		}
   1.145 -		else if(high > low)
   1.146 -		{
   1.147 -			centaur_mcr_insert(ct, top, high, key);
   1.148 -			top += high;
   1.149 -		}
   1.150 -		else if(low > 0)
   1.151 -		{
   1.152 -			base -= low;
   1.153 -			centaur_mcr_insert(ct, base, low, key);
   1.154 -		}
   1.155 -		else break;
   1.156 -		ct++;
   1.157 -	}
   1.158 -	/*
   1.159 -	 *	We loaded ct values. We now need to set the mask. The caller
   1.160 -	 *	must do this bit.
   1.161 -	 */
   1.162 -	 
   1.163 -	return ct;
   1.164 -}
   1.165 -
   1.166 -static void __init centaur_create_optimal_mcr(void)
   1.167 -{
   1.168 -	int i;
   1.169 -	/*
   1.170 -	 *	Allocate up to 6 mcrs to mark as much of ram as possible
   1.171 -	 *	as write combining and weak write ordered.
   1.172 -	 *
   1.173 -	 *	To experiment with: Linux never uses stack operations for 
   1.174 -	 *	mmio spaces so we could globally enable stack operation wc
   1.175 -	 *
   1.176 -	 *	Load the registers with type 31 - full write combining, all
   1.177 -	 *	writes weakly ordered.
   1.178 -	 */
   1.179 -	int used = centaur_mcr_compute(6, 31);
   1.180 -
   1.181 -	/*
   1.182 -	 *	Wipe unused MCRs
   1.183 -	 */
   1.184 -	 
   1.185 -	for(i=used;i<8;i++)
   1.186 -		wrmsr(MSR_IDT_MCR0+i, 0, 0);
   1.187 -}
   1.188 -
   1.189 -static void __init winchip2_create_optimal_mcr(void)
   1.190 -{
   1.191 -	u32 lo, hi;
   1.192 -	int i;
   1.193 -
   1.194 -	/*
   1.195 -	 *	Allocate up to 6 mcrs to mark as much of ram as possible
   1.196 -	 *	as write combining, weak store ordered.
   1.197 -	 *
   1.198 -	 *	Load the registers with type 25
   1.199 -	 *		8	-	weak write ordering
   1.200 -	 *		16	-	weak read ordering
   1.201 -	 *		1	-	write combining
   1.202 -	 */
   1.203 -
   1.204 -	int used = centaur_mcr_compute(6, 25);
   1.205 -	
   1.206 -	/*
   1.207 -	 *	Mark the registers we are using.
   1.208 -	 */
   1.209 -	 
   1.210 -	rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.211 -	for(i=0;i<used;i++)
   1.212 -		lo|=1<<(9+i);
   1.213 -	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.214 -	
   1.215 -	/*
   1.216 -	 *	Wipe unused MCRs
   1.217 -	 */
   1.218 -	 
   1.219 -	for(i=used;i<8;i++)
   1.220 -		wrmsr(MSR_IDT_MCR0+i, 0, 0);
   1.221 -}
   1.222 -
   1.223 -/*
   1.224 - *	Handle the MCR key on the Winchip 2.
   1.225 - */
   1.226 -
   1.227 -static void __init winchip2_unprotect_mcr(void)
   1.228 -{
   1.229 -	u32 lo, hi;
   1.230 -	u32 key;
   1.231 -	
   1.232 -	rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.233 -	lo&=~0x1C0;	/* blank bits 8-6 */
   1.234 -	key = (lo>>17) & 7;
   1.235 -	lo |= key<<6;	/* replace with unlock key */
   1.236 -	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.237 -}
   1.238 -
   1.239 -static void __init winchip2_protect_mcr(void)
   1.240 -{
   1.241 -	u32 lo, hi;
   1.242 -	
   1.243 -	rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.244 -	lo&=~0x1C0;	/* blank bits 8-6 */
   1.245 -	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.246 -}
   1.247 -#endif /* CONFIG_X86_OOSTORE */
   1.248 -
   1.249  #define ACE_PRESENT	(1 << 6)
   1.250  #define ACE_ENABLED	(1 << 7)
   1.251  #define ACE_FCR		(1 << 28)	/* MSR_VIA_FCR */
   1.252 @@ -305,146 +63,12 @@ static void __init init_c3(struct cpuinf
   1.253  
   1.254  static void __init init_centaur(struct cpuinfo_x86 *c)
   1.255  {
   1.256 -	enum {
   1.257 -		ECX8=1<<1,
   1.258 -		EIERRINT=1<<2,
   1.259 -		DPM=1<<3,
   1.260 -		DMCE=1<<4,
   1.261 -		DSTPCLK=1<<5,
   1.262 -		ELINEAR=1<<6,
   1.263 -		DSMC=1<<7,
   1.264 -		DTLOCK=1<<8,
   1.265 -		EDCTLB=1<<8,
   1.266 -		EMMX=1<<9,
   1.267 -		DPDC=1<<11,
   1.268 -		EBRPRED=1<<12,
   1.269 -		DIC=1<<13,
   1.270 -		DDC=1<<14,
   1.271 -		DNA=1<<15,
   1.272 -		ERETSTK=1<<16,
   1.273 -		E2MMX=1<<19,
   1.274 -		EAMD3D=1<<20,
   1.275 -	};
   1.276 -
   1.277 -	char *name;
   1.278 -	u32  fcr_set=0;
   1.279 -	u32  fcr_clr=0;
   1.280 -	u32  lo,hi,newlo;
   1.281 -	u32  aa,bb,cc,dd;
   1.282 -
   1.283  	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
   1.284  	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
   1.285  	clear_bit(0*32+31, c->x86_capability);
   1.286  
   1.287 -	switch (c->x86) {
   1.288 -
   1.289 -		case 5:
   1.290 -			switch(c->x86_model) {
   1.291 -			case 4:
   1.292 -				name="C6";
   1.293 -				fcr_set=ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
   1.294 -				fcr_clr=DPDC;
   1.295 -				printk(KERN_NOTICE "Disabling bugged TSC.\n");
   1.296 -				clear_bit(X86_FEATURE_TSC, c->x86_capability);
   1.297 -#ifdef CONFIG_X86_OOSTORE
   1.298 -				centaur_create_optimal_mcr();
   1.299 -				/* Enable
   1.300 -					write combining on non-stack, non-string
   1.301 -					write combining on string, all types
   1.302 -					weak write ordering 
   1.303 -					
   1.304 -				   The C6 original lacks weak read order 
   1.305 -				   
   1.306 -				   Note 0x120 is write only on Winchip 1 */
   1.307 -				   
   1.308 -				wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
   1.309 -#endif				
   1.310 -				break;
   1.311 -			case 8:
   1.312 -				switch(c->x86_mask) {
   1.313 -				default:
   1.314 -					name="2";
   1.315 -					break;
   1.316 -				case 7 ... 9:
   1.317 -					name="2A";
   1.318 -					break;
   1.319 -				case 10 ... 15:
   1.320 -					name="2B";
   1.321 -					break;
   1.322 -				}
   1.323 -				fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
   1.324 -				fcr_clr=DPDC;
   1.325 -#ifdef CONFIG_X86_OOSTORE
   1.326 -				winchip2_unprotect_mcr();
   1.327 -				winchip2_create_optimal_mcr();
   1.328 -				rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.329 -				/* Enable
   1.330 -					write combining on non-stack, non-string
   1.331 -					write combining on string, all types
   1.332 -					weak write ordering 
   1.333 -				*/
   1.334 -				lo|=31;				
   1.335 -				wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.336 -				winchip2_protect_mcr();
   1.337 -#endif
   1.338 -				break;
   1.339 -			case 9:
   1.340 -				name="3";
   1.341 -				fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
   1.342 -				fcr_clr=DPDC;
   1.343 -#ifdef CONFIG_X86_OOSTORE
   1.344 -				winchip2_unprotect_mcr();
   1.345 -				winchip2_create_optimal_mcr();
   1.346 -				rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.347 -				/* Enable
   1.348 -					write combining on non-stack, non-string
   1.349 -					write combining on string, all types
   1.350 -					weak write ordering 
   1.351 -				*/
   1.352 -				lo|=31;				
   1.353 -				wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
   1.354 -				winchip2_protect_mcr();
   1.355 -#endif
   1.356 -				break;
   1.357 -			case 10:
   1.358 -				name="4";
   1.359 -				/* no info on the WC4 yet */
   1.360 -				break;
   1.361 -			default:
   1.362 -				name="??";
   1.363 -			}
   1.364 -
   1.365 -			rdmsr(MSR_IDT_FCR1, lo, hi);
   1.366 -			newlo=(lo|fcr_set) & (~fcr_clr);
   1.367 -
   1.368 -			if (newlo!=lo) {
   1.369 -				printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo );
   1.370 -				wrmsr(MSR_IDT_FCR1, newlo, hi );
   1.371 -			} else {
   1.372 -				printk(KERN_INFO "Centaur FCR is 0x%X\n",lo);
   1.373 -			}
   1.374 -			/* Emulate MTRRs using Centaur's MCR. */
   1.375 -			set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability);
   1.376 -			/* Report CX8 */
   1.377 -			set_bit(X86_FEATURE_CX8, c->x86_capability);
   1.378 -			/* Set 3DNow! on Winchip 2 and above. */
   1.379 -			if (c->x86_model >=8)
   1.380 -				set_bit(X86_FEATURE_3DNOW, c->x86_capability);
   1.381 -			/* See if we can find out some more. */
   1.382 -			if ( cpuid_eax(0x80000000) >= 0x80000005 ) {
   1.383 -				/* Yes, we can. */
   1.384 -				cpuid(0x80000005,&aa,&bb,&cc,&dd);
   1.385 -				/* Add L1 data and code cache sizes. */
   1.386 -				c->x86_cache_size = (cc>>24)+(dd>>24);
   1.387 -			}
   1.388 -			snprintf( c->x86_model_id, sizeof(c->x86_model_id),
   1.389 -				"WinChip %s", name );
   1.390 -			break;
   1.391 -
   1.392 -		case 6:
   1.393 -			init_c3(c);
   1.394 -			break;
   1.395 -	}
   1.396 +	if (c->x86 == 6)
   1.397 +		init_c3(c);
   1.398  }
   1.399  
   1.400  static unsigned int centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size)

     2.1 --- a/xen/arch/x86/cpu/mtrr/Makefile	Wed Aug 29 11:34:01 2007 +0100
     2.2 +++ b/xen/arch/x86/cpu/mtrr/Makefile	Wed Aug 29 14:40:00 2007 +0100
     2.3 @@ -1,5 +1,4 @@
     2.4  obj-$(x86_32) += amd.o
     2.5 -obj-$(x86_32) += centaur.o
     2.6  obj-$(x86_32) += cyrix.o
     2.7  obj-y += generic.o
     2.8  obj-y += main.o

     3.1 --- a/xen/arch/x86/cpu/mtrr/centaur.c	Wed Aug 29 11:34:01 2007 +0100
     3.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.3 @@ -1,223 +0,0 @@
     3.4 -#include <xen/init.h>
     3.5 -#include <xen/mm.h>
     3.6 -#include <asm/mtrr.h>
     3.7 -#include <asm/msr.h>
     3.8 -#include "mtrr.h"
     3.9 -
    3.10 -static struct {
    3.11 -	unsigned long high;
    3.12 -	unsigned long low;
    3.13 -} centaur_mcr[8];
    3.14 -
    3.15 -static u8 centaur_mcr_reserved;
    3.16 -static u8 centaur_mcr_type;	/* 0 for winchip, 1 for winchip2 */
    3.17 -
    3.18 -/*
    3.19 - *	Report boot time MCR setups 
    3.20 - */
    3.21 -
    3.22 -static int
    3.23 -centaur_get_free_region(unsigned long base, unsigned long size)
    3.24 -/*  [SUMMARY] Get a free MTRR.
    3.25 -    <base> The starting (base) address of the region.
    3.26 -    <size> The size (in bytes) of the region.
    3.27 -    [RETURNS] The index of the region on success, else -1 on error.
    3.28 -*/
    3.29 -{
    3.30 -	int i, max;
    3.31 -	mtrr_type ltype;
    3.32 -	unsigned long lbase;
    3.33 -	unsigned int lsize;
    3.34 -
    3.35 -	max = num_var_ranges;
    3.36 -	for (i = 0; i < max; ++i) {
    3.37 -		if (centaur_mcr_reserved & (1 << i))
    3.38 -			continue;
    3.39 -		mtrr_if->get(i, &lbase, &lsize, &ltype);
    3.40 -		if (lsize == 0)
    3.41 -			return i;
    3.42 -	}
    3.43 -	return -ENOSPC;
    3.44 -}
    3.45 -
    3.46 -void
    3.47 -mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
    3.48 -{
    3.49 -	centaur_mcr[mcr].low = lo;
    3.50 -	centaur_mcr[mcr].high = hi;
    3.51 -}
    3.52 -
    3.53 -static void
    3.54 -centaur_get_mcr(unsigned int reg, unsigned long *base,
    3.55 -		unsigned int *size, mtrr_type * type)
    3.56 -{
    3.57 -	*base = centaur_mcr[reg].high >> PAGE_SHIFT;
    3.58 -	*size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT;
    3.59 -	*type = MTRR_TYPE_WRCOMB;	/*  If it is there, it is write-combining  */
    3.60 -	if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2))
    3.61 -		*type = MTRR_TYPE_UNCACHABLE;
    3.62 -	if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25)
    3.63 -		*type = MTRR_TYPE_WRBACK;
    3.64 -	if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31)
    3.65 -		*type = MTRR_TYPE_WRBACK;
    3.66 -
    3.67 -}
    3.68 -
    3.69 -static void centaur_set_mcr(unsigned int reg, unsigned long base,
    3.70 -			    unsigned long size, mtrr_type type)
    3.71 -{
    3.72 -	unsigned long low, high;
    3.73 -
    3.74 -	if (size == 0) {
    3.75 -		/*  Disable  */
    3.76 -		high = low = 0;
    3.77 -	} else {
    3.78 -		high = base << PAGE_SHIFT;
    3.79 -		if (centaur_mcr_type == 0)
    3.80 -			low = -size << PAGE_SHIFT | 0x1f;	/* only support write-combining... */
    3.81 -		else {
    3.82 -			if (type == MTRR_TYPE_UNCACHABLE)
    3.83 -				low = -size << PAGE_SHIFT | 0x02;	/* NC */
    3.84 -			else
    3.85 -				low = -size << PAGE_SHIFT | 0x09;	/* WWO,WC */
    3.86 -		}
    3.87 -	}
    3.88 -	centaur_mcr[reg].high = high;
    3.89 -	centaur_mcr[reg].low = low;
    3.90 -	wrmsr(MSR_IDT_MCR0 + reg, low, high);
    3.91 -}
    3.92 -
    3.93 -#if 0
    3.94 -/*
    3.95 - *	Initialise the later (saner) Winchip MCR variant. In this version
    3.96 - *	the BIOS can pass us the registers it has used (but not their values)
    3.97 - *	and the control register is read/write
    3.98 - */
    3.99 -
   3.100 -static void __init
   3.101 -centaur_mcr1_init(void)
   3.102 -{
   3.103 -	unsigned i;
   3.104 -	u32 lo, hi;
   3.105 -
   3.106 -	/* Unfortunately, MCR's are read-only, so there is no way to
   3.107 -	 * find out what the bios might have done.
   3.108 -	 */
   3.109 -
   3.110 -	rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
   3.111 -	if (((lo >> 17) & 7) == 1) {	/* Type 1 Winchip2 MCR */
   3.112 -		lo &= ~0x1C0;	/* clear key */
   3.113 -		lo |= 0x040;	/* set key to 1 */
   3.114 -		wrmsr(MSR_IDT_MCR_CTRL, lo, hi);	/* unlock MCR */
   3.115 -	}
   3.116 -
   3.117 -	centaur_mcr_type = 1;
   3.118 -
   3.119 -	/*
   3.120 -	 *  Clear any unconfigured MCR's.
   3.121 -	 */
   3.122 -
   3.123 -	for (i = 0; i < 8; ++i) {
   3.124 -		if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0) {
   3.125 -			if (!(lo & (1 << (9 + i))))
   3.126 -				wrmsr(MSR_IDT_MCR0 + i, 0, 0);
   3.127 -			else
   3.128 -				/*
   3.129 -				 *      If the BIOS set up an MCR we cannot see it
   3.130 -				 *      but we don't wish to obliterate it
   3.131 -				 */
   3.132 -				centaur_mcr_reserved |= (1 << i);
   3.133 -		}
   3.134 -	}
   3.135 -	/*  
   3.136 -	 *  Throw the main write-combining switch... 
   3.137 -	 *  However if OOSTORE is enabled then people have already done far
   3.138 -	 *  cleverer things and we should behave. 
   3.139 -	 */
   3.140 -
   3.141 -	lo |= 15;		/* Write combine enables */
   3.142 -	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
   3.143 -}
   3.144 -
   3.145 -/*
   3.146 - *	Initialise the original winchip with read only MCR registers
   3.147 - *	no used bitmask for the BIOS to pass on and write only control
   3.148 - */
   3.149 -
   3.150 -static void __init
   3.151 -centaur_mcr0_init(void)
   3.152 -{
   3.153 -	unsigned i;
   3.154 -
   3.155 -	/* Unfortunately, MCR's are read-only, so there is no way to
   3.156 -	 * find out what the bios might have done.
   3.157 -	 */
   3.158 -
   3.159 -	/* Clear any unconfigured MCR's.
   3.160 -	 * This way we are sure that the centaur_mcr array contains the actual
   3.161 -	 * values. The disadvantage is that any BIOS tweaks are thus undone.
   3.162 -	 *
   3.163 -	 */
   3.164 -	for (i = 0; i < 8; ++i) {
   3.165 -		if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0)
   3.166 -			wrmsr(MSR_IDT_MCR0 + i, 0, 0);
   3.167 -	}
   3.168 -
   3.169 -	wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);	/* Write only */
   3.170 -}
   3.171 -
   3.172 -/*
   3.173 - *	Initialise Winchip series MCR registers
   3.174 - */
   3.175 -
   3.176 -static void __init
   3.177 -centaur_mcr_init(void)
   3.178 -{
   3.179 -	struct set_mtrr_context ctxt;
   3.180 -
   3.181 -	set_mtrr_prepare_save(&ctxt);
   3.182 -	set_mtrr_cache_disable(&ctxt);
   3.183 -
   3.184 -	if (boot_cpu_data.x86_model == 4)
   3.185 -		centaur_mcr0_init();
   3.186 -	else if (boot_cpu_data.x86_model == 8 || boot_cpu_data.x86_model == 9)
   3.187 -		centaur_mcr1_init();
   3.188 -
   3.189 -	set_mtrr_done(&ctxt);
   3.190 -}
   3.191 -#endif
   3.192 -
   3.193 -static int centaur_validate_add_page(unsigned long base, 
   3.194 -				     unsigned long size, unsigned int type)
   3.195 -{
   3.196 -	/*
   3.197 -	 *  FIXME: Winchip2 supports uncached
   3.198 -	 */
   3.199 -	if (type != MTRR_TYPE_WRCOMB && 
   3.200 -	    (centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) {
   3.201 -		printk(KERN_WARNING
   3.202 -		       "mtrr: only write-combining%s supported\n",
   3.203 -		       centaur_mcr_type ? " and uncacheable are"
   3.204 -		       : " is");
   3.205 -		return -EINVAL;
   3.206 -	}
   3.207 -	return 0;
   3.208 -}
   3.209 -
   3.210 -static struct mtrr_ops centaur_mtrr_ops = {
   3.211 -	.vendor            = X86_VENDOR_CENTAUR,
   3.212 -//	.init              = centaur_mcr_init,
   3.213 -	.set               = centaur_set_mcr,
   3.214 -	.get               = centaur_get_mcr,
   3.215 -	.get_free_region   = centaur_get_free_region,
   3.216 -	.validate_add_page = centaur_validate_add_page,
   3.217 -	.have_wrcomb       = positive_have_wrcomb,
   3.218 -};
   3.219 -
   3.220 -int __init centaur_init_mtrr(void)
   3.221 -{
   3.222 -	set_mtrr_ops(&centaur_mtrr_ops);
   3.223 -	return 0;
   3.224 -}
   3.225 -
   3.226 -//arch_initcall(centaur_init_mtrr);

     4.1 --- a/xen/arch/x86/cpu/mtrr/main.c	Wed Aug 29 11:34:01 2007 +0100
     4.2 +++ b/xen/arch/x86/cpu/mtrr/main.c	Wed Aug 29 14:40:00 2007 +0100
     4.3 @@ -539,14 +539,12 @@ EXPORT_SYMBOL(mtrr_del);
     4.4   */
     4.5  extern void amd_init_mtrr(void);
     4.6  extern void cyrix_init_mtrr(void);
     4.7 -extern void centaur_init_mtrr(void);
     4.8  
     4.9  static void __init init_ifs(void)
    4.10  {
    4.11  #ifndef CONFIG_X86_64
    4.12  	amd_init_mtrr();
    4.13  	cyrix_init_mtrr();
    4.14 -	centaur_init_mtrr();
    4.15  #endif
    4.16  }
    4.17  
    4.18 @@ -609,13 +607,6 @@ void __init mtrr_bp_init(void)
    4.19  				size_and_mask = 0;
    4.20  			}
    4.21  			break;
    4.22 -		case X86_VENDOR_CENTAUR:
    4.23 -			if (cpu_has_centaur_mcr) {
    4.24 -				mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
    4.25 -				size_or_mask = 0xfff00000;	/* 32 bits */
    4.26 -				size_and_mask = 0;
    4.27 -			}
    4.28 -			break;
    4.29  		case X86_VENDOR_CYRIX:
    4.30  			if (cpu_has_cyrix_arr) {
    4.31  				mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];

     5.1 --- a/xen/include/asm-x86/spinlock.h	Wed Aug 29 11:34:01 2007 +0100
     5.2 +++ b/xen/include/asm-x86/spinlock.h	Wed Aug 29 14:40:00 2007 +0100
     5.3 @@ -33,18 +33,10 @@ static inline void _raw_spin_lock(spinlo
     5.4  
     5.5  static inline void _raw_spin_unlock(spinlock_t *lock)
     5.6  {
     5.7 -#if !defined(CONFIG_X86_OOSTORE)
     5.8      ASSERT(spin_is_locked(lock));
     5.9      __asm__ __volatile__ (
    5.10  	"movb $1,%0" 
    5.11          : "=m" (lock->lock) : : "memory" );
    5.12 -#else
    5.13 -    char oldval = 1;
    5.14 -    ASSERT(spin_is_locked(lock));
    5.15 -    __asm__ __volatile__ (
    5.16 -	"xchgb %b0, %1"
    5.17 -        : "=q" (oldval), "=m" (lock->lock) : "0" (oldval) : "memory" );
    5.18 -#endif
    5.19  }
    5.20  
    5.21  static inline int _raw_spin_trylock(spinlock_t *lock)

     6.1 --- a/xen/include/asm-x86/system.h	Wed Aug 29 11:34:01 2007 +0100
     6.2 +++ b/xen/include/asm-x86/system.h	Wed Aug 29 14:40:00 2007 +0100
     6.3 @@ -253,40 +253,14 @@ static always_inline unsigned long long 
     6.4  })
     6.5  #endif
     6.6  
     6.7 -/*
     6.8 - * Force strict CPU ordering.
     6.9 - * And yes, this is required on UP too when we're talking
    6.10 - * to devices.
    6.11 - *
    6.12 - * For now, "wmb()" doesn't actually do anything, as all
    6.13 - * Intel CPU's follow what Intel calls a *Processor Order*,
    6.14 - * in which all writes are seen in the program order even
    6.15 - * outside the CPU.
    6.16 - *
    6.17 - * I expect future Intel CPU's to have a weaker ordering,
    6.18 - * but I'd also expect them to finally get their act together
    6.19 - * and add some real memory barriers if so.
    6.20 - *
    6.21 - * Some non intel clones support out of order store. wmb() ceases to be a
    6.22 - * nop for these.
    6.23 - */
    6.24  #if defined(__i386__)
    6.25  #define mb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
    6.26  #define rmb()	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
    6.27 -#ifdef CONFIG_X86_OOSTORE
    6.28 -#define wmb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
    6.29 -#endif
    6.30  #elif defined(__x86_64__)
    6.31  #define mb()    __asm__ __volatile__ ("mfence":::"memory")
    6.32  #define rmb()   __asm__ __volatile__ ("lfence":::"memory")
    6.33 -#ifdef CONFIG_X86_OOSTORE
    6.34 -#define wmb()   __asm__ __volatile__ ("sfence":::"memory")
    6.35 -#endif
    6.36  #endif
    6.37 -
    6.38 -#ifndef CONFIG_X86_OOSTORE
    6.39  #define wmb()	__asm__ __volatile__ ("": : :"memory")
    6.40 -#endif
    6.41  
    6.42  #ifdef CONFIG_SMP
    6.43  #define smp_mb()	mb()