ia64/xen-unstable

changeset 4231:763faed40f9d

bitkeeper revision 1.1159.272.3 (423e7e90uxPqdRoA4EvOUikif-yhXA)

Check-in of the sparse tree for FreeBSD 5.3 (version 050317)
This currently supports running as a domU.

- to create freebsd-5.3-xenU run fbsdxensetup from anywhere in the tree
- once created go to freebsd-5.3-xenU on a FreeBSD 5.3 machine, run
xenfbsd_kernel_build - you'll find kernel and kernel.debug under
i386-xen/compile/XENCONF

See http://www.fsmware.com/xenofreebsd/5.3/xenbsdsetup.txt

Thanks to NetApp for their contributions in support of the FreeBSD port to Xen
.

Signed-off-by: Kip Macy <kip.macy@gmail.com
Signed-off-by: ian.pratt@cl.cam.ac.uk
author iap10@freefall.cl.cam.ac.uk
date Mon Mar 21 07:58:08 2005 +0000 (2005-03-21)
parents dbdf796cd98c
children 6023391d0e40
files .rootkeys freebsd-5.3-xen-sparse/conf/Makefile.i386-xen freebsd-5.3-xen-sparse/conf/files.i386-xen freebsd-5.3-xen-sparse/conf/ldscript.i386-xen freebsd-5.3-xen-sparse/conf/options.i386-xen freebsd-5.3-xen-sparse/fbsdxensetup freebsd-5.3-xen-sparse/i386-xen/Makefile freebsd-5.3-xen-sparse/i386-xen/compile/.cvsignore freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC.hints freebsd-5.3-xen-sparse/i386-xen/conf/Makefile freebsd-5.3-xen-sparse/i386-xen/conf/NOTES freebsd-5.3-xen-sparse/i386-xen/conf/OLDCARD freebsd-5.3-xen-sparse/i386-xen/conf/PAE freebsd-5.3-xen-sparse/i386-xen/conf/XENCONF freebsd-5.3-xen-sparse/i386-xen/conf/gethints.awk freebsd-5.3-xen-sparse/i386-xen/i386-xen/clock.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/critical.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/ctrl_if.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/db_interface.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/evtchn.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/exception.s freebsd-5.3-xen-sparse/i386-xen/i386-xen/genassym.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/hypervisor.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/i686_mem.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/initcpu.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/intr_machdep.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/io_apic.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/local_apic.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/locore.s freebsd-5.3-xen-sparse/i386-xen/i386-xen/machdep.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_clock.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_machdep.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/mptable.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/pmap.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/support.s freebsd-5.3-xen-sparse/i386-xen/i386-xen/swtch.s freebsd-5.3-xen-sparse/i386-xen/i386-xen/symbols.raw freebsd-5.3-xen-sparse/i386-xen/i386-xen/sys_machdep.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/trap.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/vm_machdep.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_bus.c freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_machdep.c freebsd-5.3-xen-sparse/i386-xen/include/cpufunc.h freebsd-5.3-xen-sparse/i386-xen/include/ctrl_if.h freebsd-5.3-xen-sparse/i386-xen/include/evtchn.h freebsd-5.3-xen-sparse/i386-xen/include/frame.h freebsd-5.3-xen-sparse/i386-xen/include/hypervisor-ifs.h freebsd-5.3-xen-sparse/i386-xen/include/hypervisor.h freebsd-5.3-xen-sparse/i386-xen/include/md_var.h freebsd-5.3-xen-sparse/i386-xen/include/multicall.h freebsd-5.3-xen-sparse/i386-xen/include/param.h freebsd-5.3-xen-sparse/i386-xen/include/pcb.h freebsd-5.3-xen-sparse/i386-xen/include/pcpu.h freebsd-5.3-xen-sparse/i386-xen/include/pmap.h freebsd-5.3-xen-sparse/i386-xen/include/segments.h freebsd-5.3-xen-sparse/i386-xen/include/synch_bitops.h freebsd-5.3-xen-sparse/i386-xen/include/trap.h freebsd-5.3-xen-sparse/i386-xen/include/ucontext.h freebsd-5.3-xen-sparse/i386-xen/include/vmparam.h freebsd-5.3-xen-sparse/i386-xen/include/xen-os.h freebsd-5.3-xen-sparse/i386-xen/include/xen_intr.h freebsd-5.3-xen-sparse/i386-xen/include/xenfunc.h freebsd-5.3-xen-sparse/i386-xen/include/xenpmap.h freebsd-5.3-xen-sparse/i386-xen/include/xenvar.h freebsd-5.3-xen-sparse/i386-xen/xen/blkfront/xb_blkfront.c freebsd-5.3-xen-sparse/i386-xen/xen/char/console.c freebsd-5.3-xen-sparse/i386-xen/xen/misc/evtchn_dev.c freebsd-5.3-xen-sparse/i386-xen/xen/misc/npx.c freebsd-5.3-xen-sparse/i386-xen/xen/netfront/xn_netfront.c freebsd-5.3-xen-sparse/kern/kern_fork.c freebsd-5.3-xen-sparse/mkbuildtree freebsd-5.3-xen-sparse/xenfbsd_kernel_build
line diff
     1.1 --- a/.rootkeys	Sun Mar 20 19:31:08 2005 +0000
     1.2 +++ b/.rootkeys	Mon Mar 21 07:58:08 2005 +0000
     1.3 @@ -43,6 +43,78 @@ 3f815145AYE58Kpmsj5U7oHDpVDZJA extras/mi
     1.4  3f815145CB8XdPUqsmhAjSDFuwOoqA extras/mini-os/mm.c
     1.5  3f815145vGYx1WY79voKkZB9yKwJKQ extras/mini-os/time.c
     1.6  3f815145xlKBAQmal9oces3G_Mvxqw extras/mini-os/traps.c
     1.7 +423e7e86yUUeeOvTAmjIahrpk1ksaQ freebsd-5.3-xen-sparse/conf/Makefile.i386-xen
     1.8 +423e7e86CSWbA9G8OftmMbfhStuQ6Q freebsd-5.3-xen-sparse/conf/files.i386-xen
     1.9 +423e7e86m-vV5fQ_32CjcFMEr77Fyg freebsd-5.3-xen-sparse/conf/ldscript.i386-xen
    1.10 +423e7e86Fo2PxRS_37IwkpH-x5t5xQ freebsd-5.3-xen-sparse/conf/options.i386-xen
    1.11 +423e7e868Yt0iZuEeccnczyToPPvow freebsd-5.3-xen-sparse/fbsdxensetup
    1.12 +423e7e87szZMt1H0xhO5vzyXR6d7iQ freebsd-5.3-xen-sparse/i386-xen/Makefile
    1.13 +423e7e8785O6DIEVghIvXD6tcNKonQ freebsd-5.3-xen-sparse/i386-xen/compile/.cvsignore
    1.14 +423e7e87zkFCb_Z4sHQpbec6jk3MdA freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC
    1.15 +423e7e876sW2cYvlk0qy8YnBbPlklQ freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC.hints
    1.16 +423e7e87DGOWxuyrh3sr9TmUwddFuQ freebsd-5.3-xen-sparse/i386-xen/conf/Makefile
    1.17 +423e7e87eEVyCRO7fX1xtDhf1XJkVg freebsd-5.3-xen-sparse/i386-xen/conf/NOTES
    1.18 +423e7e87XB6xpj6WE1bGhL_VMtRYzg freebsd-5.3-xen-sparse/i386-xen/conf/OLDCARD
    1.19 +423e7e87a984mQwCH2oAeQuddGgKLg freebsd-5.3-xen-sparse/i386-xen/conf/PAE
    1.20 +423e7e87Ol0GS76rWAgsk3LUwcGDxA freebsd-5.3-xen-sparse/i386-xen/conf/XENCONF
    1.21 +423e7e87J8ZFS37QDhcVwErFq0MI_Q freebsd-5.3-xen-sparse/i386-xen/conf/gethints.awk
    1.22 +423e7e879JhpmoexiNPqXRRcBmZ9gg freebsd-5.3-xen-sparse/i386-xen/i386-xen/clock.c
    1.23 +423e7e88URfvmzX5RoVTjlaUHW5-AA freebsd-5.3-xen-sparse/i386-xen/i386-xen/critical.c
    1.24 +423e7e88MJxOMvE6pfDvSHp7WuF9DQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/ctrl_if.c
    1.25 +423e7e885ZJMOinNI0XzQE4EgL0N8g freebsd-5.3-xen-sparse/i386-xen/i386-xen/db_interface.c
    1.26 +423e7e88B5vxFblc-MlhxKk9e4ieBw freebsd-5.3-xen-sparse/i386-xen/i386-xen/evtchn.c
    1.27 +423e7e88z_BrFu1O71-Ya4pXJpjAPQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/exception.s
    1.28 +423e7e88uDvAZLmABMkqOpmemyVRyw freebsd-5.3-xen-sparse/i386-xen/i386-xen/genassym.c
    1.29 +423e7e88yr5NFQudubMnkvdb_y-Gtg freebsd-5.3-xen-sparse/i386-xen/i386-xen/hypervisor.c
    1.30 +423e7e88Y-e-4RRf9nrgkVn5PXUv3Q freebsd-5.3-xen-sparse/i386-xen/i386-xen/i686_mem.c
    1.31 +423e7e88b8m2cuGtOxVvs4Sok4Vk7Q freebsd-5.3-xen-sparse/i386-xen/i386-xen/initcpu.c
    1.32 +423e7e88GWQb_EYd2ifpPwFUkLsuZg freebsd-5.3-xen-sparse/i386-xen/i386-xen/intr_machdep.c
    1.33 +423e7e88rk8Ehi__jv3lkHlY5AgJ8g freebsd-5.3-xen-sparse/i386-xen/i386-xen/io_apic.c
    1.34 +423e7e89gHdRITIMC8UcCGE8I_b1xA freebsd-5.3-xen-sparse/i386-xen/i386-xen/local_apic.c
    1.35 +423e7e89rRVY9tFlFqlknnIz3yeWbA freebsd-5.3-xen-sparse/i386-xen/i386-xen/locore.s
    1.36 +423e7e89jeY3Xt1xJzoIaMuJYTvgSA freebsd-5.3-xen-sparse/i386-xen/i386-xen/machdep.c
    1.37 +423e7e89heNir7lAB1UbeMMUqePgMw freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_clock.c
    1.38 +423e7e890R-y2KIiLL3gmhxK84t_Hw freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_machdep.c
    1.39 +423e7e890m0CRnOquORvF3Yd328kSQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/mptable.c
    1.40 +423e7e89IqeULJgwXuSF9vnCAqpnbA freebsd-5.3-xen-sparse/i386-xen/i386-xen/pmap.c
    1.41 +423e7e89gaiMYCEiHavf3VGTvD06JA freebsd-5.3-xen-sparse/i386-xen/i386-xen/support.s
    1.42 +423e7e89DDt4jyU_HE0XCkRYRqs76g freebsd-5.3-xen-sparse/i386-xen/i386-xen/swtch.s
    1.43 +423e7e89GTxBtczOgi8_jt6vWa9X7g freebsd-5.3-xen-sparse/i386-xen/i386-xen/symbols.raw
    1.44 +423e7e8988cR9BIPAYAk4mLhHzfJtw freebsd-5.3-xen-sparse/i386-xen/i386-xen/sys_machdep.c
    1.45 +423e7e8a96Rk0vPk2939cEa26JBpeQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/trap.c
    1.46 +423e7e8a0PDbz_hWtTKwo4ZKy-FNYw freebsd-5.3-xen-sparse/i386-xen/i386-xen/vm_machdep.c
    1.47 +423e7e8aMaZIkzUU5UH-VgwB6uVJDQ freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_bus.c
    1.48 +423e7e8ac9Zkao6o8lF_dpdwz6FoXg freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_machdep.c
    1.49 +423e7e8aVYTynjpZsJxUsFSlIDhpJw freebsd-5.3-xen-sparse/i386-xen/include/cpufunc.h
    1.50 +423e7e8avrrUxDugrwq_GJp499DkJw freebsd-5.3-xen-sparse/i386-xen/include/ctrl_if.h
    1.51 +423e7e8apY1r9Td-S0eZITNZZbfNTQ freebsd-5.3-xen-sparse/i386-xen/include/evtchn.h
    1.52 +423e7e8aL9DsObEegCwtILrF6SWcAQ freebsd-5.3-xen-sparse/i386-xen/include/frame.h
    1.53 +423e7e8btv8Gojq50ggnP5A1Dkc4kA freebsd-5.3-xen-sparse/i386-xen/include/hypervisor-ifs.h
    1.54 +423e7e8buhTLVFLZ33-5s8-UdADSZg freebsd-5.3-xen-sparse/i386-xen/include/hypervisor.h
    1.55 +423e7e8bnHT1kMD-FPC7zHZR7l3VXw freebsd-5.3-xen-sparse/i386-xen/include/md_var.h
    1.56 +423e7e8b9iF0oV70F62vNrZt8YbiQA freebsd-5.3-xen-sparse/i386-xen/include/multicall.h
    1.57 +423e7e8bpUbyvkZ7a8MWY0A_oWrB0w freebsd-5.3-xen-sparse/i386-xen/include/param.h
    1.58 +423e7e8bdz1fj4Rlj8W7OWXgLfBT7w freebsd-5.3-xen-sparse/i386-xen/include/pcb.h
    1.59 +423e7e8bHhHGybRm4OXwdq9NEOvZwQ freebsd-5.3-xen-sparse/i386-xen/include/pcpu.h
    1.60 +423e7e8bI1dvek3ZR7BKw7dMkVAEkA freebsd-5.3-xen-sparse/i386-xen/include/pmap.h
    1.61 +423e7e8bVOoPguCLyNj7pil-PT7Vcw freebsd-5.3-xen-sparse/i386-xen/include/segments.h
    1.62 +423e7e8c9AuwksRrt0ptRKHnNVWuNQ freebsd-5.3-xen-sparse/i386-xen/include/synch_bitops.h
    1.63 +423e7e8csdWimnMBI2HxEDJ30L42kQ freebsd-5.3-xen-sparse/i386-xen/include/trap.h
    1.64 +423e7e8cgVgn9W8sZWwfh_4938fSJQ freebsd-5.3-xen-sparse/i386-xen/include/ucontext.h
    1.65 +423e7e8cdsEhPyad2ppDoSiBR4eB9g freebsd-5.3-xen-sparse/i386-xen/include/vmparam.h
    1.66 +423e7e8ccGI7kzIlRcEVziGZzm46wg freebsd-5.3-xen-sparse/i386-xen/include/xen-os.h
    1.67 +423e7e8cVSqLIOp5vH4ADvAL_MF6Qg freebsd-5.3-xen-sparse/i386-xen/include/xen_intr.h
    1.68 +423e7e8c1vzXK91FKaMnZz0NZpb5NA freebsd-5.3-xen-sparse/i386-xen/include/xenfunc.h
    1.69 +423e7e8cLPHbgUJHLf1pPqZXlBgVqQ freebsd-5.3-xen-sparse/i386-xen/include/xenpmap.h
    1.70 +423e7e8caalqG0UsGxkk9PshfnMFtA freebsd-5.3-xen-sparse/i386-xen/include/xenvar.h
    1.71 +423e7e8c8MGTB12W2GZ-mTa-_T5Xuw freebsd-5.3-xen-sparse/i386-xen/xen/blkfront/xb_blkfront.c
    1.72 +423e7e8dL_lQk1nbqJ5MPL5cTzXR5g freebsd-5.3-xen-sparse/i386-xen/xen/char/console.c
    1.73 +423e7e8d4LBg7lzjHtssnxcZwezLJQ freebsd-5.3-xen-sparse/i386-xen/xen/misc/evtchn_dev.c
    1.74 +423e7e8dVX2QkuzWwB2rtZDxD5Y_-w freebsd-5.3-xen-sparse/i386-xen/xen/misc/npx.c
    1.75 +423e7e8d_PdWXjQeRg75twh7TleJhQ freebsd-5.3-xen-sparse/i386-xen/xen/netfront/xn_netfront.c
    1.76 +423e7e8dlsc1oCW_ul57w0AHY5jZjQ freebsd-5.3-xen-sparse/kern/kern_fork.c
    1.77 +423e7e8dVDL1WLfbmQWuXMbetYk4jA freebsd-5.3-xen-sparse/mkbuildtree
    1.78 +423e7e8dBrOrAbydK6h49bY0VvDgPw freebsd-5.3-xen-sparse/xenfbsd_kernel_build
    1.79  4187ca95_eQN62ugV1zliQcfzXrHnw install.sh
    1.80  3e5a4e6589G-U42lFKs43plskXoFxQ linux-2.4.29-xen-sparse/Makefile
    1.81  3e5a4e65IEPjnWPZ5w3TxS5scV8Ewg linux-2.4.29-xen-sparse/arch/xen/Makefile
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/freebsd-5.3-xen-sparse/conf/Makefile.i386-xen	Mon Mar 21 07:58:08 2005 +0000
     2.3 @@ -0,0 +1,51 @@
     2.4 +# Makefile.i386 -- with config changes.
     2.5 +# Copyright 1990 W. Jolitz
     2.6 +#	from: @(#)Makefile.i386	7.1 5/10/91
     2.7 +# $FreeBSD: src/sys/conf/Makefile.i386,v 1.259 2003/04/15 21:29:11 phk Exp $
     2.8 +#
     2.9 +# Makefile for FreeBSD
    2.10 +#
    2.11 +# This makefile is constructed from a machine description:
    2.12 +#	config machineid
    2.13 +# Most changes should be made in the machine description
    2.14 +#	/sys/i386/conf/``machineid''
    2.15 +# after which you should do
    2.16 +#	 config machineid
    2.17 +# Generic makefile changes should be made in
    2.18 +#	/sys/conf/Makefile.i386
    2.19 +# after which config should be rerun for all machines.
    2.20 +#
    2.21 +
    2.22 +# Which version of config(8) is required.
    2.23 +%VERSREQ=	500013
    2.24 +
    2.25 +STD8X16FONT?=	iso
    2.26 +
    2.27 +
    2.28 +
    2.29 +.if !defined(S)
    2.30 +.if exists(./@/.)
    2.31 +S=	./@
    2.32 +.else
    2.33 +S=	../../..
    2.34 +.endif
    2.35 +.endif
    2.36 +.include "$S/conf/kern.pre.mk"
    2.37 +M=	i386-xen
    2.38 +MKMODULESENV+= MACHINE=i386-xen
    2.39 +INCLUDES+= -I../../include/xen-public
    2.40 +%BEFORE_DEPEND
    2.41 +
    2.42 +%OBJS
    2.43 +
    2.44 +%FILES.c
    2.45 +
    2.46 +%FILES.s
    2.47 +
    2.48 +%FILES.m
    2.49 +
    2.50 +%CLEAN
    2.51 +
    2.52 +%RULES
    2.53 +
    2.54 +.include "$S/conf/kern.post.mk"
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/freebsd-5.3-xen-sparse/conf/files.i386-xen	Mon Mar 21 07:58:08 2005 +0000
     3.3 @@ -0,0 +1,294 @@
     3.4 +# This file tells config what files go into building a kernel,
     3.5 +# files marked standard are always included.
     3.6 +#
     3.7 +# $FreeBSD: src/sys/conf/files.i386,v 1.457 2003/12/03 23:06:30 imp Exp $
     3.8 +#
     3.9 +# The long compile-with and dependency lines are required because of
    3.10 +# limitations in config: backslash-newline doesn't work in strings, and
    3.11 +# dependency lines other than the first are silently ignored.
    3.12 +#
    3.13 +linux_genassym.o		optional	compat_linux		\
    3.14 +	dependency 	"$S/i386/linux/linux_genassym.c"		\
    3.15 +	compile-with	"${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}"	\
    3.16 +	no-obj no-implicit-rule						\
    3.17 +	clean		"linux_genassym.o"
    3.18 +#
    3.19 +linux_assym.h			optional	compat_linux		\
    3.20 +	dependency 	"$S/kern/genassym.sh linux_genassym.o"		\
    3.21 +	compile-with	"sh $S/kern/genassym.sh linux_genassym.o > ${.TARGET}" \
    3.22 +	no-obj no-implicit-rule before-depend				\
    3.23 +	clean		"linux_assym.h"
    3.24 +#
    3.25 +svr4_genassym.o			optional	compat_svr4		\
    3.26 +	dependency 	"$S/i386/svr4/svr4_genassym.c"			\
    3.27 +	compile-with	"${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}"	\
    3.28 +	no-obj no-implicit-rule						\
    3.29 +	clean		"svr4_genassym.o"
    3.30 +#
    3.31 +svr4_assym.h			optional	compat_svr4		\
    3.32 +	dependency 	"$S/kern/genassym.sh svr4_genassym.o"	   	\
    3.33 +	compile-with	"sh $S/kern/genassym.sh svr4_genassym.o > ${.TARGET}" \
    3.34 +	no-obj no-implicit-rule before-depend				\
    3.35 +	clean		"svr4_assym.h"
    3.36 +#
    3.37 +font.h				optional	sc_dflt_font		\
    3.38 +	compile-with	"uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h"									\
    3.39 +	no-obj no-implicit-rule before-depend				\
    3.40 +	clean		"font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8"
    3.41 +#
    3.42 +atkbdmap.h			optional	atkbd_dflt_keymap	\
    3.43 +	compile-with	"/usr/sbin/kbdcontrol -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h"			\
    3.44 +	no-obj no-implicit-rule before-depend				\
    3.45 +	clean		"atkbdmap.h"
    3.46 +#
    3.47 +ukbdmap.h			optional	ukbd_dflt_keymap	\
    3.48 +	compile-with	"/usr/sbin/kbdcontrol -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h"			\
    3.49 +	no-obj no-implicit-rule before-depend				\
    3.50 +	clean		"ukbdmap.h"
    3.51 +#
    3.52 +msysosak.o			optional	fla			\
    3.53 +	dependency	"$S/contrib/dev/fla/i386/msysosak.o.uu" 	\
    3.54 +	compile-with	"uudecode < $S/contrib/dev/fla/i386/msysosak.o.uu" \
    3.55 +	no-implicit-rule
    3.56 +#
    3.57 +trlld.o				optional	oltr			\
    3.58 +	dependency	"$S/contrib/dev/oltr/i386-elf.trlld.o.uu"	\
    3.59 +	compile-with	"uudecode < $S/contrib/dev/oltr/i386-elf.trlld.o.uu"	\
    3.60 +	no-implicit-rule
    3.61 +#
    3.62 +hal.o				optional	ath_hal			\
    3.63 +	dependency	"$S/contrib/dev/ath/freebsd/i386-elf.hal.o.uu"	\
    3.64 +	compile-with	"uudecode < $S/contrib/dev/ath/freebsd/i386-elf.hal.o.uu" \
    3.65 +	no-implicit-rule
    3.66 +#
    3.67 +#
    3.68 +compat/linux/linux_file.c	optional	compat_linux
    3.69 +compat/linux/linux_getcwd.c	optional	compat_linux
    3.70 +compat/linux/linux_ioctl.c	optional	compat_linux
    3.71 +compat/linux/linux_ipc.c	optional	compat_linux
    3.72 +compat/linux/linux_mib.c	optional	compat_linux
    3.73 +compat/linux/linux_misc.c	optional	compat_linux
    3.74 +compat/linux/linux_signal.c	optional	compat_linux
    3.75 +compat/linux/linux_socket.c	optional	compat_linux
    3.76 +compat/linux/linux_stats.c	optional	compat_linux
    3.77 +compat/linux/linux_sysctl.c	optional	compat_linux
    3.78 +compat/linux/linux_uid16.c	optional	compat_linux
    3.79 +compat/linux/linux_util.c	optional	compat_linux
    3.80 +compat/pecoff/imgact_pecoff.c		optional	pecoff_support
    3.81 +compat/svr4/imgact_svr4.c		optional	compat_svr4
    3.82 +compat/svr4/svr4_fcntl.c		optional	compat_svr4
    3.83 +compat/svr4/svr4_filio.c		optional	compat_svr4
    3.84 +compat/svr4/svr4_ioctl.c		optional	compat_svr4
    3.85 +compat/svr4/svr4_ipc.c			optional	compat_svr4
    3.86 +compat/svr4/svr4_misc.c			optional	compat_svr4
    3.87 +compat/svr4/svr4_resource.c		optional	compat_svr4
    3.88 +compat/svr4/svr4_signal.c		optional	compat_svr4
    3.89 +compat/svr4/svr4_socket.c		optional	compat_svr4
    3.90 +compat/svr4/svr4_sockio.c		optional	compat_svr4
    3.91 +compat/svr4/svr4_stat.c			optional	compat_svr4
    3.92 +compat/svr4/svr4_stream.c		optional	compat_svr4
    3.93 +compat/svr4/svr4_syscallnames.c		optional	compat_svr4
    3.94 +compat/svr4/svr4_sysent.c		optional	compat_svr4
    3.95 +compat/svr4/svr4_sysvec.c		optional	compat_svr4
    3.96 +compat/svr4/svr4_termios.c		optional	compat_svr4
    3.97 +compat/svr4/svr4_ttold.c		optional	compat_svr4
    3.98 +contrib/dev/fla/fla.c		optional	fla
    3.99 +contrib/dev/oltr/if_oltr.c	optional	oltr
   3.100 +contrib/dev/oltr/trlldbm.c	optional	oltr
   3.101 +contrib/dev/oltr/trlldhm.c	optional	oltr
   3.102 +contrib/dev/oltr/trlldmac.c	optional	oltr
   3.103 +bf_enc.o			optional	ipsec ipsec_esp		\
   3.104 +	dependency	"$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S"		\
   3.105 +	compile-with	"${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}"	\
   3.106 +	no-implicit-rule
   3.107 +crypto/des/arch/i386/des_enc.S		optional	ipsec ipsec_esp
   3.108 +crypto/des/des_ecb.c			optional	netsmbcrypto
   3.109 +crypto/des/arch/i386/des_enc.S		optional	netsmbcrypto
   3.110 +crypto/des/des_setkey.c			optional	netsmbcrypto
   3.111 +bf_enc.o			optional	crypto		\
   3.112 +	dependency	"$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S"		\
   3.113 +	compile-with	"${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}"	\
   3.114 +	no-implicit-rule
   3.115 +crypto/des/arch/i386/des_enc.S		optional	crypto
   3.116 +crypto/des/des_ecb.c			optional	crypto
   3.117 +crypto/des/des_setkey.c			optional	crypto
   3.118 +dev/ar/if_ar.c			optional	ar
   3.119 +dev/ar/if_ar_pci.c		optional	ar pci
   3.120 +dev/cx/csigma.c			optional	cx
   3.121 +dev/cx/cxddk.c			optional	cx
   3.122 +dev/cx/if_cx.c			optional	cx
   3.123 +dev/dgb/dgb.c			count		dgb
   3.124 +dev/fb/fb.c			optional	fb
   3.125 +dev/fb/fb.c			optional	vga
   3.126 +dev/fb/splash.c			optional	splash
   3.127 +dev/fb/vga.c			optional	vga
   3.128 +dev/kbd/atkbd.c			optional	atkbd
   3.129 +dev/kbd/atkbdc.c		optional	atkbdc
   3.130 +dev/kbd/kbd.c			optional	atkbd
   3.131 +dev/kbd/kbd.c			optional	kbd
   3.132 +dev/kbd/kbd.c			optional	sc
   3.133 +dev/kbd/kbd.c			optional	ukbd
   3.134 +dev/kbd/kbd.c			optional	vt
   3.135 +dev/mem/memutil.c		standard
   3.136 +dev/random/nehemiah.c		standard
   3.137 +dev/ppc/ppc.c			optional	ppc
   3.138 +dev/ppc/ppc_puc.c		optional	ppc puc pci
   3.139 +dev/sio/sio.c			optional	sio
   3.140 +dev/sio/sio_isa.c		optional	sio isa
   3.141 +dev/syscons/schistory.c		optional	sc
   3.142 +dev/syscons/scmouse.c		optional	sc
   3.143 +dev/syscons/scterm.c		optional	sc
   3.144 +dev/syscons/scterm-dumb.c	optional	sc
   3.145 +dev/syscons/scterm-sc.c		optional	sc
   3.146 +dev/syscons/scvesactl.c		optional	sc vga vesa
   3.147 +dev/syscons/scvgarndr.c		optional	sc vga
   3.148 +dev/syscons/scvidctl.c		optional	sc
   3.149 +dev/syscons/scvtb.c		optional	sc
   3.150 +dev/syscons/syscons.c		optional	sc
   3.151 +dev/syscons/sysmouse.c		optional	sc
   3.152 +dev/uart/uart_cpu_i386.c	optional	uart
   3.153 +geom/geom_bsd.c			standard
   3.154 +geom/geom_bsd_enc.c		standard
   3.155 +geom/geom_mbr.c			standard
   3.156 +geom/geom_mbr_enc.c		standard
   3.157 +i386/acpica/OsdEnvironment.c	optional	acpi
   3.158 +i386/acpica/acpi_machdep.c	optional	acpi
   3.159 +i386/acpica/acpi_wakeup.c	optional	acpi
   3.160 +acpi_wakecode.h			optional	acpi			\
   3.161 +	dependency 	"$S/i386/acpica/acpi_wakecode.S"		\
   3.162 +	compile-with	"${MAKE} -f $S/i386/acpica/Makefile MAKESRCPATH=$S/i386/acpica"	\
   3.163 +	no-obj no-implicit-rule before-depend				\
   3.164 +	clean		"acpi_wakecode.h acpi_wakecode.o acpi_wakecode.bin"
   3.165 +#
   3.166 +i386/acpica/madt.c		optional	acpi apic
   3.167 +i386/bios/mca_machdep.c		optional	mca
   3.168 +i386/bios/smapi.c		optional	smapi
   3.169 +i386/bios/smapi_bios.S		optional	smapi
   3.170 +i386/bios/smbios.c		optional	smbios
   3.171 +i386/bios/vpd.c			optional	vpd
   3.172 +i386/i386/apic_vector.s		optional	apic
   3.173 +i386/i386/atomic.c		standard				\
   3.174 +	compile-with	"${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}"
   3.175 +i386/i386/autoconf.c		        standard
   3.176 +i386/i386/busdma_machdep.c		standard
   3.177 +i386-xen/i386-xen/critical.c		standard
   3.178 +i386/i386/db_disasm.c			optional	ddb
   3.179 +i386-xen/i386-xen/db_interface.c	optional	ddb
   3.180 +i386/i386/db_trace.c			optional	ddb
   3.181 +i386/i386/i386-gdbstub.c		optional	ddb
   3.182 +i386/i386/dump_machdep.c		standard
   3.183 +i386/i386/elf_machdep.c	standard
   3.184 +i386-xen/i386-xen/exception.s		standard
   3.185 +i386-xen/i386-xen/i686_mem.c		standard
   3.186 +i386/i386/identcpu.c			standard
   3.187 +i386/i386/in_cksum.c			optional	inet
   3.188 +i386-xen/i386-xen/initcpu.c		standard
   3.189 +i386-xen/i386-xen/intr_machdep.c	standard
   3.190 +i386-xen/i386-xen/io_apic.c           optional        apic
   3.191 +i386/i386/legacy.c			standard
   3.192 +i386-xen/i386-xen/locore.s		standard	no-obj
   3.193 +i386-xen/i386-xen/machdep.c		standard
   3.194 +i386/i386/mem.c		                standard
   3.195 +i386-xen/i386-xen/mp_clock.c		optional	smp
   3.196 +i386-xen/i386-xen/mp_machdep.c	optional	smp
   3.197 +i386/i386/mpboot.s		optional	smp
   3.198 +i386-xen/i386-xen/mptable.c	optional	apic
   3.199 +i386-xen/i386-xen/local_apic.c	optional	apic
   3.200 +i386/i386/mptable_pci.c		optional	apic pci
   3.201 +i386/i386/nexus.c	        standard
   3.202 +i386/i386/uio_machdep.c	        standard
   3.203 +i386/i386/perfmon.c		optional	perfmon
   3.204 +i386/i386/perfmon.c		optional	perfmon	profiling-routine
   3.205 +i386-xen/i386-xen/pmap.c	standard
   3.206 +i386-xen/i386-xen/support.s	standard
   3.207 +i386-xen/i386-xen/swtch.s	standard
   3.208 +i386-xen/i386-xen/sys_machdep.c		standard
   3.209 +i386-xen/i386-xen/trap.c	standard
   3.210 +i386/i386/tsc.c			standard
   3.211 +i386-xen/i386-xen/vm_machdep.c		standard
   3.212 +i386-xen/i386-xen/clock.c	standard
   3.213 +
   3.214 +# xen specific arch-dep files
   3.215 +i386-xen/i386-xen/hypervisor.c	standard
   3.216 +i386-xen/i386-xen/xen_machdep.c	standard
   3.217 +i386-xen/i386-xen/xen_bus.c		standard
   3.218 +i386-xen/i386-xen/evtchn.c		standard
   3.219 +i386-xen/i386-xen/ctrl_if.c		standard
   3.220 +
   3.221 +
   3.222 +i386/isa/asc.c			count		asc
   3.223 +i386/isa/ctx.c			optional	ctx
   3.224 +i386/isa/cy.c			count		cy
   3.225 +i386/isa/elink.c		optional	ep
   3.226 +i386/isa/elink.c		optional	ie
   3.227 +i386/isa/gpib.c			optional	gp
   3.228 +i386/isa/gsc.c			count		gsc
   3.229 +i386/isa/istallion.c		optional	stli nowerror
   3.230 +i386/isa/loran.c		optional	loran
   3.231 +i386/isa/mse.c			optional	mse
   3.232 +i386/isa/nmi.c			standard
   3.233 +
   3.234 +# drivers
   3.235 +i386-xen/xen/misc/npx.c	optional	npx
   3.236 +i386-xen/xen/misc/evtchn_dev.c	standard
   3.237 +i386-xen/xen/char/console.c	standard
   3.238 +i386-xen/xen/netfront/xn_netfront.c	standard
   3.239 +i386-xen/xen/blkfront/xb_blkfront.c	standard
   3.240 +
   3.241 +
   3.242 +
   3.243 +i386/isa/pcf.c			optional	pcf
   3.244 +i386/isa/pcvt/pcvt_drv.c	optional	vt
   3.245 +i386/isa/pcvt/pcvt_ext.c	optional	vt
   3.246 +i386/isa/pcvt/pcvt_kbd.c	optional	vt
   3.247 +i386/isa/pcvt/pcvt_out.c	optional	vt
   3.248 +i386/isa/pcvt/pcvt_sup.c	optional	vt
   3.249 +i386/isa/pcvt/pcvt_vtf.c	optional	vt
   3.250 +i386/isa/pmtimer.c		optional	pmtimer
   3.251 +i386/isa/prof_machdep.c		optional	profiling-routine
   3.252 +i386/isa/spic.c			optional	spic
   3.253 +i386/isa/spigot.c		count		spigot
   3.254 +i386/isa/spkr.c			optional	speaker
   3.255 +i386/isa/stallion.c		optional	stl nowerror
   3.256 +i386/isa/vesa.c			optional	vga vesa
   3.257 +i386/isa/wt.c			count		wt
   3.258 +i386/linux/imgact_linux.c	optional	compat_linux
   3.259 +i386/linux/linux_dummy.c	optional	compat_linux
   3.260 +i386/linux/linux_locore.s	optional	compat_linux		\
   3.261 +	dependency 	"linux_assym.h"
   3.262 +i386/linux/linux_machdep.c	optional	compat_linux
   3.263 +i386/linux/linux_ptrace.c	optional	compat_linux
   3.264 +i386/linux/linux_sysent.c	optional	compat_linux
   3.265 +i386/linux/linux_sysvec.c	optional	compat_linux
   3.266 +i386/pci/pci_cfgreg.c		optional	pci
   3.267 +i386/pci/pci_bus.c		optional	pci
   3.268 +i386/svr4/svr4_locore.s		optional	compat_svr4		\
   3.269 +	dependency	"svr4_assym.h"	\
   3.270 +	warning "COMPAT_SVR4 is broken and should be avoided"
   3.271 +i386/svr4/svr4_machdep.c	optional	compat_svr4
   3.272 +isa/atkbd_isa.c			optional	atkbd
   3.273 +isa/atkbdc_isa.c		optional	atkbdc
   3.274 +isa/fd.c			optional	fdc
   3.275 +isa/psm.c			optional	psm
   3.276 +isa/syscons_isa.c		optional	sc
   3.277 +isa/vga_isa.c			optional	vga
   3.278 +kern/imgact_aout.c		optional	compat_aout
   3.279 +kern/imgact_gzip.c		optional	gzip
   3.280 +libkern/divdi3.c		standard
   3.281 +libkern/moddi3.c		standard
   3.282 +libkern/qdivrem.c		standard
   3.283 +libkern/ucmpdi2.c		standard
   3.284 +libkern/udivdi3.c		standard
   3.285 +libkern/umoddi3.c		standard
   3.286 +libkern/flsl.c			standard
   3.287 +libkern/ffsl.c			standard
   3.288 +
   3.289 +pci/cy_pci.c			optional	cy pci
   3.290 +pci/agp_intel.c			optional	agp
   3.291 +pci/agp_via.c			optional	agp
   3.292 +pci/agp_sis.c			optional	agp
   3.293 +pci/agp_ali.c			optional	agp
   3.294 +pci/agp_amd.c			optional	agp
   3.295 +pci/agp_i810.c			optional	agp
   3.296 +pci/agp_nvidia.c		optional	agp
   3.297 +
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/freebsd-5.3-xen-sparse/conf/ldscript.i386-xen	Mon Mar 21 07:58:08 2005 +0000
     4.3 @@ -0,0 +1,134 @@
     4.4 +/* $FreeBSD: src/sys/conf/ldscript.i386,v 1.9 2003/12/03 07:40:03 phk Exp $ */
     4.5 +OUTPUT_FORMAT("elf32-i386-freebsd", "elf32-i386-freebsd", "elf32-i386-freebsd")
     4.6 +OUTPUT_ARCH(i386)
     4.7 +ENTRY(btext)
     4.8 +SEARCH_DIR(/usr/lib);
     4.9 +SECTIONS
    4.10 +{
    4.11 +  /* Read-only sections, merged into text segment: */
    4.12 +  . = kernbase + SIZEOF_HEADERS;
    4.13 +  .interp     : { *(.interp) 	}
    4.14 +  .hash          : { *(.hash)		}
    4.15 +  .dynsym        : { *(.dynsym)		}
    4.16 +  .dynstr        : { *(.dynstr)		}
    4.17 +  .gnu.version   : { *(.gnu.version)	}
    4.18 +  .gnu.version_d   : { *(.gnu.version_d)	}
    4.19 +  .gnu.version_r   : { *(.gnu.version_r)	}
    4.20 +  .rel.text      :
    4.21 +    { *(.rel.text) *(.rel.gnu.linkonce.t*) }
    4.22 +  .rela.text     :
    4.23 +    { *(.rela.text) *(.rela.gnu.linkonce.t*) }
    4.24 +  .rel.data      :
    4.25 +    { *(.rel.data) *(.rel.gnu.linkonce.d*) }
    4.26 +  .rela.data     :
    4.27 +    { *(.rela.data) *(.rela.gnu.linkonce.d*) }
    4.28 +  .rel.rodata    :
    4.29 +    { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
    4.30 +  .rela.rodata   :
    4.31 +    { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
    4.32 +  .rel.got       : { *(.rel.got)		}
    4.33 +  .rela.got      : { *(.rela.got)		}
    4.34 +  .rel.ctors     : { *(.rel.ctors)	}
    4.35 +  .rela.ctors    : { *(.rela.ctors)	}
    4.36 +  .rel.dtors     : { *(.rel.dtors)	}
    4.37 +  .rela.dtors    : { *(.rela.dtors)	}
    4.38 +  .rel.init      : { *(.rel.init)	}
    4.39 +  .rela.init     : { *(.rela.init)	}
    4.40 +  .rel.fini      : { *(.rel.fini)	}
    4.41 +  .rela.fini     : { *(.rela.fini)	}
    4.42 +  .rel.bss       : { *(.rel.bss)		}
    4.43 +  .rela.bss      : { *(.rela.bss)		}
    4.44 +  .rel.plt       : { *(.rel.plt)		}
    4.45 +  .rela.plt      : { *(.rela.plt)		}
    4.46 +  .init          : { *(.init)	} =0x9090
    4.47 +  .plt      : { *(.plt)	}
    4.48 +  .text      :
    4.49 +  {
    4.50 +    *(.text)
    4.51 +    *(.stub)
    4.52 +    /* .gnu.warning sections are handled specially by elf32.em.  */
    4.53 +    *(.gnu.warning)
    4.54 +    *(.gnu.linkonce.t*)
    4.55 +  } =0x9090
    4.56 +  _etext = .;
    4.57 +  PROVIDE (etext = .);
    4.58 +  .fini      : { *(.fini)    } =0x9090
    4.59 +  .rodata    : { *(.rodata) *(.gnu.linkonce.r*) }
    4.60 +  .rodata1   : { *(.rodata1) }
    4.61 +  /* Adjust the address for the data segment.  We want to adjust up to
    4.62 +     the same address within the page on the next page up.  */
    4.63 +  . = ALIGN(0x1000) + (. & (0x1000 - 1)) ; 
    4.64 +  .data    :
    4.65 +  {
    4.66 +    *(.data)
    4.67 +    *(.gnu.linkonce.d*)
    4.68 +    CONSTRUCTORS
    4.69 +  }
    4.70 +  .data1   : { *(.data1) }
    4.71 +  . = ALIGN(32 / 8);
    4.72 +  _start_ctors = .;
    4.73 +  PROVIDE (start_ctors = .);
    4.74 +  .ctors         :
    4.75 +  {
    4.76 +    *(.ctors)
    4.77 +  }
    4.78 +  _stop_ctors = .;
    4.79 +  PROVIDE (stop_ctors = .);
    4.80 +  .dtors         :
    4.81 +  {
    4.82 +    *(.dtors)
    4.83 +  }
    4.84 +  .got           : { *(.got.plt) *(.got) }
    4.85 +  .dynamic       : { *(.dynamic) }
    4.86 +  /* We want the small data sections together, so single-instruction offsets
    4.87 +     can access them all, and initialized data all before uninitialized, so
    4.88 +     we can shorten the on-disk segment size.  */
    4.89 +  .sdata     : { *(.sdata) }
    4.90 +  _edata  =  .;
    4.91 +  PROVIDE (edata = .);
    4.92 +  __bss_start = .;
    4.93 +  .sbss      : { *(.sbss) *(.scommon) }
    4.94 +  .bss       :
    4.95 +  {
    4.96 +   *(.dynbss)
    4.97 +   *(.bss)
    4.98 +   *(COMMON)
    4.99 +  }
   4.100 +  . = ALIGN(32 / 8);
   4.101 +  _end = . ;
   4.102 +  PROVIDE (end = .);
   4.103 +  /* Stabs debugging sections.  */
   4.104 +  .stab 0 : { *(.stab) }
   4.105 +  .stabstr 0 : { *(.stabstr) }
   4.106 +  .stab.excl 0 : { *(.stab.excl) }
   4.107 +  .stab.exclstr 0 : { *(.stab.exclstr) }
   4.108 +  .stab.index 0 : { *(.stab.index) }
   4.109 +  .stab.indexstr 0 : { *(.stab.indexstr) }
   4.110 +  .comment 0 : { *(.comment) }
   4.111 +  /* DWARF debug sections.
   4.112 +     Symbols in the DWARF debugging sections are relative to the beginning
   4.113 +     of the section so we begin them at 0.  */
   4.114 +  /* DWARF 1 */
   4.115 +  .debug          0 : { *(.debug) }
   4.116 +  .line           0 : { *(.line) }
   4.117 +  /* GNU DWARF 1 extensions */
   4.118 +  .debug_srcinfo  0 : { *(.debug_srcinfo) }
   4.119 +  .debug_sfnames  0 : { *(.debug_sfnames) }
   4.120 +  /* DWARF 1.1 and DWARF 2 */
   4.121 +  .debug_aranges  0 : { *(.debug_aranges) }
   4.122 +  .debug_pubnames 0 : { *(.debug_pubnames) }
   4.123 +  /* DWARF 2 */
   4.124 +  .debug_info     0 : { *(.debug_info) }
   4.125 +  .debug_abbrev   0 : { *(.debug_abbrev) }
   4.126 +  .debug_line     0 : { *(.debug_line) }
   4.127 +  .debug_frame    0 : { *(.debug_frame) }
   4.128 +  .debug_str      0 : { *(.debug_str) }
   4.129 +  .debug_loc      0 : { *(.debug_loc) }
   4.130 +  .debug_macinfo  0 : { *(.debug_macinfo) }
   4.131 +  /* SGI/MIPS DWARF 2 extensions */
   4.132 +  .debug_weaknames 0 : { *(.debug_weaknames) }
   4.133 +  .debug_funcnames 0 : { *(.debug_funcnames) }
   4.134 +  .debug_typenames 0 : { *(.debug_typenames) }
   4.135 +  .debug_varnames  0 : { *(.debug_varnames) }
   4.136 +  /* These must appear regardless of  .  */
   4.137 +}
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/freebsd-5.3-xen-sparse/conf/options.i386-xen	Mon Mar 21 07:58:08 2005 +0000
     5.3 @@ -0,0 +1,162 @@
     5.4 +# $FreeBSD: src/sys/conf/options.i386,v 1.204 2003/12/03 23:06:30 imp Exp $
     5.5 +# Options specific to the i386 platform kernels
     5.6 +
     5.7 +AUTO_EOI_1		opt_auto_eoi.h
     5.8 +AUTO_EOI_2		opt_auto_eoi.h
     5.9 +BROKEN_KEYBOARD_RESET	opt_reset.h
    5.10 +COMPAT_OLDISA
    5.11 +I586_PMC_GUPROF		opt_i586_guprof.h
    5.12 +MAXMEM
    5.13 +MPTABLE_FORCE_HTT
    5.14 +NO_MIXED_MODE
    5.15 +PERFMON
    5.16 +DISABLE_PSE		opt_pmap.h
    5.17 +DISABLE_PG_G		opt_pmap.h
    5.18 +PMAP_SHPGPERPROC	opt_pmap.h
    5.19 +PPC_PROBE_CHIPSET	opt_ppc.h
    5.20 +PPC_DEBUG		opt_ppc.h
    5.21 +POWERFAIL_NMI		opt_trap.h
    5.22 +MP_WATCHDOG             opt_mp_watchdog.h
    5.23 +
    5.24 +
    5.25 +
    5.26 +# Options for emulators.  These should only be used at config time, so
    5.27 +# they are handled like options for static filesystems
    5.28 +# (see src/sys/conf/options), except for broken debugging options.
    5.29 +COMPAT_AOUT		opt_dontuse.h
    5.30 +IBCS2			opt_dontuse.h
    5.31 +COMPAT_LINUX		opt_dontuse.h
    5.32 +COMPAT_SVR4		opt_dontuse.h
    5.33 +DEBUG_SVR4		opt_svr4.h
    5.34 +PECOFF_SUPPORT		opt_dontuse.h
    5.35 +PECOFF_DEBUG		opt_pecoff.h
    5.36 +
    5.37 +# Change KVM size.  Changes things all over the kernel.
    5.38 +KVA_PAGES		opt_global.h
    5.39 +XEN			opt_global.h
    5.40 +XENDEV			opt_xen.h
    5.41 +NOXENDEBUG		opt_xen.h
    5.42 +# Physical address extensions and support for >4G ram.  As above.
    5.43 +PAE			opt_global.h
    5.44 +
    5.45 +CLK_CALIBRATION_LOOP		opt_clock.h
    5.46 +CLK_USE_I8254_CALIBRATION	opt_clock.h
    5.47 +CLK_USE_TSC_CALIBRATION		opt_clock.h
    5.48 +TIMER_FREQ			opt_clock.h
    5.49 +
    5.50 +CPU_ATHLON_SSE_HACK		opt_cpu.h
    5.51 +CPU_BLUELIGHTNING_3X		opt_cpu.h
    5.52 +CPU_BLUELIGHTNING_FPU_OP_CACHE	opt_cpu.h
    5.53 +CPU_BTB_EN			opt_cpu.h
    5.54 +CPU_CYRIX_NO_LOCK		opt_cpu.h
    5.55 +CPU_DIRECT_MAPPED_CACHE		opt_cpu.h
    5.56 +CPU_DISABLE_5X86_LSSER		opt_cpu.h
    5.57 +CPU_DISABLE_CMPXCHG		opt_global.h	# XXX global, unlike other CPU_*
    5.58 +CPU_DISABLE_SSE			opt_cpu.h
    5.59 +CPU_ELAN			opt_cpu.h
    5.60 +CPU_ELAN_XTAL			opt_cpu.h
    5.61 +CPU_ELAN_PPS			opt_cpu.h
    5.62 +CPU_ENABLE_SSE			opt_cpu.h
    5.63 +CPU_FASTER_5X86_FPU		opt_cpu.h
    5.64 +CPU_GEODE			opt_cpu.h
    5.65 +CPU_I486_ON_386			opt_cpu.h
    5.66 +CPU_IORT			opt_cpu.h
    5.67 +CPU_L2_LATENCY			opt_cpu.h
    5.68 +CPU_LOOP_EN			opt_cpu.h
    5.69 +CPU_PPRO2CELERON		opt_cpu.h
    5.70 +CPU_RSTK_EN			opt_cpu.h
    5.71 +CPU_SOEKRIS			opt_cpu.h
    5.72 +CPU_SUSP_HLT			opt_cpu.h
    5.73 +CPU_UPGRADE_HW_CACHE		opt_cpu.h
    5.74 +CPU_WT_ALLOC			opt_cpu.h
    5.75 +CYRIX_CACHE_REALLY_WORKS	opt_cpu.h
    5.76 +CYRIX_CACHE_WORKS		opt_cpu.h
    5.77 +NO_F00F_HACK			opt_cpu.h
    5.78 +NO_MEMORY_HOLE			opt_cpu.h
    5.79 +
    5.80 +# The CPU type affects the endian conversion functions all over the kernel.
    5.81 +I386_CPU		opt_global.h
    5.82 +I486_CPU		opt_global.h
    5.83 +I586_CPU		opt_global.h
    5.84 +I686_CPU		opt_global.h
    5.85 +
    5.86 +VGA_ALT_SEQACCESS	opt_vga.h
    5.87 +VGA_DEBUG		opt_vga.h
    5.88 +VGA_NO_FONT_LOADING	opt_vga.h
    5.89 +VGA_NO_MODE_CHANGE	opt_vga.h
    5.90 +VGA_SLOW_IOACCESS	opt_vga.h
    5.91 +VGA_WIDTH90		opt_vga.h
    5.92 +
    5.93 +VESA
    5.94 +VESA_DEBUG		opt_vesa.h
    5.95 +
    5.96 +PSM_HOOKRESUME		opt_psm.h
    5.97 +PSM_RESETAFTERSUSPEND	opt_psm.h
    5.98 +PSM_DEBUG		opt_psm.h
    5.99 +
   5.100 +ATKBD_DFLT_KEYMAP	opt_atkbd.h
   5.101 +
   5.102 +# pcvt(4) has a bunch of options
   5.103 +FAT_CURSOR		opt_pcvt.h
   5.104 +XSERVER			opt_pcvt.h
   5.105 +PCVT_24LINESDEF		opt_pcvt.h
   5.106 +PCVT_CTRL_ALT_DEL	opt_pcvt.h
   5.107 +PCVT_META_ESC		opt_pcvt.h
   5.108 +PCVT_NSCREENS		opt_pcvt.h
   5.109 +PCVT_PRETTYSCRNS	opt_pcvt.h
   5.110 +PCVT_SCANSET		opt_pcvt.h
   5.111 +PCVT_SCREENSAVER	opt_pcvt.h
   5.112 +PCVT_USEKBDSEC		opt_pcvt.h
   5.113 +PCVT_VT220KEYB		opt_pcvt.h
   5.114 +PCVT_GREENSAVER		opt_pcvt.h
   5.115 +
   5.116 +# Video spigot
   5.117 +SPIGOT_UNSECURE		opt_spigot.h
   5.118 +
   5.119 +# Enables NETGRAPH support for Cronyx adapters
   5.120 +NETGRAPH_CRONYX		opt_ng_cronyx.h
   5.121 +
   5.122 +# -------------------------------
   5.123 +# isdn4bsd: passive ISA cards
   5.124 +# -------------------------------
   5.125 +TEL_S0_8		opt_i4b.h
   5.126 +TEL_S0_16		opt_i4b.h
   5.127 +TEL_S0_16_3		opt_i4b.h
   5.128 +AVM_A1			opt_i4b.h
   5.129 +USR_STI			opt_i4b.h
   5.130 +ITKIX1			opt_i4b.h
   5.131 +ELSA_PCC16		opt_i4b.h
   5.132 +# -------------------------------
   5.133 +# isdn4bsd: passive ISA PnP cards
   5.134 +# -------------------------------
   5.135 +CRTX_S0_P		opt_i4b.h
   5.136 +DRN_NGO                 opt_i4b.h
   5.137 +TEL_S0_16_3_P		opt_i4b.h
   5.138 +SEDLBAUER		opt_i4b.h
   5.139 +DYNALINK		opt_i4b.h
   5.140 +ASUSCOM_IPAC		opt_i4b.h
   5.141 +ELSA_QS1ISA		opt_i4b.h
   5.142 +SIEMENS_ISURF2		opt_i4b.h
   5.143 +EICON_DIVA		opt_i4b.h
   5.144 +COMPAQ_M610		opt_i4b.h
   5.145 +# -------------------------------
   5.146 +# isdn4bsd: passive PCI cards
   5.147 +# -------------------------------
   5.148 +ELSA_QS1PCI		opt_i4b.h
   5.149 +# -------------------------------
   5.150 +# isdn4bsd: misc options
   5.151 +# -------------------------------
   5.152 +# temporary workaround for SMP machines
   5.153 +I4B_SMP_WORKAROUND      opt_i4b.h
   5.154 +# enable VJ compression code for ipr i/f
   5.155 +IPR_VJ			opt_i4b.h
   5.156 +IPR_LOG			opt_i4b.h
   5.157 +
   5.158 +# Device options
   5.159 +DEV_ACPI		opt_acpi.h
   5.160 +DEV_APIC		opt_apic.h
   5.161 +DEV_NPX			opt_npx.h
   5.162 +
   5.163 +# -------------------------------
   5.164 +# EOF
   5.165 +# -------------------------------
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/freebsd-5.3-xen-sparse/fbsdxensetup	Mon Mar 21 07:58:08 2005 +0000
     6.3 @@ -0,0 +1,39 @@
     6.4 +#!/bin/csh -f
     6.5 +
     6.6 +setenv XENROOT `bk root`
     6.7 +rm -rf $XENROOT/fbsdtmp $XENROOT/freebsd-5.3-xenU
     6.8 +mkdir -p $XENROOT/fbsdtmp
     6.9 +cd $XENROOT/fbsdtmp
    6.10 +echo "step 1"
    6.11 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.aa
    6.12 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ab
    6.13 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ac
    6.14 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ad
    6.15 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ae
    6.16 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.af
    6.17 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ag
    6.18 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ah
    6.19 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ai
    6.20 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.aj
    6.21 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.ak
    6.22 +wget ftp://ftp.freebsd.org/pub/FreeBSD/releases/i386/5.3-RELEASE/src/ssys.al
    6.23 +mkdir -p foo
    6.24 +cat ssys.?? | tar --unlink -xpzf - -C foo/
    6.25 +mkdir -p $XENROOT/freebsd-5.3-xenU
    6.26 +mv foo/sys/* $XENROOT/freebsd-5.3-xenU
    6.27 +cd $XENROOT
    6.28 +rm -rf $XENROOT/fbsdtmp
    6.29 +echo "step 2"
    6.30 +mkdir -p $XENROOT/freebsd-5.3-xenU/i386-xen/include
    6.31 +cd $XENROOT/freebsd-5.3-xenU/i386-xen/include/
    6.32 +foreach file (../../i386/include/*)
    6.33 +	ln -s $file
    6.34 +end 
    6.35 +echo "step 3"
    6.36 +cd $XENROOT/freebsd-5.3-xen-sparse
    6.37 +echo "step 4"
    6.38 +./mkbuildtree ../freebsd-5.3-xenU
    6.39 +echo "step 5"
    6.40 +cd $XENROOT/freebsd-5.3-xenU/i386-xen/include
    6.41 +ln -s $XENROOT/xen/include/public xen-public
    6.42 +echo "done"
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/Makefile	Mon Mar 21 07:58:08 2005 +0000
     7.3 @@ -0,0 +1,40 @@
     7.4 +# $FreeBSD: src/sys/i386/Makefile,v 1.11 2002/06/21 06:18:02 mckusick Exp $
     7.5 +#	@(#)Makefile	8.1 (Berkeley) 6/11/93
     7.6 +
     7.7 +# Makefile for i386 links, tags file
     7.8 +
     7.9 +# SYS is normally set in Make.tags.inc
    7.10 +# SYS=/sys
    7.11 +SYS=/nsys
    7.12 +
    7.13 +TAGDIR=	i386
    7.14 +
    7.15 +.include "../kern/Make.tags.inc"
    7.16 +
    7.17 +all:
    7.18 +	@echo "make links or tags only"
    7.19 +
    7.20 +# Directories in which to place i386 tags links
    7.21 +DI386=	apm i386 ibcs2 include isa linux
    7.22 +
    7.23 +links::
    7.24 +	-for i in ${COMMDIR1}; do \
    7.25 +	    (cd $$i && { rm -f tags; ln -s ../${TAGDIR}/tags tags; }) done
    7.26 +	-for i in ${COMMDIR2}; do \
    7.27 +	    (cd $$i && { rm -f tags; ln -s ../../${TAGDIR}/tags tags; }) done
    7.28 +	-for i in ${DI386}; do \
    7.29 +	    (cd $$i && { rm -f tags; ln -s ../tags tags; }) done
    7.30 +
    7.31 +SI386=	${SYS}/i386/apm/*.[ch] \
    7.32 +	${SYS}/i386/i386/*.[ch] ${SYS}/i386/ibcs2/*.[ch] \
    7.33 +	${SYS}/i386/include/*.[ch] ${SYS}/i386/isa/*.[ch] \
    7.34 +	${SYS}/i386/linux/*.[ch]
    7.35 +AI386=	${SYS}/i386/i386/*.s
    7.36 +
    7.37 +tags::
    7.38 +	-ctags -wdt ${COMM} ${SI386}
    7.39 +	egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AI386} | \
    7.40 +	    sed "s;\([^:]*\):\([^(]*\)(\([^, )]*\)\(.*\);\3 \1 /^\2(\3\4$$/;" \
    7.41 +		>> tags
    7.42 +	sort -o tags tags
    7.43 +	chmod 444 tags
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/compile/.cvsignore	Mon Mar 21 07:58:08 2005 +0000
     8.3 @@ -0,0 +1,1 @@
     8.4 +[A-Za-z0-9]*
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC	Mon Mar 21 07:58:08 2005 +0000
     9.3 @@ -0,0 +1,273 @@
     9.4 +#
     9.5 +# GENERIC -- Generic kernel configuration file for FreeBSD/i386
     9.6 +#
     9.7 +# For more information on this file, please read the handbook section on
     9.8 +# Kernel Configuration Files:
     9.9 +#
    9.10 +#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
    9.11 +#
    9.12 +# The handbook is also available locally in /usr/share/doc/handbook
    9.13 +# if you've installed the doc distribution, otherwise always see the
    9.14 +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
    9.15 +# latest information.
    9.16 +#
    9.17 +# An exhaustive list of options and more detailed explanations of the
    9.18 +# device lines is also present in the ../../conf/NOTES and NOTES files. 
    9.19 +# If you are in doubt as to the purpose or necessity of a line, check first 
    9.20 +# in NOTES.
    9.21 +#
    9.22 +# $FreeBSD: src/sys/i386/conf/GENERIC,v 1.394.2.3 2004/01/26 19:42:11 nectar Exp $
    9.23 +
    9.24 +machine		i386
    9.25 +cpu		I486_CPU
    9.26 +cpu		I586_CPU
    9.27 +cpu		I686_CPU
    9.28 +ident		GENERIC
    9.29 +
    9.30 +#To statically compile in device wiring instead of /boot/device.hints
    9.31 +#hints		"GENERIC.hints"		#Default places to look for devices.
    9.32 +
    9.33 +#makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
    9.34 +
    9.35 +options 	SCHED_4BSD		#4BSD scheduler
    9.36 +options 	INET			#InterNETworking
    9.37 +options 	INET6			#IPv6 communications protocols
    9.38 +options 	FFS			#Berkeley Fast Filesystem
    9.39 +options 	SOFTUPDATES		#Enable FFS soft updates support
    9.40 +options 	UFS_ACL			#Support for access control lists
    9.41 +options 	UFS_DIRHASH		#Improve performance on big directories
    9.42 +options 	MD_ROOT			#MD is a potential root device
    9.43 +options 	NFSCLIENT		#Network Filesystem Client
    9.44 +options 	NFSSERVER		#Network Filesystem Server
    9.45 +options 	NFS_ROOT		#NFS usable as /, requires NFSCLIENT
    9.46 +options 	MSDOSFS			#MSDOS Filesystem
    9.47 +options 	CD9660			#ISO 9660 Filesystem
    9.48 +options 	PROCFS			#Process filesystem (requires PSEUDOFS)
    9.49 +options 	PSEUDOFS		#Pseudo-filesystem framework
    9.50 +options 	COMPAT_43		#Compatible with BSD 4.3 [KEEP THIS!]
    9.51 +options 	COMPAT_FREEBSD4		#Compatible with FreeBSD4
    9.52 +options 	SCSI_DELAY=15000	#Delay (in ms) before probing SCSI
    9.53 +options 	KTRACE			#ktrace(1) support
    9.54 +options 	SYSVSHM			#SYSV-style shared memory
    9.55 +options 	SYSVMSG			#SYSV-style message queues
    9.56 +options 	SYSVSEM			#SYSV-style semaphores
    9.57 +options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
    9.58 +options 	KBD_INSTALL_CDEV	# install a CDEV entry in /dev
    9.59 +options 	AHC_REG_PRETTY_PRINT	# Print register bitfields in debug
    9.60 +					# output.  Adds ~128k to driver.
    9.61 +options 	AHD_REG_PRETTY_PRINT	# Print register bitfields in debug
    9.62 +					# output.  Adds ~215k to driver.
    9.63 +options 	PFIL_HOOKS		# pfil(9) framework
    9.64 +
    9.65 +# Debugging for use in -current
    9.66 +#options 	DDB			#Enable the kernel debugger
    9.67 +#options 	INVARIANTS		#Enable calls of extra sanity checking
    9.68 +options 	INVARIANT_SUPPORT	#Extra sanity checks of internal structures, required by INVARIANTS
    9.69 +#options 	WITNESS			#Enable checks to detect deadlocks and cycles
    9.70 +#options 	WITNESS_SKIPSPIN	#Don't run witness on spinlocks for speed
    9.71 +
    9.72 +# To make an SMP kernel, the next two are needed
    9.73 +options 	SMP			# Symmetric MultiProcessor Kernel
    9.74 +device		apic			# I/O APIC
    9.75 +
    9.76 +device		isa
    9.77 +device		eisa
    9.78 +device		pci
    9.79 +
    9.80 +# Floppy drives
    9.81 +device		fdc
    9.82 +
    9.83 +# ATA and ATAPI devices
    9.84 +device		ata
    9.85 +device		atadisk			# ATA disk drives
    9.86 +device		ataraid			# ATA RAID drives
    9.87 +device		atapicd			# ATAPI CDROM drives
    9.88 +device		atapifd			# ATAPI floppy drives
    9.89 +device		atapist			# ATAPI tape drives
    9.90 +options 	ATA_STATIC_ID		#Static device numbering
    9.91 +
    9.92 +# SCSI Controllers
    9.93 +device		ahb		# EISA AHA1742 family
    9.94 +device		ahc		# AHA2940 and onboard AIC7xxx devices
    9.95 +device		ahd		# AHA39320/29320 and onboard AIC79xx devices
    9.96 +device		amd		# AMD 53C974 (Tekram DC-390(T))
    9.97 +device		isp		# Qlogic family
    9.98 +device		mpt		# LSI-Logic MPT-Fusion
    9.99 +#device		ncr		# NCR/Symbios Logic
   9.100 +device		sym		# NCR/Symbios Logic (newer chipsets + those of `ncr')
   9.101 +device		trm		# Tekram DC395U/UW/F DC315U adapters
   9.102 +
   9.103 +device		adv		# Advansys SCSI adapters
   9.104 +device		adw		# Advansys wide SCSI adapters
   9.105 +device		aha		# Adaptec 154x SCSI adapters
   9.106 +device		aic		# Adaptec 15[012]x SCSI adapters, AIC-6[23]60.
   9.107 +device		bt		# Buslogic/Mylex MultiMaster SCSI adapters
   9.108 +
   9.109 +device		ncv		# NCR 53C500
   9.110 +device		nsp		# Workbit Ninja SCSI-3
   9.111 +device		stg		# TMC 18C30/18C50
   9.112 +
   9.113 +# SCSI peripherals
   9.114 +device		scbus		# SCSI bus (required for SCSI)
   9.115 +device		ch		# SCSI media changers
   9.116 +device		da		# Direct Access (disks)
   9.117 +device		sa		# Sequential Access (tape etc)
   9.118 +device		cd		# CD
   9.119 +device		pass		# Passthrough device (direct SCSI access)
   9.120 +device		ses		# SCSI Environmental Services (and SAF-TE)
   9.121 +
   9.122 +# RAID controllers interfaced to the SCSI subsystem
   9.123 +device		amr		# AMI MegaRAID
   9.124 +device		asr		# DPT SmartRAID V, VI and Adaptec SCSI RAID
   9.125 +device		ciss		# Compaq Smart RAID 5*
   9.126 +device		dpt		# DPT Smartcache III, IV - See NOTES for options
   9.127 +device		iir		# Intel Integrated RAID
   9.128 +device		ips		# IBM (Adaptec) ServeRAID
   9.129 +device		mly		# Mylex AcceleRAID/eXtremeRAID
   9.130 +
   9.131 +# RAID controllers
   9.132 +device		aac		# Adaptec FSA RAID
   9.133 +device		aacp		# SCSI passthrough for aac (requires CAM)
   9.134 +device		ida		# Compaq Smart RAID
   9.135 +device		mlx		# Mylex DAC960 family
   9.136 +device		pst		# Promise Supertrak SX6000
   9.137 +device		twe		# 3ware ATA RAID
   9.138 +
   9.139 +# atkbdc0 controls both the keyboard and the PS/2 mouse
   9.140 +device		atkbdc		# AT keyboard controller
   9.141 +device		atkbd		# AT keyboard
   9.142 +device		psm		# PS/2 mouse
   9.143 +
   9.144 +device		vga		# VGA video card driver
   9.145 +
   9.146 +device		splash		# Splash screen and screen saver support
   9.147 +
   9.148 +# syscons is the default console driver, resembling an SCO console
   9.149 +device		sc
   9.150 +
   9.151 +# Enable this for the pcvt (VT220 compatible) console driver
   9.152 +#device		vt
   9.153 +#options 	XSERVER			# support for X server on a vt console
   9.154 +#options 	FAT_CURSOR		# start with block cursor
   9.155 +
   9.156 +device		agp		# support several AGP chipsets
   9.157 +
   9.158 +# Floating point support - do not disable.
   9.159 +device		npx
   9.160 +
   9.161 +# Power management support (see NOTES for more options)
   9.162 +#device		apm
   9.163 +# Add suspend/resume support for the i8254.
   9.164 +device		pmtimer
   9.165 +
   9.166 +# PCCARD (PCMCIA) support
   9.167 +# Pcmcia and cardbus bridge support
   9.168 +device		cbb			# cardbus (yenta) bridge
   9.169 +#device		pcic			# ExCA ISA and PCI bridges
   9.170 +device		pccard			# PC Card (16-bit) bus
   9.171 +device		cardbus			# CardBus (32-bit) bus
   9.172 +
   9.173 +# Serial (COM) ports
   9.174 +device		sio		# 8250, 16[45]50 based serial ports
   9.175 +
   9.176 +# Parallel port
   9.177 +device		ppc
   9.178 +device		ppbus		# Parallel port bus (required)
   9.179 +device		lpt		# Printer
   9.180 +device		plip		# TCP/IP over parallel
   9.181 +device		ppi		# Parallel port interface device
   9.182 +#device		vpo		# Requires scbus and da
   9.183 +
   9.184 +# If you've got a "dumb" serial or parallel PCI card that is
   9.185 +# supported by the puc(4) glue driver, uncomment the following
   9.186 +# line to enable it (connects to the sio and/or ppc drivers):
   9.187 +#device         puc
   9.188 +
   9.189 +# PCI Ethernet NICs.
   9.190 +device		de		# DEC/Intel DC21x4x (``Tulip'')
   9.191 +device		em		# Intel PRO/1000 adapter Gigabit Ethernet Card
   9.192 +device		txp		# 3Com 3cR990 (``Typhoon'')
   9.193 +device		vx		# 3Com 3c590, 3c595 (``Vortex'')
   9.194 +
   9.195 +# PCI Ethernet NICs that use the common MII bus controller code.
   9.196 +# NOTE: Be sure to keep the 'device miibus' line in order to use these NICs!
   9.197 +device		miibus		# MII bus support
   9.198 +device		bfe		# Broadcom BCM440x 10/100 ethernet
   9.199 +device		bge		# Broadcom BCM570xx Gigabit Ethernet
   9.200 +device		dc		# DEC/Intel 21143 and various workalikes
   9.201 +device		fxp		# Intel EtherExpress PRO/100B (82557, 82558)
   9.202 +device		pcn		# AMD Am79C97x PCI 10/100 (precedence over 'lnc')
   9.203 +device		re		# RealTek 8139C+/8169/8169S/8110S
   9.204 +device		rl		# RealTek 8129/8139
   9.205 +device		sf		# Adaptec AIC-6915 (``Starfire'')
   9.206 +device		sis		# Silicon Integrated Systems SiS 900/SiS 7016
   9.207 +device		sk		# SysKonnect SK-984x and SK-982x gigabit ethernet
   9.208 +device		ste		# Sundance ST201 (D-Link DFE-550TX)
   9.209 +device		ti		# Alteon Networks Tigon I/II gigabit ethernet
   9.210 +device		tl		# Texas Instruments ThunderLAN
   9.211 +device		tx		# SMC EtherPower II (83c170 ``EPIC'')
   9.212 +device		vr		# VIA Rhine, Rhine II
   9.213 +device		wb		# Winbond W89C840F
   9.214 +device		xl		# 3Com 3c90x (``Boomerang'', ``Cyclone'')
   9.215 +
   9.216 +# ISA Ethernet NICs.  pccard nics included.
   9.217 +device		cs		# Crystal Semiconductor CS89x0 NIC
   9.218 +# 'device ed' requires 'device miibus'
   9.219 +device		ed		# NE[12]000, SMC Ultra, 3c503, DS8390 cards
   9.220 +device		ex		# Intel EtherExpress Pro/10 and Pro/10+
   9.221 +device		ep		# Etherlink III based cards
   9.222 +device		fe		# Fujitsu MB8696x based cards
   9.223 +device		ie		# EtherExpress 8/16, 3C507, StarLAN 10 etc.
   9.224 +device		lnc		# NE2100, NE32-VL Lance Ethernet cards
   9.225 +device		sn		# SMC's 9000 series of ethernet chips
   9.226 +device		xe		# Xircom pccard ethernet
   9.227 +
   9.228 +# ISA devices that use the old ISA shims
   9.229 +#device		le
   9.230 +
   9.231 +# Wireless NIC cards
   9.232 +device		wlan		# 802.11 support
   9.233 +device		an		# Aironet 4500/4800 802.11 wireless NICs. 
   9.234 +device		awi		# BayStack 660 and others
   9.235 +device		wi		# WaveLAN/Intersil/Symbol 802.11 wireless NICs.
   9.236 +#device		wl		# Older non 802.11 Wavelan wireless NIC.
   9.237 +
   9.238 +# Pseudo devices - the number indicates how many units to allocate.
   9.239 +device		random		# Entropy device
   9.240 +device		loop		# Network loopback
   9.241 +device		ether		# Ethernet support
   9.242 +device		sl		# Kernel SLIP
   9.243 +device		ppp		# Kernel PPP
   9.244 +device		tun		# Packet tunnel.
   9.245 +device		pty		# Pseudo-ttys (telnet etc)
   9.246 +device		md		# Memory "disks"
   9.247 +device		gif		# IPv6 and IPv4 tunneling
   9.248 +device		faith		# IPv6-to-IPv4 relaying (translation)
   9.249 +
   9.250 +# The `bpf' device enables the Berkeley Packet Filter.
   9.251 +# Be aware of the administrative consequences of enabling this!
   9.252 +device		bpf		# Berkeley packet filter
   9.253 +
   9.254 +# USB support
   9.255 +device		uhci		# UHCI PCI->USB interface
   9.256 +device		ohci		# OHCI PCI->USB interface
   9.257 +device		usb		# USB Bus (required)
   9.258 +#device		udbp		# USB Double Bulk Pipe devices
   9.259 +device		ugen		# Generic
   9.260 +device		uhid		# "Human Interface Devices"
   9.261 +device		ukbd		# Keyboard
   9.262 +device		ulpt		# Printer
   9.263 +device		umass		# Disks/Mass storage - Requires scbus and da
   9.264 +device		ums		# Mouse
   9.265 +device		urio		# Diamond Rio 500 MP3 player
   9.266 +device		uscanner	# Scanners
   9.267 +# USB Ethernet, requires mii
   9.268 +device		aue		# ADMtek USB ethernet
   9.269 +device		axe		# ASIX Electronics USB ethernet
   9.270 +device		cue		# CATC USB ethernet
   9.271 +device		kue		# Kawasaki LSI USB ethernet
   9.272 +
   9.273 +# FireWire support
   9.274 +device		firewire	# FireWire bus code
   9.275 +device		sbp		# SCSI over FireWire (Requires scbus and da)
   9.276 +device		fwe		# Ethernet over FireWire (non-standard!)
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/GENERIC.hints	Mon Mar 21 07:58:08 2005 +0000
    10.3 @@ -0,0 +1,93 @@
    10.4 +# $FreeBSD: src/sys/i386/conf/GENERIC.hints,v 1.11 2002/12/05 22:49:47 jhb Exp $
    10.5 +hint.fdc.0.at="isa"
    10.6 +hint.fdc.0.port="0x3F0"
    10.7 +hint.fdc.0.irq="6"
    10.8 +hint.fdc.0.drq="2"
    10.9 +hint.fd.0.at="fdc0"
   10.10 +hint.fd.0.drive="0"
   10.11 +hint.fd.1.at="fdc0"
   10.12 +hint.fd.1.drive="1"
   10.13 +hint.ata.0.at="isa"
   10.14 +hint.ata.0.port="0x1F0"
   10.15 +hint.ata.0.irq="14"
   10.16 +hint.ata.1.at="isa"
   10.17 +hint.ata.1.port="0x170"
   10.18 +hint.ata.1.irq="15"
   10.19 +hint.adv.0.at="isa"
   10.20 +hint.adv.0.disabled="1"
   10.21 +hint.bt.0.at="isa"
   10.22 +hint.bt.0.disabled="1"
   10.23 +hint.aha.0.at="isa"
   10.24 +hint.aha.0.disabled="1"
   10.25 +hint.aic.0.at="isa"
   10.26 +hint.aic.0.disabled="1"
   10.27 +hint.atkbdc.0.at="isa"
   10.28 +hint.atkbdc.0.port="0x060"
   10.29 +hint.atkbd.0.at="atkbdc"
   10.30 +hint.atkbd.0.irq="1"
   10.31 +hint.atkbd.0.flags="0x1"
   10.32 +hint.psm.0.at="atkbdc"
   10.33 +hint.psm.0.irq="12"
   10.34 +hint.vga.0.at="isa"
   10.35 +hint.sc.0.at="isa"
   10.36 +hint.sc.0.flags="0x100"
   10.37 +hint.vt.0.at="isa"
   10.38 +hint.vt.0.disabled="1"
   10.39 +hint.apm.0.disabled="1"
   10.40 +hint.apm.0.flags="0x20"
   10.41 +hint.pcic.0.at="isa"
   10.42 +# hint.pcic.0.irq="10"	# Default to polling
   10.43 +hint.pcic.0.port="0x3e0"
   10.44 +hint.pcic.0.maddr="0xd0000"
   10.45 +hint.pcic.1.at="isa"
   10.46 +hint.pcic.1.irq="11"
   10.47 +hint.pcic.1.port="0x3e2"
   10.48 +hint.pcic.1.maddr="0xd4000"
   10.49 +hint.pcic.1.disabled="1"
   10.50 +hint.sio.0.at="isa"
   10.51 +hint.sio.0.port="0x3F8"
   10.52 +hint.sio.0.flags="0x10"
   10.53 +hint.sio.0.irq="4"
   10.54 +hint.sio.1.at="isa"
   10.55 +hint.sio.1.port="0x2F8"
   10.56 +hint.sio.1.irq="3"
   10.57 +hint.sio.2.at="isa"
   10.58 +hint.sio.2.disabled="1"
   10.59 +hint.sio.2.port="0x3E8"
   10.60 +hint.sio.2.irq="5"
   10.61 +hint.sio.3.at="isa"
   10.62 +hint.sio.3.disabled="1"
   10.63 +hint.sio.3.port="0x2E8"
   10.64 +hint.sio.3.irq="9"
   10.65 +hint.ppc.0.at="isa"
   10.66 +hint.ppc.0.irq="7"
   10.67 +hint.ed.0.at="isa"
   10.68 +hint.ed.0.disabled="1"
   10.69 +hint.ed.0.port="0x280"
   10.70 +hint.ed.0.irq="10"
   10.71 +hint.ed.0.maddr="0xd8000"
   10.72 +hint.cs.0.at="isa"
   10.73 +hint.cs.0.disabled="1"
   10.74 +hint.cs.0.port="0x300"
   10.75 +hint.sn.0.at="isa"
   10.76 +hint.sn.0.disabled="1"
   10.77 +hint.sn.0.port="0x300"
   10.78 +hint.sn.0.irq="10"
   10.79 +hint.ie.0.at="isa"
   10.80 +hint.ie.0.disabled="1"
   10.81 +hint.ie.0.port="0x300"
   10.82 +hint.ie.0.irq="10"
   10.83 +hint.ie.0.maddr="0xd0000"
   10.84 +hint.fe.0.at="isa"
   10.85 +hint.fe.0.disabled="1"
   10.86 +hint.fe.0.port="0x300"
   10.87 +hint.le.0.at="isa"
   10.88 +hint.le.0.disabled="1"
   10.89 +hint.le.0.port="0x300"
   10.90 +hint.le.0.irq="5"
   10.91 +hint.le.0.maddr="0xd0000"
   10.92 +hint.lnc.0.at="isa"
   10.93 +hint.lnc.0.disabled="1"
   10.94 +hint.lnc.0.port="0x280"
   10.95 +hint.lnc.0.irq="10"
   10.96 +hint.lnc.0.drq="0"
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/Makefile	Mon Mar 21 07:58:08 2005 +0000
    11.3 @@ -0,0 +1,3 @@
    11.4 +# $FreeBSD: src/sys/i386/conf/Makefile,v 1.9 2003/02/26 23:36:58 ru Exp $
    11.5 +
    11.6 +.include "${.CURDIR}/../../conf/makeLINT.mk"
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/NOTES	Mon Mar 21 07:58:08 2005 +0000
    12.3 @@ -0,0 +1,1115 @@
    12.4 +#
    12.5 +# NOTES -- Lines that can be cut/pasted into kernel and hints configs.
    12.6 +#
    12.7 +# This file contains machine dependent kernel configuration notes.  For
    12.8 +# machine independent notes, look in /sys/conf/NOTES.
    12.9 +#
   12.10 +# $FreeBSD: src/sys/i386/conf/NOTES,v 1.1108 2003/12/04 19:57:56 phk Exp $
   12.11 +#
   12.12 +
   12.13 +#
   12.14 +# This directive is mandatory; it defines the architecture to be
   12.15 +# configured for; in this case, the 386 family based IBM-PC and
   12.16 +# compatibles.
   12.17 +#
   12.18 +machine		i386
   12.19 +
   12.20 +# 
   12.21 +# We want LINT to cover profiling as well
   12.22 +profile         2
   12.23 +
   12.24 +
   12.25 +#####################################################################
   12.26 +# SMP OPTIONS:
   12.27 +#
   12.28 +# The apic device enables the use of the I/O APIC for interrupt delivery.
   12.29 +# The apic device can be used in both UP and SMP kernels, but is required
   12.30 +# for SMP kernels.  Thus, the apic device is not strictly an SMP option,
   12.31 +# but it is a prerequisite for SMP.
   12.32 +#
   12.33 +# Notes:
   12.34 +#
   12.35 +# Be sure to disable 'cpu I386_CPU' for SMP kernels.
   12.36 +#
   12.37 +# By default, mixed mode is used to route IRQ0 from the AT timer via
   12.38 +# the 8259A master PIC through the ExtINT pin on the first I/O APIC.
   12.39 +# This can be disabled via the NO_MIXED_MODE option.  In that case,
   12.40 +# IRQ0 will be routed via an intpin on the first I/O APIC.  Not all
   12.41 +# motherboards hook IRQ0 up to the first I/O APIC even though their
   12.42 +# MP table or MADT may claim to do so.  That is why mixed mode is
   12.43 +# enabled by default.
   12.44 +#
   12.45 +# HTT CPUs should only be used if they are enabled in the BIOS.  For
   12.46 +# the ACPI case, ACPI only correctly tells us about any HTT CPUs if
   12.47 +# they are enabled.  However, most HTT systems do not list HTT CPUs
   12.48 +# in the MP Table if they are enabled, thus we guess at the HTT CPUs
   12.49 +# for the MP Table case.  However, we shouldn't try to guess and use
   12.50 +# these CPUs if HTTT is disabled.  Thus, HTT guessing is only enabled
   12.51 +# for the MP Table if the user explicitly asks for it via the
   12.52 +# MPTABLE_FORCE_HTT option.  Do NOT use this option if you have HTT
   12.53 +# disabled in your BIOS.
   12.54 +#
   12.55 +
   12.56 +# Mandatory:
   12.57 +device		apic			# I/O apic
   12.58 +
   12.59 +# Optional:
   12.60 +options		MPTABLE_FORCE_HTT	# Enable HTT CPUs with the MP Table
   12.61 +options 	NO_MIXED_MODE		# Disable use of mixed mode
   12.62 +
   12.63 +
   12.64 +#####################################################################
   12.65 +# CPU OPTIONS
   12.66 +
   12.67 +#
   12.68 +# You must specify at least one CPU (the one you intend to run on);
   12.69 +# deleting the specification for CPUs you don't need to use may make
   12.70 +# parts of the system run faster.
   12.71 +# I386_CPU is mutually exclusive with the other CPU types.
   12.72 +#
   12.73 +#cpu		I386_CPU		
   12.74 +cpu		I486_CPU
   12.75 +cpu		I586_CPU		# aka Pentium(tm)
   12.76 +cpu		I686_CPU		# aka Pentium Pro(tm)
   12.77 +
   12.78 +#
   12.79 +# Options for CPU features.
   12.80 +#
   12.81 +# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has
   12.82 +# forgotten to enable them.
   12.83 +#
   12.84 +# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
   12.85 +# BlueLightning CPU.  It works only with Cyrix FPU, and this option
   12.86 +# should not be used with Intel FPU.
   12.87 +#
   12.88 +# CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning
   12.89 +# CPU if CPU supports it. The default is double-clock mode on
   12.90 +# BlueLightning CPU box.
   12.91 +#
   12.92 +# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
   12.93 +#
   12.94 +# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
   12.95 +# mapped mode.  Default is 2-way set associative mode.
   12.96 +#
   12.97 +# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
   12.98 +# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
   12.99 +# Otherwise, the NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
  12.100 +#
  12.101 +# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
  12.102 +# reorder).  This option should not be used if you use memory mapped
  12.103 +# I/O device(s).
  12.104 +#
  12.105 +# CPU_ELAN enables support for AMDs ElanSC520 CPU.
  12.106 +#    CPU_ELAN_XTAL sets the clock crystal frequency in Hz
  12.107 +#    CPU_ELAN_PPS enables precision timestamp code.
  12.108 +#
  12.109 +# CPU_SOEKRIS enables support www.soekris.com hardware.
  12.110 +#
  12.111 +# CPU_ENABLE_SSE enables SSE/MMX2 instructions support.  This is default
  12.112 +# on I686_CPU and above.
  12.113 +# CPU_DISABLE_SSE explicitly prevent I686_CPU from turning on SSE.
  12.114 +#
  12.115 +# CPU_FASTER_5X86_FPU enables faster FPU exception handler.
  12.116 +#
  12.117 +# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
  12.118 +# for i386 machines.
  12.119 +#
  12.120 +# CPU_IORT defines I/O clock delay time (NOTE 1).  Default values of
  12.121 +# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
  12.122 +# (no clock delay).
  12.123 +#
  12.124 +# CPU_L2_LATENCY specifed the L2 cache latency value.  This option is used
  12.125 +# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
  12.126 +# The default value is 5.
  12.127 +#
  12.128 +# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
  12.129 +# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
  12.130 +# 1).
  12.131 +#
  12.132 +# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs.  This option
  12.133 +# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
  12.134 +# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
  12.135 +#
  12.136 +# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
  12.137 +#
  12.138 +# CPU_SUSP_HLT enables suspend on HALT.  If this option is set, CPU
  12.139 +# enters suspend mode following execution of HALT instruction.
  12.140 +#
  12.141 +# CPU_UPGRADE_HW_CACHE eliminates unneeded cache flush instruction(s).
  12.142 +#
  12.143 +# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
  12.144 +# K5/K6/K6-2 cpus.
  12.145 +#
  12.146 +# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
  12.147 +# flush at hold state.
  12.148 +#
  12.149 +# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
  12.150 +# without cache flush at hold state, and (2) write-back CPU cache on
  12.151 +# Cyrix 6x86 whose revision < 2.7 (NOTE 2).
  12.152 +#
  12.153 +# NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY
  12.154 +# Pentiums) from locking up when a LOCK CMPXCHG8B instruction is
  12.155 +# executed.  This option is only needed if I586_CPU is also defined,
  12.156 +# and should be included for any non-Pentium CPU that defines it.
  12.157 +#
  12.158 +# NO_MEMORY_HOLE is an optimisation for systems with AMD K6 processors
  12.159 +# which indicates that the 15-16MB range is *definitely* not being
  12.160 +# occupied by an ISA memory hole.
  12.161 +#
  12.162 +# CPU_DISABLE_CMPXCHG disables the CMPXCHG instruction on > i386 IA32 
  12.163 +# machines.  VmWare seems to emulate this instruction poorly, causing 
  12.164 +# the guest OS to run very slowly.  Enabling this with a SMP kernel
  12.165 +# will cause the kernel to be unusable.
  12.166 +#
  12.167 +# NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT,
  12.168 +# CPU_LOOP_EN and CPU_RSTK_EN should not be used because of CPU bugs.
  12.169 +# These options may crash your system.
  12.170 +#
  12.171 +# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled
  12.172 +# in write-through mode when revision < 2.7.  If revision of Cyrix
  12.173 +# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
  12.174 +#
  12.175 +# NOTE 3: This option may cause failures for software that requires
  12.176 +# locked cycles in order to operate correctly.
  12.177 +#
  12.178 +options 	CPU_ATHLON_SSE_HACK
  12.179 +options 	CPU_BLUELIGHTNING_FPU_OP_CACHE
  12.180 +options 	CPU_BLUELIGHTNING_3X
  12.181 +options 	CPU_BTB_EN
  12.182 +options 	CPU_DIRECT_MAPPED_CACHE
  12.183 +options 	CPU_DISABLE_5X86_LSSER
  12.184 +options 	CPU_ELAN
  12.185 +options 	CPU_SOEKRIS
  12.186 +options 	CPU_ELAN_XTAL=32768000
  12.187 +options 	CPU_ELAN_PPS
  12.188 +options 	CPU_ENABLE_SSE
  12.189 +#options 	CPU_DISABLE_SSE
  12.190 +options 	CPU_FASTER_5X86_FPU
  12.191 +options 	CPU_I486_ON_386
  12.192 +options 	CPU_IORT
  12.193 +options 	CPU_L2_LATENCY=5
  12.194 +options 	CPU_LOOP_EN
  12.195 +options 	CPU_PPRO2CELERON
  12.196 +options 	CPU_RSTK_EN
  12.197 +options 	CPU_SUSP_HLT
  12.198 +options 	CPU_UPGRADE_HW_CACHE
  12.199 +options 	CPU_WT_ALLOC
  12.200 +options 	CYRIX_CACHE_WORKS
  12.201 +options 	CYRIX_CACHE_REALLY_WORKS
  12.202 +#options 	NO_F00F_HACK
  12.203 +options 	CPU_DISABLE_CMPXCHG
  12.204 +
  12.205 +# Debug options
  12.206 +options 	NPX_DEBUG	# enable npx debugging (FPU/math emu)
  12.207 +					#new math emulator
  12.208 +
  12.209 +#
  12.210 +# PERFMON causes the driver for Pentium/Pentium Pro performance counters
  12.211 +# to be compiled.  See perfmon(4) for more information.
  12.212 +#
  12.213 +options 	PERFMON
  12.214 +
  12.215 +
  12.216 +#####################################################################
  12.217 +# NETWORKING OPTIONS
  12.218 +
  12.219 +#
  12.220 +# DEVICE_POLLING adds support for mixed interrupt-polling handling
  12.221 +# of network device drivers, which has significant benefits in terms
  12.222 +# of robustness to overloads and responsivity, as well as permitting
  12.223 +# accurate scheduling of the CPU time between kernel network processing
  12.224 +# and other activities. The drawback is a moderate (up to 1/HZ seconds)
  12.225 +# potential increase in response times.
  12.226 +# It is strongly recommended to use HZ=1000 or 2000 with DEVICE_POLLING
  12.227 +# to achieve smoother behaviour.
  12.228 +# Additionally, you can enable/disable polling at runtime with the
  12.229 +# sysctl variable kern.polling.enable (defaults off), and select
  12.230 +# the CPU fraction reserved to userland with the sysctl variable
  12.231 +# kern.polling.user_frac (default 50, range 0..100).
  12.232 +#
  12.233 +# Only the "dc" "fxp" and "sis" devices support this mode of operation at
  12.234 +# the time of this writing.
  12.235 +
  12.236 +options 	DEVICE_POLLING
  12.237 +
  12.238 +
  12.239 +#####################################################################
  12.240 +# CLOCK OPTIONS
  12.241 +
  12.242 +# The following options are used for debugging clock behavior only, and
  12.243 +# should not be used for production systems.
  12.244 +#
  12.245 +# CLK_CALIBRATION_LOOP will run the clock calibration loop at startup
  12.246 +# until the user presses a key.
  12.247 +
  12.248 +options 	CLK_CALIBRATION_LOOP
  12.249 +
  12.250 +# The following two options measure the frequency of the corresponding
  12.251 +# clock relative to the RTC (onboard mc146818a).
  12.252 +
  12.253 +options 	CLK_USE_I8254_CALIBRATION
  12.254 +options 	CLK_USE_TSC_CALIBRATION
  12.255 +
  12.256 +
  12.257 +#####################################################################
  12.258 +# MISCELLANEOUS DEVICES AND OPTIONS
  12.259 +
  12.260 +device		speaker		#Play IBM BASIC-style noises out your speaker
  12.261 +hint.speaker.0.at="isa"
  12.262 +hint.speaker.0.port="0x61"
  12.263 +device		gzip		#Exec gzipped a.out's. REQUIRES COMPAT_AOUT!
  12.264 +device		apm_saver	# Requires APM
  12.265 +
  12.266 +
  12.267 +#####################################################################
  12.268 +# HARDWARE BUS CONFIGURATION
  12.269 +
  12.270 +#
  12.271 +# ISA bus
  12.272 +#
  12.273 +device		isa
  12.274 +
  12.275 +#
  12.276 +# Options for `isa':
  12.277 +#
  12.278 +# AUTO_EOI_1 enables the `automatic EOI' feature for the master 8259A
  12.279 +# interrupt controller.  This saves about 0.7-1.25 usec for each interrupt.
  12.280 +# This option breaks suspend/resume on some portables.
  12.281 +#
  12.282 +# AUTO_EOI_2 enables the `automatic EOI' feature for the slave 8259A
  12.283 +# interrupt controller.  This saves about 0.7-1.25 usec for each interrupt.
  12.284 +# Automatic EOI is documented not to work for for the slave with the
  12.285 +# original i8259A, but it works for some clones and some integrated
  12.286 +# versions.
  12.287 +#
  12.288 +# MAXMEM specifies the amount of RAM on the machine; if this is not
  12.289 +# specified, FreeBSD will first read the amount of memory from the CMOS
  12.290 +# RAM, so the amount of memory will initially be limited to 64MB or 16MB
  12.291 +# depending on the BIOS.  If the BIOS reports 64MB, a memory probe will
  12.292 +# then attempt to detect the installed amount of RAM.  If this probe
  12.293 +# fails to detect >64MB RAM you will have to use the MAXMEM option.
  12.294 +# The amount is in kilobytes, so for a machine with 128MB of RAM, it would
  12.295 +# be 131072 (128 * 1024).
  12.296 +#
  12.297 +# BROKEN_KEYBOARD_RESET disables the use of the keyboard controller to
  12.298 +# reset the CPU for reboot.  This is needed on some systems with broken
  12.299 +# keyboard controllers.
  12.300 +
  12.301 +options 	COMPAT_OLDISA	#Use ISA shims and glue for old drivers
  12.302 +options 	AUTO_EOI_1
  12.303 +#options 	AUTO_EOI_2
  12.304 +
  12.305 +options 	MAXMEM=(128*1024)
  12.306 +#options 	BROKEN_KEYBOARD_RESET
  12.307 +
  12.308 +# 
  12.309 +# EISA bus
  12.310 +#
  12.311 +# The EISA bus device is `eisa'.  It provides auto-detection and
  12.312 +# configuration support for all devices on the EISA bus.
  12.313 +
  12.314 +device		eisa
  12.315 +
  12.316 +# By default, only 10 EISA slots are probed, since the slot numbers
  12.317 +# above clash with the configuration address space of the PCI subsystem,
  12.318 +# and the EISA probe is not very smart about this.  This is sufficient
  12.319 +# for most machines, but in particular the HP NetServer LC series comes
  12.320 +# with an onboard AIC7770 dual-channel SCSI controller on EISA slot #11,
  12.321 +# thus you need to bump this figure to 12 for them.
  12.322 +options 	EISA_SLOTS=12
  12.323 +
  12.324 +#
  12.325 +# MCA bus:
  12.326 +#
  12.327 +# The MCA bus device is `mca'.  It provides auto-detection and
  12.328 +# configuration support for all devices on the MCA bus.
  12.329 +# No hints are required for MCA.
  12.330 +
  12.331 +device		mca
  12.332 +
  12.333 +#
  12.334 +# PCI bus & PCI options:
  12.335 +#
  12.336 +device		pci
  12.337 +
  12.338 +#
  12.339 +# AGP GART support
  12.340 +device		agp
  12.341 +
  12.342 +
  12.343 +#####################################################################
  12.344 +# HARDWARE DEVICE CONFIGURATION
  12.345 +
  12.346 +#
  12.347 +# Mandatory devices:
  12.348 +#
  12.349 +
  12.350 +# To include support for VGA VESA video modes
  12.351 +options 	VESA
  12.352 +
  12.353 +# Turn on extra debugging checks and output for VESA support.
  12.354 +options 	VESA_DEBUG
  12.355 +
  12.356 +# The pcvt console driver (vt220 compatible).
  12.357 +device		vt
  12.358 +hint.vt.0.at="isa"
  12.359 +options 	XSERVER			# support for running an X server on vt
  12.360 +options 	FAT_CURSOR		# start with block cursor
  12.361 +# This PCVT option is for keyboards such as those used on really old ThinkPads
  12.362 +options 	PCVT_SCANSET=2
  12.363 +# Other PCVT options are documented in pcvt(4).
  12.364 +options 	PCVT_24LINESDEF
  12.365 +options 	PCVT_CTRL_ALT_DEL
  12.366 +options 	PCVT_META_ESC
  12.367 +options 	PCVT_NSCREENS=9
  12.368 +options 	PCVT_PRETTYSCRNS
  12.369 +options 	PCVT_SCREENSAVER
  12.370 +options 	PCVT_USEKBDSEC
  12.371 +options 	PCVT_VT220KEYB
  12.372 +options 	PCVT_GREENSAVER
  12.373 +
  12.374 +#
  12.375 +# The Numeric Processing eXtension driver.  In addition to this, you
  12.376 +# may configure a math emulator (see above).  If your machine has a
  12.377 +# hardware FPU and the kernel configuration includes the npx device
  12.378 +# *and* a math emulator compiled into the kernel, the hardware FPU
  12.379 +# will be used, unless it is found to be broken or unless "flags" to
  12.380 +# npx0 includes "0x08", which requests preference for the emulator.
  12.381 +device		npx
  12.382 +hint.npx.0.flags="0x0"
  12.383 +hint.npx.0.irq="13"
  12.384 +
  12.385 +#
  12.386 +# `flags' for npx0:
  12.387 +#	0x01	don't use the npx registers to optimize bcopy.
  12.388 +#	0x02	don't use the npx registers to optimize bzero.
  12.389 +#	0x04	don't use the npx registers to optimize copyin or copyout.
  12.390 +#	0x08	use emulator even if hardware FPU is available.
  12.391 +# The npx registers are normally used to optimize copying and zeroing when
  12.392 +# all of the following conditions are satisfied:
  12.393 +#	I586_CPU is an option
  12.394 +#	the cpu is an i586 (perhaps not a Pentium)
  12.395 +#	the probe for npx0 succeeds
  12.396 +#	INT 16 exception handling works.
  12.397 +# Then copying and zeroing using the npx registers is normally 30-100% faster.
  12.398 +# The flags can be used to control cases where it doesn't work or is slower.
  12.399 +# Setting them at boot time using userconfig works right (the optimizations
  12.400 +# are not used until later in the bootstrap when npx0 is attached).
  12.401 +# Flag 0x08 automatically disables the i586 optimized routines.
  12.402 +#
  12.403 +
  12.404 +#
  12.405 +# Optional devices:
  12.406 +#
  12.407 +
  12.408 +# 3Dfx Voodoo Graphics, Voodoo II /dev/3dfx CDEV support. This will create
  12.409 +# the /dev/3dfx0 device to work with glide implementations. This should get
  12.410 +# linked to /dev/3dfx and /dev/voodoo. Note that this is not the same as
  12.411 +# the tdfx DRI module from XFree86 and is completely unrelated.
  12.412 +#
  12.413 +# To enable Linuxulator support, one must also include COMPAT_LINUX in the
  12.414 +# config as well, or you will not have the dependencies. The other option
  12.415 +# is to load both as modules.
  12.416 +
  12.417 +device 		tdfx			# Enable 3Dfx Voodoo support
  12.418 +options 	TDFX_LINUX		# Enable Linuxulator support
  12.419 +
  12.420 +#
  12.421 +# ACPI support using the Intel ACPI Component Architecture reference
  12.422 +# implementation.
  12.423 +#
  12.424 +# ACPI_DEBUG enables the use of the debug.acpi.level and debug.acpi.layer
  12.425 +# kernel environment variables to select initial debugging levels for the
  12.426 +# Intel ACPICA code.  (Note that the Intel code must also have USE_DEBUGGER
  12.427 +# defined when it is built).
  12.428 +#
  12.429 +# ACPI_MAX_THREADS sets the number of task threads started.
  12.430 +#
  12.431 +# ACPI_NO_SEMAPHORES makes the AcpiOs*Semaphore routines a no-op.
  12.432 +#
  12.433 +# ACPICA_PEDANTIC enables strict checking of AML.  Our default is to
  12.434 +# relax these checks to allow code generated by the Microsoft compiler
  12.435 +# to still execute.
  12.436 +#
  12.437 +# Note that building ACPI into the kernel is deprecated; the module is
  12.438 +# normally loaded automatically by the loader.
  12.439 +#
  12.440 +device		acpi
  12.441 +options 	ACPI_DEBUG
  12.442 +options 	ACPI_MAX_THREADS=1
  12.443 +#!options 	ACPI_NO_SEMAPHORES
  12.444 +#!options 	ACPICA_PEDANTIC
  12.445 +
  12.446 +# DRM options:
  12.447 +# mgadrm:    AGP Matrox G200, G400, G450, G550
  12.448 +# r128drm:   ATI Rage 128
  12.449 +# radeondrm: ATI Radeon up to 9000/9100
  12.450 +# sisdrm:    SiS 300/305,540,630
  12.451 +# tdfxdrm:   3dfx Voodoo 3/4/5 and Banshee
  12.452 +# DRM_DEBUG: include debug printfs, very slow
  12.453 +#
  12.454 +# mga requires AGP in the kernel, and it is recommended
  12.455 +# for AGP r128 and radeon cards.
  12.456 +
  12.457 +device		mgadrm
  12.458 +device		"r128drm"
  12.459 +device		radeondrm
  12.460 +device		sisdrm
  12.461 +device		tdfxdrm
  12.462 +
  12.463 +options 	DRM_DEBUG
  12.464 +
  12.465 +# M-systems DiskOnchip products see src/sys/contrib/dev/fla/README
  12.466 +device		fla
  12.467 +hint.fla.0.at="isa"
  12.468 +
  12.469 +#
  12.470 +# mse: Logitech and ATI InPort bus mouse ports
  12.471 +
  12.472 +device		mse
  12.473 +hint.mse.0.at="isa"
  12.474 +hint.mse.0.port="0x23c"
  12.475 +hint.mse.0.irq="5"
  12.476 +
  12.477 +#
  12.478 +# Network interfaces:
  12.479 +#
  12.480 +
  12.481 +# ar:   Arnet SYNC/570i hdlc sync 2/4 port V.35/X.21 serial driver
  12.482 +#       (requires sppp)
  12.483 +# ath:	Atheros a/b/g WiFi adapters (requires ath_hal and wlan)
  12.484 +# cx:   Cronyx/Sigma multiport sync/async (with Cisco or PPP framing)
  12.485 +# ed:   Western Digital and SMC 80xx; Novell NE1000 and NE2000; 3Com 3C503
  12.486 +#       HP PC Lan+, various PC Card devices (refer to etc/defauls/pccard.conf)
  12.487 +#       (requires miibus)
  12.488 +# el:   3Com 3C501 (slow!)
  12.489 +# ie:   AT&T StarLAN 10 and EN100; 3Com 3C507; unknown NI5210;
  12.490 +#       Intel EtherExpress
  12.491 +# le:   Digital Equipment EtherWorks 2 and EtherWorks 3 (DEPCA, DE100,
  12.492 +#       DE101, DE200, DE201, DE202, DE203, DE204, DE205, DE422)
  12.493 +# lnc:  Lance/PCnet cards (Isolan, Novell NE2100, NE32-VL, AMD Am7990 and
  12.494 +#       Am79C960)
  12.495 +# oltr: Olicom ISA token-ring adapters OC-3115, OC-3117, OC-3118 and OC-3133
  12.496 +#       (no hints needed).
  12.497 +#       Olicom PCI token-ring adapters OC-3136, OC-3137, OC-3139, OC-3140,
  12.498 +#       OC-3141, OC-3540, OC-3250
  12.499 +# rdp:  RealTek RTL 8002-based pocket ethernet adapters
  12.500 +# sbni:	Granch SBNI12-xx ISA and PCI adapters
  12.501 +# sr:   RISCom/N2 hdlc sync 1/2 port V.35/X.21 serial driver (requires sppp)
  12.502 +# wl:	Lucent Wavelan (ISA card only).
  12.503 +
  12.504 +# Order for ISA/EISA devices is important here
  12.505 +
  12.506 +device		ar
  12.507 +hint.ar.0.at="isa"
  12.508 +hint.ar.0.port="0x300"
  12.509 +hint.ar.0.irq="10"
  12.510 +hint.ar.0.maddr="0xd0000"
  12.511 +device		cx
  12.512 +hint.cx.0.at="isa"
  12.513 +hint.cx.0.port="0x240"
  12.514 +hint.cx.0.irq="15"
  12.515 +hint.cx.0.drq="7"
  12.516 +device		ed
  12.517 +#options 	ED_NO_MIIBUS		# Disable ed miibus support
  12.518 +hint.ed.0.at="isa"
  12.519 +hint.ed.0.port="0x280"
  12.520 +hint.ed.0.irq="5"
  12.521 +hint.ed.0.maddr="0xd8000"
  12.522 +device		el	1
  12.523 +hint.el.0.at="isa"
  12.524 +hint.el.0.port="0x300"
  12.525 +hint.el.0.irq="9"
  12.526 +device		ie			# Hints only required for Starlan
  12.527 +hint.ie.2.at="isa"
  12.528 +hint.ie.2.port="0x300"
  12.529 +hint.ie.2.irq="5"
  12.530 +hint.ie.2.maddr="0xd0000"
  12.531 +device		le	1
  12.532 +hint.le.0.at="isa"
  12.533 +hint.le.0.port="0x300"
  12.534 +hint.le.0.irq="5"
  12.535 +hint.le.0.maddr="0xd0000"
  12.536 +device		lnc
  12.537 +hint.lnc.0.at="isa"
  12.538 +hint.lnc.0.port="0x280"
  12.539 +hint.lnc.0.irq="10"
  12.540 +hint.lnc.0.drq="0"
  12.541 +device		rdp	1
  12.542 +hint.rdp.0.at="isa"
  12.543 +hint.rdp.0.port="0x378"
  12.544 +hint.rdp.0.irq="7"
  12.545 +hint.rdp.0.flags="2"
  12.546 +device		sbni
  12.547 +hint.sbni.0.at="isa"
  12.548 +hint.sbni.0.port="0x210"
  12.549 +hint.sbni.0.irq="0xefdead"
  12.550 +hint.sbni.0.flags="0"
  12.551 +device		sr
  12.552 +hint.sr.0.at="isa"
  12.553 +hint.sr.0.port="0x300"
  12.554 +hint.sr.0.irq="5"
  12.555 +hint.sr.0.maddr="0xd0000"
  12.556 +device		oltr
  12.557 +hint.oltr.0.at="isa"
  12.558 +device		wl
  12.559 +hint.wl.0.at="isa"
  12.560 +hint.wl.0.port="0x300"
  12.561 +options 	WLCACHE		# enables the signal-strength cache
  12.562 +options 	WLDEBUG		# enables verbose debugging output
  12.563 +
  12.564 +device		ath
  12.565 +device		ath_hal		# Atheros HAL (includes binary component)
  12.566 +#device		wlan		# 802.11 layer
  12.567 +
  12.568 +#
  12.569 +# ATA raid adapters
  12.570 +#
  12.571 +device		pst
  12.572 +
  12.573 +# 
  12.574 +# SCSI host adapters:
  12.575 +# 
  12.576 +# ncv: NCR 53C500 based SCSI host adapters.
  12.577 +# nsp: Workbit Ninja SCSI-3 based PC Card SCSI host adapters.
  12.578 +# stg: TMC 18C30, 18C50 based SCSI host adapters.
  12.579 +
  12.580 +device          ncv
  12.581 +device          nsp
  12.582 +device          stg
  12.583 +hint.stg.0.at="isa"
  12.584 +hint.stg.0.port="0x140"
  12.585 +hint.stg.0.port="11"
  12.586 +
  12.587 +#
  12.588 +# Adaptec FSA RAID controllers, including integrated DELL controllers,
  12.589 +# the Dell PERC 2/QC and the HP NetRAID-4M
  12.590 +device		aac
  12.591 +device		aacp	# SCSI Passthrough interface (optional, CAM required)
  12.592 +
  12.593 +#
  12.594 +# IBM (now Adaptec) ServeRAID controllers
  12.595 +device		ips
  12.596 +
  12.597 +#
  12.598 +# SafeNet crypto driver: can be moved to the MI NOTES as soon as
  12.599 +# it's tested on a big-endian machine
  12.600 +#
  12.601 +device		safe		# SafeNet 1141
  12.602 +options		SAFE_DEBUG	# enable debugging support: hw.safe.debug
  12.603 +options		SAFE_RNDTEST	# enable rndtest support
  12.604 +
  12.605 +#####################################################################
  12.606 +
  12.607 +#
  12.608 +# Miscellaneous hardware:
  12.609 +#
  12.610 +# wt: Wangtek and Archive QIC-02/QIC-36 tape drives
  12.611 +# ctx: Cortex-I frame grabber
  12.612 +# apm: Laptop Advanced Power Management (experimental)
  12.613 +# pmtimer: Timer device driver for power management events (APM or ACPI)
  12.614 +# spigot: The Creative Labs Video Spigot video-acquisition board
  12.615 +# dgb: Digiboard PC/Xi and PC/Xe series driver (ALPHA QUALITY!)
  12.616 +# digi: Digiboard driver
  12.617 +# gp:  National Instruments AT-GPIB and AT-GPIB/TNT board, PCMCIA-GPIB
  12.618 +# asc: GI1904-based hand scanners, e.g. the Trust Amiscan Grey
  12.619 +# gsc: Genius GS-4500 hand scanner.
  12.620 +# spic: Sony Programmable I/O controller (VAIO notebooks)
  12.621 +# stl: Stallion EasyIO and EasyConnection 8/32 (cd1400 based)
  12.622 +# stli: Stallion EasyConnection 8/64, ONboard, Brumby (intelligent)
  12.623 +
  12.624 +# Notes on APM
  12.625 +#  The flags takes the following meaning for apm0:
  12.626 +#    0x0020  Statclock is broken.
  12.627 +#  If apm is omitted, some systems require sysctl kern.timecounter.method=1
  12.628 +#  for correct timekeeping.
  12.629 +
  12.630 +# Notes on the spigot:
  12.631 +#  The video spigot is at 0xad6.  This port address can not be changed.
  12.632 +#  The irq values may only be 10, 11, or 15
  12.633 +#  I/O memory is an 8kb region.  Possible values are:
  12.634 +#    0a0000, 0a2000, ..., 0fffff, f00000, f02000, ..., ffffff
  12.635 +#    The start address must be on an even boundary.
  12.636 +#  Add the following option if you want to allow non-root users to be able
  12.637 +#  to access the spigot.  This option is not secure because it allows users
  12.638 +#  direct access to the I/O page.
  12.639 +#  	options SPIGOT_UNSECURE
  12.640 +
  12.641 +# Notes on the Specialix SI/XIO driver:
  12.642 +#  The host card is memory, not IO mapped.
  12.643 +#  The Rev 1 host cards use a 64K chunk, on a 32K boundary.
  12.644 +#  The Rev 2 host cards use a 32K chunk, on a 32K boundary.
  12.645 +#  The cards can use an IRQ of 11, 12 or 15.
  12.646 +
  12.647 +# Notes on the Sony Programmable I/O controller
  12.648 +#  This is a temporary driver that should someday be replaced by something
  12.649 +#  that hooks into the ACPI layer. The device is hooked to the PIIX4's
  12.650 +#  General Device 10 decoder, which means you have to fiddle with PCI
  12.651 +#  registers to map it in, even though it is otherwise treated here as
  12.652 +#  an ISA device. At the moment, the driver polls, although the device
  12.653 +#  is capable of generating interrupts. It largely undocumented.
  12.654 +#  The port location in the hint is where you WANT the device to be
  12.655 +#  mapped. 0x10a0 seems to be traditional. At the moment the jogdial
  12.656 +#  is the only thing truly supported, but aparently a fair percentage
  12.657 +#  of the Vaio extra features are controlled by this device.
  12.658 +
  12.659 +# Notes on the Stallion stl and stli drivers:
  12.660 +#  See src/i386/isa/README.stl for complete instructions.
  12.661 +#  This is version 0.0.5alpha, unsupported by Stallion.
  12.662 +#  The stl driver has a secondary IO port hard coded at 0x280.  You need
  12.663 +#     to change src/i386/isa/stallion.c if you reconfigure this on the boards.
  12.664 +#  The "flags" and "msize" settings on the stli driver depend on the board:
  12.665 +#	EasyConnection 8/64 ISA:     flags 23         msize 0x1000
  12.666 +#	EasyConnection 8/64 EISA:    flags 24         msize 0x10000
  12.667 +#	EasyConnection 8/64 MCA:     flags 25         msize 0x1000
  12.668 +#	ONboard ISA:                 flags 4          msize 0x10000
  12.669 +#	ONboard EISA:                flags 7          msize 0x10000
  12.670 +#	ONboard MCA:                 flags 3          msize 0x10000
  12.671 +#	Brumby:                      flags 2          msize 0x4000
  12.672 +#	Stallion:                    flags 1          msize 0x10000
  12.673 +
  12.674 +# Notes on the Digiboard PC/Xi and PC/Xe series driver
  12.675 +#               
  12.676 +# The NDGBPORTS option specifies the number of ports controlled by the
  12.677 +# dgb(4) driver.  The default value is 16 ports per device.
  12.678 +#
  12.679 +# The following flag values have special meanings in dgb:
  12.680 +#	0x01 - alternate layout of pins
  12.681 +#	0x02 - use the windowed PC/Xe in 64K mode
  12.682 +
  12.683 +device		wt	1
  12.684 +hint.wt.0.at="isa"
  12.685 +hint.wt.0.port="0x300"
  12.686 +hint.wt.0.irq="5"
  12.687 +hint.wt.0.drq="1"
  12.688 +device		ctx
  12.689 +hint.ctx.0.at="isa"
  12.690 +hint.ctx.0.port="0x230"
  12.691 +hint.ctx.0.maddr="0xd0000"
  12.692 +device		spigot	1
  12.693 +hint.spigot.0.at="isa"
  12.694 +hint.spigot.0.port="0xad6"
  12.695 +hint.spigot.0.irq="15"
  12.696 +hint.spigot.0.maddr="0xee000"
  12.697 +device		apm
  12.698 +hint.apm.0.flags="0x20"
  12.699 +device		pmtimer			# Adjust system timer at wakeup time
  12.700 +device		gp
  12.701 +hint.gp.0.at="isa"
  12.702 +hint.gp.0.port="0x2c0"
  12.703 +device		gsc	1
  12.704 +hint.gsc.0.at="isa"
  12.705 +hint.gsc.0.port="0x270"
  12.706 +hint.gsc.0.drq="3"
  12.707 +device		dgb	  1
  12.708 +options		NDGBPORTS=17
  12.709 +hint.dgb.0.at="isa"
  12.710 +hint.dgb.0.port="0x220"
  12.711 +hint.dgb.0.maddr="0xfc000"
  12.712 +device		digi
  12.713 +hint.digi.0.at="isa"
  12.714 +hint.digi.0.port="0x104"
  12.715 +hint.digi.0.maddr="0xd0000"
  12.716 +# BIOS & FEP/OS components of device digi.
  12.717 +device		digi_CX
  12.718 +device		digi_CX_PCI
  12.719 +device		digi_EPCX
  12.720 +device		digi_EPCX_PCI
  12.721 +device		digi_Xe
  12.722 +device		digi_Xem
  12.723 +device		digi_Xr
  12.724 +device		asc	1
  12.725 +hint.asc.0.at="isa"
  12.726 +hint.asc.0.port="0x3EB"
  12.727 +hint.asc.0.drq="3"
  12.728 +hint.asc.0.irq="10"
  12.729 +device		spic
  12.730 +hint.spic.0.at="isa"
  12.731 +hint.spic.0.port="0x10a0"
  12.732 +device		stl
  12.733 +hint.stl.0.at="isa"
  12.734 +hint.stl.0.port="0x2a0"
  12.735 +hint.stl.0.irq="10"
  12.736 +device		stli
  12.737 +hint.stli.0.at="isa"
  12.738 +hint.stli.0.port="0x2a0"
  12.739 +hint.stli.0.maddr="0xcc000"
  12.740 +hint.stli.0.flags="23"
  12.741 +hint.stli.0.msize="0x1000"
  12.742 +# You are unlikely to have the hardware for loran <phk@FreeBSD.org>
  12.743 +device		loran
  12.744 +hint.loran.0.at="isa"
  12.745 +hint.loran.0.irq="5"
  12.746 +# HOT1 Xilinx 6200 card (http://www.vcc.com/)
  12.747 +device		xrpu
  12.748 +
  12.749 +#
  12.750 +# Laptop/Notebook options:
  12.751 +#
  12.752 +# See also:
  12.753 +#  apm under `Miscellaneous hardware'
  12.754 +# above.
  12.755 +
  12.756 +# For older notebooks that signal a powerfail condition (external
  12.757 +# power supply dropped, or battery state low) by issuing an NMI:
  12.758 +
  12.759 +options 	POWERFAIL_NMI	# make it beep instead of panicing
  12.760 +
  12.761 +#
  12.762 +# I2C Bus
  12.763 +#
  12.764 +# Philips i2c bus support is provided by the `iicbus' device.
  12.765 +#
  12.766 +# Supported interfaces:
  12.767 +# pcf	Philips PCF8584 ISA-bus controller
  12.768 +#
  12.769 +device		pcf
  12.770 +hint.pcf.0.at="isa"
  12.771 +hint.pcf.0.port="0x320"
  12.772 +hint.pcf.0.irq="5"
  12.773 +
  12.774 +#---------------------------------------------------------------------------
  12.775 +# ISDN4BSD
  12.776 +#
  12.777 +# See /usr/share/examples/isdn/ROADMAP for an introduction to isdn4bsd.
  12.778 +#
  12.779 +# i4b passive ISDN cards support contains the following hardware drivers:
  12.780 +#
  12.781 +#	isic  - Siemens/Infineon ISDN ISAC/HSCX/IPAC chipset driver
  12.782 +#	iwic  - Winbond W6692 PCI bus ISDN S/T interface controller
  12.783 +#	ifpi  - AVM Fritz!Card PCI driver
  12.784 +#	ifpi2  - AVM Fritz!Card PCI version 2 driver
  12.785 +#	ihfc  - Cologne Chip HFC ISA/ISA-PnP chipset driver
  12.786 +#	ifpnp - AVM Fritz!Card PnP driver 
  12.787 +#	itjc  - Siemens ISAC / TJNet Tiger300/320 chipset
  12.788 +#
  12.789 +# i4b active ISDN cards support contains the following hardware drivers:
  12.790 +#
  12.791 +#	iavc  - AVM B1 PCI, AVM B1 ISA, AVM T1
  12.792 +#
  12.793 +# Note that the ``options'' (if given) and ``device'' lines must BOTH
  12.794 +# be uncommented to enable support for a given card !
  12.795 +#
  12.796 +# In addition to a hardware driver (and probably an option) the mandatory
  12.797 +# ISDN protocol stack devices and the mandatory support device must be 
  12.798 +# enabled as well as one or more devices from the optional devices section.
  12.799 +#
  12.800 +#---------------------------------------------------------------------------
  12.801 +#	isic driver (Siemens/Infineon chipsets)
  12.802 +#
  12.803 +device	isic
  12.804 +#
  12.805 +# ISA bus non-PnP Cards:
  12.806 +# ----------------------
  12.807 +#
  12.808 +# Teles S0/8 or Niccy 1008
  12.809 +options 	TEL_S0_8
  12.810 +hint.isic.0.at="isa"
  12.811 +hint.isic.0.maddr="0xd0000"
  12.812 +hint.isic.0.irq="5"
  12.813 +hint.isic.0.flags="1"
  12.814 +#
  12.815 +# Teles S0/16 or Creatix ISDN-S0 or Niccy 1016
  12.816 +options 	TEL_S0_16
  12.817 +hint.isic.0.at="isa"
  12.818 +hint.isic.0.port="0xd80"
  12.819 +hint.isic.0.maddr="0xd0000"
  12.820 +hint.isic.0.irq="5"
  12.821 +hint.isic.0.flags="2"
  12.822 +#
  12.823 +# Teles S0/16.3
  12.824 +options 	TEL_S0_16_3
  12.825 +hint.isic.0.at="isa"
  12.826 +hint.isic.0.port="0xd80"
  12.827 +hint.isic.0.irq="5"
  12.828 +hint.isic.0.flags="3"
  12.829 +#
  12.830 +# AVM A1 or AVM Fritz!Card
  12.831 +options 	AVM_A1
  12.832 +hint.isic.0.at="isa"
  12.833 +hint.isic.0.port="0x340"
  12.834 +hint.isic.0.irq="5"
  12.835 +hint.isic.0.flags="4"
  12.836 +#
  12.837 +# USRobotics Sportster ISDN TA intern
  12.838 +options 	USR_STI
  12.839 +hint.isic.0.at="isa"
  12.840 +hint.isic.0.port="0x268"
  12.841 +hint.isic.0.irq="5"
  12.842 +hint.isic.0.flags="7"
  12.843 +#
  12.844 +# ITK ix1 Micro ( < V.3, non-PnP version )
  12.845 +options 	ITKIX1
  12.846 +hint.isic.0.at="isa"
  12.847 +hint.isic.0.port="0x398"
  12.848 +hint.isic.0.irq="10"
  12.849 +hint.isic.0.flags="18"
  12.850 +#
  12.851 +# ELSA PCC-16
  12.852 +options 	ELSA_PCC16
  12.853 +hint.isic.0.at="isa"
  12.854 +hint.isic.0.port="0x360"
  12.855 +hint.isic.0.irq="10"
  12.856 +hint.isic.0.flags="20"
  12.857 +#
  12.858 +# ISA bus PnP Cards:
  12.859 +# ------------------
  12.860 +#
  12.861 +# Teles S0/16.3 PnP
  12.862 +options 	TEL_S0_16_3_P
  12.863 +#
  12.864 +# Creatix ISDN-S0 P&P
  12.865 +options 	CRTX_S0_P
  12.866 +#
  12.867 +# Dr. Neuhaus Niccy Go@
  12.868 +options 	DRN_NGO
  12.869 +#
  12.870 +# Sedlbauer Win Speed
  12.871 +options 	SEDLBAUER
  12.872 +#
  12.873 +# Dynalink IS64PH
  12.874 +options 	DYNALINK 
  12.875 +#
  12.876 +# ELSA QuickStep 1000pro ISA
  12.877 +options 	ELSA_QS1ISA
  12.878 +#
  12.879 +# Siemens I-Surf 2.0
  12.880 +options 	SIEMENS_ISURF2
  12.881 +#
  12.882 +# Asuscom ISDNlink 128K ISA
  12.883 +options 	ASUSCOM_IPAC
  12.884 +#
  12.885 +# Eicon Diehl DIVA 2.0 and 2.02
  12.886 +options 	EICON_DIVA
  12.887 +#
  12.888 +# Compaq Microcom 610 ISDN card (Compaq series PSB2222I)
  12.889 +options 	COMPAQ_M610
  12.890 +#
  12.891 +# PCI bus Cards:
  12.892 +# --------------
  12.893 +#
  12.894 +# Cyclades Cyclom-Y PCI serial driver
  12.895 +device		cy	1
  12.896 +options 	CY_PCI_FASTINTR		# Use with cy_pci unless irq is shared
  12.897 +hint.cy.0.at="isa"
  12.898 +hint.cy.0.irq="10"
  12.899 +hint.cy.0.maddr="0xd4000"
  12.900 +hint.cy.0.msize="0x2000"
  12.901 +#
  12.902 +#---------------------------------------------------------------------------
  12.903 +# ELSA MicroLink ISDN/PCI (same as ELSA QuickStep 1000pro PCI)
  12.904 +options 	ELSA_QS1PCI
  12.905 +#
  12.906 +#
  12.907 +#---------------------------------------------------------------------------
  12.908 +#	ifpnp driver for AVM Fritz!Card PnP
  12.909 +#
  12.910 +# AVM Fritz!Card PnP
  12.911 +device ifpnp
  12.912 +#
  12.913 +#---------------------------------------------------------------------------
  12.914 +#	ihfc driver for Cologne Chip ISA chipsets (experimental!)
  12.915 +#
  12.916 +# Teles 16.3c ISA PnP
  12.917 +# AcerISDN P10 ISA PnP
  12.918 +# TELEINT ISDN SPEED No.1
  12.919 +device ihfc
  12.920 +#
  12.921 +#---------------------------------------------------------------------------
  12.922 +#	ifpi driver for AVM Fritz!Card PCI
  12.923 +#
  12.924 +# AVM Fritz!Card PCI
  12.925 +device  ifpi
  12.926 +#
  12.927 +#---------------------------------------------------------------------------
  12.928 +#	ifpi2 driver for AVM Fritz!Card PCI version 2
  12.929 +#
  12.930 +# AVM Fritz!Card PCI version 2
  12.931 +device  "ifpi2"
  12.932 +#
  12.933 +#---------------------------------------------------------------------------
  12.934 +#	iwic driver for Winbond W6692 chipset
  12.935 +#
  12.936 +# ASUSCOM P-IN100-ST-D (and other Winbond W6692 based cards)
  12.937 +device  iwic
  12.938 +#
  12.939 +#---------------------------------------------------------------------------
  12.940 +#	itjc driver for Simens ISAC / TJNet Tiger300/320 chipset
  12.941 +#
  12.942 +# Traverse Technologies NETjet-S
  12.943 +# Teles PCI-TJ
  12.944 +device  itjc
  12.945 +#
  12.946 +#---------------------------------------------------------------------------
  12.947 +#	iavc driver (AVM active cards, needs i4bcapi driver!)
  12.948 +#
  12.949 +device	iavc
  12.950 +#
  12.951 +# AVM B1 ISA bus (PnP mode not supported!)
  12.952 +# ----------------------------------------
  12.953 +hint.iavc.0.at="isa"
  12.954 +hint.iavc.0.port="0x150"
  12.955 +hint.iavc.0.irq="5"
  12.956 +#
  12.957 +#---------------------------------------------------------------------------
  12.958 +#	ISDN Protocol Stack - mandatory for all hardware drivers
  12.959 +#
  12.960 +# Q.921 / layer 2 - i4b passive cards D channel handling
  12.961 +device		"i4bq921"
  12.962 +#
  12.963 +# Q.931 / layer 3 - i4b passive cards D channel handling
  12.964 +device		"i4bq931"
  12.965 +#
  12.966 +# layer 4 - i4b common passive and active card handling
  12.967 +device		"i4b"
  12.968 +#
  12.969 +#---------------------------------------------------------------------------
  12.970 +#	ISDN devices - mandatory for all hardware drivers
  12.971 +#
  12.972 +# userland driver to do ISDN tracing (for passive cards only)
  12.973 +device		"i4btrc"	4
  12.974 +#
  12.975 +# userland driver to control the whole thing
  12.976 +device		"i4bctl"
  12.977 +#
  12.978 +#---------------------------------------------------------------------------
  12.979 +#	ISDN devices - optional
  12.980 +#
  12.981 +# userland driver for access to raw B channel
  12.982 +device		"i4brbch"	4
  12.983 +#
  12.984 +# userland driver for telephony
  12.985 +device		"i4btel"	2
  12.986 +#
  12.987 +# network driver for IP over raw HDLC ISDN
  12.988 +device		"i4bipr"	4
  12.989 +# enable VJ header compression detection for ipr i/f
  12.990 +options 	IPR_VJ
  12.991 +# enable logging of the first n IP packets to isdnd (n=32 here)
  12.992 +options 	IPR_LOG=32
  12.993 +#
  12.994 +# network driver for sync PPP over ISDN; requires an equivalent
  12.995 +# number of sppp device to be configured
  12.996 +device		"i4bisppp"	4
  12.997 +#
  12.998 +# B-channel interface to the netgraph subsystem
  12.999 +device		"i4bing"	2
 12.1000 +#
 12.1001 +# CAPI driver needed for active ISDN cards (see iavc driver above)
 12.1002 +device		"i4bcapi"
 12.1003 +#
 12.1004 +#---------------------------------------------------------------------------
 12.1005 +
 12.1006 +#
 12.1007 +# Set the number of PV entries per process.  Increasing this can
 12.1008 +# stop panics related to heavy use of shared memory. However, that can
 12.1009 +# (combined with large amounts of physical memory) cause panics at
 12.1010 +# boot time due the kernel running out of VM space.
 12.1011 +#
 12.1012 +# If you're tweaking this, you might also want to increase the sysctls
 12.1013 +# "vm.v_free_min", "vm.v_free_reserved", and "vm.v_free_target".
 12.1014 +#
 12.1015 +# The value below is the one more than the default.
 12.1016 +#
 12.1017 +options 	PMAP_SHPGPERPROC=201
 12.1018 +
 12.1019 +#
 12.1020 +# Change the size of the kernel virtual address space.  Due to
 12.1021 +# constraints in loader(8) on i386, this must be a multiple of 4.
 12.1022 +# 256 = 1 GB of kernel address space.  Increasing this also causes
 12.1023 +# a reduction of the address space in user processes.  512 splits
 12.1024 +# the 4GB cpu address space in half (2GB user, 2GB kernel).
 12.1025 +#
 12.1026 +options 	KVA_PAGES=260
 12.1027 +
 12.1028 +
 12.1029 +#####################################################################
 12.1030 +# ABI Emulation
 12.1031 +
 12.1032 +# Enable iBCS2 runtime support for SCO and ISC binaries
 12.1033 +options 	IBCS2
 12.1034 +
 12.1035 +# Emulate spx device for client side of SVR3 local X interface
 12.1036 +options 	SPX_HACK
 12.1037 +
 12.1038 +# Enable Linux ABI emulation
 12.1039 +options 	COMPAT_LINUX
 12.1040 +
 12.1041 +# Enable i386 a.out binary support
 12.1042 +options 	COMPAT_AOUT
 12.1043 +
 12.1044 +# Enable the linux-like proc filesystem support (requires COMPAT_LINUX
 12.1045 +# and PSEUDOFS)
 12.1046 +options 	LINPROCFS
 12.1047 +
 12.1048 +#
 12.1049 +# SysVR4 ABI emulation
 12.1050 +#
 12.1051 +# The svr4 ABI emulator can be statically compiled into the kernel or loaded as
 12.1052 +# a KLD module.  
 12.1053 +# The STREAMS network emulation code can also be compiled statically or as a 
 12.1054 +# module.  If loaded as a module, it must be loaded before the svr4 module
 12.1055 +# (the /usr/sbin/svr4 script does this for you).  If compiling statically,
 12.1056 +# the `streams' device must be configured into any kernel which also
 12.1057 +# specifies COMPAT_SVR4.  It is possible to have a statically-configured 
 12.1058 +# STREAMS device and a dynamically loadable svr4 emulator;  the /usr/sbin/svr4
 12.1059 +# script understands that it doesn't need to load the `streams' module under
 12.1060 +# those circumstances.
 12.1061 +# Caveat:  At this time, `options KTRACE' is required for the svr4 emulator
 12.1062 +# (whether static or dynamic).  
 12.1063 +# 
 12.1064 +options 	COMPAT_SVR4	# build emulator statically
 12.1065 +options 	DEBUG_SVR4	# enable verbose debugging
 12.1066 +device		streams		# STREAMS network driver (required for svr4).
 12.1067 +
 12.1068 +
 12.1069 +#####################################################################
 12.1070 +# VM OPTIONS
 12.1071 +
 12.1072 +# Disable the 4 MByte page PSE CPU feature.  The PSE feature allows the
 12.1073 +# kernel to use a 4 MByte pages to map the kernel instead of 4k pages.
 12.1074 +# This saves on the amount of memory needed for page tables needed to
 12.1075 +# map the kernel.  You should only disable this feature as a temporary
 12.1076 +# workaround if you are having problems with it enabled.
 12.1077 +#
 12.1078 +#options 	DISABLE_PSE
 12.1079 +
 12.1080 +# Disable the global pages PGE CPU feature.  The PGE feature allows pages
 12.1081 +# to be marked with the PG_G bit.  TLB entries for these pages are not
 12.1082 +# flushed from the cache when %cr3 is reloaded.  This can make context
 12.1083 +# switches less expensive.  You should only disable this feature as a
 12.1084 +# temporary workaround if you are having problems with it enabled.
 12.1085 +#
 12.1086 +#options 	DISABLE_PG_G
 12.1087 +
 12.1088 +# KSTACK_PAGES is the number of memory pages to assign to the kernel
 12.1089 +# stack of each thread.
 12.1090 +
 12.1091 +options 	KSTACK_PAGES=3
 12.1092 +
 12.1093 +#####################################################################
 12.1094 +
 12.1095 +# More undocumented options for linting.
 12.1096 +# Note that documenting these are not considered an affront.
 12.1097 +
 12.1098 +options 	FB_INSTALL_CDEV		# install a CDEV entry in /dev
 12.1099 +
 12.1100 +# PECOFF module (Win32 Execution Format)
 12.1101 +options 	PECOFF_SUPPORT
 12.1102 +options 	PECOFF_DEBUG
 12.1103 +
 12.1104 +options 	ENABLE_ALART
 12.1105 +options 	I4B_SMP_WORKAROUND
 12.1106 +options 	I586_PMC_GUPROF=0x70000
 12.1107 +options 	KBDIO_DEBUG=2
 12.1108 +options 	KBD_MAXRETRY=4
 12.1109 +options 	KBD_MAXWAIT=6
 12.1110 +options 	KBD_RESETDELAY=201
 12.1111 +
 12.1112 +options 	PSM_DEBUG=1
 12.1113 +
 12.1114 +options 	TIMER_FREQ=((14318182+6)/12)
 12.1115 +
 12.1116 +options 	VM_KMEM_SIZE
 12.1117 +options 	VM_KMEM_SIZE_MAX
 12.1118 +options 	VM_KMEM_SIZE_SCALE
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/OLDCARD	Mon Mar 21 07:58:08 2005 +0000
    13.3 @@ -0,0 +1,17 @@
    13.4 +#
    13.5 +# OLDCARD -- Generic kernel configuration file for FreeBSD/i386
    13.6 +#            using the OLDCARD pccard system.
    13.7 +#
    13.8 +# $FreeBSD: src/sys/i386/conf/OLDCARD,v 1.18 2003/02/15 02:39:13 ru Exp $
    13.9 +
   13.10 +include GENERIC
   13.11 +
   13.12 +ident		OLDCARD
   13.13 +
   13.14 +# PCCARD (PCMCIA) support
   13.15 +nodevice	cbb		# cardbus (yenta) bridge
   13.16 +#nodevice	pcic		# ExCA ISA and PCI bridges
   13.17 +nodevice	pccard		# PC Card (16-bit) bus
   13.18 +nodevice	cardbus		# CardBus (32-bit) bus
   13.19 +device		card	1	# pccard bus
   13.20 +device		pcic		# PCMCIA bridge
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/PAE	Mon Mar 21 07:58:08 2005 +0000
    14.3 @@ -0,0 +1,99 @@
    14.4 +#
    14.5 +# PAE -- Generic kernel configuration file for FreeBSD/i386 PAE
    14.6 +#
    14.7 +# $FreeBSD: src/sys/i386/conf/PAE,v 1.8 2003/11/03 22:49:19 jhb Exp $
    14.8 +
    14.9 +include GENERIC
   14.10 +
   14.11 +ident		PAE-GENERIC
   14.12 +
   14.13 +# To make a PAE kernel, the next option is needed
   14.14 +options		PAE			# Physical Address Extensions Kernel
   14.15 +
   14.16 +# Compile acpi in statically since the module isn't built properly.  Most
   14.17 +# machines which support large amounts of memory require acpi.
   14.18 +device		acpi
   14.19 +
   14.20 +# Don't build modules with this kernel config, since they are not built with
   14.21 +# the correct options headers.
   14.22 +makeoptions	NO_MODULES=yes
   14.23 +
   14.24 +# What follows is a list of drivers that are normally in GENERIC, but either
   14.25 +# don't work or are untested with PAE.  Be very careful before enabling any
   14.26 +# of these drivers.  Drivers which use DMA and don't handle 64 bit physical
   14.27 +# address properly may cause data corruption when used in a machine with more
   14.28 +# than 4 gigabytes of memory.
   14.29 +
   14.30 +nodevice	ahb
   14.31 +nodevice	amd
   14.32 +nodevice	isp
   14.33 +nodevice	sym
   14.34 +nodevice	trm
   14.35 +
   14.36 +nodevice	adv
   14.37 +nodevice	adw
   14.38 +nodevice	aha
   14.39 +nodevice	aic
   14.40 +nodevice	bt
   14.41 +
   14.42 +nodevice	ncv
   14.43 +nodevice	nsp
   14.44 +nodevice	stg
   14.45 +
   14.46 +nodevice	asr
   14.47 +nodevice	dpt
   14.48 +nodevice	iir
   14.49 +nodevice	mly
   14.50 +
   14.51 +nodevice	amr
   14.52 +nodevice	ida
   14.53 +nodevice	mlx
   14.54 +nodevice	pst
   14.55 +
   14.56 +nodevice	agp
   14.57 +
   14.58 +nodevice	de
   14.59 +nodevice	txp
   14.60 +nodevice	vx
   14.61 +
   14.62 +nodevice	dc
   14.63 +nodevice	pcn
   14.64 +nodevice	rl
   14.65 +nodevice	sf
   14.66 +nodevice	sis
   14.67 +nodevice	ste
   14.68 +nodevice	tl
   14.69 +nodevice	tx
   14.70 +nodevice	vr
   14.71 +nodevice	wb
   14.72 +
   14.73 +nodevice	cs
   14.74 +nodevice	ed
   14.75 +nodevice	ex
   14.76 +nodevice	ep
   14.77 +nodevice	fe
   14.78 +nodevice	ie
   14.79 +nodevice	lnc
   14.80 +nodevice	sn
   14.81 +nodevice	xe
   14.82 +
   14.83 +nodevice	wlan
   14.84 +nodevice	an
   14.85 +nodevice	awi
   14.86 +nodevice	wi
   14.87 +
   14.88 +nodevice	uhci
   14.89 +nodevice	ohci
   14.90 +nodevice	usb
   14.91 +nodevice	ugen
   14.92 +nodevice	uhid
   14.93 +nodevice	ukbd
   14.94 +nodevice	ulpt
   14.95 +nodevice	umass
   14.96 +nodevice	ums
   14.97 +nodevice	urio
   14.98 +nodevice	uscanner
   14.99 +nodevice	aue
  14.100 +nodevice	axe
  14.101 +nodevice	cue
  14.102 +nodevice	kue
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/XENCONF	Mon Mar 21 07:58:08 2005 +0000
    15.3 @@ -0,0 +1,137 @@
    15.4 +#
    15.5 +# GENERIC -- Generic kernel configuration file for FreeBSD/i386
    15.6 +#
    15.7 +# For more information on this file, please read the handbook section on
    15.8 +# Kernel Configuration Files:
    15.9 +#
   15.10 +#    http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
   15.11 +#
   15.12 +# The handbook is also available locally in /usr/share/doc/handbook
   15.13 +# if you've installed the doc distribution, otherwise always see the
   15.14 +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
   15.15 +# latest information.
   15.16 +#
   15.17 +# An exhaustive list of options and more detailed explanations of the
   15.18 +# device lines is also present in the ../../conf/NOTES and NOTES files. 
   15.19 +# If you are in doubt as to the purpose or necessity of a line, check first 
   15.20 +# in NOTES.
   15.21 +#
   15.22 +# $FreeBSD: src/sys/i386/conf/GENERIC,v 1.394.2.3 2004/01/26 19:42:11 nectar Exp $
   15.23 +
   15.24 +machine		i386-xen
   15.25 +cpu		I686_CPU
   15.26 +ident		XEN
   15.27 +
   15.28 +#To statically compile in device wiring instead of /boot/device.hints
   15.29 +#hints		"GENERIC.hints"		#Default places to look for devices.
   15.30 +
   15.31 +makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
   15.32 +
   15.33 +options 	SCHED_4BSD		#4BSD scheduler
   15.34 +options 	INET			#InterNETworking
   15.35 +options 	INET6			#IPv6 communications protocols
   15.36 +options 	FFS			#Berkeley Fast Filesystem
   15.37 +options 	SOFTUPDATES		#Enable FFS soft updates support
   15.38 +options 	UFS_ACL			#Support for access control lists
   15.39 +options 	UFS_DIRHASH		#Improve performance on big directories
   15.40 +options 	MD_ROOT			#MD is a potential root device
   15.41 +options 	NFSCLIENT		#Network Filesystem Client
   15.42 +options 	NFSSERVER		#Network Filesystem Server
   15.43 +# options 	NFS_ROOT		#NFS usable as /, requires NFSCLIENT
   15.44 +#options 	MSDOSFS			#MSDOS Filesystem
   15.45 +#options 	CD9660			#ISO 9660 Filesystem
   15.46 +options 	PROCFS			#Process filesystem (requires PSEUDOFS)
   15.47 +options 	PSEUDOFS		#Pseudo-filesystem framework
   15.48 +options 	COMPAT_43		#Compatible with BSD 4.3 [KEEP THIS!]
   15.49 +options 	COMPAT_FREEBSD4		#Compatible with FreeBSD4
   15.50 +options 	SCSI_DELAY=15000	#Delay (in ms) before probing SCSI
   15.51 +options 	KTRACE			#ktrace(1) support
   15.52 +options 	SYSVSHM			#SYSV-style shared memory
   15.53 +options 	SYSVMSG			#SYSV-style message queues
   15.54 +options 	SYSVSEM			#SYSV-style semaphores
   15.55 +options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
   15.56 +options 	KBD_INSTALL_CDEV	# install a CDEV entry in /dev
   15.57 +options		CPU_DISABLE_SSE		# don't turn on SSE framework with Xen
   15.58 +#options 	PFIL_HOOKS		# pfil(9) framework
   15.59 +
   15.60 +# Debugging for use in -current
   15.61 +options 	KDB			#Enable the kernel debugger
   15.62 +options 	INVARIANTS		#Enable calls of extra sanity checking
   15.63 +options 	INVARIANT_SUPPORT	#Extra sanity checks of internal structures, required by INVARIANTS
   15.64 +#options 	WITNESS			#Enable checks to detect deadlocks and cycles
   15.65 +#options 	WITNESS_SKIPSPIN	#Don't run witness on spinlocks for speed
   15.66 +
   15.67 +# To make an SMP kernel, the next two are needed
   15.68 +#options 	SMP		# Symmetric MultiProcessor Kernel
   15.69 +#device		apic		# I/O APIC
   15.70 +
   15.71 +# SCSI peripherals
   15.72 +device		scbus		# SCSI bus (required for SCSI)
   15.73 +#device		ch		# SCSI media changers
   15.74 +device		da		# Direct Access (disks)
   15.75 +#device		sa		# Sequential Access (tape etc)
   15.76 +#device		cd		# CD
   15.77 +device		pass		# Passthrough device (direct SCSI access)
   15.78 +#device		ses		# SCSI Environmental Services (and SAF-TE)
   15.79 +
   15.80 +# atkbdc0 controls both the keyboard and the PS/2 mouse
   15.81 +#device		atkbdc		# AT keyboard controller
   15.82 +#device		atkbd		# AT keyboard
   15.83 +#device		psm		# PS/2 mouse
   15.84 +
   15.85 +# device		vga	# VGA video card driver
   15.86 +
   15.87 +#device		splash		# Splash screen and screen saver support
   15.88 +
   15.89 +# syscons is the default console driver, resembling an SCO console
   15.90 +#device		sc
   15.91 +
   15.92 +# Enable this for the pcvt (VT220 compatible) console driver
   15.93 +#device		vt
   15.94 +#options 	XSERVER			# support for X server on a vt console
   15.95 +#options 	FAT_CURSOR		# start with block cursor
   15.96 +
   15.97 +#device		agp		# support several AGP chipsets
   15.98 +
   15.99 +# Floating point support - do not disable. 
  15.100 +device		npx
  15.101 +
  15.102 +# Serial (COM) ports
  15.103 +#device		sio		# 8250, 16[45]50 based serial ports
  15.104 +
  15.105 +# Parallel port
  15.106 +#device		ppc
  15.107 +#device		ppbus		# Parallel port bus (required)
  15.108 +#device		lpt		# Printer
  15.109 +#device		plip		# TCP/IP over parallel
  15.110 +#device		ppi		# Parallel port interface device
  15.111 +#device		vpo		# Requires scbus and da
  15.112 +
  15.113 +# If you've got a "dumb" serial or parallel PCI card that is
  15.114 +# supported by the puc(4) glue driver, uncomment the following
  15.115 +# line to enable it (connects to the sio and/or ppc drivers):
  15.116 +#device         puc
  15.117 +
  15.118 +
  15.119 +# Pseudo devices - the number indicates how many units to allocate.
  15.120 +device		random		# Entropy device
  15.121 +device		loop		# Network loopback
  15.122 +device		ether		# Ethernet support
  15.123 +device		tun		# Packet tunnel.
  15.124 +device		pty		# Pseudo-ttys (telnet etc)
  15.125 +device		md		# Memory "disks"
  15.126 +device		gif		# IPv6 and IPv4 tunneling
  15.127 +device		faith		# IPv6-to-IPv4 relaying (translation)
  15.128 +
  15.129 +# The `bpf' device enables the Berkeley Packet Filter.
  15.130 +# Be aware of the administrative consequences of enabling this!
  15.131 +device		bpf		# Berkeley packet filter
  15.132 +
  15.133 +#options		BOOTP
  15.134 +options		XEN
  15.135 +options		MCLSHIFT=12	# this has to be enabled for Xen as we can only have one cluster per page
  15.136 +options		MSIZE=256 
  15.137 +options 	DIAGNOSTIC
  15.138 +options		MAXMEM=(256*1024)
  15.139 +options		NOXENDEBUG=1 		# Turn off Debugging printfs
  15.140 +
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/conf/gethints.awk	Mon Mar 21 07:58:08 2005 +0000
    16.3 @@ -0,0 +1,116 @@
    16.4 +#! /usr/bin/awk -f
    16.5 +#
    16.6 +# This is a transition aid. It extracts old-style configuration information
    16.7 +# from a config file and writes an equivalent device.hints file to stdout.
    16.8 +# You can use that with loader(8) or statically compile it in with the
    16.9 +# 'hints' directive.  See how GENERIC and GENERIC.hints fit together for
   16.10 +# a static example.  You should use loader(8) if at all possible.
   16.11 +#
   16.12 +# $FreeBSD: src/sys/i386/conf/gethints.awk,v 1.2 2002/07/26 03:52:30 peter Exp $
   16.13 +
   16.14 +# skip commented lines, empty lines and not "device" lines
   16.15 +/^[ \t]*#/ || /^[ \t]*$/ || !/[ \t]*device/ { next; }
   16.16 +
   16.17 +# input format :
   16.18 +#    device <name><unit> at <controler>[?] [key [val]]...
   16.19 +# possible keys are :
   16.20 +#    disable, port #, irq #, drq #, drive #, iomem #, iosiz #,
   16.21 +#    flags #, bus #, target #, unit #.
   16.22 +# output format :
   16.23 +#    hint.<name>.<unit>.<key>=<val>
   16.24 +# mapped keys are :
   16.25 +#    iomem -> maddr, iosiz -> msize.
   16.26 +{
   16.27 +	gsub ("#.*", "");		# delete comments
   16.28 +	gsub ("\"", "");		# and double-quotes
   16.29 +	nameunit = $2;			# <name><unit>
   16.30 +	at = $3;			# at
   16.31 +	controler = $4;			# <controler>[?]
   16.32 +	rest = 5;			# optional keys begin at indice 5
   16.33 +	if (at != "at" || controler == "")
   16.34 +		next;			# skip devices w/o controlers
   16.35 +	name = nameunit;
   16.36 +	sub ("[0-9]*$", "", name);	# get the name
   16.37 +	unit = nameunit;
   16.38 +	sub ("^" name, "", unit);	# and the unit
   16.39 +	sub ("\?$", "", controler);
   16.40 +	printf "hint.%s.%s.at=\"%s\"\n", name, unit, controler;
   16.41 +	# for each keys, if any ?
   16.42 +	for (key = $rest; rest <= NF; key = $(++rest)) {
   16.43 +		# skip auto-detect keys (the one w/ a ?)
   16.44 +		if (key == "port?" || key == "drq?" || key == "irq?" || \
   16.45 +		    key == "iomem?" || key == "iosiz?")
   16.46 +			continue;
   16.47 +		# disable has no value, so, give it one
   16.48 +		if (key == "disable") {
   16.49 +			printf "hint.%s.%s.disabled=\"1\"\n", name, unit;
   16.50 +			continue;
   16.51 +		}
   16.52 +		# recognized keys
   16.53 +		if (key == "port" || key == "irq" || key == "drq" || \
   16.54 +		    key == "drive" || key == "iomem" || key == "iosiz" || \
   16.55 +		    key == "flags" || key == "bus" || key == "target" || \
   16.56 +		    key == "unit") {
   16.57 +			val = $(++rest);
   16.58 +			if (val == "?")	# has above
   16.59 +				continue;
   16.60 +			if (key == "port") {
   16.61 +				# map port macros to static values
   16.62 +				sub ("IO_AHA0", "0x330", val);
   16.63 +				sub ("IO_AHA1", "0x334", val);
   16.64 +				sub ("IO_ASC1", "0x3EB", val);
   16.65 +				sub ("IO_ASC2", "0x22B", val);
   16.66 +				sub ("IO_ASC3", "0x26B", val);
   16.67 +				sub ("IO_ASC4", "0x2AB", val);
   16.68 +				sub ("IO_ASC5", "0x2EB", val);
   16.69 +				sub ("IO_ASC6", "0x32B", val);
   16.70 +				sub ("IO_ASC7", "0x36B", val);
   16.71 +				sub ("IO_ASC8", "0x3AB", val);
   16.72 +				sub ("IO_BT0", "0x330", val);
   16.73 +				sub ("IO_BT1", "0x334", val);
   16.74 +				sub ("IO_CGA", "0x3D0", val);
   16.75 +				sub ("IO_COM1", "0x3F8", val);
   16.76 +				sub ("IO_COM2", "0x2F8", val);
   16.77 +				sub ("IO_COM3", "0x3E8", val);
   16.78 +				sub ("IO_COM4", "0x2E8", val);
   16.79 +				sub ("IO_DMA1", "0x000", val);
   16.80 +				sub ("IO_DMA2", "0x0C0", val);
   16.81 +				sub ("IO_DMAPG", "0x080", val);
   16.82 +				sub ("IO_FD1", "0x3F0", val);
   16.83 +				sub ("IO_FD2", "0x370", val);
   16.84 +				sub ("IO_GAME", "0x201", val);
   16.85 +				sub ("IO_GSC1", "0x270", val);
   16.86 +				sub ("IO_GSC2", "0x2E0", val);
   16.87 +				sub ("IO_GSC3", "0x370", val);
   16.88 +				sub ("IO_GSC4", "0x3E0", val);
   16.89 +				sub ("IO_ICU1", "0x020", val);
   16.90 +				sub ("IO_ICU2", "0x0A0", val);
   16.91 +				sub ("IO_KBD", "0x060", val);
   16.92 +				sub ("IO_LPT1", "0x378", val);
   16.93 +				sub ("IO_LPT2", "0x278", val);
   16.94 +				sub ("IO_LPT3", "0x3BC", val);
   16.95 +				sub ("IO_MDA", "0x3B0", val);
   16.96 +				sub ("IO_NMI", "0x070", val);
   16.97 +				sub ("IO_NPX", "0x0F0", val);
   16.98 +				sub ("IO_PMP1", "0x026", val);
   16.99 +				sub ("IO_PMP2", "0x178", val);
  16.100 +				sub ("IO_PPI", "0x061", val);
  16.101 +				sub ("IO_RTC", "0x070", val);
  16.102 +				sub ("IO_TIMER1", "0x040", val);
  16.103 +				sub ("IO_TIMER2", "0x048", val);
  16.104 +				sub ("IO_UHA0", "0x330", val);
  16.105 +				sub ("IO_VGA", "0x3C0", val);
  16.106 +				sub ("IO_WD1", "0x1F0", val);
  16.107 +				sub ("IO_WD2", "0x170", val);
  16.108 +			} else {
  16.109 +				# map key names
  16.110 +				sub ("iomem", "maddr", key);
  16.111 +				sub ("iosiz", "msize", key);
  16.112 +			}
  16.113 +			printf "hint.%s.%s.%s=\"%s\"\n", name, unit, key, val;
  16.114 +			continue;
  16.115 +		}
  16.116 +		printf ("unrecognized config token '%s:%s' on line %s\n",
  16.117 +			rest, key, NR); # > "/dev/stderr";
  16.118 +	}
  16.119 +}
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/clock.c	Mon Mar 21 07:58:08 2005 +0000
    17.3 @@ -0,0 +1,511 @@
    17.4 +/*-
    17.5 + * Copyright (c) 1990 The Regents of the University of California.
    17.6 + * All rights reserved.
    17.7 + *
    17.8 + * This code is derived from software contributed to Berkeley by
    17.9 + * William Jolitz and Don Ahn.
   17.10 + *
   17.11 + * Redistribution and use in source and binary forms, with or without
   17.12 + * modification, are permitted provided that the following conditions
   17.13 + * are met:
   17.14 + * 1. Redistributions of source code must retain the above copyright
   17.15 + *    notice, this list of conditions and the following disclaimer.
   17.16 + * 2. Redistributions in binary form must reproduce the above copyright
   17.17 + *    notice, this list of conditions and the following disclaimer in the
   17.18 + *    documentation and/or other materials provided with the distribution.
   17.19 + * 3. All advertising materials mentioning features or use of this software
   17.20 + *    must display the following acknowledgement:
   17.21 + *	This product includes software developed by the University of
   17.22 + *	California, Berkeley and its contributors.
   17.23 + * 4. Neither the name of the University nor the names of its contributors
   17.24 + *    may be used to endorse or promote products derived from this software
   17.25 + *    without specific prior written permission.
   17.26 + *
   17.27 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   17.28 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17.29 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17.30 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   17.31 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   17.32 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   17.33 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   17.34 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   17.35 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   17.36 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   17.37 + * SUCH DAMAGE.
   17.38 + *
   17.39 + *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
   17.40 + */
   17.41 +
   17.42 +#include <sys/cdefs.h>
   17.43 +__FBSDID("$FreeBSD: src/sys/i386/isa/clock.c,v 1.207 2003/11/13 10:02:12 phk Exp $");
   17.44 +
   17.45 +/* #define DELAYDEBUG */
   17.46 +/*
   17.47 + * Routines to handle clock hardware.
   17.48 + */
   17.49 +
   17.50 +/*
   17.51 + * inittodr, settodr and support routines written
   17.52 + * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
   17.53 + *
   17.54 + * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
   17.55 + */
   17.56 +
   17.57 +#include "opt_clock.h"
   17.58 +#include "opt_isa.h"
   17.59 +#include "opt_mca.h"
   17.60 +
   17.61 +#include <sys/param.h>
   17.62 +#include <sys/systm.h>
   17.63 +#include <sys/bus.h>
   17.64 +#include <sys/lock.h>
   17.65 +#include <sys/mutex.h>
   17.66 +#include <sys/proc.h>
   17.67 +#include <sys/time.h>
   17.68 +#include <sys/timetc.h>
   17.69 +#include <sys/kernel.h>
   17.70 +#include <sys/limits.h>
   17.71 +#include <sys/sysctl.h>
   17.72 +#include <sys/cons.h>
   17.73 +#include <sys/power.h>
   17.74 +
   17.75 +#include <machine/clock.h>
   17.76 +#include <machine/cputypes.h>
   17.77 +#include <machine/frame.h>
   17.78 +#include <machine/intr_machdep.h>
   17.79 +#include <machine/md_var.h>
   17.80 +#include <machine/psl.h>
   17.81 +#if defined(SMP)
   17.82 +#include <machine/smp.h>
   17.83 +#endif
   17.84 +#include <machine/specialreg.h>
   17.85 +
   17.86 +#include <i386/isa/icu.h>
   17.87 +#include <i386/isa/isa.h>
   17.88 +#include <isa/rtc.h>
   17.89 +#include <i386/isa/timerreg.h>
   17.90 +
   17.91 +/* XEN specific defines */
   17.92 +#include <machine/xen_intr.h>
   17.93 +
   17.94 +/*
   17.95 + * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
   17.96 + * can use a simple formula for leap years.
   17.97 + */
   17.98 +#define	LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0)
   17.99 +#define DAYSPERYEAR   (31+28+31+30+31+30+31+31+30+31+30+31)
  17.100 +
  17.101 +int	adjkerntz;		/* local offset from GMT in seconds */
  17.102 +int	clkintr_pending;
  17.103 +int	disable_rtc_set = 1;	/* disable resettodr() if != 0 */
  17.104 +int	pscnt = 1;
  17.105 +int	psdiv = 1;
  17.106 +int	statclock_disable;
  17.107 +#ifndef TIMER_FREQ
  17.108 +#define TIMER_FREQ   1193182
  17.109 +#endif
  17.110 +u_int	timer_freq = TIMER_FREQ;
  17.111 +
  17.112 +static	const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
  17.113 +
  17.114 +/* Values for timerX_state: */
  17.115 +#define	RELEASED	0
  17.116 +#define	RELEASE_PENDING	1
  17.117 +#define	ACQUIRED	2
  17.118 +#define	ACQUIRE_PENDING	3
  17.119 +
  17.120 +/* Cached *multiplier* to convert TSC counts to microseconds.
  17.121 + * (see the equation below).
  17.122 + * Equal to 2^32 * (1 / (clocks per usec) ).
  17.123 + * Initialized in time_init.
  17.124 + */
  17.125 +static unsigned long fast_gettimeoffset_quotient;
  17.126 +
  17.127 +/* These are peridically updated in shared_info, and then copied here. */
  17.128 +static uint32_t shadow_tsc_stamp;
  17.129 +static uint64_t shadow_system_time;
  17.130 +static uint32_t shadow_time_version;
  17.131 +static struct timeval shadow_tv;
  17.132 +
  17.133 +static uint64_t processed_system_time;/* System time (ns) at last processing. */
  17.134 +
  17.135 +#define NS_PER_TICK (1000000000ULL/hz)
  17.136 +
  17.137 +/* convert from cycles(64bits) => nanoseconds (64bits)
  17.138 + *  basic equation:
  17.139 + *		ns = cycles / (freq / ns_per_sec)
  17.140 + *		ns = cycles * (ns_per_sec / freq)
  17.141 + *		ns = cycles * (10^9 / (cpu_mhz * 10^6))
  17.142 + *		ns = cycles * (10^3 / cpu_mhz)
  17.143 + *
  17.144 + *	Then we use scaling math (suggested by george@mvista.com) to get:
  17.145 + *		ns = cycles * (10^3 * SC / cpu_mhz) / SC
  17.146 + *		ns = cycles * cyc2ns_scale / SC
  17.147 + *
  17.148 + *	And since SC is a constant power of two, we can convert the div
  17.149 + *  into a shift.   
  17.150 + *			-johnstul@us.ibm.com "math is hard, lets go shopping!"
  17.151 + */
  17.152 +static unsigned long cyc2ns_scale; 
  17.153 +#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
  17.154 +
  17.155 +static inline void set_cyc2ns_scale(unsigned long cpu_mhz)
  17.156 +{
  17.157 +	cyc2ns_scale = (1000 << CYC2NS_SCALE_FACTOR)/cpu_mhz;
  17.158 +}
  17.159 +
  17.160 +static inline unsigned long long cycles_2_ns(unsigned long long cyc)
  17.161 +{
  17.162 +	return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
  17.163 +}
  17.164 +
  17.165 +/*
  17.166 + * Reads a consistent set of time-base values from Xen, into a shadow data
  17.167 + * area. Must be called with the xtime_lock held for writing.
  17.168 + */
  17.169 +static void __get_time_values_from_xen(void)
  17.170 +{
  17.171 +	shared_info_t *s = HYPERVISOR_shared_info;
  17.172 +
  17.173 +	do {
  17.174 +		shadow_time_version = s->time_version2;
  17.175 +		rmb();
  17.176 +		shadow_tv.tv_sec    = s->wc_sec;
  17.177 +		shadow_tv.tv_usec   = s->wc_usec;
  17.178 +		shadow_tsc_stamp    = (uint32_t)s->tsc_timestamp;
  17.179 +		shadow_system_time  = s->system_time;
  17.180 +		rmb();
  17.181 +	}
  17.182 +	while (shadow_time_version != s->time_version1);
  17.183 +}
  17.184 +
  17.185 +#define TIME_VALUES_UP_TO_DATE \
  17.186 +	(shadow_time_version == HYPERVISOR_shared_info->time_version2)
  17.187 +
  17.188 +static	void	(*timer_func)(struct clockframe *frame) = hardclock;
  17.189 +
  17.190 +static	unsigned xen_get_offset(void);
  17.191 +static	unsigned xen_get_timecount(struct timecounter *tc);
  17.192 +
  17.193 +static struct timecounter xen_timecounter = {
  17.194 +	xen_get_timecount,	/* get_timecount */
  17.195 +	0,			/* no poll_pps */
  17.196 +	~0u,			/* counter_mask */
  17.197 +	0,			/* frequency */
  17.198 +	"ixen",			/* name */
  17.199 +	0			/* quality */
  17.200 +};
  17.201 +
  17.202 +
  17.203 +static void 
  17.204 +clkintr(struct clockframe *frame)
  17.205 +{
  17.206 +    int64_t delta;
  17.207 +    long ticks = 0;
  17.208 +
  17.209 +
  17.210 +    do {
  17.211 +    	__get_time_values_from_xen();
  17.212 +    	delta = (int64_t)(shadow_system_time + 
  17.213 +			  xen_get_offset() * 1000 - 
  17.214 +			  processed_system_time);
  17.215 +    } while (!TIME_VALUES_UP_TO_DATE);
  17.216 +
  17.217 +    if (unlikely(delta < 0)) {
  17.218 +        printk("Timer ISR: Time went backwards: %lld\n", delta);
  17.219 +        return;
  17.220 +    }
  17.221 +
  17.222 +    /* Process elapsed ticks since last call. */
  17.223 +    while ( delta >= NS_PER_TICK )
  17.224 +    {
  17.225 +        ticks++;
  17.226 +        delta -= NS_PER_TICK;
  17.227 +        processed_system_time += NS_PER_TICK;
  17.228 +    }
  17.229 +
  17.230 +    if (ticks > 0) {
  17.231 +	if (frame)
  17.232 +		timer_func(frame);
  17.233 +#ifdef SMP
  17.234 +	if (timer_func == hardclock && frame)
  17.235 +		forward_hardclock();
  17.236 +#endif
  17.237 +    }
  17.238 +}
  17.239 +
  17.240 +#include "opt_ddb.h"
  17.241 +static uint32_t
  17.242 +getit(void)
  17.243 +{
  17.244 +	__get_time_values_from_xen();
  17.245 +	return shadow_tsc_stamp;
  17.246 +}
  17.247 +
  17.248 +/*
  17.249 + * Wait "n" microseconds.
  17.250 + * Relies on timer 1 counting down from (timer_freq / hz)
  17.251 + * Note: timer had better have been programmed before this is first used!
  17.252 + */
  17.253 +void
  17.254 +DELAY(int n)
  17.255 +{
  17.256 +	int delta, ticks_left;
  17.257 +	uint32_t tick, prev_tick;
  17.258 +#ifdef DELAYDEBUG
  17.259 +	int getit_calls = 1;
  17.260 +	int n1;
  17.261 +	static int state = 0;
  17.262 +
  17.263 +	if (state == 0) {
  17.264 +		state = 1;
  17.265 +		for (n1 = 1; n1 <= 10000000; n1 *= 10)
  17.266 +			DELAY(n1);
  17.267 +		state = 2;
  17.268 +	}
  17.269 +	if (state == 1)
  17.270 +		printf("DELAY(%d)...", n);
  17.271 +#endif
  17.272 +	/*
  17.273 +	 * Read the counter first, so that the rest of the setup overhead is
  17.274 +	 * counted.  Guess the initial overhead is 20 usec (on most systems it
  17.275 +	 * takes about 1.5 usec for each of the i/o's in getit().  The loop
  17.276 +	 * takes about 6 usec on a 486/33 and 13 usec on a 386/20.  The
  17.277 +	 * multiplications and divisions to scale the count take a while).
  17.278 +	 *
  17.279 +	 * However, if ddb is active then use a fake counter since reading
  17.280 +	 * the i8254 counter involves acquiring a lock.  ddb must not go
  17.281 +	 * locking for many reasons, but it calls here for at least atkbd
  17.282 +	 * input.
  17.283 +	 */
  17.284 +	prev_tick = getit();
  17.285 +
  17.286 +	n -= 0;			/* XXX actually guess no initial overhead */
  17.287 +	/*
  17.288 +	 * Calculate (n * (timer_freq / 1e6)) without using floating point
  17.289 +	 * and without any avoidable overflows.
  17.290 +	 */
  17.291 +	if (n <= 0)
  17.292 +		ticks_left = 0;
  17.293 +	else if (n < 256)
  17.294 +		/*
  17.295 +		 * Use fixed point to avoid a slow division by 1000000.
  17.296 +		 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
  17.297 +		 * 2^15 is the first power of 2 that gives exact results
  17.298 +		 * for n between 0 and 256.
  17.299 +		 */
  17.300 +		ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
  17.301 +	else
  17.302 +		/*
  17.303 +		 * Don't bother using fixed point, although gcc-2.7.2
  17.304 +		 * generates particularly poor code for the long long
  17.305 +		 * division, since even the slow way will complete long
  17.306 +		 * before the delay is up (unless we're interrupted).
  17.307 +		 */
  17.308 +		ticks_left = ((u_int)n * (long long)timer_freq + 999999)
  17.309 +			     / 1000000;
  17.310 +
  17.311 +	while (ticks_left > 0) {
  17.312 +		tick = getit();
  17.313 +#ifdef DELAYDEBUG
  17.314 +		++getit_calls;
  17.315 +#endif
  17.316 +		delta = tick - prev_tick;
  17.317 +		prev_tick = tick;
  17.318 +		if (delta < 0) {
  17.319 +			/*
  17.320 +			 * Guard against timer0_max_count being wrong.
  17.321 +			 * This shouldn't happen in normal operation,
  17.322 +			 * but it may happen if set_timer_freq() is
  17.323 +			 * traced.
  17.324 +			 */
  17.325 +			/* delta += timer0_max_count; ??? */
  17.326 +			if (delta < 0)
  17.327 +				delta = 0;
  17.328 +		}
  17.329 +		ticks_left -= delta;
  17.330 +	}
  17.331 +#ifdef DELAYDEBUG
  17.332 +	if (state == 1)
  17.333 +		printf(" %d calls to getit() at %d usec each\n",
  17.334 +		       getit_calls, (n + 5) / getit_calls);
  17.335 +#endif
  17.336 +}
  17.337 +
  17.338 +
  17.339 +int
  17.340 +sysbeep(int pitch, int period)
  17.341 +{
  17.342 +	return (0);
  17.343 +}
  17.344 +
  17.345 +/*
  17.346 + * Restore all the timers non-atomically (XXX: should be atomically).
  17.347 + *
  17.348 + * This function is called from pmtimer_resume() to restore all the timers.
  17.349 + * This should not be necessary, but there are broken laptops that do not
  17.350 + * restore all the timers on resume.
  17.351 + */
  17.352 +void
  17.353 +timer_restore(void)
  17.354 +{
  17.355 +    /* Get timebases for new environment. */ 
  17.356 +    __get_time_values_from_xen();
  17.357 +
  17.358 +    /* Reset our own concept of passage of system time. */
  17.359 +    processed_system_time = shadow_system_time;
  17.360 +}
  17.361 +
  17.362 +void
  17.363 +startrtclock()
  17.364 +{
  17.365 +	unsigned long long alarm;
  17.366 +	uint64_t __cpu_khz;
  17.367 +	uint32_t cpu_khz;
  17.368 +
  17.369 +	__cpu_khz = HYPERVISOR_shared_info->cpu_freq;
  17.370 +	__cpu_khz /= 1000;
  17.371 +	cpu_khz = (uint32_t)__cpu_khz;
  17.372 +	printk("Xen reported: %lu.%03lu MHz processor.\n", 
  17.373 +	       cpu_khz / 1000, cpu_khz % 1000);
  17.374 +
  17.375 +	/* (10^6 * 2^32) / cpu_hz = (10^3 * 2^32) / cpu_khz =
  17.376 +	   (2^32 * 1 / (clocks/us)) */
  17.377 +	{	
  17.378 +		unsigned long eax=0, edx=1000;
  17.379 +		__asm__("divl %2"
  17.380 +		    :"=a" (fast_gettimeoffset_quotient), "=d" (edx)
  17.381 +		    :"r" (cpu_khz),
  17.382 +		    "0" (eax), "1" (edx));
  17.383 +	}
  17.384 +
  17.385 +	set_cyc2ns_scale(cpu_khz/1000);
  17.386 +	timer_freq = tsc_freq = xen_timecounter.tc_frequency = cpu_khz * 1000;
  17.387 +        tc_init(&xen_timecounter);
  17.388 +
  17.389 +
  17.390 +	rdtscll(alarm);
  17.391 +}
  17.392 +
  17.393 +/*
  17.394 + * Initialize the time of day register, based on the time base which is, e.g.
  17.395 + * from a filesystem.
  17.396 + */
  17.397 +void
  17.398 +inittodr(time_t base)
  17.399 +{
  17.400 +	int		s, y;
  17.401 +	struct timespec ts;
  17.402 +
  17.403 +	s = splclock();
  17.404 +	if (base) {
  17.405 +		ts.tv_sec = base;
  17.406 +		ts.tv_nsec = 0;
  17.407 +		tc_setclock(&ts);
  17.408 +	}
  17.409 +
  17.410 +	y = time_second - shadow_tv.tv_sec;
  17.411 +	if (y <= -2 || y >= 2) {
  17.412 +		/* badly off, adjust it */
  17.413 +		ts.tv_sec = shadow_tv.tv_sec;
  17.414 +		ts.tv_nsec = shadow_tv.tv_usec * 1000;
  17.415 +		tc_setclock(&ts);
  17.416 +	}
  17.417 +	splx(s);
  17.418 +}
  17.419 +
  17.420 +/*
  17.421 + * Write system time back to RTC.  Not supported for guest domains.
  17.422 + */
  17.423 +void
  17.424 +resettodr()
  17.425 +{
  17.426 +}
  17.427 +
  17.428 +
  17.429 +/*
  17.430 + * Start clocks running.
  17.431 + */
  17.432 +void
  17.433 +cpu_initclocks()
  17.434 +{
  17.435 +	int diag;
  17.436 +	int time_irq = bind_virq_to_irq(VIRQ_TIMER);
  17.437 +
  17.438 +        if ((diag = intr_add_handler("clk", time_irq,
  17.439 +				     (driver_intr_t *)clkintr, NULL,
  17.440 +				     INTR_TYPE_CLK | INTR_FAST, NULL))) {
  17.441 +		panic("failed to register clock interrupt: %d\n", diag);
  17.442 +	}
  17.443 +
  17.444 +	/* should fast clock be enabled ? */
  17.445 +
  17.446 +	/* initialize xen values */
  17.447 +	__get_time_values_from_xen();
  17.448 +	processed_system_time = shadow_system_time;
  17.449 +}
  17.450 +
  17.451 +void
  17.452 +cpu_startprofclock(void)
  17.453 +{
  17.454 +
  17.455 +    	printf("cpu_startprofclock: profiling clock is not supported\n");
  17.456 +}
  17.457 +
  17.458 +void
  17.459 +cpu_stopprofclock(void)
  17.460 +{
  17.461 +
  17.462 +    	printf("cpu_stopprofclock: profiling clock is not supported\n");
  17.463 +}
  17.464 +
  17.465 +static uint32_t
  17.466 +xen_get_timecount(struct timecounter *tc)
  17.467 +{
  17.468 +    	__get_time_values_from_xen();
  17.469 +	return shadow_tsc_stamp;
  17.470 +}
  17.471 +
  17.472 +/*
  17.473 + * Track behavior of cur_timer->get_offset() functionality in timer_tsc.c
  17.474 + */
  17.475 +#undef rdtsc
  17.476 +#define rdtsc(low,high) \
  17.477 +     __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
  17.478 +
  17.479 +static uint32_t
  17.480 +xen_get_offset(void)
  17.481 +{
  17.482 +	register unsigned long eax, edx;
  17.483 +
  17.484 +	/* Read the Time Stamp Counter */
  17.485 +
  17.486 +	rdtsc(eax,edx);
  17.487 +
  17.488 +	/* .. relative to previous jiffy (32 bits is enough) */
  17.489 +	eax -= shadow_tsc_stamp;
  17.490 +
  17.491 +	/*
  17.492 +	 * Time offset = (tsc_low delta) * fast_gettimeoffset_quotient
  17.493 +	 *             = (tsc_low delta) * (usecs_per_clock)
  17.494 +	 *             = (tsc_low delta) * (usecs_per_jiffy / clocks_per_jiffy)
  17.495 +	 *
  17.496 +	 * Using a mull instead of a divl saves up to 31 clock cycles
  17.497 +	 * in the critical path.
  17.498 +	 */
  17.499 +
  17.500 +	__asm__("mull %2"
  17.501 +		:"=a" (eax), "=d" (edx)
  17.502 +		:"rm" (fast_gettimeoffset_quotient),
  17.503 +		 "0" (eax));
  17.504 +
  17.505 +	/* our adjusted time offset in microseconds */
  17.506 +	return edx;
  17.507 +}
  17.508 +
  17.509 +void
  17.510 +idle_block(void)
  17.511 +{
  17.512 +	if (HYPERVISOR_set_timer_op(processed_system_time + NS_PER_TICK) == 0)
  17.513 +		HYPERVISOR_block();
  17.514 +}
    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/critical.c	Mon Mar 21 07:58:08 2005 +0000
    18.3 @@ -0,0 +1,46 @@
    18.4 +/*-
    18.5 + * Copyright (c) 2002 Matthew Dillon.  All Rights Reserved.
    18.6 + * Redistribution and use in source and binary forms, with or without
    18.7 + * modification, are permitted provided that the following conditions
    18.8 + * are met:
    18.9 + * 1. Redistributions of source code must retain the above copyright
   18.10 + *    notice, this list of conditions and the following disclaimer.
   18.11 + * 2. Redistributions in binary form must reproduce the above copyright
   18.12 + *    notice, this list of conditions and the following disclaimer in the
   18.13 + *    documentation and/or other materials provided with the distribution.
   18.14 + * 4. Neither the name of the University nor the names of its contributors
   18.15 + *    may be used to endorse or promote products derived from this software
   18.16 + *    without specific prior written permission.
   18.17 + *
   18.18 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
   18.19 + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   18.20 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18.21 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
   18.22 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18.23 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
   18.24 + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   18.25 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   18.26 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
   18.27 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   18.28 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   18.29 + */
   18.30 +
   18.31 +#include <sys/cdefs.h>
   18.32 +__FBSDID("$FreeBSD: src/sys/i386/i386/critical.c,v 1.12 2003/11/03 21:06:54 jhb Exp $");
   18.33 +
   18.34 +#include <sys/param.h>
   18.35 +#include <sys/systm.h>
   18.36 +#include <sys/proc.h>
   18.37 +#include <machine/critical.h>
   18.38 +#include <machine/psl.h>
   18.39 +
   18.40 +/*
   18.41 + * cpu_critical_fork_exit() - cleanup after fork
   18.42 + *
   18.43 + *	Enable interrupts in the saved copy of eflags.
   18.44 + */
   18.45 +void
   18.46 +cpu_critical_fork_exit(void)
   18.47 +{
   18.48 +    curthread->td_md.md_savecrit = 0;
   18.49 +}
    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/ctrl_if.c	Mon Mar 21 07:58:08 2005 +0000
    19.3 @@ -0,0 +1,476 @@
    19.4 +/******************************************************************************
    19.5 + * ctrl_if.c
    19.6 + * 
    19.7 + * Management functions for special interface to the domain controller.
    19.8 + * 
    19.9 + * Copyright (c) 2004, K A Fraser
   19.10 + * Copyright (c) 2004, K M Macy
   19.11 + */
   19.12 +
   19.13 +#include <sys/param.h>
   19.14 +#include <sys/systm.h>
   19.15 +#include <sys/uio.h>
   19.16 +#include <sys/bus.h>
   19.17 +#include <sys/malloc.h>
   19.18 +#include <sys/kernel.h>
   19.19 +#include <sys/lock.h>
   19.20 +#include <sys/mutex.h>
   19.21 +#include <sys/selinfo.h>
   19.22 +#include <sys/poll.h>
   19.23 +#include <sys/conf.h>
   19.24 +#include <sys/fcntl.h>
   19.25 +#include <sys/ioccom.h>
   19.26 +#include <sys/taskqueue.h>
   19.27 +
   19.28 +
   19.29 +#include <machine/cpufunc.h>
   19.30 +#include <machine/intr_machdep.h>
   19.31 +#include <machine/xen-os.h>
   19.32 +#include <machine/xen_intr.h>
   19.33 +#include <machine/bus.h>
   19.34 +#include <sys/rman.h>
   19.35 +#include <machine/resource.h>
   19.36 +#include <machine/synch_bitops.h>
   19.37 +
   19.38 +
   19.39 +#include <machine/hypervisor-ifs.h>
   19.40 +
   19.41 +#include <machine/ctrl_if.h>
   19.42 +#include <machine/evtchn.h>
   19.43 +
   19.44 +/*
   19.45 + * Only used by initial domain which must create its own control-interface
   19.46 + * event channel. This value is picked up by the user-space domain controller
   19.47 + * via an ioctl.
   19.48 + */
   19.49 +int initdom_ctrlif_domcontroller_port = -1;
   19.50 +
   19.51 +static int        ctrl_if_evtchn;
   19.52 +static int        ctrl_if_irq;
   19.53 +static struct mtx ctrl_if_lock;
   19.54 +static int *      ctrl_if_wchan = &ctrl_if_evtchn;
   19.55 +
   19.56 +
   19.57 +static CONTROL_RING_IDX ctrl_if_tx_resp_cons;
   19.58 +static CONTROL_RING_IDX ctrl_if_rx_req_cons;
   19.59 +
   19.60 +/* Incoming message requests. */
   19.61 +    /* Primary message type -> message handler. */
   19.62 +static ctrl_msg_handler_t ctrl_if_rxmsg_handler[256];
   19.63 +    /* Primary message type -> callback in process context? */
   19.64 +static unsigned long ctrl_if_rxmsg_blocking_context[256/sizeof(unsigned long)];
   19.65 +    /* Queue up messages to be handled in process context. */
   19.66 +static ctrl_msg_t ctrl_if_rxmsg_deferred[CONTROL_RING_SIZE];
   19.67 +static CONTROL_RING_IDX ctrl_if_rxmsg_deferred_prod;
   19.68 +static CONTROL_RING_IDX ctrl_if_rxmsg_deferred_cons;
   19.69 +
   19.70 +/* Incoming message responses: message identifier -> message handler/id. */
   19.71 +static struct {
   19.72 +    ctrl_msg_handler_t fn;
   19.73 +    unsigned long      id;
   19.74 +} ctrl_if_txmsg_id_mapping[CONTROL_RING_SIZE];
   19.75 +
   19.76 +/*
   19.77 + * FreeBSD task queues don't allow you to requeue an already executing task.
   19.78 + * Since ctrl_if_interrupt clears the TX_FULL condition and schedules any 
   19.79 + * waiting tasks, which themselves may need to schedule a new task 
   19.80 + * (due to new a TX_FULL condition), we ping-pong between these A/B task queues.
   19.81 + * The interrupt runs anything on the current queue and moves the index so that
   19.82 + * future schedulings occur on the next queue.  We should never get into a 
   19.83 + * situation where there is a task scheduleded on both the A & B queues.
   19.84 + */
   19.85 +TASKQUEUE_DECLARE(ctrl_if_txA);
   19.86 +TASKQUEUE_DEFINE(ctrl_if_txA, NULL, NULL, {});
   19.87 +TASKQUEUE_DECLARE(ctrl_if_txB);
   19.88 +TASKQUEUE_DEFINE(ctrl_if_txB, NULL, NULL, {});
   19.89 +struct taskqueue **taskqueue_ctrl_if_tx[2] = { &taskqueue_ctrl_if_txA,
   19.90 +    				               &taskqueue_ctrl_if_txB };
   19.91 +int ctrl_if_idx;
   19.92 +
   19.93 +static struct task ctrl_if_rx_tasklet;
   19.94 +static struct task ctrl_if_tx_tasklet;
   19.95 +    /* Passed to schedule_task(). */
   19.96 +static struct task ctrl_if_rxmsg_deferred_task;
   19.97 +
   19.98 +
   19.99 +
  19.100 +#define get_ctrl_if() ((control_if_t *)((char *)HYPERVISOR_shared_info + 2048))
  19.101 +#define TX_FULL(_c)   \
  19.102 +    (((_c)->tx_req_prod - ctrl_if_tx_resp_cons) == CONTROL_RING_SIZE)
  19.103 +
  19.104 +static void 
  19.105 +ctrl_if_notify_controller(void)
  19.106 +{
  19.107 +    notify_via_evtchn(ctrl_if_evtchn);
  19.108 +}
  19.109 +
  19.110 +static void 
  19.111 +ctrl_if_rxmsg_default_handler(ctrl_msg_t *msg, unsigned long id)
  19.112 +{
  19.113 +    msg->length = 0;
  19.114 +    ctrl_if_send_response(msg);
  19.115 +}
  19.116 +
  19.117 +static void 
  19.118 +__ctrl_if_tx_tasklet(void *context __unused, int pending __unused)
  19.119 +{
  19.120 +    control_if_t *ctrl_if = get_ctrl_if();
  19.121 +    ctrl_msg_t   *msg;
  19.122 +    int           was_full = TX_FULL(ctrl_if);
  19.123 +
  19.124 +    while ( ctrl_if_tx_resp_cons != ctrl_if->tx_resp_prod )
  19.125 +    {
  19.126 +        msg = &ctrl_if->tx_ring[MASK_CONTROL_IDX(ctrl_if_tx_resp_cons)];
  19.127 +
  19.128 +        /* Execute the callback handler, if one was specified. */
  19.129 +        if ( msg->id != 0xFF )
  19.130 +        {
  19.131 +            (*ctrl_if_txmsg_id_mapping[msg->id].fn)(
  19.132 +                msg, ctrl_if_txmsg_id_mapping[msg->id].id);
  19.133 +            smp_mb(); /* Execute, /then/ free. */
  19.134 +            ctrl_if_txmsg_id_mapping[msg->id].fn = NULL;
  19.135 +        }
  19.136 +
  19.137 +        /*
  19.138 +         * Step over the message in the ring /after/ finishing reading it. As 
  19.139 +         * soon as the index is updated then the message may get blown away.
  19.140 +         */
  19.141 +        smp_mb();
  19.142 +        ctrl_if_tx_resp_cons++;
  19.143 +    }
  19.144 +
  19.145 +    if ( was_full && !TX_FULL(ctrl_if) )
  19.146 +    {
  19.147 +        wakeup(ctrl_if_wchan);
  19.148 +
  19.149 +	/* bump idx so future enqueues will occur on the next taskq
  19.150 +	 * process any currently pending tasks
  19.151 +	 */
  19.152 +	ctrl_if_idx++;		
  19.153 +        taskqueue_run(*taskqueue_ctrl_if_tx[(ctrl_if_idx-1) & 1]);
  19.154 +    }
  19.155 +}
  19.156 +
  19.157 +static void 
  19.158 +__ctrl_if_rxmsg_deferred_task(void *context __unused, int pending __unused)
  19.159 +{
  19.160 +    ctrl_msg_t *msg;
  19.161 +
  19.162 +    while ( ctrl_if_rxmsg_deferred_cons != ctrl_if_rxmsg_deferred_prod )
  19.163 +    {
  19.164 +        msg = &ctrl_if_rxmsg_deferred[MASK_CONTROL_IDX(
  19.165 +            ctrl_if_rxmsg_deferred_cons++)];
  19.166 +        (*ctrl_if_rxmsg_handler[msg->type])(msg, 0);
  19.167 +    }
  19.168 +}
  19.169 +
  19.170 +static void 
  19.171 +__ctrl_if_rx_tasklet(void *context __unused, int pending __unused)
  19.172 +{
  19.173 +    control_if_t *ctrl_if = get_ctrl_if();
  19.174 +    ctrl_msg_t    msg, *pmsg;
  19.175 +
  19.176 +    while ( ctrl_if_rx_req_cons != ctrl_if->rx_req_prod )
  19.177 +    {
  19.178 +        pmsg = &ctrl_if->rx_ring[MASK_CONTROL_IDX(ctrl_if_rx_req_cons++)];
  19.179 +        memcpy(&msg, pmsg, offsetof(ctrl_msg_t, msg));
  19.180 +        if ( msg.length != 0 )
  19.181 +            memcpy(msg.msg, pmsg->msg, msg.length);
  19.182 +        if ( test_bit(msg.type, &ctrl_if_rxmsg_blocking_context) )
  19.183 +        {
  19.184 +            pmsg = &ctrl_if_rxmsg_deferred[MASK_CONTROL_IDX(
  19.185 +                ctrl_if_rxmsg_deferred_prod++)];
  19.186 +            memcpy(pmsg, &msg, offsetof(ctrl_msg_t, msg) + msg.length);
  19.187 +            taskqueue_enqueue(taskqueue_thread, &ctrl_if_rxmsg_deferred_task);
  19.188 +        }
  19.189 +        else
  19.190 +        {
  19.191 +            (*ctrl_if_rxmsg_handler[msg.type])(&msg, 0);
  19.192 +        }
  19.193 +    }
  19.194 +}
  19.195 +
  19.196 +static void 
  19.197 +ctrl_if_interrupt(void *ctrl_sc)
  19.198 +/* (int irq, void *dev_id, struct pt_regs *regs) */
  19.199 +{
  19.200 +    control_if_t *ctrl_if = get_ctrl_if();
  19.201 +
  19.202 +    if ( ctrl_if_tx_resp_cons != ctrl_if->tx_resp_prod )
  19.203 +	taskqueue_enqueue(taskqueue_swi, &ctrl_if_tx_tasklet);
  19.204 +    
  19.205 +
  19.206 +    if ( ctrl_if_rx_req_cons != ctrl_if->rx_req_prod )
  19.207 + 	taskqueue_enqueue(taskqueue_swi, &ctrl_if_rx_tasklet);
  19.208 +}
  19.209 +
  19.210 +int 
  19.211 +ctrl_if_send_message_noblock(
  19.212 +    ctrl_msg_t *msg, 
  19.213 +    ctrl_msg_handler_t hnd,
  19.214 +    unsigned long id)
  19.215 +{
  19.216 +    control_if_t *ctrl_if = get_ctrl_if();
  19.217 +    unsigned long flags;
  19.218 +    int           i;
  19.219 +
  19.220 +    mtx_lock_irqsave(&ctrl_if_lock, flags);
  19.221 +
  19.222 +    if ( TX_FULL(ctrl_if) )
  19.223 +    {
  19.224 +        mtx_unlock_irqrestore(&ctrl_if_lock, flags);
  19.225 +        return EAGAIN;
  19.226 +    }
  19.227 +
  19.228 +    msg->id = 0xFF;
  19.229 +    if ( hnd != NULL )
  19.230 +    {
  19.231 +        for ( i = 0; ctrl_if_txmsg_id_mapping[i].fn != NULL; i++ )
  19.232 +            continue;
  19.233 +        ctrl_if_txmsg_id_mapping[i].fn = hnd;
  19.234 +        ctrl_if_txmsg_id_mapping[i].id = id;
  19.235 +        msg->id = i;
  19.236 +    }
  19.237 +
  19.238 +    memcpy(&ctrl_if->tx_ring[MASK_CONTROL_IDX(ctrl_if->tx_req_prod)], 
  19.239 +           msg, sizeof(*msg));
  19.240 +    wmb(); /* Write the message before letting the controller peek at it. */
  19.241 +    ctrl_if->tx_req_prod++;
  19.242 +
  19.243 +    mtx_unlock_irqrestore(&ctrl_if_lock, flags);
  19.244 +
  19.245 +    ctrl_if_notify_controller();
  19.246 +
  19.247 +    return 0;
  19.248 +}
  19.249 +
  19.250 +int 
  19.251 +ctrl_if_send_message_block(
  19.252 +    ctrl_msg_t *msg, 
  19.253 +    ctrl_msg_handler_t hnd, 
  19.254 +    unsigned long id,
  19.255 +    long wait_state)
  19.256 +{
  19.257 +    int rc, sst = 0;
  19.258 +
  19.259 +    /* Fast path. */
  19.260 +    if ( (rc = ctrl_if_send_message_noblock(msg, hnd, id)) != EAGAIN )
  19.261 +        return rc;
  19.262 +
  19.263 +
  19.264 +    for ( ; ; )
  19.265 +    {
  19.266 +
  19.267 +        if ( (rc = ctrl_if_send_message_noblock(msg, hnd, id)) != EAGAIN )
  19.268 +            break;
  19.269 +
  19.270 +        if ( sst != 0) 
  19.271 +	    return EINTR;
  19.272 +
  19.273 +        sst = tsleep(ctrl_if_wchan, PWAIT|PCATCH, "ctlrwt", 10);
  19.274 +    }
  19.275 +
  19.276 +    return rc;
  19.277 +}
  19.278 +
  19.279 +int 
  19.280 +ctrl_if_enqueue_space_callback(struct task *task)
  19.281 +{
  19.282 +    control_if_t *ctrl_if = get_ctrl_if();
  19.283 +
  19.284 +    /* Fast path. */
  19.285 +    if ( !TX_FULL(ctrl_if) )
  19.286 +        return 0;
  19.287 +
  19.288 +    (void)taskqueue_enqueue(*taskqueue_ctrl_if_tx[(ctrl_if_idx & 1)], task);
  19.289 +
  19.290 +    /*
  19.291 +     * We may race execution of the task queue, so return re-checked status. If
  19.292 +     * the task is not executed despite the ring being non-full then we will
  19.293 +     * certainly return 'not full'.
  19.294 +     */
  19.295 +    smp_mb();
  19.296 +    return TX_FULL(ctrl_if);
  19.297 +}
  19.298 +
  19.299 +void 
  19.300 +ctrl_if_send_response(ctrl_msg_t *msg)
  19.301 +{
  19.302 +    control_if_t *ctrl_if = get_ctrl_if();
  19.303 +    unsigned long flags;
  19.304 +    ctrl_msg_t   *dmsg;
  19.305 +
  19.306 +    /*
  19.307 +     * NB. The response may the original request message, modified in-place.
  19.308 +     * In this situation we may have src==dst, so no copying is required.
  19.309 +     */
  19.310 +    mtx_lock_irqsave(&ctrl_if_lock, flags);
  19.311 +    dmsg = &ctrl_if->rx_ring[MASK_CONTROL_IDX(ctrl_if->rx_resp_prod)];
  19.312 +    if ( dmsg != msg )
  19.313 +        memcpy(dmsg, msg, sizeof(*msg));
  19.314 +    wmb(); /* Write the message before letting the controller peek at it. */
  19.315 +    ctrl_if->rx_resp_prod++;
  19.316 +    mtx_unlock_irqrestore(&ctrl_if_lock, flags);
  19.317 +
  19.318 +    ctrl_if_notify_controller();
  19.319 +}
  19.320 +
  19.321 +int 
  19.322 +ctrl_if_register_receiver(
  19.323 +    uint8_t type, 
  19.324 +    ctrl_msg_handler_t hnd, 
  19.325 +    unsigned int flags)
  19.326 +{
  19.327 +    unsigned long _flags;
  19.328 +    int inuse;
  19.329 +
  19.330 +    mtx_lock_irqsave(&ctrl_if_lock, _flags);
  19.331 +
  19.332 +    inuse = (ctrl_if_rxmsg_handler[type] != ctrl_if_rxmsg_default_handler);
  19.333 +
  19.334 +    if ( inuse )
  19.335 +    {
  19.336 +        printk("Receiver %p already established for control "
  19.337 +               "messages of type %d.\n", ctrl_if_rxmsg_handler[type], type);
  19.338 +    }
  19.339 +    else
  19.340 +    {
  19.341 +        ctrl_if_rxmsg_handler[type] = hnd;
  19.342 +        clear_bit(type, &ctrl_if_rxmsg_blocking_context);
  19.343 +        if ( flags == CALLBACK_IN_BLOCKING_CONTEXT )
  19.344 +        {
  19.345 +            set_bit(type, &ctrl_if_rxmsg_blocking_context);
  19.346 +        }
  19.347 +    }
  19.348 +
  19.349 +    mtx_unlock_irqrestore(&ctrl_if_lock, _flags);
  19.350 +
  19.351 +    return !inuse;
  19.352 +}
  19.353 +
  19.354 +void 
  19.355 +ctrl_if_unregister_receiver(uint8_t type, ctrl_msg_handler_t hnd)
  19.356 +{
  19.357 +    unsigned long flags;
  19.358 +
  19.359 +    mtx_lock_irqsave(&ctrl_if_lock, flags);
  19.360 +
  19.361 +    if ( ctrl_if_rxmsg_handler[type] != hnd )
  19.362 +        printk("Receiver %p is not registered for control "
  19.363 +               "messages of type %d.\n", hnd, type);
  19.364 +    else
  19.365 +        ctrl_if_rxmsg_handler[type] = ctrl_if_rxmsg_default_handler;
  19.366 +
  19.367 +    mtx_unlock_irqrestore(&ctrl_if_lock, flags);
  19.368 +
  19.369 +    /* Ensure that @hnd will not be executed after this function returns. */
  19.370 +    /* XXX need rx_tasklet_lock -- can cheat for now?*/
  19.371 +#ifdef notyet
  19.372 +    tasklet_unlock_wait(&ctrl_if_rx_tasklet);
  19.373 +#endif
  19.374 +}
  19.375 +
  19.376 +void 
  19.377 +ctrl_if_suspend(void)
  19.378 +{
  19.379 +    /* I'm not sure what the equivalent is - we aren't going to support suspend 
  19.380 +     * yet anyway 
  19.381 +     */
  19.382 +#ifdef notyet
  19.383 +    free_irq(ctrl_if_irq, NULL);
  19.384 +#endif
  19.385 +    unbind_evtchn_from_irq(ctrl_if_evtchn);
  19.386 +}
  19.387 + 
  19.388 +/** Reset the control interface progress pointers.
  19.389 + * Marks the queues empty if 'clear' non-zero.
  19.390 + */
  19.391 +static void 
  19.392 +ctrl_if_reset(int clear)
  19.393 +{
  19.394 +    control_if_t *ctrl_if = get_ctrl_if();
  19.395 +
  19.396 +    if (clear) {
  19.397 +	*ctrl_if = (control_if_t){};
  19.398 +    }
  19.399 +    
  19.400 +    ctrl_if_tx_resp_cons = ctrl_if->tx_resp_prod;
  19.401 +    ctrl_if_rx_req_cons  = ctrl_if->rx_resp_prod;
  19.402 +}
  19.403 +
  19.404 +
  19.405 +void 
  19.406 +ctrl_if_resume(void)
  19.407 +{
  19.408 +    if ( xen_start_info->flags & SIF_INITDOMAIN )
  19.409 +    {
  19.410 +        /*
  19.411 +         * The initial domain must create its own domain-controller link.
  19.412 +         * The controller is probably not running at this point, but will
  19.413 +         * pick up its end of the event channel from 
  19.414 +         */
  19.415 +        evtchn_op_t op;
  19.416 +        op.cmd = EVTCHNOP_bind_interdomain;
  19.417 +        op.u.bind_interdomain.dom1 = DOMID_SELF;
  19.418 +        op.u.bind_interdomain.dom2 = DOMID_SELF;
  19.419 +        op.u.bind_interdomain.port1 = 0;
  19.420 +        op.u.bind_interdomain.port2 = 0;
  19.421 +        if ( HYPERVISOR_event_channel_op(&op) != 0 )
  19.422 +            panic("event_channel_op failed\n");
  19.423 +        xen_start_info->domain_controller_evtchn = op.u.bind_interdomain.port1;
  19.424 +        initdom_ctrlif_domcontroller_port   = op.u.bind_interdomain.port2;
  19.425 +    }
  19.426 +    
  19.427 +    ctrl_if_reset(0);
  19.428 +
  19.429 +    ctrl_if_evtchn = xen_start_info->domain_controller_evtchn;
  19.430 +    ctrl_if_irq    = bind_evtchn_to_irq(ctrl_if_evtchn);
  19.431 +    
  19.432 +    /*
  19.433 +     * I have not taken the time to determine what the interrupt thread priorities
  19.434 +     * correspond to - this interface is used for network and disk, network would
  19.435 +     * seem higher priority, hence I'm using it
  19.436 +     */
  19.437 +
  19.438 +    intr_add_handler("ctrl-if", ctrl_if_irq, (driver_intr_t*)ctrl_if_interrupt,
  19.439 +		     NULL, INTR_TYPE_NET | INTR_MPSAFE, NULL);
  19.440 +}
  19.441 +
  19.442 +static void 
  19.443 +ctrl_if_init(void *dummy __unused)
  19.444 +{
  19.445 +    int i;
  19.446 +
  19.447 +    for ( i = 0; i < 256; i++ )
  19.448 +        ctrl_if_rxmsg_handler[i] = ctrl_if_rxmsg_default_handler;
  19.449 +    
  19.450 +    mtx_init(&ctrl_if_lock, "ctrlif", NULL, MTX_SPIN | MTX_NOWITNESS);
  19.451 +    
  19.452 +    TASK_INIT(&ctrl_if_tx_tasklet, 0, __ctrl_if_tx_tasklet, NULL);
  19.453 +
  19.454 +    TASK_INIT(&ctrl_if_rx_tasklet, 0, __ctrl_if_rx_tasklet, NULL);
  19.455 +
  19.456 +    TASK_INIT(&ctrl_if_rxmsg_deferred_task, 0, __ctrl_if_rxmsg_deferred_task, NULL);
  19.457 +
  19.458 +    ctrl_if_reset(1);
  19.459 +    ctrl_if_resume();
  19.460 +}
  19.461 +
  19.462 +/*
  19.463 + * !! The following are DANGEROUS FUNCTIONS !!
  19.464 + * Use with care [for example, see xencons_force_flush()].
  19.465 + */
  19.466 +
  19.467 +int 
  19.468 +ctrl_if_transmitter_empty(void)
  19.469 +{
  19.470 +    return (get_ctrl_if()->tx_req_prod == ctrl_if_tx_resp_cons);
  19.471 +}
  19.472 +
  19.473 +void 
  19.474 +ctrl_if_discard_responses(void)
  19.475 +{
  19.476 +    ctrl_if_tx_resp_cons = get_ctrl_if()->tx_resp_prod;
  19.477 +}
  19.478 +
  19.479 +SYSINIT(ctrl_if_init, SI_SUB_DRIVERS, SI_ORDER_FIRST, ctrl_if_init, NULL);
    20.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/db_interface.c	Mon Mar 21 07:58:08 2005 +0000
    20.3 @@ -0,0 +1,209 @@
    20.4 +/*
    20.5 + * Mach Operating System
    20.6 + * Copyright (c) 1991,1990 Carnegie Mellon University
    20.7 + * All Rights Reserved.
    20.8 + *
    20.9 + * Permission to use, copy, modify and distribute this software and its
   20.10 + * documentation is hereby granted, provided that both the copyright
   20.11 + * notice and this permission notice appear in all copies of the
   20.12 + * software, derivative works or modified versions, and any portions
   20.13 + * thereof, and that both notices appear in supporting documentation.
   20.14 + *
   20.15 + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
   20.16 + * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
   20.17 + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   20.18 + *
   20.19 + * Carnegie Mellon requests users of this software to return to
   20.20 + *
   20.21 + *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   20.22 + *  School of Computer Science
   20.23 + *  Carnegie Mellon University
   20.24 + *  Pittsburgh PA 15213-3890
   20.25 + *
   20.26 + * any improvements or extensions that they make and grant Carnegie the
   20.27 + * rights to redistribute these changes.
   20.28 + */
   20.29 +
   20.30 +#include <sys/cdefs.h>
   20.31 +__FBSDID("$FreeBSD: src/sys/i386/i386/db_interface.c,v 1.77 2003/11/08 03:01:26 alc Exp $");
   20.32 +
   20.33 +/*
   20.34 + * Interface to new debugger.
   20.35 + */
   20.36 +#include <sys/param.h>
   20.37 +#include <sys/systm.h>
   20.38 +#include <sys/reboot.h>
   20.39 +#include <sys/cons.h>
   20.40 +#include <sys/pcpu.h>
   20.41 +#include <sys/proc.h>
   20.42 +#include <sys/smp.h>
   20.43 +
   20.44 +#include <machine/cpu.h>
   20.45 +#ifdef SMP
   20.46 +#include <machine/smptests.h>	/** CPUSTOP_ON_DDBBREAK */
   20.47 +#endif
   20.48 +
   20.49 +#include <vm/vm.h>
   20.50 +#include <vm/pmap.h>
   20.51 +
   20.52 +#include <ddb/ddb.h>
   20.53 +
   20.54 +#include <machine/setjmp.h>
   20.55 +#include <machine/xenfunc.h>
   20.56 +
   20.57 +
   20.58 +static jmp_buf *db_nofault = 0;
   20.59 +extern jmp_buf	db_jmpbuf;
   20.60 +
   20.61 +extern void	gdb_handle_exception(db_regs_t *, int, int);
   20.62 +
   20.63 +int	db_active;
   20.64 +db_regs_t ddb_regs;
   20.65 +
   20.66 +static __inline u_short
   20.67 +rss(void)
   20.68 +{
   20.69 +	u_short ss;
   20.70 +#ifdef __GNUC__
   20.71 +	__asm __volatile("mov %%ss,%0" : "=r" (ss));
   20.72 +#else
   20.73 +	ss = 0; /* XXXX Fix for other compilers. */
   20.74 +#endif
   20.75 +	return ss;
   20.76 +}
   20.77 +
   20.78 +/*
   20.79 + *  kdb_trap - field a TRACE or BPT trap
   20.80 + */
   20.81 +int
   20.82 +kdb_trap(int type, int code, struct i386_saved_state *regs)
   20.83 +{
   20.84 +	volatile int ddb_mode = !(boothowto & RB_GDB);
   20.85 +
   20.86 +	disable_intr();
   20.87 +
   20.88 +	if (ddb_mode) {
   20.89 +	    	/* we can't do much as a guest domain except print a 
   20.90 +		 * backtrace and die gracefuly.  The reason is that we
   20.91 +		 * can't get character input to make this work.
   20.92 +		 */
   20.93 +	    	db_active = 1;
   20.94 +		db_print_backtrace(); 
   20.95 +		db_printf("************ Domain shutting down ************\n");
   20.96 +		HYPERVISOR_shutdown();
   20.97 +	} else {
   20.98 +	    	Debugger("kdb_trap");
   20.99 +	}
  20.100 +	return (1);
  20.101 +}
  20.102 +
  20.103 +/*
  20.104 + * Read bytes from kernel address space for debugger.
  20.105 + */
  20.106 +void
  20.107 +db_read_bytes(vm_offset_t addr, size_t size, char *data)
  20.108 +{
  20.109 +	char	*src;
  20.110 +
  20.111 +	db_nofault = &db_jmpbuf;
  20.112 +
  20.113 +	src = (char *)addr;
  20.114 +	while (size-- > 0)
  20.115 +	    *data++ = *src++;
  20.116 +
  20.117 +	db_nofault = 0;
  20.118 +}
  20.119 +
  20.120 +/*
  20.121 + * Write bytes to kernel address space for debugger.
  20.122 + */
  20.123 +void
  20.124 +db_write_bytes(vm_offset_t addr, size_t size, char *data)
  20.125 +{
  20.126 +	char	*dst;
  20.127 +
  20.128 +	pt_entry_t	*ptep0 = NULL;
  20.129 +	pt_entry_t	oldmap0 = 0;
  20.130 +	vm_offset_t	addr1;
  20.131 +	pt_entry_t	*ptep1 = NULL;
  20.132 +	pt_entry_t	oldmap1 = 0;
  20.133 +
  20.134 +	db_nofault = &db_jmpbuf;
  20.135 +
  20.136 +	if (addr > trunc_page((vm_offset_t)btext) - size &&
  20.137 +	    addr < round_page((vm_offset_t)etext)) {
  20.138 +
  20.139 +	    ptep0 = pmap_pte(kernel_pmap, addr);
  20.140 +	    oldmap0 = *ptep0;
  20.141 +	    *ptep0 |= PG_RW;
  20.142 +
  20.143 +	    /* Map another page if the data crosses a page boundary. */
  20.144 +	    if ((*ptep0 & PG_PS) == 0) {
  20.145 +	    	addr1 = trunc_page(addr + size - 1);
  20.146 +	    	if (trunc_page(addr) != addr1) {
  20.147 +		    ptep1 = pmap_pte(kernel_pmap, addr1);
  20.148 +		    oldmap1 = *ptep1;
  20.149 +		    *ptep1 |= PG_RW;
  20.150 +	    	}
  20.151 +	    } else {
  20.152 +		addr1 = trunc_4mpage(addr + size - 1);
  20.153 +		if (trunc_4mpage(addr) != addr1) {
  20.154 +		    ptep1 = pmap_pte(kernel_pmap, addr1);
  20.155 +		    oldmap1 = *ptep1;
  20.156 +		    *ptep1 |= PG_RW;
  20.157 +		}
  20.158 +	    }
  20.159 +
  20.160 +	    invltlb();
  20.161 +	}
  20.162 +
  20.163 +	dst = (char *)addr;
  20.164 +
  20.165 +	while (size-- > 0)
  20.166 +	    *dst++ = *data++;
  20.167 +
  20.168 +	db_nofault = 0;
  20.169 +
  20.170 +	if (ptep0) {
  20.171 +	    *ptep0 = oldmap0;
  20.172 +
  20.173 +	    if (ptep1)
  20.174 +		*ptep1 = oldmap1;
  20.175 +
  20.176 +	    invltlb();
  20.177 +	}
  20.178 +}
  20.179 +
  20.180 +/*
  20.181 + * XXX
  20.182 + * Move this to machdep.c and allow it to be called if any debugger is
  20.183 + * installed.
  20.184 + */
  20.185 +void
  20.186 +Debugger(const char *msg)
  20.187 +{
  20.188 +	static volatile u_int in_Debugger;
  20.189 +
  20.190 +	/*
  20.191 +	 * XXX
  20.192 +	 * Do nothing if the console is in graphics mode.  This is
  20.193 +	 * OK if the call is for the debugger hotkey but not if the call
  20.194 +	 * is a weak form of panicing.
  20.195 +	 */
  20.196 +	if (cons_unavail && !(boothowto & RB_GDB))
  20.197 +	    return;
  20.198 +
  20.199 +	if (atomic_cmpset_acq_int(&in_Debugger, 0, 1)) {
  20.200 +	    db_printf("Debugger(\"%s\")\n", msg);
  20.201 +	    breakpoint();
  20.202 +	    atomic_store_rel_int(&in_Debugger, 0);
  20.203 +	}
  20.204 +}
  20.205 +
  20.206 +void
  20.207 +db_show_mdpcpu(struct pcpu *pc)
  20.208 +{
  20.209 +
  20.210 +	db_printf("APIC ID      = %d\n", pc->pc_apic_id);
  20.211 +	db_printf("currentldt   = 0x%x\n", pc->pc_currentldt);
  20.212 +}
    21.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/evtchn.c	Mon Mar 21 07:58:08 2005 +0000
    21.3 @@ -0,0 +1,580 @@
    21.4 +/******************************************************************************
    21.5 + * evtchn.c
    21.6 + * 
    21.7 + * Communication via Xen event channels.
    21.8 + * 
    21.9 + * Copyright (c) 2002-2004, K A Fraser
   21.10 + */
   21.11 +#include <sys/param.h>
   21.12 +#include <sys/systm.h>
   21.13 +#include <sys/bus.h>
   21.14 +#include <sys/malloc.h>
   21.15 +#include <sys/kernel.h>
   21.16 +#include <sys/lock.h>
   21.17 +#include <sys/mutex.h>
   21.18 +
   21.19 +#include <machine/cpufunc.h>
   21.20 +#include <machine/intr_machdep.h>
   21.21 +#include <machine/xen-os.h>
   21.22 +#include <machine/xen_intr.h>
   21.23 +#include <machine/synch_bitops.h>
   21.24 +#include <machine/evtchn.h>
   21.25 +#include <machine/hypervisor.h>
   21.26 +#include <machine/hypervisor-ifs.h>
   21.27 +
   21.28 +
   21.29 +static struct mtx irq_mapping_update_lock;
   21.30 +
   21.31 +#define TODO            printf("%s: not implemented!\n", __func__) 
   21.32 +
   21.33 +/* IRQ <-> event-channel mappings. */
   21.34 +static int evtchn_to_irq[NR_EVENT_CHANNELS];
   21.35 +static int irq_to_evtchn[NR_IRQS];
   21.36 +
   21.37 +/* IRQ <-> VIRQ mapping. */
   21.38 +static int virq_to_irq[NR_VIRQS];
   21.39 +
   21.40 +/* Reference counts for bindings to IRQs. */
   21.41 +static int irq_bindcount[NR_IRQS];
   21.42 +
   21.43 +#define VALID_EVTCHN(_chn) ((_chn) != -1)
   21.44 +
   21.45 +/*
   21.46 + * Force a proper event-channel callback from Xen after clearing the
   21.47 + * callback mask. We do this in a very simple manner, by making a call
   21.48 + * down into Xen. The pending flag will be checked by Xen on return.
   21.49 + */
   21.50 +void force_evtchn_callback(void)
   21.51 +{
   21.52 +    (void)HYPERVISOR_xen_version(0);
   21.53 +}
   21.54 +
   21.55 +void 
   21.56 +evtchn_do_upcall(struct intrframe *frame) 
   21.57 +{
   21.58 +    unsigned long  l1, l2;
   21.59 +    unsigned int   l1i, l2i, port;
   21.60 +    int            irq, owned;
   21.61 +    unsigned long  flags;
   21.62 +    shared_info_t *s = HYPERVISOR_shared_info;
   21.63 +
   21.64 +    local_irq_save(flags);
   21.65 +
   21.66 +    while ( s->vcpu_data[0].evtchn_upcall_pending )
   21.67 +    {
   21.68 +        s->vcpu_data[0].evtchn_upcall_pending = 0;
   21.69 +        /* NB. No need for a barrier here -- XCHG is a barrier on x86. */
   21.70 +        l1 = xen_xchg(&s->evtchn_pending_sel, 0);
   21.71 +        while ( (l1i = ffs(l1)) != 0 )
   21.72 +        {
   21.73 +            l1i--;
   21.74 +            l1 &= ~(1 << l1i);
   21.75 +        
   21.76 +            l2 = s->evtchn_pending[l1i] & ~s->evtchn_mask[l1i];
   21.77 +            while ( (l2i = ffs(l2)) != 0 )
   21.78 +            {
   21.79 +                l2i--;
   21.80 +                l2 &= ~(1 << l2i);
   21.81 +            
   21.82 +                port = (l1i << 5) + l2i;
   21.83 +		if ((owned = mtx_owned(&sched_lock)) != 0)
   21.84 +		    mtx_unlock_spin_flags(&sched_lock, MTX_QUIET);
   21.85 +                if ( (irq = evtchn_to_irq[port]) != -1 ) {
   21.86 +		    struct intsrc *isrc = intr_lookup_source(irq);
   21.87 +		    intr_execute_handlers(isrc, frame);
   21.88 +
   21.89 +		} else {
   21.90 +                    evtchn_device_upcall(port);
   21.91 +		}
   21.92 +		if (owned)
   21.93 +		    mtx_lock_spin_flags(&sched_lock, MTX_QUIET);
   21.94 +            }
   21.95 +        }
   21.96 +    }
   21.97 +
   21.98 +    local_irq_restore(flags);
   21.99 +
  21.100 +}
  21.101 +
  21.102 +
  21.103 +static int 
  21.104 +find_unbound_irq(void)
  21.105 +{
  21.106 +    int irq;
  21.107 +
  21.108 +    for ( irq = 0; irq < NR_IRQS; irq++ )
  21.109 +        if ( irq_bindcount[irq] == 0 )
  21.110 +            break;
  21.111 +
  21.112 +    if ( irq == NR_IRQS )
  21.113 +        panic("No available IRQ to bind to: increase NR_IRQS!\n");
  21.114 +
  21.115 +    return irq;
  21.116 +}
  21.117 +
  21.118 +int 
  21.119 +bind_virq_to_irq(int virq)
  21.120 +{
  21.121 +    evtchn_op_t op;
  21.122 +    int evtchn, irq;
  21.123 +
  21.124 +    mtx_lock(&irq_mapping_update_lock);
  21.125 +
  21.126 +    if ( (irq = virq_to_irq[virq]) == -1 )
  21.127 +    {
  21.128 +        op.cmd              = EVTCHNOP_bind_virq;
  21.129 +        op.u.bind_virq.virq = virq;
  21.130 +        if ( HYPERVISOR_event_channel_op(&op) != 0 )
  21.131 +            panic("Failed to bind virtual IRQ %d\n", virq);
  21.132 +        evtchn = op.u.bind_virq.port;
  21.133 +
  21.134 +        irq = find_unbound_irq();
  21.135 +        evtchn_to_irq[evtchn] = irq;
  21.136 +        irq_to_evtchn[irq]    = evtchn;
  21.137 +
  21.138 +        virq_to_irq[virq] = irq;
  21.139 +    }
  21.140 +
  21.141 +    irq_bindcount[irq]++;
  21.142 +
  21.143 +    mtx_unlock(&irq_mapping_update_lock);
  21.144 +    
  21.145 +    return irq;
  21.146 +}
  21.147 +
  21.148 +void 
  21.149 +unbind_virq_from_irq(int virq)
  21.150 +{
  21.151 +    evtchn_op_t op;
  21.152 +    int irq    = virq_to_irq[virq];
  21.153 +    int evtchn = irq_to_evtchn[irq];
  21.154 +
  21.155 +    mtx_lock(&irq_mapping_update_lock);
  21.156 +
  21.157 +    if ( --irq_bindcount[irq] == 0 )
  21.158 +    {
  21.159 +        op.cmd          = EVTCHNOP_close;
  21.160 +        op.u.close.dom  = DOMID_SELF;
  21.161 +        op.u.close.port = evtchn;
  21.162 +        if ( HYPERVISOR_event_channel_op(&op) != 0 )
  21.163 +            panic("Failed to unbind virtual IRQ %d\n", virq);
  21.164 +
  21.165 +        evtchn_to_irq[evtchn] = -1;
  21.166 +        irq_to_evtchn[irq]    = -1;
  21.167 +        virq_to_irq[virq]     = -1;
  21.168 +    }
  21.169 +
  21.170 +    mtx_unlock(&irq_mapping_update_lock);
  21.171 +}
  21.172 +
  21.173 +int 
  21.174 +bind_evtchn_to_irq(int evtchn)
  21.175 +{
  21.176 +    int irq;
  21.177 +
  21.178 +    mtx_lock(&irq_mapping_update_lock);
  21.179 +
  21.180 +    if ( (irq = evtchn_to_irq[evtchn]) == -1 )
  21.181 +    {
  21.182 +        irq = find_unbound_irq();
  21.183 +        evtchn_to_irq[evtchn] = irq;
  21.184 +        irq_to_evtchn[irq]    = evtchn;
  21.185 +    }
  21.186 +
  21.187 +    irq_bindcount[irq]++;
  21.188 +
  21.189 +    mtx_unlock(&irq_mapping_update_lock);
  21.190 +    
  21.191 +    return irq;
  21.192 +}
  21.193 +
  21.194 +void 
  21.195 +unbind_evtchn_from_irq(int evtchn)
  21.196 +{
  21.197 +    int irq = evtchn_to_irq[evtchn];
  21.198 +
  21.199 +    mtx_lock(&irq_mapping_update_lock);
  21.200 +
  21.201 +    if ( --irq_bindcount[irq] == 0 )
  21.202 +    {
  21.203 +        evtchn_to_irq[evtchn] = -1;
  21.204 +        irq_to_evtchn[irq]    = -1;
  21.205 +    }
  21.206 +
  21.207 +    mtx_unlock(&irq_mapping_update_lock);
  21.208 +}
  21.209 +
  21.210 +
  21.211 +/*
  21.212 + * Interface to generic handling in intr_machdep.c
  21.213 + */
  21.214 +
  21.215 +
  21.216 +/*------------ interrupt handling --------------------------------------*/
  21.217 +#define TODO            printf("%s: not implemented!\n", __func__) 
  21.218 +
  21.219 + struct mtx xenpic_lock;
  21.220 +
  21.221 +struct xenpic_intsrc {
  21.222 +    struct intsrc xp_intsrc;
  21.223 +    uint8_t       xp_vector;
  21.224 +    boolean_t	  xp_masked;
  21.225 +};
  21.226 +
  21.227 +struct xenpic { 
  21.228 +    struct pic xp_pic; /* this MUST be first */
  21.229 +    uint16_t xp_numintr; 
  21.230 +    struct xenpic_intsrc xp_pins[0]; 
  21.231 +}; 
  21.232 +
  21.233 +static void     xenpic_enable_dynirq_source(struct intsrc *isrc); 
  21.234 +static void     xenpic_disable_dynirq_source(struct intsrc *isrc, int); 
  21.235 +static void     xenpic_eoi_source(struct intsrc *isrc); 
  21.236 +static void     xenpic_enable_dynirq_intr(struct intsrc *isrc); 
  21.237 +static int      xenpic_vector(struct intsrc *isrc); 
  21.238 +static int      xenpic_source_pending(struct intsrc *isrc); 
  21.239 +static void     xenpic_suspend(struct intsrc *isrc); 
  21.240 +static void     xenpic_resume(struct intsrc *isrc); 
  21.241 +
  21.242 +
  21.243 +struct pic xenpic_template  =  { 
  21.244 +    xenpic_enable_dynirq_source, 
  21.245 +    xenpic_disable_dynirq_source,
  21.246 +    xenpic_eoi_source, 
  21.247 +    xenpic_enable_dynirq_intr, 
  21.248 +    xenpic_vector, 
  21.249 +    xenpic_source_pending,
  21.250 +    xenpic_suspend, 
  21.251 +    xenpic_resume 
  21.252 +};
  21.253 +
  21.254 +
  21.255 +void 
  21.256 +xenpic_enable_dynirq_source(struct intsrc *isrc)
  21.257 +{
  21.258 +    unsigned int irq;
  21.259 +    struct xenpic_intsrc *xp;
  21.260 +
  21.261 +    xp = (struct xenpic_intsrc *)isrc;
  21.262 +
  21.263 +    if (xp->xp_masked) {
  21.264 +	irq = xenpic_vector(isrc);
  21.265 +	unmask_evtchn(irq_to_evtchn[irq]);
  21.266 +	xp->xp_masked = FALSE;
  21.267 +    }
  21.268 +}
  21.269 +
  21.270 +static void 
  21.271 +xenpic_disable_dynirq_source(struct intsrc *isrc, int foo)
  21.272 +{
  21.273 +    unsigned int irq;
  21.274 +    struct xenpic_intsrc *xp;
  21.275 +
  21.276 +    xp = (struct xenpic_intsrc *)isrc;
  21.277 +
  21.278 +    if (!xp->xp_masked) {
  21.279 +	irq = xenpic_vector(isrc);
  21.280 +	mask_evtchn(irq_to_evtchn[irq]);
  21.281 +	xp->xp_masked = TRUE;
  21.282 +    }
  21.283 +
  21.284 +}
  21.285 +
  21.286 +static void 
  21.287 +xenpic_enable_dynirq_intr(struct intsrc *isrc)
  21.288 +{
  21.289 +    unsigned int irq;
  21.290 +
  21.291 +    irq = xenpic_vector(isrc);
  21.292 +    unmask_evtchn(irq_to_evtchn[irq]);
  21.293 +}
  21.294 +
  21.295 +static void 
  21.296 +xenpic_eoi_source(struct intsrc *isrc)
  21.297 +{
  21.298 +    unsigned int irq = xenpic_vector(isrc);
  21.299 +    clear_evtchn(irq_to_evtchn[irq]);
  21.300 +}
  21.301 +
  21.302 +static int
  21.303 +xenpic_vector(struct intsrc *isrc)
  21.304 +{
  21.305 +    struct xenpic_intsrc *pin = (struct xenpic_intsrc *)isrc;
  21.306 +    return (pin->xp_vector);
  21.307 +}
  21.308 +
  21.309 +static int
  21.310 +xenpic_source_pending(struct intsrc *isrc)
  21.311 +{
  21.312 +    TODO;
  21.313 +    return 0;
  21.314 +}
  21.315 +
  21.316 +static void 
  21.317 +xenpic_suspend(struct intsrc *isrc) 
  21.318 +{ 
  21.319 +    TODO; 
  21.320 +} 
  21.321 + 
  21.322 +static void 
  21.323 +xenpic_resume(struct intsrc *isrc) 
  21.324 +{ 
  21.325 +    TODO; 
  21.326 +} 
  21.327 +
  21.328 +#ifdef CONFIG_PHYSDEV
  21.329 +/* required for support of physical devices */
  21.330 +static inline void 
  21.331 +pirq_unmask_notify(int pirq)
  21.332 +{
  21.333 +    physdev_op_t op;
  21.334 +    if ( unlikely(test_bit(pirq, &pirq_needs_unmask_notify[0])) )
  21.335 +    {
  21.336 +        op.cmd = PHYSDEVOP_IRQ_UNMASK_NOTIFY;
  21.337 +        (void)HYPERVISOR_physdev_op(&op);
  21.338 +    }
  21.339 +}
  21.340 +
  21.341 +static inline void 
  21.342 +pirq_query_unmask(int pirq)
  21.343 +{
  21.344 +    physdev_op_t op;
  21.345 +    op.cmd = PHYSDEVOP_IRQ_STATUS_QUERY;
  21.346 +    op.u.irq_status_query.irq = pirq;
  21.347 +    (void)HYPERVISOR_physdev_op(&op);
  21.348 +    clear_bit(pirq, &pirq_needs_unmask_notify[0]);
  21.349 +    if ( op.u.irq_status_query.flags & PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY )
  21.350 +        set_bit(pirq, &pirq_needs_unmask_notify[0]);
  21.351 +}
  21.352 +
  21.353 +/*
  21.354 + * On startup, if there is no action associated with the IRQ then we are
  21.355 + * probing. In this case we should not share with others as it will confuse us.
  21.356 + */
  21.357 +#define probing_irq(_irq) (irq_desc[(_irq)].action == NULL)
  21.358 +
  21.359 +static unsigned int startup_pirq(unsigned int irq)
  21.360 +{
  21.361 +    evtchn_op_t op;
  21.362 +    int evtchn;
  21.363 +
  21.364 +    op.cmd               = EVTCHNOP_bind_pirq;
  21.365 +    op.u.bind_pirq.pirq  = irq;
  21.366 +    /* NB. We are happy to share unless we are probing. */
  21.367 +    op.u.bind_pirq.flags = probing_irq(irq) ? 0 : BIND_PIRQ__WILL_SHARE;
  21.368 +    if ( HYPERVISOR_event_channel_op(&op) != 0 )
  21.369 +    {
  21.370 +        if ( !probing_irq(irq) ) /* Some failures are expected when probing. */
  21.371 +            printk(KERN_INFO "Failed to obtain physical IRQ %d\n", irq);
  21.372 +        return 0;
  21.373 +    }
  21.374 +    evtchn = op.u.bind_pirq.port;
  21.375 +
  21.376 +    pirq_query_unmask(irq_to_pirq(irq));
  21.377 +
  21.378 +    evtchn_to_irq[evtchn] = irq;
  21.379 +    irq_to_evtchn[irq]    = evtchn;
  21.380 +
  21.381 +    unmask_evtchn(evtchn);
  21.382 +    pirq_unmask_notify(irq_to_pirq(irq));
  21.383 +
  21.384 +    return 0;
  21.385 +}
  21.386 +
  21.387 +static void shutdown_pirq(unsigned int irq)
  21.388 +{
  21.389 +    evtchn_op_t op;
  21.390 +    int evtchn = irq_to_evtchn[irq];
  21.391 +
  21.392 +    if ( !VALID_EVTCHN(evtchn) )
  21.393 +        return;
  21.394 +
  21.395 +    mask_evtchn(evtchn);
  21.396 +
  21.397 +    op.cmd          = EVTCHNOP_close;
  21.398 +    op.u.close.dom  = DOMID_SELF;
  21.399 +    op.u.close.port = evtchn;
  21.400 +    if ( HYPERVISOR_event_channel_op(&op) != 0 )
  21.401 +        panic("Failed to unbind physical IRQ %d\n", irq);
  21.402 +
  21.403 +    evtchn_to_irq[evtchn] = -1;
  21.404 +    irq_to_evtchn[irq]    = -1;
  21.405 +}
  21.406 +
  21.407 +static void enable_pirq(unsigned int irq)
  21.408 +{
  21.409 +    int evtchn = irq_to_evtchn[irq];
  21.410 +    if ( !VALID_EVTCHN(evtchn) )
  21.411 +        return;
  21.412 +    unmask_evtchn(evtchn);
  21.413 +    pirq_unmask_notify(irq_to_pirq(irq));
  21.414 +}
  21.415 +
  21.416 +static void disable_pirq(unsigned int irq)
  21.417 +{
  21.418 +    int evtchn = irq_to_evtchn[irq];
  21.419 +    if ( !VALID_EVTCHN(evtchn) )
  21.420 +        return;
  21.421 +    mask_evtchn(evtchn);
  21.422 +}
  21.423 +
  21.424 +static void ack_pirq(unsigned int irq)
  21.425 +{
  21.426 +    int evtchn = irq_to_evtchn[irq];
  21.427 +    if ( !VALID_EVTCHN(evtchn) )
  21.428 +        return;
  21.429 +    mask_evtchn(evtchn);
  21.430 +    clear_evtchn(evtchn);
  21.431 +}
  21.432 +
  21.433 +static void end_pirq(unsigned int irq)
  21.434 +{
  21.435 +    int evtchn = irq_to_evtchn[irq];
  21.436 +    if ( !VALID_EVTCHN(evtchn) )
  21.437 +        return;
  21.438 +    if ( !(irq_desc[irq].status & IRQ_DISABLED) )
  21.439 +    {
  21.440 +        unmask_evtchn(evtchn);
  21.441 +        pirq_unmask_notify(irq_to_pirq(irq));
  21.442 +    }
  21.443 +}
  21.444 +
  21.445 +static struct hw_interrupt_type pirq_type = {
  21.446 +    "Phys-irq",
  21.447 +    startup_pirq,
  21.448 +    shutdown_pirq,
  21.449 +    enable_pirq,
  21.450 +    disable_pirq,
  21.451 +    ack_pirq,
  21.452 +    end_pirq,
  21.453 +    NULL
  21.454 +};
  21.455 +#endif
  21.456 +
  21.457 +
  21.458 +static void 
  21.459 +misdirect_interrupt(void *sc)
  21.460 +{
  21.461 +}
  21.462 +
  21.463 +void irq_suspend(void)
  21.464 +{
  21.465 +    int virq, irq, evtchn;
  21.466 +
  21.467 +    /* Unbind VIRQs from event channels. */
  21.468 +    for ( virq = 0; virq < NR_VIRQS; virq++ )
  21.469 +    {
  21.470 +        if ( (irq = virq_to_irq[virq]) == -1 )
  21.471 +            continue;
  21.472 +        evtchn = irq_to_evtchn[irq];
  21.473 +
  21.474 +        /* Mark the event channel as unused in our table. */
  21.475 +        evtchn_to_irq[evtchn] = -1;
  21.476 +        irq_to_evtchn[irq]    = -1;
  21.477 +    }
  21.478 +
  21.479 +    /*
  21.480 +     * We should now be unbound from all event channels. Stale bindings to 
  21.481 +     * PIRQs and/or inter-domain event channels will cause us to barf here.
  21.482 +     */
  21.483 +    for ( evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++ )
  21.484 +        if ( evtchn_to_irq[evtchn] != -1 )
  21.485 +            panic("Suspend attempted while bound to evtchn %d.\n", evtchn);
  21.486 +}
  21.487 +
  21.488 +
  21.489 +void irq_resume(void)
  21.490 +{
  21.491 +    evtchn_op_t op;
  21.492 +    int         virq, irq, evtchn;
  21.493 +
  21.494 +    for ( evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++ )
  21.495 +        mask_evtchn(evtchn); /* New event-channel space is not 'live' yet. */
  21.496 +
  21.497 +    for ( virq = 0; virq < NR_VIRQS; virq++ )
  21.498 +    {
  21.499 +        if ( (irq = virq_to_irq[virq]) == -1 )
  21.500 +            continue;
  21.501 +
  21.502 +        /* Get a new binding from Xen. */
  21.503 +        op.cmd              = EVTCHNOP_bind_virq;
  21.504 +        op.u.bind_virq.virq = virq;
  21.505 +        if ( HYPERVISOR_event_channel_op(&op) != 0 )
  21.506 +            panic("Failed to bind virtual IRQ %d\n", virq);
  21.507 +        evtchn = op.u.bind_virq.port;
  21.508 +        
  21.509 +        /* Record the new mapping. */
  21.510 +        evtchn_to_irq[evtchn] = irq;
  21.511 +        irq_to_evtchn[irq]    = evtchn;
  21.512 +
  21.513 +        /* Ready for use. */
  21.514 +        unmask_evtchn(evtchn);
  21.515 +    }
  21.516 +}
  21.517 +
  21.518 +static void 
  21.519 +evtchn_init(void *dummy __unused)
  21.520 +{
  21.521 +    int i;
  21.522 +    struct xenpic *xp;
  21.523 +    struct xenpic_intsrc *pin;
  21.524 +
  21.525 +    /*
  21.526 +     * xenpic_lock: in order to allow an interrupt to occur in a critical
  21.527 +     * 	        section, to set pcpu->ipending (etc...) properly, we
  21.528 +     *	        must be able to get the icu lock, so it can't be
  21.529 +     *	        under witness.
  21.530 +     */
  21.531 +    mtx_init(&irq_mapping_update_lock, "xp", NULL, MTX_DEF);
  21.532 +
  21.533 +    /* No VIRQ -> IRQ mappings. */
  21.534 +    for ( i = 0; i < NR_VIRQS; i++ )
  21.535 +        virq_to_irq[i] = -1;
  21.536 +
  21.537 +    /* No event-channel -> IRQ mappings. */
  21.538 +    for ( i = 0; i < NR_EVENT_CHANNELS; i++ )
  21.539 +    {
  21.540 +        evtchn_to_irq[i] = -1;
  21.541 +        mask_evtchn(i); /* No event channels are 'live' right now. */
  21.542 +    }
  21.543 +
  21.544 +    /* No IRQ -> event-channel mappings. */
  21.545 +    for ( i = 0; i < NR_IRQS; i++ )
  21.546 +        irq_to_evtchn[i] = -1;
  21.547 +
  21.548 +    xp = malloc(sizeof(struct xenpic) + NR_DYNIRQS*sizeof(struct xenpic_intsrc), M_DEVBUF, M_WAITOK);
  21.549 +    xp->xp_pic = xenpic_template;
  21.550 +    xp->xp_numintr = NR_DYNIRQS;
  21.551 +    bzero(xp->xp_pins, sizeof(struct xenpic_intsrc) * NR_DYNIRQS);
  21.552 +
  21.553 +    for ( i = 0, pin = xp->xp_pins; i < NR_DYNIRQS; i++, pin++ )
  21.554 +    {
  21.555 +        /* Dynamic IRQ space is currently unbound. Zero the refcnts. */
  21.556 +        irq_bindcount[dynirq_to_irq(i)] = 0;
  21.557 +
  21.558 +	pin->xp_intsrc.is_pic = (struct pic *)xp;
  21.559 +	pin->xp_vector = i;
  21.560 +	intr_register_source(&pin->xp_intsrc);
  21.561 +    }
  21.562 +    /* We don't currently have any support for physical devices in XenoFreeBSD 
  21.563 +     * so leaving this out for the moment for the sake of expediency.
  21.564 +     */
  21.565 +#ifdef notyet
  21.566 +    for ( i = 0; i < NR_PIRQS; i++ )
  21.567 +    {
  21.568 +        /* Phys IRQ space is statically bound (1:1 mapping). Nail refcnts. */
  21.569 +        irq_bindcount[pirq_to_irq(i)] = 1;
  21.570 +
  21.571 +        irq_desc[pirq_to_irq(i)].status  = IRQ_DISABLED;
  21.572 +        irq_desc[pirq_to_irq(i)].action  = 0;
  21.573 +        irq_desc[pirq_to_irq(i)].depth   = 1;
  21.574 +        irq_desc[pirq_to_irq(i)].handler = &pirq_type;
  21.575 +    }
  21.576 +
  21.577 +#endif
  21.578 +    (void) intr_add_handler("xb_mis", bind_virq_to_irq(VIRQ_MISDIRECT),
  21.579 +	    	            (driver_intr_t *)misdirect_interrupt, 
  21.580 +			    NULL, INTR_TYPE_MISC, NULL);
  21.581 +}
  21.582 +
  21.583 +SYSINIT(evtchn_init, SI_SUB_INTR, SI_ORDER_ANY, evtchn_init, NULL);
    22.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/exception.s	Mon Mar 21 07:58:08 2005 +0000
    22.3 @@ -0,0 +1,428 @@
    22.4 +/*-
    22.5 + * Copyright (c) 1989, 1990 William F. Jolitz.
    22.6 + * Copyright (c) 1990 The Regents of the University of California.
    22.7 + * All rights reserved.
    22.8 + *
    22.9 + * Redistribution and use in source and binary forms, with or without
   22.10 + * modification, are permitted provided that the following conditions
   22.11 + * are met:
   22.12 + * 1. Redistributions of source code must retain the above copyright
   22.13 + *    notice, this list of conditions and the following disclaimer.
   22.14 + * 2. Redistributions in binary form must reproduce the above copyright
   22.15 + *    notice, this list of conditions and the following disclaimer in the
   22.16 + *    documentation and/or other materials provided with the distribution.
   22.17 + * 4. Neither the name of the University nor the names of its contributors
   22.18 + *    may be used to endorse or promote products derived from this software
   22.19 + *    without specific prior written permission.
   22.20 + *
   22.21 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   22.22 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22.23 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22.24 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22.25 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22.26 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22.27 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22.28 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22.29 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22.30 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   22.31 + * SUCH DAMAGE.
   22.32 + *
   22.33 + * $FreeBSD: src/sys/i386/i386/exception.s,v 1.106 2003/11/03 22:08:52 jhb Exp $
   22.34 + */
   22.35 +
   22.36 +#include "opt_npx.h"
   22.37 +
   22.38 +#include <machine/asmacros.h>
   22.39 +#include <machine/psl.h>
   22.40 +#include <machine/trap.h>
   22.41 +
   22.42 +#include "assym.s"
   22.43 +
   22.44 +#define	SEL_RPL_MASK	0x0002
   22.45 +/* Offsets into shared_info_t. */
   22.46 +#define evtchn_upcall_pending /* 0 */
   22.47 +#define evtchn_upcall_mask       1
   22.48 +#define XEN_BLOCK_EVENTS(reg)     movb $1,evtchn_upcall_mask(reg)
   22.49 +#define XEN_UNBLOCK_EVENTS(reg)   movb $0,evtchn_upcall_mask(reg)
   22.50 +#define XEN_TEST_PENDING(reg)     testb $0x1,evtchn_upcall_pending(reg)
   22.51 +	 
   22.52 +	
   22.53 +#define POPA \
   22.54 +	popl %edi; \
   22.55 +	popl %esi; \
   22.56 +	popl %ebp; \
   22.57 +	popl %ebx; \
   22.58 +	popl %ebx; \
   22.59 +	popl %edx; \
   22.60 +	popl %ecx; \
   22.61 +	popl %eax;
   22.62 +
   22.63 +	.text
   22.64 +
   22.65 +/*****************************************************************************/
   22.66 +/* Trap handling                                                             */
   22.67 +/*****************************************************************************/
   22.68 +/*
   22.69 + * Trap and fault vector routines.
   22.70 + *
   22.71 + * Most traps are 'trap gates', SDT_SYS386TGT.  A trap gate pushes state on
   22.72 + * the stack that mostly looks like an interrupt, but does not disable 
   22.73 + * interrupts.  A few of the traps we are use are interrupt gates, 
   22.74 + * SDT_SYS386IGT, which are nearly the same thing except interrupts are
   22.75 + * disabled on entry.
   22.76 + *
   22.77 + * The cpu will push a certain amount of state onto the kernel stack for
   22.78 + * the current process.  The amount of state depends on the type of trap 
   22.79 + * and whether the trap crossed rings or not.  See i386/include/frame.h.  
   22.80 + * At the very least the current EFLAGS (status register, which includes 
   22.81 + * the interrupt disable state prior to the trap), the code segment register,
   22.82 + * and the return instruction pointer are pushed by the cpu.  The cpu 
   22.83 + * will also push an 'error' code for certain traps.  We push a dummy 
   22.84 + * error code for those traps where the cpu doesn't in order to maintain 
   22.85 + * a consistent frame.  We also push a contrived 'trap number'.
   22.86 + *
   22.87 + * The cpu does not push the general registers, we must do that, and we 
   22.88 + * must restore them prior to calling 'iret'.  The cpu adjusts the %cs and
   22.89 + * %ss segment registers, but does not mess with %ds, %es, or %fs.  Thus we
   22.90 + * must load them with appropriate values for supervisor mode operation.
   22.91 + */
   22.92 +
   22.93 +MCOUNT_LABEL(user)
   22.94 +MCOUNT_LABEL(btrap)
   22.95 +
   22.96 +IDTVEC(div)
   22.97 +	pushl $0; pushl $0; TRAP(T_DIVIDE)
   22.98 +IDTVEC(dbg)
   22.99 +	pushl $0; pushl $0; TRAP(T_TRCTRAP)
  22.100 +IDTVEC(nmi)
  22.101 +	pushl $0; pushl $0; TRAP(T_NMI)
  22.102 +IDTVEC(bpt)
  22.103 +	pushl $0; pushl $0; TRAP(T_BPTFLT)
  22.104 +IDTVEC(ofl)
  22.105 +	pushl $0; pushl $0; TRAP(T_OFLOW)
  22.106 +IDTVEC(bnd)
  22.107 +	pushl $0; pushl $0; TRAP(T_BOUND)
  22.108 +IDTVEC(ill)
  22.109 +	pushl $0; pushl $0; TRAP(T_PRIVINFLT)
  22.110 +IDTVEC(dna)
  22.111 +	pushl $0; pushl $0; TRAP(T_DNA)
  22.112 +IDTVEC(fpusegm)
  22.113 +	pushl $0; pushl $0; TRAP(T_FPOPFLT)
  22.114 +IDTVEC(tss)
  22.115 +	pushl $0; TRAP(T_TSSFLT)
  22.116 +IDTVEC(missing)
  22.117 +	pushl $0; TRAP(T_SEGNPFLT)
  22.118 +IDTVEC(stk)
  22.119 +	pushl $0; TRAP(T_STKFLT)
  22.120 +IDTVEC(prot)
  22.121 +	pushl $0; TRAP(T_PROTFLT)
  22.122 +IDTVEC(page)
  22.123 +	TRAP(T_PAGEFLT)
  22.124 +IDTVEC(mchk)
  22.125 +	pushl $0; pushl $0; TRAP(T_MCHK)
  22.126 +IDTVEC(rsvd)
  22.127 +	pushl $0; pushl $0; TRAP(T_RESERVED)
  22.128 +IDTVEC(fpu)
  22.129 +	pushl $0; pushl $0; TRAP(T_ARITHTRAP)
  22.130 +IDTVEC(align)
  22.131 +	pushl $0; TRAP(T_ALIGNFLT)
  22.132 +
  22.133 +IDTVEC(xmm)
  22.134 +	pushl $0; pushl $0; TRAP(T_XMMFLT)
  22.135 +
  22.136 +IDTVEC(hypervisor_callback)
  22.137 +	 pushl $T_HYPCALLBACK;  pushl %eax; TRAP(T_HYPCALLBACK)
  22.138 +
  22.139 +hypervisor_callback_pending:
  22.140 +	movl	$T_HYPCALLBACK,TF_TRAPNO(%esp)
  22.141 +	movl	$T_HYPCALLBACK,TF_ERR(%esp)
  22.142 +	jmp	11f
  22.143 +	
  22.144 +	/*
  22.145 +	 * alltraps entry point.  Interrupts are enabled if this was a trap
  22.146 +	 * gate (TGT), else disabled if this was an interrupt gate (IGT).
  22.147 +	 * Note that int0x80_syscall is a trap gate.  Only page faults
  22.148 +	 * use an interrupt gate.
  22.149 +	 */
  22.150 +
  22.151 +	SUPERALIGN_TEXT
  22.152 +	.globl	alltraps
  22.153 +	.type	alltraps,@function
  22.154 +alltraps:
  22.155 +	cld
  22.156 +	pushal
  22.157 +	pushl	%ds
  22.158 +	pushl	%es
  22.159 +	pushl	%fs
  22.160 +alltraps_with_regs_pushed:
  22.161 +	movl	$KDSEL,%eax
  22.162 +	movl	%eax,%ds
  22.163 +	movl	%eax,%es
  22.164 +	movl	$KPSEL,%eax
  22.165 +	movl	%eax,%fs
  22.166 +	FAKE_MCOUNT(TF_EIP(%esp))
  22.167 +calltrap:
  22.168 +	movl	TF_EIP(%esp),%eax
  22.169 +	cmpl	$scrit,%eax
  22.170 +	jb	11f
  22.171 +	cmpl	$ecrit,%eax
  22.172 +	jb	critical_region_fixup
  22.173 +11:	call	trap
  22.174 +
  22.175 +	/*
  22.176 +	 * Return via doreti to handle ASTs.
  22.177 +	 */
  22.178 +	MEXITCOUNT
  22.179 +	jmp	doreti
  22.180 +
  22.181 +/*
  22.182 + * SYSCALL CALL GATE (old entry point for a.out binaries)
  22.183 + *
  22.184 + * The intersegment call has been set up to specify one dummy parameter.
  22.185 + *
  22.186 + * This leaves a place to put eflags so that the call frame can be
  22.187 + * converted to a trap frame. Note that the eflags is (semi-)bogusly
  22.188 + * pushed into (what will be) tf_err and then copied later into the
  22.189 + * final spot. It has to be done this way because esp can't be just
  22.190 + * temporarily altered for the pushfl - an interrupt might come in
  22.191 + * and clobber the saved cs/eip.
  22.192 + */
  22.193 +	SUPERALIGN_TEXT
  22.194 +IDTVEC(lcall_syscall)
  22.195 +	pushfl				/* save eflags */
  22.196 +	popl	8(%esp)			/* shuffle into tf_eflags */
  22.197 +	pushl	$7			/* sizeof "lcall 7,0" */
  22.198 +	subl	$4,%esp			/* skip over tf_trapno */
  22.199 +	pushal
  22.200 +	pushl	%ds
  22.201 +	pushl	%es
  22.202 +	pushl	%fs
  22.203 +	movl	$KDSEL,%eax		/* switch to kernel segments */
  22.204 +	movl	%eax,%ds
  22.205 +	movl	%eax,%es
  22.206 +	movl	$KPSEL,%eax
  22.207 +	movl	%eax,%fs
  22.208 +	FAKE_MCOUNT(TF_EIP(%esp))
  22.209 +	call	syscall
  22.210 +	MEXITCOUNT
  22.211 +	jmp	doreti
  22.212 +
  22.213 +/*
  22.214 + * Call gate entry for FreeBSD ELF and Linux/NetBSD syscall (int 0x80)
  22.215 + *
  22.216 + * Even though the name says 'int0x80', this is actually a TGT (trap gate)
  22.217 + * rather then an IGT (interrupt gate).  Thus interrupts are enabled on
  22.218 + * entry just as they are for a normal syscall.
  22.219 + */
  22.220 +	SUPERALIGN_TEXT
  22.221 +IDTVEC(int0x80_syscall)
  22.222 +	pushl	$2			/* sizeof "int 0x80" */
  22.223 +	pushl	$0xCAFE
  22.224 +	pushl	$0xDEAD
  22.225 +	pushal
  22.226 +	pushl	%ds
  22.227 +	pushl	%es
  22.228 +	pushl	%fs
  22.229 +	movl	$KDSEL,%eax		/* switch to kernel segments */
  22.230 +	movl	%eax,%ds
  22.231 +	movl	%eax,%es
  22.232 +	movl	$KPSEL,%eax
  22.233 +	movl	%eax,%fs
  22.234 +	FAKE_MCOUNT(TF_EIP(%esp))
  22.235 +	call	syscall
  22.236 +	MEXITCOUNT
  22.237 +	jmp	doreti
  22.238 +
  22.239 +ENTRY(fork_trampoline)
  22.240 +	pushl	%esp			/* trapframe pointer */
  22.241 +	pushl	%ebx			/* arg1 */
  22.242 +	pushl	%esi			/* function */
  22.243 +	call	fork_exit
  22.244 +	addl	$12,%esp               
  22.245 +	/* cut from syscall */
  22.246 +
  22.247 +	/*
  22.248 +	 * Return via doreti to handle ASTs.
  22.249 +	 */
  22.250 +	MEXITCOUNT
  22.251 +	jmp	doreti
  22.252 +
  22.253 +
  22.254 +/*
  22.255 +# A note on the "critical region" in our callback handler.
  22.256 +# We want to avoid stacking callback handlers due to events occurring
  22.257 +# during handling of the last event. To do this, we keep events disabled
  22.258 +# until weve done all processing. HOWEVER, we must enable events before
  22.259 +# popping the stack frame (cant be done atomically) and so it would still
  22.260 +# be possible to get enough handler activations to overflow the stack.
  22.261 +# Although unlikely, bugs of that kind are hard to track down, so wed
  22.262 +# like to avoid the possibility.
  22.263 +# So, on entry to the handler we detect whether we interrupted an
  22.264 +# existing activation in its critical region -- if so, we pop the current
  22.265 +# activation and restart the handler using the previous one.
  22.266 +*/
  22.267 +
  22.268 +
  22.269 +/*
  22.270 + * void doreti(struct trapframe)
  22.271 + *
  22.272 + * Handle return from interrupts, traps and syscalls.
  22.273 + */
  22.274 +	.text
  22.275 +	SUPERALIGN_TEXT
  22.276 +	.globl	doreti
  22.277 +	.type	doreti,@function
  22.278 +doreti:
  22.279 +	FAKE_MCOUNT(bintr)		/* init "from" bintr -> doreti */	
  22.280 +doreti_next:
  22.281 +	testb	$SEL_RPL_MASK,TF_CS(%esp) /* are we returning to user mode? */
  22.282 +	jz	doreti_exit		  /* #can't handle ASTs now if not */
  22.283 +
  22.284 +doreti_ast:
  22.285 +	/*
  22.286 +	 * Check for ASTs atomically with returning.  Disabling CPU
  22.287 +	 * interrupts provides sufficient locking even in the SMP case,
  22.288 +	 * since we will be informed of any new ASTs by an IPI.
  22.289 +	 */
  22.290 +	
  22.291 +	movl	HYPERVISOR_shared_info,%esi
  22.292 +	XEN_BLOCK_EVENTS(%esi) 
  22.293 +	movl	PCPU(CURTHREAD),%eax
  22.294 +	testl	$TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%eax)
  22.295 +	je	doreti_exit
  22.296 +	XEN_UNBLOCK_EVENTS(%esi) 
  22.297 +	pushl	%esp		/* pass a pointer to the trapframe */
  22.298 +	call	ast
  22.299 +	add	$4,%esp
  22.300 +	jmp	doreti_ast
  22.301 +
  22.302 +doreti_exit:
  22.303 +	/*
  22.304 +	 * doreti_exit:	pop registers, iret.
  22.305 +	 *
  22.306 +	 *	The segment register pop is a special case, since it may
  22.307 +	 *	fault if (for example) a sigreturn specifies bad segment
  22.308 +	 *	registers.  The fault is handled in trap.c.
  22.309 +	 */
  22.310 +
  22.311 +	movl	HYPERVISOR_shared_info,%esi
  22.312 +	XEN_UNBLOCK_EVENTS(%esi) # reenable event callbacks (sti)
  22.313 +
  22.314 +	.globl	scrit
  22.315 +scrit:
  22.316 +	XEN_TEST_PENDING(%esi)
  22.317 +        jnz	hypervisor_callback_pending	/* More to go  */
  22.318 +	MEXITCOUNT
  22.319 +
  22.320 +	.globl	doreti_popl_fs
  22.321 +doreti_popl_fs:
  22.322 +	popl	%fs
  22.323 +	.globl	doreti_popl_es
  22.324 +doreti_popl_es:
  22.325 +	popl	%es
  22.326 +	.globl	doreti_popl_ds
  22.327 +doreti_popl_ds:
  22.328 +	popl	%ds
  22.329 +	POPA
  22.330 +	addl	$12,%esp
  22.331 +	.globl	doreti_iret
  22.332 +doreti_iret:
  22.333 +	iret
  22.334 +	.globl	ecrit
  22.335 +ecrit:
  22.336 +
  22.337 +	/*
  22.338 +	 * doreti_iret_fault and friends.  Alternative return code for
  22.339 +	 * the case where we get a fault in the doreti_exit code
  22.340 +	 * above.  trap() (i386/i386/trap.c) catches this specific
  22.341 +	 * case, sends the process a signal and continues in the
  22.342 +	 * corresponding place in the code below.
  22.343 +	 */
  22.344 +	ALIGN_TEXT
  22.345 +	.globl	doreti_iret_fault
  22.346 +doreti_iret_fault:
  22.347 +	subl	$12,%esp
  22.348 +	pushal
  22.349 +	pushl	%ds
  22.350 +	.globl	doreti_popl_ds_fault
  22.351 +doreti_popl_ds_fault:
  22.352 +	pushl	%es
  22.353 +	.globl	doreti_popl_es_fault
  22.354 +doreti_popl_es_fault:
  22.355 +	pushl	%fs
  22.356 +	.globl	doreti_popl_fs_fault
  22.357 +doreti_popl_fs_fault:
  22.358 +	movl	$0,TF_ERR(%esp)	/* XXX should be the error code */
  22.359 +	movl	$T_PROTFLT,TF_TRAPNO(%esp)
  22.360 +	jmp	alltraps_with_regs_pushed
  22.361 +
  22.362 +
  22.363 +
  22.364 +
  22.365 +/*
  22.366 +# [How we do the fixup]. We want to merge the current stack frame with the
  22.367 +# just-interrupted frame. How we do this depends on where in the critical
  22.368 +# region the interrupted handler was executing, and so how many saved
  22.369 +# registers are in each frame. We do this quickly using the lookup table
  22.370 +# 'critical_fixup_table'. For each byte offset in the critical region, it
  22.371 +# provides the number of bytes which have already been popped from the
  22.372 +# interrupted stack frame.
  22.373 +*/
  22.374 +
  22.375 +.globl critical_region_fixup
  22.376 +critical_region_fixup:
  22.377 +	addl $critical_fixup_table-scrit,%eax
  22.378 +	movzbl (%eax),%eax    # %eax contains num bytes popped
  22.379 +        movl  %esp,%esi
  22.380 +        add  %eax,%esi        # %esi points at end of src region
  22.381 +        movl  %esp,%edi
  22.382 +        add  $0x44,%edi       # %edi points at end of dst region
  22.383 +        movl  %eax,%ecx
  22.384 +        shr  $2,%ecx          # convert bytes to words
  22.385 +        je   16f              # skip loop if nothing to copy
  22.386 +15:     subl $4,%esi          # pre-decrementing copy loop
  22.387 +        subl $4,%edi
  22.388 +        movl (%esi),%eax
  22.389 +        movl %eax,(%edi)
  22.390 +        loop 15b
  22.391 +16:     movl %edi,%esp        # final %edi is top of merged stack
  22.392 +	jmp  hypervisor_callback_pending
  22.393 +
  22.394 +
  22.395 +critical_fixup_table:        
  22.396 +.byte   0x0,0x0,0x0			#testb  $0x1,(%esi)
  22.397 +.byte   0x0,0x0,0x0,0x0,0x0,0x0		#jne    ea 
  22.398 +.byte   0x0,0x0				#pop    %fs
  22.399 +.byte   0x04				#pop    %es
  22.400 +.byte   0x08				#pop    %ds
  22.401 +.byte   0x0c				#pop    %edi
  22.402 +.byte   0x10	                        #pop    %esi
  22.403 +.byte   0x14	                        #pop    %ebp
  22.404 +.byte   0x18	                        #pop    %ebx
  22.405 +.byte   0x1c	                        #pop    %ebx
  22.406 +.byte   0x20	                        #pop    %edx
  22.407 +.byte   0x24	                        #pop    %ecx
  22.408 +.byte   0x28	                        #pop    %eax
  22.409 +.byte   0x2c,0x2c,0x2c                  #add    $0xc,%esp
  22.410 +.byte   0x38	                        #iret   
  22.411 +
  22.412 +	
  22.413 +/* # Hypervisor uses this for application faults while it executes.*/
  22.414 +ENTRY(failsafe_callback)
  22.415 +	pushal
  22.416 +	call xen_failsafe_handler
  22.417 +/*#	call install_safe_pf_handler */
  22.418 +        movl 32(%esp),%ebx
  22.419 +1:      movl %ebx,%ds
  22.420 +        movl 36(%esp),%ebx
  22.421 +2:      movl %ebx,%es
  22.422 +        movl 40(%esp),%ebx
  22.423 +3:      movl %ebx,%fs
  22.424 +        movl 44(%esp),%ebx
  22.425 +4:      movl %ebx,%gs
  22.426 +/*#        call install_normal_pf_handler */
  22.427 +	popal
  22.428 +	addl $16,%esp
  22.429 +	iret
  22.430 +
  22.431 +
    23.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/genassym.c	Mon Mar 21 07:58:08 2005 +0000
    23.3 @@ -0,0 +1,234 @@
    23.4 +/*-
    23.5 + * Copyright (c) 1982, 1990 The Regents of the University of California.
    23.6 + * All rights reserved.
    23.7 + *
    23.8 + * This code is derived from software contributed to Berkeley by
    23.9 + * William Jolitz.
   23.10 + *
   23.11 + * Redistribution and use in source and binary forms, with or without
   23.12 + * modification, are permitted provided that the following conditions
   23.13 + * are met:
   23.14 + * 1. Redistributions of source code must retain the above copyright
   23.15 + *    notice, this list of conditions and the following disclaimer.
   23.16 + * 2. Redistributions in binary form must reproduce the above copyright
   23.17 + *    notice, this list of conditions and the following disclaimer in the
   23.18 + *    documentation and/or other materials provided with the distribution.
   23.19 + * 3. All advertising materials mentioning features or use of this software
   23.20 + *    must display the following acknowledgement:
   23.21 + *	This product includes software developed by the University of
   23.22 + *	California, Berkeley and its contributors.
   23.23 + * 4. Neither the name of the University nor the names of its contributors
   23.24 + *    may be used to endorse or promote products derived from this software
   23.25 + *    without specific prior written permission.
   23.26 + *
   23.27 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   23.28 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23.29 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23.30 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   23.31 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23.32 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23.33 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23.34 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23.35 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23.36 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23.37 + * SUCH DAMAGE.
   23.38 + *
   23.39 + *	from: @(#)genassym.c	5.11 (Berkeley) 5/10/91
   23.40 + */
   23.41 +
   23.42 +#include <sys/cdefs.h>
   23.43 +__FBSDID("$FreeBSD: src/sys/i386/i386/genassym.c,v 1.146 2003/11/12 18:14:34 jhb Exp $");
   23.44 +
   23.45 +#include "opt_apic.h"
   23.46 +#include "opt_compat.h"
   23.47 +#include "opt_kstack_pages.h"
   23.48 +
   23.49 +#include <sys/param.h>
   23.50 +#include <sys/systm.h>
   23.51 +#include <sys/assym.h>
   23.52 +#include <sys/bio.h>
   23.53 +#include <sys/buf.h>
   23.54 +#include <sys/proc.h>
   23.55 +#include <sys/errno.h>
   23.56 +#include <sys/mount.h>
   23.57 +#include <sys/mutex.h>
   23.58 +#include <sys/socket.h>
   23.59 +#include <sys/resourcevar.h>
   23.60 +#include <sys/ucontext.h>
   23.61 +#include <sys/user.h>
   23.62 +#include <machine/bootinfo.h>
   23.63 +#include <machine/tss.h>
   23.64 +#include <sys/vmmeter.h>
   23.65 +#include <vm/vm.h>
   23.66 +#include <vm/vm_param.h>
   23.67 +#include <vm/pmap.h>
   23.68 +#include <vm/vm_map.h>
   23.69 +#include <sys/user.h>
   23.70 +#include <sys/proc.h>
   23.71 +#include <net/if.h>
   23.72 +#include <netinet/in.h>
   23.73 +#include <nfs/nfsproto.h>
   23.74 +#include <nfs/rpcv2.h>
   23.75 +#include <nfsclient/nfs.h>
   23.76 +#include <nfsclient/nfsdiskless.h>
   23.77 +#ifdef DEV_APIC
   23.78 +#include <machine/apicreg.h>
   23.79 +#endif
   23.80 +#include <machine/cpu.h>
   23.81 +#include <machine/sigframe.h>
   23.82 +#include <machine/proc.h>
   23.83 +
   23.84 +ASSYM(P_VMSPACE, offsetof(struct proc, p_vmspace));
   23.85 +ASSYM(VM_PMAP, offsetof(struct vmspace, vm_pmap));
   23.86 +ASSYM(PM_ACTIVE, offsetof(struct pmap, pm_active));
   23.87 +ASSYM(P_SFLAG, offsetof(struct proc, p_sflag));
   23.88 +ASSYM(P_UAREA, offsetof(struct proc, p_uarea));
   23.89 +
   23.90 +ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
   23.91 +ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
   23.92 +ASSYM(TD_PROC, offsetof(struct thread, td_proc));
   23.93 +ASSYM(TD_MD, offsetof(struct thread, td_md));
   23.94 +
   23.95 +ASSYM(P_MD, offsetof(struct proc, p_md));
   23.96 +ASSYM(MD_LDT, offsetof(struct mdproc, md_ldt));
   23.97 +
   23.98 +ASSYM(TDF_ASTPENDING, TDF_ASTPENDING);
   23.99 +ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED);
  23.100 +
  23.101 +ASSYM(V_TRAP, offsetof(struct vmmeter, v_trap));
  23.102 +ASSYM(V_SYSCALL, offsetof(struct vmmeter, v_syscall));
  23.103 +ASSYM(V_INTR, offsetof(struct vmmeter, v_intr));
  23.104 +/* ASSYM(UPAGES, UPAGES);*/
  23.105 +ASSYM(UAREA_PAGES, UAREA_PAGES);
  23.106 +ASSYM(KSTACK_PAGES, KSTACK_PAGES);
  23.107 +ASSYM(PAGE_SIZE, PAGE_SIZE);
  23.108 +ASSYM(NPTEPG, NPTEPG);
  23.109 +ASSYM(NPDEPG, NPDEPG);
  23.110 +ASSYM(NPDEPTD, NPDEPTD);
  23.111 +ASSYM(NPGPTD, NPGPTD);
  23.112 +ASSYM(PDESIZE, sizeof(pd_entry_t));
  23.113 +ASSYM(PTESIZE, sizeof(pt_entry_t));
  23.114 +ASSYM(PDESHIFT, PDESHIFT);
  23.115 +ASSYM(PTESHIFT, PTESHIFT);
  23.116 +ASSYM(PAGE_SHIFT, PAGE_SHIFT);
  23.117 +ASSYM(PAGE_MASK, PAGE_MASK);
  23.118 +ASSYM(PDRSHIFT, PDRSHIFT);
  23.119 +ASSYM(PDRMASK, PDRMASK);
  23.120 +ASSYM(USRSTACK, USRSTACK);
  23.121 +ASSYM(VM_MAXUSER_ADDRESS, VM_MAXUSER_ADDRESS);
  23.122 +ASSYM(KERNBASE, KERNBASE);
  23.123 +ASSYM(KERNLOAD, KERNLOAD);
  23.124 +ASSYM(MCLBYTES, MCLBYTES);
  23.125 +ASSYM(PCB_CR3, offsetof(struct pcb, pcb_cr3));
  23.126 +ASSYM(PCB_EDI, offsetof(struct pcb, pcb_edi));
  23.127 +ASSYM(PCB_ESI, offsetof(struct pcb, pcb_esi));
  23.128 +ASSYM(PCB_EBP, offsetof(struct pcb, pcb_ebp));
  23.129 +ASSYM(PCB_ESP, offsetof(struct pcb, pcb_esp));
  23.130 +ASSYM(PCB_EBX, offsetof(struct pcb, pcb_ebx));
  23.131 +ASSYM(PCB_EIP, offsetof(struct pcb, pcb_eip));
  23.132 +ASSYM(TSS_ESP0, offsetof(struct i386tss, tss_esp0));
  23.133 +
  23.134 +ASSYM(PCB_GS, offsetof(struct pcb, pcb_gs));
  23.135 +ASSYM(PCB_DR0, offsetof(struct pcb, pcb_dr0));
  23.136 +ASSYM(PCB_DR1, offsetof(struct pcb, pcb_dr1));
  23.137 +ASSYM(PCB_DR2, offsetof(struct pcb, pcb_dr2));
  23.138 +ASSYM(PCB_DR3, offsetof(struct pcb, pcb_dr3));
  23.139 +ASSYM(PCB_DR6, offsetof(struct pcb, pcb_dr6));
  23.140 +ASSYM(PCB_DR7, offsetof(struct pcb, pcb_dr7));
  23.141 +ASSYM(PCB_PSL, offsetof(struct pcb, pcb_psl));
  23.142 +ASSYM(PCB_DBREGS, PCB_DBREGS);
  23.143 +ASSYM(PCB_EXT, offsetof(struct pcb, pcb_ext));
  23.144 +
  23.145 +ASSYM(PCB_SPARE, offsetof(struct pcb, __pcb_spare));
  23.146 +ASSYM(PCB_FLAGS, offsetof(struct pcb, pcb_flags));
  23.147 +ASSYM(PCB_SAVEFPU, offsetof(struct pcb, pcb_save));
  23.148 +ASSYM(PCB_SAVEFPU_SIZE, sizeof(union savefpu));
  23.149 +ASSYM(PCB_ONFAULT, offsetof(struct pcb, pcb_onfault));
  23.150 +ASSYM(PCB_SWITCHOUT, offsetof(struct pcb, pcb_switchout));
  23.151 +
  23.152 +ASSYM(PCB_SIZE, sizeof(struct pcb));
  23.153 +
  23.154 +ASSYM(TF_TRAPNO, offsetof(struct trapframe, tf_trapno));
  23.155 +ASSYM(TF_ERR, offsetof(struct trapframe, tf_err));
  23.156 +ASSYM(TF_CS, offsetof(struct trapframe, tf_cs));
  23.157 +ASSYM(TF_EFLAGS, offsetof(struct trapframe, tf_eflags));
  23.158 +ASSYM(TF_EIP, offsetof(struct trapframe, tf_eip));
  23.159 +ASSYM(SIGF_HANDLER, offsetof(struct sigframe, sf_ahu.sf_handler));
  23.160 +#ifdef COMPAT_43
  23.161 +ASSYM(SIGF_SC, offsetof(struct osigframe, sf_siginfo.si_sc));
  23.162 +#endif
  23.163 +ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc));
  23.164 +#ifdef COMPAT_FREEBSD4
  23.165 +ASSYM(SIGF_UC4, offsetof(struct sigframe4, sf_uc));
  23.166 +#endif
  23.167 +#ifdef COMPAT_43
  23.168 +ASSYM(SC_PS, offsetof(struct osigcontext, sc_ps));
  23.169 +ASSYM(SC_FS, offsetof(struct osigcontext, sc_fs));
  23.170 +ASSYM(SC_GS, offsetof(struct osigcontext, sc_gs));
  23.171 +ASSYM(SC_TRAPNO, offsetof(struct osigcontext, sc_trapno));
  23.172 +#endif
  23.173 +#ifdef COMPAT_FREEBSD4
  23.174 +ASSYM(UC4_EFLAGS, offsetof(struct ucontext4, uc_mcontext.mc_eflags));
  23.175 +ASSYM(UC4_GS, offsetof(struct ucontext4, uc_mcontext.mc_gs));
  23.176 +#endif
  23.177 +ASSYM(UC_EFLAGS, offsetof(ucontext_t, uc_mcontext.mc_eflags));
  23.178 +ASSYM(UC_GS, offsetof(ucontext_t, uc_mcontext.mc_gs));
  23.179 +ASSYM(ENOENT, ENOENT);
  23.180 +ASSYM(EFAULT, EFAULT);
  23.181 +ASSYM(ENAMETOOLONG, ENAMETOOLONG);
  23.182 +ASSYM(MAXCOMLEN, MAXCOMLEN);
  23.183 +ASSYM(MAXPATHLEN, MAXPATHLEN);
  23.184 +ASSYM(BOOTINFO_SIZE, sizeof(struct bootinfo));
  23.185 +ASSYM(BI_VERSION, offsetof(struct bootinfo, bi_version));
  23.186 +ASSYM(BI_KERNELNAME, offsetof(struct bootinfo, bi_kernelname));
  23.187 +ASSYM(BI_NFS_DISKLESS, offsetof(struct bootinfo, bi_nfs_diskless));
  23.188 +ASSYM(BI_ENDCOMMON, offsetof(struct bootinfo, bi_endcommon));
  23.189 +ASSYM(NFSDISKLESS_SIZE, sizeof(struct nfs_diskless));
  23.190 +ASSYM(BI_SIZE, offsetof(struct bootinfo, bi_size));
  23.191 +ASSYM(BI_SYMTAB, offsetof(struct bootinfo, bi_symtab));
  23.192 +ASSYM(BI_ESYMTAB, offsetof(struct bootinfo, bi_esymtab));
  23.193 +ASSYM(BI_KERNEND, offsetof(struct bootinfo, bi_kernend));
  23.194 +ASSYM(PC_SIZEOF, sizeof(struct pcpu));
  23.195 +ASSYM(PC_PRVSPACE, offsetof(struct pcpu, pc_prvspace));
  23.196 +ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread));
  23.197 +ASSYM(PC_FPCURTHREAD, offsetof(struct pcpu, pc_fpcurthread));
  23.198 +ASSYM(PC_IDLETHREAD, offsetof(struct pcpu, pc_idlethread));
  23.199 +ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
  23.200 +ASSYM(PC_COMMON_TSS, offsetof(struct pcpu, pc_common_tss));
  23.201 +ASSYM(PC_COMMON_TSSD, offsetof(struct pcpu, pc_common_tssd));
  23.202 +ASSYM(PC_TSS_GDT, offsetof(struct pcpu, pc_tss_gdt));
  23.203 +ASSYM(PC_CURRENTLDT, offsetof(struct pcpu, pc_currentldt));
  23.204 +ASSYM(PC_CPUID, offsetof(struct pcpu, pc_cpuid));
  23.205 +ASSYM(PC_CURPMAP, offsetof(struct pcpu, pc_curpmap));
  23.206 +ASSYM(PC_TRAP_NESTING, offsetof(struct pcpu, pc_trap_nesting));
  23.207 +
  23.208 +ASSYM(PC_CR3, offsetof(struct pcpu, pc_pdir));
  23.209 +
  23.210 +#ifdef DEV_APIC
  23.211 +ASSYM(LA_VER, offsetof(struct LAPIC, version));
  23.212 +ASSYM(LA_TPR, offsetof(struct LAPIC, tpr));
  23.213 +ASSYM(LA_EOI, offsetof(struct LAPIC, eoi));
  23.214 +ASSYM(LA_SVR, offsetof(struct LAPIC, svr));
  23.215 +ASSYM(LA_ICR_LO, offsetof(struct LAPIC, icr_lo));
  23.216 +ASSYM(LA_ICR_HI, offsetof(struct LAPIC, icr_hi));
  23.217 +ASSYM(LA_ISR, offsetof(struct LAPIC, isr0));
  23.218 +#endif
  23.219 +
  23.220 +ASSYM(KCSEL, GSEL(GCODE_SEL, SEL_KPL));
  23.221 +ASSYM(KDSEL, GSEL(GDATA_SEL, SEL_KPL));
  23.222 +ASSYM(KPSEL, GSEL(GPRIV_SEL, SEL_KPL));
  23.223 +
  23.224 +ASSYM(BC32SEL, GSEL(GBIOSCODE32_SEL, SEL_KPL));
  23.225 +ASSYM(GPROC0_SEL, GPROC0_SEL);
  23.226 +
  23.227 +ASSYM(MTX_LOCK, offsetof(struct mtx, mtx_lock));
  23.228 +ASSYM(MTX_RECURSECNT, offsetof(struct mtx, mtx_recurse));
  23.229 +
  23.230 +#ifdef PC98
  23.231 +#include <machine/bus.h>
  23.232 +
  23.233 +ASSYM(BUS_SPACE_HANDLE_BASE, offsetof(struct bus_space_handle, bsh_base));
  23.234 +ASSYM(BUS_SPACE_HANDLE_IAT, offsetof(struct bus_space_handle, bsh_iat));
  23.235 +#endif
  23.236 +
  23.237 +ASSYM(HYPERVISOR_STACK_SWITCH, __HYPERVISOR_stack_switch);
    24.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/hypervisor.c	Mon Mar 21 07:58:08 2005 +0000
    24.3 @@ -0,0 +1,107 @@
    24.4 +/******************************************************************************
    24.5 + * hypervisor.c
    24.6 + * 
    24.7 + * Communication to/from hypervisor.
    24.8 + * 
    24.9 + * Copyright (c) 2002-2003, K A Fraser
   24.10 + * 
   24.11 + * Permission is hereby granted, free of charge, to any person obtaining a copy
   24.12 + * of this software and associated documentation files (the "Software"), to
   24.13 + * deal in the Software without restriction, including without limitation the
   24.14 + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
   24.15 + * sell copies of the Software, and to permit persons to whom the Software is
   24.16 + * furnished to do so, subject to the following conditions:
   24.17 + * 
   24.18 + * The above copyright notice and this permission notice shall be included in
   24.19 + * all copies or substantial portions of the Software.
   24.20 + * 
   24.21 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
   24.22 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIEAS OF MERCHANTABILITY, 
   24.23 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
   24.24 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
   24.25 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
   24.26 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
   24.27 + * DEALINGS IN THE SOFTWARE.
   24.28 + */
   24.29 +
   24.30 +#include <machine/xen-os.h>
   24.31 +#include <machine/hypervisor.h>
   24.32 +#include <machine/xenvar.h>
   24.33 +#include <machine/multicall.h>
   24.34 +
   24.35 +/* XXX need to verify what the caller save registers are on x86 KMM */
   24.36 +#define CALLER_SAVE __asm__("pushal; ")
   24.37 +#define CALLER_RESTORE __asm__("popal;")
   24.38 +
   24.39 +
   24.40 +/* ni == non-inline - these are only intended for use from assembler
   24.41 + * no reason to have them in a header - 
   24.42 + *
   24.43 + */
   24.44 +void ni_queue_multicall0(unsigned long op); 
   24.45 +void ni_queue_multicall1(unsigned long op, unsigned long arg1); 
   24.46 +void ni_queue_multicall2(unsigned long op, unsigned long arg1,
   24.47 +			 unsigned long arg2); 
   24.48 +void ni_queue_multicall3(unsigned long op, unsigned long arg1,
   24.49 +			 unsigned long arg2, unsigned long arg3); 
   24.50 +void ni_queue_multicall4(unsigned long op, unsigned long arg1,
   24.51 +			 unsigned long arg2, unsigned long arg4,
   24.52 +			 unsigned long arg5); 
   24.53 +
   24.54 +void ni_execute_multicall_list(void);
   24.55 +
   24.56 +multicall_entry_t multicall_list[MAX_MULTICALL_ENTS];
   24.57 +int nr_multicall_ents = 0;
   24.58 +
   24.59 +
   24.60 +void 
   24.61 +ni_queue_multicall0(unsigned long op) 
   24.62 +{
   24.63 +    CALLER_SAVE;
   24.64 +    queue_multicall0(op);
   24.65 +    CALLER_RESTORE;
   24.66 +}
   24.67 +
   24.68 +void 
   24.69 +ni_queue_multicall1(unsigned long op, unsigned long arg1) 
   24.70 +{
   24.71 +    CALLER_SAVE;
   24.72 +    queue_multicall1(op, arg1);
   24.73 +    CALLER_RESTORE;
   24.74 +}
   24.75 +
   24.76 +void 
   24.77 +ni_queue_multicall2(unsigned long op, unsigned long arg1, 
   24.78 +		    unsigned long arg2) 
   24.79 +{
   24.80 +    CALLER_SAVE;
   24.81 +    queue_multicall2(op, arg1, arg2);
   24.82 +    CALLER_RESTORE;
   24.83 +}
   24.84 +
   24.85 +void 
   24.86 +ni_queue_multicall3(unsigned long op, unsigned long arg1, 
   24.87 +		    unsigned long arg2, unsigned long arg3) 
   24.88 +{
   24.89 +    CALLER_SAVE;
   24.90 +    queue_multicall3(op, arg1, arg2, arg3);
   24.91 +    CALLER_RESTORE;
   24.92 +}
   24.93 +
   24.94 +void 
   24.95 +ni_queue_multicall4(unsigned long op, unsigned long arg1,
   24.96 +		    unsigned long arg2, unsigned long arg3,
   24.97 +		    unsigned long arg4) 
   24.98 +{
   24.99 +    CALLER_SAVE;    
  24.100 +    queue_multicall4(op, arg1, arg2, arg3, arg4);
  24.101 +    CALLER_RESTORE;
  24.102 +}
  24.103 +
  24.104 +void
  24.105 +ni_execute_multicall_list(void)
  24.106 +{
  24.107 +    CALLER_SAVE;
  24.108 +    execute_multicall_list();
  24.109 +    CALLER_RESTORE;
  24.110 +}
    25.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/i686_mem.c	Mon Mar 21 07:58:08 2005 +0000
    25.3 @@ -0,0 +1,626 @@
    25.4 +/*-
    25.5 + * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
    25.6 + * All rights reserved.
    25.7 + *
    25.8 + * Redistribution and use in source and binary forms, with or without
    25.9 + * modification, are permitted provided that the following conditions
   25.10 + * are met:
   25.11 + * 1. Redistributions of source code must retain the above copyright
   25.12 + *    notice, this list of conditions and the following disclaimer.
   25.13 + * 2. Redistributions in binary form must reproduce the above copyright
   25.14 + *    notice, this list of conditions and the following disclaimer in the
   25.15 + *    documentation and/or other materials provided with the distribution.
   25.16 + *
   25.17 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   25.18 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25.19 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25.20 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   25.21 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25.22 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25.23 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25.24 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25.25 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25.26 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25.27 + * SUCH DAMAGE.
   25.28 + */
   25.29 +
   25.30 +#include <sys/cdefs.h>
   25.31 +__FBSDID("$FreeBSD: src/sys/i386/i386/i686_mem.c,v 1.23 2003/10/21 18:28:34 silby Exp $");
   25.32 +
   25.33 +#include <sys/param.h>
   25.34 +#include <sys/kernel.h>
   25.35 +#include <sys/systm.h>
   25.36 +#include <sys/malloc.h>
   25.37 +#include <sys/memrange.h>
   25.38 +#include <sys/smp.h>
   25.39 +#include <sys/sysctl.h>
   25.40 +
   25.41 +#include <machine/md_var.h>
   25.42 +#include <machine/specialreg.h>
   25.43 +
   25.44 +/*
   25.45 + * i686 memory range operations
   25.46 + *
   25.47 + * This code will probably be impenetrable without reference to the
   25.48 + * Intel Pentium Pro documentation.
   25.49 + */
   25.50 +
   25.51 +static char *mem_owner_bios = "BIOS";
   25.52 +
   25.53 +#define MR686_FIXMTRR	(1<<0)
   25.54 +
   25.55 +#define mrwithin(mr, a) \
   25.56 +    (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
   25.57 +#define mroverlap(mra, mrb) \
   25.58 +    (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base))
   25.59 +
   25.60 +#define mrvalid(base, len) 						\
   25.61 +    ((!(base & ((1 << 12) - 1))) && 	/* base is multiple of 4k */	\
   25.62 +     ((len) >= (1 << 12)) && 		/* length is >= 4k */		\
   25.63 +     powerof2((len)) && 		/* ... and power of two */	\
   25.64 +     !((base) & ((len) - 1)))		/* range is not discontiuous */
   25.65 +
   25.66 +#define mrcopyflags(curr, new) (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK))
   25.67 +
   25.68 +static int			mtrrs_disabled;
   25.69 +TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled);
   25.70 +SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN,
   25.71 +	&mtrrs_disabled, 0, "Disable i686 MTRRs.");
   25.72 +
   25.73 +static void			i686_mrinit(struct mem_range_softc *sc);
   25.74 +static int			i686_mrset(struct mem_range_softc *sc,
   25.75 +					   struct mem_range_desc *mrd,
   25.76 +					   int *arg);
   25.77 +static void			i686_mrAPinit(struct mem_range_softc *sc);
   25.78 +
   25.79 +static struct mem_range_ops i686_mrops = {
   25.80 +    i686_mrinit,
   25.81 +    i686_mrset,
   25.82 +    i686_mrAPinit
   25.83 +};
   25.84 +
   25.85 +/* XXX for AP startup hook */
   25.86 +static u_int64_t		mtrrcap, mtrrdef;
   25.87 +
   25.88 +static struct mem_range_desc	*mem_range_match(struct mem_range_softc *sc,
   25.89 +						 struct mem_range_desc *mrd);
   25.90 +static void			i686_mrfetch(struct mem_range_softc *sc);
   25.91 +static int			i686_mtrrtype(int flags);
   25.92 +#if 0
   25.93 +static int			i686_mrt2mtrr(int flags, int oldval);
   25.94 +#endif
   25.95 +static int			i686_mtrrconflict(int flag1, int flag2);
   25.96 +static void			i686_mrstore(struct mem_range_softc *sc);
   25.97 +static void			i686_mrstoreone(void *arg);
   25.98 +static struct mem_range_desc	*i686_mtrrfixsearch(struct mem_range_softc *sc,
   25.99 +						    u_int64_t addr);
  25.100 +static int			i686_mrsetlow(struct mem_range_softc *sc,
  25.101 +					      struct mem_range_desc *mrd,
  25.102 +					      int *arg);
  25.103 +static int			i686_mrsetvariable(struct mem_range_softc *sc,
  25.104 +						   struct mem_range_desc *mrd,
  25.105 +						   int *arg);
  25.106 +
  25.107 +/* i686 MTRR type to memory range type conversion */
  25.108 +static int i686_mtrrtomrt[] = {
  25.109 +    MDF_UNCACHEABLE,
  25.110 +    MDF_WRITECOMBINE,
  25.111 +    MDF_UNKNOWN,
  25.112 +    MDF_UNKNOWN,
  25.113 +    MDF_WRITETHROUGH,
  25.114 +    MDF_WRITEPROTECT,
  25.115 +    MDF_WRITEBACK
  25.116 +};
  25.117 +
  25.118 +#define MTRRTOMRTLEN (sizeof(i686_mtrrtomrt) / sizeof(i686_mtrrtomrt[0]))
  25.119 +
  25.120 +static int
  25.121 +i686_mtrr2mrt(int val) {
  25.122 +	if (val < 0 || val >= MTRRTOMRTLEN)
  25.123 +		return MDF_UNKNOWN;
  25.124 +	return i686_mtrrtomrt[val];
  25.125 +}
  25.126 +
  25.127 +/* 
  25.128 + * i686 MTRR conflicts. Writeback and uncachable may overlap.
  25.129 + */
  25.130 +static int
  25.131 +i686_mtrrconflict(int flag1, int flag2) {
  25.132 +	flag1 &= MDF_ATTRMASK;
  25.133 +	flag2 &= MDF_ATTRMASK;
  25.134 +	if (flag1 == flag2 ||
  25.135 +	    (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) ||
  25.136 +	    (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE))
  25.137 +		return 0;
  25.138 +	return 1;
  25.139 +}
  25.140 +
  25.141 +/*
  25.142 + * Look for an exactly-matching range.
  25.143 + */
  25.144 +static struct mem_range_desc *
  25.145 +mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd) 
  25.146 +{
  25.147 +    struct mem_range_desc	*cand;
  25.148 +    int				i;
  25.149 +	
  25.150 +    for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
  25.151 +	if ((cand->mr_base == mrd->mr_base) &&
  25.152 +	    (cand->mr_len == mrd->mr_len))
  25.153 +	    return(cand);
  25.154 +    return(NULL);
  25.155 +}
  25.156 +
  25.157 +/*
  25.158 + * Fetch the current mtrr settings from the current CPU (assumed to all
  25.159 + * be in sync in the SMP case).  Note that if we are here, we assume
  25.160 + * that MTRRs are enabled, and we may or may not have fixed MTRRs.
  25.161 + */
  25.162 +static void
  25.163 +i686_mrfetch(struct mem_range_softc *sc)
  25.164 +{
  25.165 +    struct mem_range_desc	*mrd;
  25.166 +    u_int64_t			msrv;
  25.167 +    int				i, j, msr;
  25.168 +
  25.169 +    mrd = sc->mr_desc;
  25.170 +
  25.171 +    /* Get fixed-range MTRRs */
  25.172 +    if (sc->mr_cap & MR686_FIXMTRR) {
  25.173 +	msr = MSR_MTRR64kBase;
  25.174 +	for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
  25.175 +	    msrv = rdmsr(msr);
  25.176 +	    for (j = 0; j < 8; j++, mrd++) {
  25.177 +		mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  25.178 +		    i686_mtrr2mrt(msrv & 0xff) |
  25.179 +		    MDF_ACTIVE;
  25.180 +		if (mrd->mr_owner[0] == 0)
  25.181 +		    strcpy(mrd->mr_owner, mem_owner_bios);
  25.182 +		msrv = msrv >> 8;
  25.183 +	    }
  25.184 +	}
  25.185 +	msr = MSR_MTRR16kBase;
  25.186 +	for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
  25.187 +	    msrv = rdmsr(msr);
  25.188 +	    for (j = 0; j < 8; j++, mrd++) {
  25.189 +		mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  25.190 +		    i686_mtrr2mrt(msrv & 0xff) |
  25.191 +		    MDF_ACTIVE;
  25.192 +		if (mrd->mr_owner[0] == 0)
  25.193 +		    strcpy(mrd->mr_owner, mem_owner_bios);
  25.194 +		msrv = msrv >> 8;
  25.195 +	    }
  25.196 +	}
  25.197 +	msr = MSR_MTRR4kBase;
  25.198 +	for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
  25.199 +	    msrv = rdmsr(msr);
  25.200 +	    for (j = 0; j < 8; j++, mrd++) {
  25.201 +		mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  25.202 +		    i686_mtrr2mrt(msrv & 0xff) |
  25.203 +		    MDF_ACTIVE;
  25.204 +		if (mrd->mr_owner[0] == 0)
  25.205 +		    strcpy(mrd->mr_owner, mem_owner_bios);
  25.206 +		msrv = msrv >> 8;
  25.207 +	    }
  25.208 +	}
  25.209 +    }
  25.210 +
  25.211 +    /* Get remainder which must be variable MTRRs */
  25.212 +    msr = MSR_MTRRVarBase;
  25.213 +    for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
  25.214 +	msrv = rdmsr(msr);
  25.215 +	mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  25.216 +	    i686_mtrr2mrt(msrv & 0xff);
  25.217 +	mrd->mr_base = msrv & 0x0000000ffffff000LL;
  25.218 +	msrv = rdmsr(msr + 1);
  25.219 +	mrd->mr_flags = (msrv & 0x800) ? 
  25.220 +	    (mrd->mr_flags | MDF_ACTIVE) :
  25.221 +	    (mrd->mr_flags & ~MDF_ACTIVE);
  25.222 +	/* Compute the range from the mask. Ick. */
  25.223 +	mrd->mr_len = (~(msrv & 0x0000000ffffff000LL) & 0x0000000fffffffffLL) + 1;
  25.224 +	if (!mrvalid(mrd->mr_base, mrd->mr_len))
  25.225 +	    mrd->mr_flags |= MDF_BOGUS;
  25.226 +	/* If unclaimed and active, must be the BIOS */
  25.227 +	if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0))
  25.228 +	    strcpy(mrd->mr_owner, mem_owner_bios);
  25.229 +    }
  25.230 +}
  25.231 +
  25.232 +/*
  25.233 + * Return the MTRR memory type matching a region's flags
  25.234 + */
  25.235 +static int
  25.236 +i686_mtrrtype(int flags)
  25.237 +{
  25.238 +    int		i;
  25.239 +
  25.240 +    flags &= MDF_ATTRMASK;
  25.241 +
  25.242 +    for (i = 0; i < MTRRTOMRTLEN; i++) {
  25.243 +	if (i686_mtrrtomrt[i] == MDF_UNKNOWN)
  25.244 +	    continue;
  25.245 +	if (flags == i686_mtrrtomrt[i])
  25.246 +	    return(i);
  25.247 +    }
  25.248 +    return(-1);
  25.249 +}
  25.250 +#if 0
  25.251 +static int
  25.252 +i686_mrt2mtrr(int flags, int oldval)
  25.253 +{
  25.254 +	int val;
  25.255 +
  25.256 +	if ((val = i686_mtrrtype(flags)) == -1)
  25.257 +		return oldval & 0xff;
  25.258 +	return val & 0xff;
  25.259 +}
  25.260 +#endif
  25.261 +/*
  25.262 + * Update running CPU(s) MTRRs to match the ranges in the descriptor
  25.263 + * list.
  25.264 + *
  25.265 + * XXX Must be called with interrupts enabled.
  25.266 + */
  25.267 +static void
  25.268 +i686_mrstore(struct mem_range_softc *sc)
  25.269 +{
  25.270 +#ifdef SMP
  25.271 +    /*
  25.272 +     * We should use ipi_all_but_self() to call other CPUs into a 
  25.273 +     * locking gate, then call a target function to do this work.
  25.274 +     * The "proper" solution involves a generalised locking gate
  25.275 +     * implementation, not ready yet.
  25.276 +     */
  25.277 +    smp_rendezvous(NULL, i686_mrstoreone, NULL, (void *)sc);
  25.278 +#else
  25.279 +    disable_intr();				/* disable interrupts */
  25.280 +    i686_mrstoreone((void *)sc);
  25.281 +    enable_intr();
  25.282 +#endif
  25.283 +}
  25.284 +
  25.285 +/*
  25.286 + * Update the current CPU's MTRRs with those represented in the
  25.287 + * descriptor list.  Note that we do this wholesale rather than
  25.288 + * just stuffing one entry; this is simpler (but slower, of course).
  25.289 + */
  25.290 +static void
  25.291 +i686_mrstoreone(void *arg)
  25.292 +{
  25.293 +#if 0
  25.294 +    struct mem_range_softc 	*sc = (struct mem_range_softc *)arg;
  25.295 +    struct mem_range_desc	*mrd;
  25.296 +    u_int64_t			omsrv, msrv;
  25.297 +    int				i, j, msr;
  25.298 +    u_int			cr4save;
  25.299 +
  25.300 +    mrd = sc->mr_desc;
  25.301 +
  25.302 +    cr4save = rcr4();				/* save cr4 */
  25.303 +    if (cr4save & CR4_PGE)
  25.304 +	load_cr4(cr4save & ~CR4_PGE);
  25.305 +    load_cr0((rcr0() & ~CR0_NW) | CR0_CD);	/* disable caches (CD = 1, NW = 0) */
  25.306 +    wbinvd();					/* flush caches, TLBs */
  25.307 +    wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800);	/* disable MTRRs (E = 0) */
  25.308 +
  25.309 +    /* Set fixed-range MTRRs */
  25.310 +    if (sc->mr_cap & MR686_FIXMTRR) {
  25.311 +	msr = MSR_MTRR64kBase;
  25.312 +	for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
  25.313 +	    msrv = 0;
  25.314 +	    omsrv = rdmsr(msr);
  25.315 +	    for (j = 7; j >= 0; j--) {
  25.316 +		msrv = msrv << 8;
  25.317 +		msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8));
  25.318 +	    }
  25.319 +	    wrmsr(msr, msrv);
  25.320 +	    mrd += 8;
  25.321 +	}
  25.322 +	msr = MSR_MTRR16kBase;
  25.323 +	for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
  25.324 +	    msrv = 0;
  25.325 +	    omsrv = rdmsr(msr);
  25.326 +	    for (j = 7; j >= 0; j--) {
  25.327 +		msrv = msrv << 8;
  25.328 +		msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8));
  25.329 +	    }
  25.330 +	    wrmsr(msr, msrv);
  25.331 +	    mrd += 8;
  25.332 +	}
  25.333 +	msr = MSR_MTRR4kBase;
  25.334 +	for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
  25.335 +	    msrv = 0;
  25.336 +	    omsrv = rdmsr(msr);
  25.337 +	    for (j = 7; j >= 0; j--) {
  25.338 +		msrv = msrv << 8;
  25.339 +		msrv |= i686_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8));
  25.340 +	    }
  25.341 +	    wrmsr(msr, msrv);
  25.342 +	    mrd += 8;
  25.343 +	}
  25.344 +    }
  25.345 +
  25.346 +    /* Set remainder which must be variable MTRRs */
  25.347 +    msr = MSR_MTRRVarBase;
  25.348 +    for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
  25.349 +	/* base/type register */
  25.350 +	omsrv = rdmsr(msr);
  25.351 +	if (mrd->mr_flags & MDF_ACTIVE) {
  25.352 +	    msrv = mrd->mr_base & 0x0000000ffffff000LL;
  25.353 +	    msrv |= i686_mrt2mtrr(mrd->mr_flags, omsrv);
  25.354 +	} else {
  25.355 +	    msrv = 0;
  25.356 +	}
  25.357 +	wrmsr(msr, msrv);	
  25.358 +	    
  25.359 +	/* mask/active register */
  25.360 +	if (mrd->mr_flags & MDF_ACTIVE) {
  25.361 +	    msrv = 0x800 | (~(mrd->mr_len - 1) & 0x0000000ffffff000LL);
  25.362 +	} else {
  25.363 +	    msrv = 0;
  25.364 +	}
  25.365 +	wrmsr(msr + 1, msrv);
  25.366 +    }
  25.367 +    wbinvd();							/* flush caches, TLBs */
  25.368 +    wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | 0x800);	/* restore MTRR state */
  25.369 +    load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  			/* enable caches CD = 0 and NW = 0 */
  25.370 +    load_cr4(cr4save);						/* restore cr4 */
  25.371 +#endif
  25.372 +}
  25.373 +
  25.374 +/*
  25.375 + * Hunt for the fixed MTRR referencing (addr)
  25.376 + */
  25.377 +static struct mem_range_desc *
  25.378 +i686_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
  25.379 +{
  25.380 +    struct mem_range_desc *mrd;
  25.381 +    int			i;
  25.382 +    
  25.383 +    for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); i++, mrd++)
  25.384 +	if ((addr >= mrd->mr_base) && (addr < (mrd->mr_base + mrd->mr_len)))
  25.385 +	    return(mrd);
  25.386 +    return(NULL);
  25.387 +}
  25.388 +
  25.389 +/*
  25.390 + * Try to satisfy the given range request by manipulating the fixed MTRRs that
  25.391 + * cover low memory.
  25.392 + *
  25.393 + * Note that we try to be generous here; we'll bloat the range out to the 
  25.394 + * next higher/lower boundary to avoid the consumer having to know too much
  25.395 + * about the mechanisms here.
  25.396 + *
  25.397 + * XXX note that this will have to be updated when we start supporting "busy" ranges.
  25.398 + */
  25.399 +static int
  25.400 +i686_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  25.401 +{
  25.402 +    struct mem_range_desc	*first_md, *last_md, *curr_md;
  25.403 +
  25.404 +    /* range check */
  25.405 +    if (((first_md = i686_mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
  25.406 +	((last_md = i686_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
  25.407 +	return(EINVAL);
  25.408 +
  25.409 +    /* check we aren't doing something risky */
  25.410 +    if (!(mrd->mr_flags & MDF_FORCE))
  25.411 +	for (curr_md = first_md; curr_md <= last_md; curr_md++) {
  25.412 +	    if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)
  25.413 +		return (EACCES);
  25.414 +	}
  25.415 +
  25.416 +    /* set flags, clear set-by-firmware flag */
  25.417 +    for (curr_md = first_md; curr_md <= last_md; curr_md++) {
  25.418 +	curr_md->mr_flags = mrcopyflags(curr_md->mr_flags & ~MDF_FIRMWARE, mrd->mr_flags);
  25.419 +	bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
  25.420 +    }
  25.421 +
  25.422 +    return(0);
  25.423 +}
  25.424 +
  25.425 +
  25.426 +/*
  25.427 + * Modify/add a variable MTRR to satisfy the request.
  25.428 + *
  25.429 + * XXX needs to be updated to properly support "busy" ranges.
  25.430 + */
  25.431 +static int
  25.432 +i686_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  25.433 +{
  25.434 +    struct mem_range_desc	*curr_md, *free_md;
  25.435 +    int				i;
  25.436 +    
  25.437 +    /* 
  25.438 +     * Scan the currently active variable descriptors, look for 
  25.439 +     * one we exactly match (straight takeover) and for possible
  25.440 +     * accidental overlaps.
  25.441 +     * Keep track of the first empty variable descriptor in case we
  25.442 +     * can't perform a takeover.
  25.443 +     */
  25.444 +    i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
  25.445 +    curr_md = sc->mr_desc + i;
  25.446 +    free_md = NULL;
  25.447 +    for (; i < sc->mr_ndesc; i++, curr_md++) {
  25.448 +	if (curr_md->mr_flags & MDF_ACTIVE) {
  25.449 +	    /* exact match? */
  25.450 +	    if ((curr_md->mr_base == mrd->mr_base) &&
  25.451 +		(curr_md->mr_len == mrd->mr_len)) {
  25.452 +		/* whoops, owned by someone */
  25.453 +		if (curr_md->mr_flags & MDF_BUSY)
  25.454 +		    return(EBUSY);
  25.455 +		/* check we aren't doing something risky */
  25.456 +		if (!(mrd->mr_flags & MDF_FORCE) &&
  25.457 +		  ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN))
  25.458 +		    return (EACCES);
  25.459 +		/* Ok, just hijack this entry */
  25.460 +		free_md = curr_md;
  25.461 +		break;
  25.462 +	    }
  25.463 +	    /* non-exact overlap ? */
  25.464 +	    if (mroverlap(curr_md, mrd)) {
  25.465 +		/* between conflicting region types? */
  25.466 +		if (i686_mtrrconflict(curr_md->mr_flags, mrd->mr_flags))
  25.467 +		    return(EINVAL);
  25.468 +	    }
  25.469 +	} else if (free_md == NULL) {
  25.470 +	    free_md = curr_md;
  25.471 +	}
  25.472 +    }
  25.473 +    /* got somewhere to put it? */
  25.474 +    if (free_md == NULL)
  25.475 +	return(ENOSPC);
  25.476 +
  25.477 +    /* Set up new descriptor */
  25.478 +    free_md->mr_base = mrd->mr_base;
  25.479 +    free_md->mr_len = mrd->mr_len;
  25.480 +    free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags);
  25.481 +    bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner));
  25.482 +    return(0);
  25.483 +}
  25.484 +
  25.485 +/*
  25.486 + * Handle requests to set memory range attributes by manipulating MTRRs.
  25.487 + *
  25.488 + */
  25.489 +static int
  25.490 +i686_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  25.491 +{
  25.492 +    struct mem_range_desc	*targ;
  25.493 +    int				error = 0;
  25.494 +
  25.495 +    switch(*arg) {
  25.496 +    case MEMRANGE_SET_UPDATE:
  25.497 +	/* make sure that what's being asked for is even possible at all */
  25.498 +	if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
  25.499 +	    i686_mtrrtype(mrd->mr_flags) == -1)
  25.500 +	    return(EINVAL);
  25.501 +
  25.502 +#define FIXTOP	((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000))
  25.503 +
  25.504 +	/* are the "low memory" conditions applicable? */
  25.505 +	if ((sc->mr_cap & MR686_FIXMTRR) &&
  25.506 +	    ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
  25.507 +	    if ((error = i686_mrsetlow(sc, mrd, arg)) != 0)
  25.508 +		return(error);
  25.509 +	} else {
  25.510 +	    /* it's time to play with variable MTRRs */
  25.511 +	    if ((error = i686_mrsetvariable(sc, mrd, arg)) != 0)
  25.512 +		return(error);
  25.513 +	}
  25.514 +	break;
  25.515 +
  25.516 +    case MEMRANGE_SET_REMOVE:
  25.517 +	if ((targ = mem_range_match(sc, mrd)) == NULL)
  25.518 +	    return(ENOENT);
  25.519 +	if (targ->mr_flags & MDF_FIXACTIVE)
  25.520 +	    return(EPERM);
  25.521 +	if (targ->mr_flags & MDF_BUSY)
  25.522 +	    return(EBUSY);
  25.523 +	targ->mr_flags &= ~MDF_ACTIVE;
  25.524 +	targ->mr_owner[0] = 0;
  25.525 +	break;
  25.526 +
  25.527 +    default:
  25.528 +	return(EOPNOTSUPP);
  25.529 +    }
  25.530 +
  25.531 +    /* update the hardware */
  25.532 +    i686_mrstore(sc);
  25.533 +    i686_mrfetch(sc);	/* refetch to see where we're at */
  25.534 +    return(0);
  25.535 +}
  25.536 +
  25.537 +/*
  25.538 + * Work out how many ranges we support, initialise storage for them, 
  25.539 + * fetch the initial settings.
  25.540 + */
  25.541 +static void
  25.542 +i686_mrinit(struct mem_range_softc *sc)
  25.543 +{
  25.544 +    struct mem_range_desc	*mrd;
  25.545 +    int				nmdesc = 0;
  25.546 +    int				i;
  25.547 +
  25.548 +    /* XXX */
  25.549 +    return;
  25.550 +
  25.551 +    mtrrcap = rdmsr(MSR_MTRRcap);
  25.552 +    mtrrdef = rdmsr(MSR_MTRRdefType);
  25.553 +
  25.554 +    /* For now, bail out if MTRRs are not enabled */
  25.555 +    if (!(mtrrdef & 0x800)) {
  25.556 +	if (bootverbose)
  25.557 +	    printf("CPU supports MTRRs but not enabled\n");
  25.558 +	return;
  25.559 +    }
  25.560 +    nmdesc = mtrrcap & 0xff;
  25.561 +    printf("Pentium Pro MTRR support enabled\n");
  25.562 +
  25.563 +    /* If fixed MTRRs supported and enabled */
  25.564 +    if ((mtrrcap & 0x100) && (mtrrdef & 0x400)) {
  25.565 +	sc->mr_cap = MR686_FIXMTRR;
  25.566 +	nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
  25.567 +    }
  25.568 +
  25.569 +    sc->mr_desc = 
  25.570 +	(struct mem_range_desc *)malloc(nmdesc * sizeof(struct mem_range_desc), 
  25.571 +					M_MEMDESC, M_WAITOK | M_ZERO);
  25.572 +    sc->mr_ndesc = nmdesc;
  25.573 +
  25.574 +    mrd = sc->mr_desc;
  25.575 +
  25.576 +    /* Populate the fixed MTRR entries' base/length */
  25.577 +    if (sc->mr_cap & MR686_FIXMTRR) {
  25.578 +	for (i = 0; i < MTRR_N64K; i++, mrd++) {
  25.579 +	    mrd->mr_base = i * 0x10000;
  25.580 +	    mrd->mr_len = 0x10000;
  25.581 +	    mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE;
  25.582 +	}
  25.583 +	for (i = 0; i < MTRR_N16K; i++, mrd++) {
  25.584 +	    mrd->mr_base = i * 0x4000 + 0x80000;
  25.585 +	    mrd->mr_len = 0x4000;
  25.586 +	    mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE;
  25.587 +	}
  25.588 +	for (i = 0; i < MTRR_N4K; i++, mrd++) {
  25.589 +	    mrd->mr_base = i * 0x1000 + 0xc0000;
  25.590 +	    mrd->mr_len = 0x1000;
  25.591 +	    mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE;
  25.592 +	}
  25.593 +    }
  25.594 +
  25.595 +    /* 
  25.596 +     * Get current settings, anything set now is considered to have 
  25.597 +     * been set by the firmware. (XXX has something already played here?)
  25.598 +     */
  25.599 +    i686_mrfetch(sc);
  25.600 +    mrd = sc->mr_desc;
  25.601 +    for (i = 0; i < sc->mr_ndesc; i++, mrd++) {
  25.602 +	if (mrd->mr_flags & MDF_ACTIVE)
  25.603 +	    mrd->mr_flags |= MDF_FIRMWARE;
  25.604 +    }
  25.605 +}
  25.606 +
  25.607 +/*
  25.608 + * Initialise MTRRs on an AP after the BSP has run the init code.
  25.609 + */
  25.610 +static void
  25.611 +i686_mrAPinit(struct mem_range_softc *sc)
  25.612 +{
  25.613 +    i686_mrstoreone((void *)sc);	/* set MTRRs to match BSP */
  25.614 +    wrmsr(MSR_MTRRdefType, mtrrdef);	/* set MTRR behaviour to match BSP */
  25.615 +}
  25.616 +
  25.617 +static void
  25.618 +i686_mem_drvinit(void *unused)
  25.619 +{
  25.620 +    /* Try for i686 MTRRs */
  25.621 +    if (!mtrrs_disabled && (cpu_feature & CPUID_MTRR) &&
  25.622 +	((cpu_id & 0xf00) == 0x600 || (cpu_id & 0xf00) == 0xf00) &&
  25.623 +	((strcmp(cpu_vendor, "GenuineIntel") == 0) ||
  25.624 +	(strcmp(cpu_vendor, "AuthenticAMD") == 0))) {
  25.625 +	mem_range_softc.mr_op = &i686_mrops;
  25.626 +    }
  25.627 +}
  25.628 +
  25.629 +SYSINIT(i686memdev,SI_SUB_DRIVERS,SI_ORDER_FIRST,i686_mem_drvinit,NULL)
    26.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/initcpu.c	Mon Mar 21 07:58:08 2005 +0000
    26.3 @@ -0,0 +1,889 @@
    26.4 +/*-
    26.5 + * Copyright (c) KATO Takenori, 1997, 1998.
    26.6 + * 
    26.7 + * All rights reserved.  Unpublished rights reserved under the copyright
    26.8 + * laws of Japan.
    26.9 + * 
   26.10 + * Redistribution and use in source and binary forms, with or without
   26.11 + * modification, are permitted provided that the following conditions
   26.12 + * are met:
   26.13 + * 
   26.14 + * 1. Redistributions of source code must retain the above copyright
   26.15 + *    notice, this list of conditions and the following disclaimer as
   26.16 + *    the first lines of this file unmodified.
   26.17 + * 2. Redistributions in binary form must reproduce the above copyright
   26.18 + *    notice, this list of conditions and the following disclaimer in the
   26.19 + *    documentation and/or other materials provided with the distribution.
   26.20 + * 
   26.21 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   26.22 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   26.23 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   26.24 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   26.25 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   26.26 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   26.27 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   26.28 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   26.29 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26.30 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   26.31 + */
   26.32 +
   26.33 +#include <sys/cdefs.h>
   26.34 +__FBSDID("$FreeBSD: src/sys/i386/i386/initcpu.c,v 1.49 2003/11/10 15:48:30 jhb Exp $");
   26.35 +
   26.36 +#include "opt_cpu.h"
   26.37 +
   26.38 +#include <sys/param.h>
   26.39 +#include <sys/kernel.h>
   26.40 +#include <sys/systm.h>
   26.41 +#include <sys/sysctl.h>
   26.42 +
   26.43 +#include <machine/cputypes.h>
   26.44 +#include <machine/md_var.h>
   26.45 +#include <machine/specialreg.h>
   26.46 +
   26.47 +#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU)
   26.48 +#define CPU_ENABLE_SSE
   26.49 +#endif
   26.50 +#if defined(CPU_DISABLE_SSE)
   26.51 +#undef CPU_ENABLE_SSE
   26.52 +#endif
   26.53 +
   26.54 +void initializecpu(void);
   26.55 +#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
   26.56 +void	enable_K5_wt_alloc(void);
   26.57 +void	enable_K6_wt_alloc(void);
   26.58 +void	enable_K6_2_wt_alloc(void);
   26.59 +#endif
   26.60 +
   26.61 +#ifdef I486_CPU
   26.62 +static void init_5x86(void);
   26.63 +static void init_bluelightning(void);
   26.64 +static void init_486dlc(void);
   26.65 +static void init_cy486dx(void);
   26.66 +#ifdef CPU_I486_ON_386
   26.67 +static void init_i486_on_386(void);
   26.68 +#endif
   26.69 +static void init_6x86(void);
   26.70 +#endif /* I486_CPU */
   26.71 +
   26.72 +#ifdef I686_CPU
   26.73 +static void	init_6x86MX(void);
   26.74 +static void	init_ppro(void);
   26.75 +static void	init_mendocino(void);
   26.76 +#endif
   26.77 +
   26.78 +static int	hw_instruction_sse;
   26.79 +SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
   26.80 +    &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
   26.81 +
   26.82 +/* Must *NOT* be BSS or locore will bzero these after setting them */
   26.83 +int	cpu = 0;		/* Are we 386, 386sx, 486, etc? */
   26.84 +u_int	cpu_feature = 0;	/* Feature flags */
   26.85 +u_int	cpu_high = 0;		/* Highest arg to CPUID */
   26.86 +u_int	cpu_id = 0;		/* Stepping ID */
   26.87 +u_int	cpu_procinfo = 0;	/* HyperThreading Info / Brand Index / CLFUSH */
   26.88 +char	cpu_vendor[20] = "";	/* CPU Origin code */
   26.89 +
   26.90 +#ifdef CPU_ENABLE_SSE
   26.91 +u_int	cpu_fxsr;		/* SSE enabled */
   26.92 +#endif
   26.93 +
   26.94 +#ifdef I486_CPU
   26.95 +/*
   26.96 + * IBM Blue Lightning
   26.97 + */
   26.98 +static void
   26.99 +init_bluelightning(void)
  26.100 +{
  26.101 +#if 0
  26.102 +	u_long	eflags;
  26.103 +
  26.104 +#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  26.105 +	need_post_dma_flush = 1;
  26.106 +#endif
  26.107 +
  26.108 +	eflags = read_eflags();
  26.109 +	disable_intr();
  26.110 +
  26.111 +	load_cr0(rcr0() | CR0_CD | CR0_NW);
  26.112 +	invd();
  26.113 +
  26.114 +#ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
  26.115 +	wrmsr(0x1000, 0x9c92LL);	/* FP operand can be cacheable on Cyrix FPU */
  26.116 +#else
  26.117 +	wrmsr(0x1000, 0x1c92LL);	/* Intel FPU */
  26.118 +#endif
  26.119 +	/* Enables 13MB and 0-640KB cache. */
  26.120 +	wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
  26.121 +#ifdef CPU_BLUELIGHTNING_3X
  26.122 +	wrmsr(0x1002, 0x04000000LL);	/* Enables triple-clock mode. */
  26.123 +#else
  26.124 +	wrmsr(0x1002, 0x03000000LL);	/* Enables double-clock mode. */
  26.125 +#endif
  26.126 +
  26.127 +	/* Enable caching in CR0. */
  26.128 +	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
  26.129 +	invd();
  26.130 +	write_eflags(eflags);
  26.131 +#endif
  26.132 +}
  26.133 +
  26.134 +/*
  26.135 + * Cyrix 486SLC/DLC/SR/DR series
  26.136 + */
  26.137 +static void
  26.138 +init_486dlc(void)
  26.139 +{
  26.140 +	u_long	eflags;
  26.141 +	u_char	ccr0;
  26.142 +
  26.143 +	eflags = read_eflags();
  26.144 +	disable_intr();
  26.145 +	invd();
  26.146 +
  26.147 +	ccr0 = read_cyrix_reg(CCR0);
  26.148 +#ifndef CYRIX_CACHE_WORKS
  26.149 +	ccr0 |= CCR0_NC1 | CCR0_BARB;
  26.150 +	write_cyrix_reg(CCR0, ccr0);
  26.151 +	invd();
  26.152 +#else
  26.153 +	ccr0 &= ~CCR0_NC0;
  26.154 +#ifndef CYRIX_CACHE_REALLY_WORKS
  26.155 +	ccr0 |= CCR0_NC1 | CCR0_BARB;
  26.156 +#else
  26.157 +	ccr0 |= CCR0_NC1;
  26.158 +#endif
  26.159 +#ifdef CPU_DIRECT_MAPPED_CACHE
  26.160 +	ccr0 |= CCR0_CO;			/* Direct mapped mode. */
  26.161 +#endif
  26.162 +	write_cyrix_reg(CCR0, ccr0);
  26.163 +
  26.164 +	/* Clear non-cacheable region. */
  26.165 +	write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
  26.166 +	write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
  26.167 +	write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
  26.168 +	write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
  26.169 +
  26.170 +	write_cyrix_reg(0, 0);	/* dummy write */
  26.171 +
  26.172 +	/* Enable caching in CR0. */
  26.173 +	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
  26.174 +	invd();
  26.175 +#endif /* !CYRIX_CACHE_WORKS */
  26.176 +	write_eflags(eflags);
  26.177 +}
  26.178 +
  26.179 +
  26.180 +/*
  26.181 + * Cyrix 486S/DX series
  26.182 + */
  26.183 +static void
  26.184 +init_cy486dx(void)
  26.185 +{
  26.186 +	u_long	eflags;
  26.187 +	u_char	ccr2;
  26.188 +
  26.189 +	eflags = read_eflags();
  26.190 +	disable_intr();
  26.191 +	invd();
  26.192 +
  26.193 +	ccr2 = read_cyrix_reg(CCR2);
  26.194 +#ifdef CPU_SUSP_HLT
  26.195 +	ccr2 |= CCR2_SUSP_HLT;
  26.196 +#endif
  26.197 +
  26.198 +#ifdef PC98
  26.199 +	/* Enables WB cache interface pin and Lock NW bit in CR0. */
  26.200 +	ccr2 |= CCR2_WB | CCR2_LOCK_NW;
  26.201 +	/* Unlock NW bit in CR0. */
  26.202 +	write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
  26.203 +	load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0, NW = 1 */
  26.204 +#endif
  26.205 +
  26.206 +	write_cyrix_reg(CCR2, ccr2);
  26.207 +	write_eflags(eflags);
  26.208 +}
  26.209 +
  26.210 +
  26.211 +/*
  26.212 + * Cyrix 5x86
  26.213 + */
  26.214 +static void
  26.215 +init_5x86(void)
  26.216 +{
  26.217 +	u_long	eflags;
  26.218 +	u_char	ccr2, ccr3, ccr4, pcr0;
  26.219 +
  26.220 +	eflags = read_eflags();
  26.221 +	disable_intr();
  26.222 +
  26.223 +	load_cr0(rcr0() | CR0_CD | CR0_NW);
  26.224 +	wbinvd();
  26.225 +
  26.226 +	(void)read_cyrix_reg(CCR3);		/* dummy */
  26.227 +
  26.228 +	/* Initialize CCR2. */
  26.229 +	ccr2 = read_cyrix_reg(CCR2);
  26.230 +	ccr2 |= CCR2_WB;
  26.231 +#ifdef CPU_SUSP_HLT
  26.232 +	ccr2 |= CCR2_SUSP_HLT;
  26.233 +#else
  26.234 +	ccr2 &= ~CCR2_SUSP_HLT;
  26.235 +#endif
  26.236 +	ccr2 |= CCR2_WT1;
  26.237 +	write_cyrix_reg(CCR2, ccr2);
  26.238 +
  26.239 +	/* Initialize CCR4. */
  26.240 +	ccr3 = read_cyrix_reg(CCR3);
  26.241 +	write_cyrix_reg(CCR3, CCR3_MAPEN0);
  26.242 +
  26.243 +	ccr4 = read_cyrix_reg(CCR4);
  26.244 +	ccr4 |= CCR4_DTE;
  26.245 +	ccr4 |= CCR4_MEM;
  26.246 +#ifdef CPU_FASTER_5X86_FPU
  26.247 +	ccr4 |= CCR4_FASTFPE;
  26.248 +#else
  26.249 +	ccr4 &= ~CCR4_FASTFPE;
  26.250 +#endif
  26.251 +	ccr4 &= ~CCR4_IOMASK;
  26.252 +	/********************************************************************
  26.253 +	 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
  26.254 +	 * should be 0 for errata fix.
  26.255 +	 ********************************************************************/
  26.256 +#ifdef CPU_IORT
  26.257 +	ccr4 |= CPU_IORT & CCR4_IOMASK;
  26.258 +#endif
  26.259 +	write_cyrix_reg(CCR4, ccr4);
  26.260 +
  26.261 +	/* Initialize PCR0. */
  26.262 +	/****************************************************************
  26.263 +	 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
  26.264 +	 * BTB_EN might make your system unstable.
  26.265 +	 ****************************************************************/
  26.266 +	pcr0 = read_cyrix_reg(PCR0);
  26.267 +#ifdef CPU_RSTK_EN
  26.268 +	pcr0 |= PCR0_RSTK;
  26.269 +#else
  26.270 +	pcr0 &= ~PCR0_RSTK;
  26.271 +#endif
  26.272 +#ifdef CPU_BTB_EN
  26.273 +	pcr0 |= PCR0_BTB;
  26.274 +#else
  26.275 +	pcr0 &= ~PCR0_BTB;
  26.276 +#endif
  26.277 +#ifdef CPU_LOOP_EN
  26.278 +	pcr0 |= PCR0_LOOP;
  26.279 +#else
  26.280 +	pcr0 &= ~PCR0_LOOP;
  26.281 +#endif
  26.282 +
  26.283 +	/****************************************************************
  26.284 +	 * WARNING: if you use a memory mapped I/O device, don't use
  26.285 +	 * DISABLE_5X86_LSSER option, which may reorder memory mapped
  26.286 +	 * I/O access.
  26.287 +	 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
  26.288 +	 ****************************************************************/
  26.289 +#ifdef CPU_DISABLE_5X86_LSSER
  26.290 +	pcr0 &= ~PCR0_LSSER;
  26.291 +#else
  26.292 +	pcr0 |= PCR0_LSSER;
  26.293 +#endif
  26.294 +	write_cyrix_reg(PCR0, pcr0);
  26.295 +
  26.296 +	/* Restore CCR3. */
  26.297 +	write_cyrix_reg(CCR3, ccr3);
  26.298 +
  26.299 +	(void)read_cyrix_reg(0x80);		/* dummy */
  26.300 +
  26.301 +	/* Unlock NW bit in CR0. */
  26.302 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  26.303 +	load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0, NW = 1 */
  26.304 +	/* Lock NW bit in CR0. */
  26.305 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  26.306 +
  26.307 +	write_eflags(eflags);
  26.308 +}
  26.309 +
  26.310 +#ifdef CPU_I486_ON_386
  26.311 +/*
  26.312 + * There are i486 based upgrade products for i386 machines.
  26.313 + * In this case, BIOS doesn't enables CPU cache.
  26.314 + */
  26.315 +static void
  26.316 +init_i486_on_386(void)
  26.317 +{
  26.318 +	u_long	eflags;
  26.319 +
  26.320 +#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  26.321 +	need_post_dma_flush = 1;
  26.322 +#endif
  26.323 +
  26.324 +	eflags = read_eflags();
  26.325 +	disable_intr();
  26.326 +
  26.327 +	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0, NW = 0 */
  26.328 +
  26.329 +	write_eflags(eflags);
  26.330 +}
  26.331 +#endif
  26.332 +
  26.333 +/*
  26.334 + * Cyrix 6x86
  26.335 + *
  26.336 + * XXX - What should I do here?  Please let me know.
  26.337 + */
  26.338 +static void
  26.339 +init_6x86(void)
  26.340 +{
  26.341 +	u_long	eflags;
  26.342 +	u_char	ccr3, ccr4;
  26.343 +
  26.344 +	eflags = read_eflags();
  26.345 +	disable_intr();
  26.346 +
  26.347 +	load_cr0(rcr0() | CR0_CD | CR0_NW);
  26.348 +	wbinvd();
  26.349 +
  26.350 +	/* Initialize CCR0. */
  26.351 +	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
  26.352 +
  26.353 +	/* Initialize CCR1. */
  26.354 +#ifdef CPU_CYRIX_NO_LOCK
  26.355 +	write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
  26.356 +#else
  26.357 +	write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
  26.358 +#endif
  26.359 +
  26.360 +	/* Initialize CCR2. */
  26.361 +#ifdef CPU_SUSP_HLT
  26.362 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
  26.363 +#else
  26.364 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
  26.365 +#endif
  26.366 +
  26.367 +	ccr3 = read_cyrix_reg(CCR3);
  26.368 +	write_cyrix_reg(CCR3, CCR3_MAPEN0);
  26.369 +
  26.370 +	/* Initialize CCR4. */
  26.371 +	ccr4 = read_cyrix_reg(CCR4);
  26.372 +	ccr4 |= CCR4_DTE;
  26.373 +	ccr4 &= ~CCR4_IOMASK;
  26.374 +#ifdef CPU_IORT
  26.375 +	write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
  26.376 +#else
  26.377 +	write_cyrix_reg(CCR4, ccr4 | 7);
  26.378 +#endif
  26.379 +
  26.380 +	/* Initialize CCR5. */
  26.381 +#ifdef CPU_WT_ALLOC
  26.382 +	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
  26.383 +#endif
  26.384 +
  26.385 +	/* Restore CCR3. */
  26.386 +	write_cyrix_reg(CCR3, ccr3);
  26.387 +
  26.388 +	/* Unlock NW bit in CR0. */
  26.389 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  26.390 +
  26.391 +	/*
  26.392 +	 * Earlier revision of the 6x86 CPU could crash the system if
  26.393 +	 * L1 cache is in write-back mode.
  26.394 +	 */
  26.395 +	if ((cyrix_did & 0xff00) > 0x1600)
  26.396 +		load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
  26.397 +	else {
  26.398 +		/* Revision 2.6 and lower. */
  26.399 +#ifdef CYRIX_CACHE_REALLY_WORKS
  26.400 +		load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
  26.401 +#else
  26.402 +		load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0 and NW = 1 */
  26.403 +#endif
  26.404 +	}
  26.405 +
  26.406 +	/* Lock NW bit in CR0. */
  26.407 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  26.408 +
  26.409 +	write_eflags(eflags);
  26.410 +}
  26.411 +#endif /* I486_CPU */
  26.412 +
  26.413 +#ifdef I686_CPU
  26.414 +/*
  26.415 + * Cyrix 6x86MX (code-named M2)
  26.416 + *
  26.417 + * XXX - What should I do here?  Please let me know.
  26.418 + */
  26.419 +static void
  26.420 +init_6x86MX(void)
  26.421 +{
  26.422 +#if 0
  26.423 +	u_long	eflags;
  26.424 +	u_char	ccr3, ccr4;
  26.425 +
  26.426 +	eflags = read_eflags();
  26.427 +	disable_intr();
  26.428 +
  26.429 +	load_cr0(rcr0() | CR0_CD | CR0_NW);
  26.430 +	wbinvd();
  26.431 +
  26.432 +	/* Initialize CCR0. */
  26.433 +	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
  26.434 +
  26.435 +	/* Initialize CCR1. */
  26.436 +#ifdef CPU_CYRIX_NO_LOCK
  26.437 +	write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
  26.438 +#else
  26.439 +	write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
  26.440 +#endif
  26.441 +
  26.442 +	/* Initialize CCR2. */
  26.443 +#ifdef CPU_SUSP_HLT
  26.444 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
  26.445 +#else
  26.446 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
  26.447 +#endif
  26.448 +
  26.449 +	ccr3 = read_cyrix_reg(CCR3);
  26.450 +	write_cyrix_reg(CCR3, CCR3_MAPEN0);
  26.451 +
  26.452 +	/* Initialize CCR4. */
  26.453 +	ccr4 = read_cyrix_reg(CCR4);
  26.454 +	ccr4 &= ~CCR4_IOMASK;
  26.455 +#ifdef CPU_IORT
  26.456 +	write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
  26.457 +#else
  26.458 +	write_cyrix_reg(CCR4, ccr4 | 7);
  26.459 +#endif
  26.460 +
  26.461 +	/* Initialize CCR5. */
  26.462 +#ifdef CPU_WT_ALLOC
  26.463 +	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
  26.464 +#endif
  26.465 +
  26.466 +	/* Restore CCR3. */
  26.467 +	write_cyrix_reg(CCR3, ccr3);
  26.468 +
  26.469 +	/* Unlock NW bit in CR0. */
  26.470 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
  26.471 +
  26.472 +	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));	/* CD = 0 and NW = 0 */
  26.473 +
  26.474 +	/* Lock NW bit in CR0. */
  26.475 +	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
  26.476 +
  26.477 +	write_eflags(eflags);
  26.478 +#endif
  26.479 +}
  26.480 +
  26.481 +static void
  26.482 +init_ppro(void)
  26.483 +{
  26.484 +	u_int64_t	apicbase;
  26.485 +
  26.486 +	/*
  26.487 +	 * Local APIC should be disabled if it is not going to be used.
  26.488 +	 */
  26.489 +	apicbase = rdmsr(MSR_APICBASE);
  26.490 +	apicbase &= ~APICBASE_ENABLED;
  26.491 +	wrmsr(MSR_APICBASE, apicbase);
  26.492 +}
  26.493 +
  26.494 +/*
  26.495 + * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
  26.496 + * L2 cache).
  26.497 + */
  26.498 +static void
  26.499 +init_mendocino(void)
  26.500 +{
  26.501 +#ifdef CPU_PPRO2CELERON
  26.502 +	u_long	eflags;
  26.503 +	u_int64_t	bbl_cr_ctl3;
  26.504 +
  26.505 +	eflags = read_eflags();
  26.506 +	disable_intr();
  26.507 +
  26.508 +	load_cr0(rcr0() | CR0_CD | CR0_NW);
  26.509 +	wbinvd();
  26.510 +
  26.511 +	bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
  26.512 +
  26.513 +	/* If the L2 cache is configured, do nothing. */
  26.514 +	if (!(bbl_cr_ctl3 & 1)) {
  26.515 +		bbl_cr_ctl3 = 0x134052bLL;
  26.516 +
  26.517 +		/* Set L2 Cache Latency (Default: 5). */
  26.518 +#ifdef	CPU_CELERON_L2_LATENCY
  26.519 +#if CPU_L2_LATENCY > 15
  26.520 +#error invalid CPU_L2_LATENCY.
  26.521 +#endif
  26.522 +		bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
  26.523 +#else
  26.524 +		bbl_cr_ctl3 |= 5 << 1;
  26.525 +#endif
  26.526 +		wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
  26.527 +	}
  26.528 +
  26.529 +	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
  26.530 +	write_eflags(eflags);
  26.531 +#endif /* CPU_PPRO2CELERON */
  26.532 +}
  26.533 +
  26.534 +#endif /* I686_CPU */
  26.535 +
  26.536 +/*
  26.537 + * Initialize CR4 (Control register 4) to enable SSE instructions.
  26.538 + */
  26.539 +void
  26.540 +enable_sse(void)
  26.541 +{
  26.542 +#ifdef XEN 
  26.543 +    return;
  26.544 +#endif
  26.545 +#if defined(CPU_ENABLE_SSE)
  26.546 +	if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
  26.547 +		load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
  26.548 +		cpu_fxsr = hw_instruction_sse = 1;
  26.549 +	}
  26.550 +#endif
  26.551 +}
  26.552 +
  26.553 +void
  26.554 +initializecpu(void)
  26.555 +{
  26.556 +
  26.557 +	switch (cpu) {
  26.558 +#ifdef I486_CPU
  26.559 +	case CPU_BLUE:
  26.560 +		init_bluelightning();
  26.561 +		break;
  26.562 +	case CPU_486DLC:
  26.563 +		init_486dlc();
  26.564 +		break;
  26.565 +	case CPU_CY486DX:
  26.566 +		init_cy486dx();
  26.567 +		break;
  26.568 +	case CPU_M1SC:
  26.569 +		init_5x86();
  26.570 +		break;
  26.571 +#ifdef CPU_I486_ON_386
  26.572 +	case CPU_486:
  26.573 +		init_i486_on_386();
  26.574 +		break;
  26.575 +#endif
  26.576 +	case CPU_M1:
  26.577 +		init_6x86();
  26.578 +		break;
  26.579 +#endif /* I486_CPU */
  26.580 +#ifdef I686_CPU
  26.581 +	case CPU_M2:
  26.582 +		init_6x86MX();
  26.583 +		break;
  26.584 +	case CPU_686:
  26.585 +		if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  26.586 +			switch (cpu_id & 0xff0) {
  26.587 +			case 0x610:
  26.588 +				init_ppro();
  26.589 +				break;
  26.590 +			case 0x660:
  26.591 +				init_mendocino();
  26.592 +				break;
  26.593 +			}
  26.594 +		} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  26.595 +#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
  26.596 +			/*
  26.597 +			 * Sometimes the BIOS doesn't enable SSE instructions.
  26.598 +			 * According to AMD document 20734, the mobile
  26.599 +			 * Duron, the (mobile) Athlon 4 and the Athlon MP
  26.600 +			 * support SSE. These correspond to cpu_id 0x66X
  26.601 +			 * or 0x67X.
  26.602 +			 */
  26.603 +			if ((cpu_feature & CPUID_XMM) == 0 &&
  26.604 +			    ((cpu_id & ~0xf) == 0x660 ||
  26.605 +			     (cpu_id & ~0xf) == 0x670 ||
  26.606 +			     (cpu_id & ~0xf) == 0x680)) {
  26.607 +				u_int regs[4];
  26.608 +				wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
  26.609 +				do_cpuid(1, regs);
  26.610 +				cpu_feature = regs[3];
  26.611 +			}
  26.612 +#endif
  26.613 +		}
  26.614 +		break;
  26.615 +#endif
  26.616 +	default:
  26.617 +		break;
  26.618 +	}
  26.619 +	enable_sse();
  26.620 +
  26.621 +#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
  26.622 +	/*
  26.623 +	 * OS should flush L1 cache by itself because no PC-98 supports
  26.624 +	 * non-Intel CPUs.  Use wbinvd instruction before DMA transfer
  26.625 +	 * when need_pre_dma_flush = 1, use invd instruction after DMA
  26.626 +	 * transfer when need_post_dma_flush = 1.  If your CPU upgrade
  26.627 +	 * product supports hardware cache control, you can add the
  26.628 +	 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
  26.629 +	 * This option eliminates unneeded cache flush instruction(s).
  26.630 +	 */
  26.631 +	if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
  26.632 +		switch (cpu) {
  26.633 +#ifdef I486_CPU
  26.634 +		case CPU_486DLC:
  26.635 +			need_post_dma_flush = 1;
  26.636 +			break;
  26.637 +		case CPU_M1SC:
  26.638 +			need_pre_dma_flush = 1;
  26.639 +			break;
  26.640 +		case CPU_CY486DX:
  26.641 +			need_pre_dma_flush = 1;
  26.642 +#ifdef CPU_I486_ON_386
  26.643 +			need_post_dma_flush = 1;
  26.644 +#endif
  26.645 +			break;
  26.646 +#endif
  26.647 +		default:
  26.648 +			break;
  26.649 +		}
  26.650 +	} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  26.651 +		switch (cpu_id & 0xFF0) {
  26.652 +		case 0x470:		/* Enhanced Am486DX2 WB */
  26.653 +		case 0x490:		/* Enhanced Am486DX4 WB */
  26.654 +		case 0x4F0:		/* Am5x86 WB */
  26.655 +			need_pre_dma_flush = 1;
  26.656 +			break;
  26.657 +		}
  26.658 +	} else if (strcmp(cpu_vendor, "IBM") == 0) {
  26.659 +		need_post_dma_flush = 1;
  26.660 +	} else {
  26.661 +#ifdef CPU_I486_ON_386
  26.662 +		need_pre_dma_flush = 1;
  26.663 +#endif
  26.664 +	}
  26.665 +#endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
  26.666 +}
  26.667 +
  26.668 +#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  26.669 +/*
  26.670 + * Enable write allocate feature of AMD processors.
  26.671 + * Following two functions require the Maxmem variable being set.
  26.672 + */
  26.673 +void
  26.674 +enable_K5_wt_alloc(void)
  26.675 +{
  26.676 +	u_int64_t	msr;
  26.677 +	register_t	savecrit;
  26.678 +
  26.679 +	/*
  26.680 +	 * Write allocate is supported only on models 1, 2, and 3, with
  26.681 +	 * a stepping of 4 or greater.
  26.682 +	 */
  26.683 +	if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
  26.684 +		savecrit = intr_disable();
  26.685 +		msr = rdmsr(0x83);		/* HWCR */
  26.686 +		wrmsr(0x83, msr & !(0x10));
  26.687 +
  26.688 +		/*
  26.689 +		 * We have to tell the chip where the top of memory is,
  26.690 +		 * since video cards could have frame bufferes there,
  26.691 +		 * memory-mapped I/O could be there, etc.
  26.692 +		 */
  26.693 +		if(Maxmem > 0)
  26.694 +		  msr = Maxmem / 16;
  26.695 +		else
  26.696 +		  msr = 0;
  26.697 +		msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
  26.698 +#ifdef PC98
  26.699 +		if (!(inb(0x43b) & 4)) {
  26.700 +			wrmsr(0x86, 0x0ff00f0);
  26.701 +			msr |= AMD_WT_ALLOC_PRE;
  26.702 +		}
  26.703 +#else
  26.704 +		/*
  26.705 +		 * There is no way to know wheter 15-16M hole exists or not. 
  26.706 +		 * Therefore, we disable write allocate for this range.
  26.707 +		 */
  26.708 +			wrmsr(0x86, 0x0ff00f0);
  26.709 +			msr |= AMD_WT_ALLOC_PRE;
  26.710 +#endif
  26.711 +		wrmsr(0x85, msr);
  26.712 +
  26.713 +		msr=rdmsr(0x83);
  26.714 +		wrmsr(0x83, msr|0x10); /* enable write allocate */
  26.715 +		intr_restore(savecrit);
  26.716 +	}
  26.717 +}
  26.718 +
  26.719 +void
  26.720 +enable_K6_wt_alloc(void)
  26.721 +{
  26.722 +	quad_t	size;
  26.723 +	u_int64_t	whcr;
  26.724 +	u_long	eflags;
  26.725 +
  26.726 +	eflags = read_eflags();
  26.727 +	disable_intr();
  26.728 +	wbinvd();
  26.729 +
  26.730 +#ifdef CPU_DISABLE_CACHE
  26.731 +	/*
  26.732 +	 * Certain K6-2 box becomes unstable when write allocation is
  26.733 +	 * enabled.
  26.734 +	 */
  26.735 +	/*
  26.736 +	 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
  26.737 +	 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
  26.738 +	 * All other bits in TR12 have no effect on the processer's operation.
  26.739 +	 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
  26.740 +	 * on the AMD-K6.
  26.741 +	 */
  26.742 +	wrmsr(0x0000000e, (u_int64_t)0x0008);
  26.743 +#endif
  26.744 +	/* Don't assume that memory size is aligned with 4M. */
  26.745 +	if (Maxmem > 0)
  26.746 +	  size = ((Maxmem >> 8) + 3) >> 2;
  26.747 +	else
  26.748 +	  size = 0;
  26.749 +
  26.750 +	/* Limit is 508M bytes. */
  26.751 +	if (size > 0x7f)
  26.752 +		size = 0x7f;
  26.753 +	whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
  26.754 +
  26.755 +#if defined(PC98) || defined(NO_MEMORY_HOLE)
  26.756 +	if (whcr & (0x7fLL << 1)) {
  26.757 +#ifdef PC98
  26.758 +		/*
  26.759 +		 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
  26.760 +		 * 15-16M range.
  26.761 +		 */
  26.762 +		if (!(inb(0x43b) & 4))
  26.763 +			whcr &= ~0x0001LL;
  26.764 +		else
  26.765 +#endif
  26.766 +			whcr |=  0x0001LL;
  26.767 +	}
  26.768 +#else
  26.769 +	/*
  26.770 +	 * There is no way to know wheter 15-16M hole exists or not. 
  26.771 +	 * Therefore, we disable write allocate for this range.
  26.772 +	 */
  26.773 +	whcr &= ~0x0001LL;
  26.774 +#endif
  26.775 +	wrmsr(0x0c0000082, whcr);
  26.776 +
  26.777 +	write_eflags(eflags);
  26.778 +}
  26.779 +
  26.780 +void
  26.781 +enable_K6_2_wt_alloc(void)
  26.782 +{
  26.783 +	quad_t	size;
  26.784 +	u_int64_t	whcr;
  26.785 +	u_long	eflags;
  26.786 +
  26.787 +	eflags = read_eflags();
  26.788 +	disable_intr();
  26.789 +	wbinvd();
  26.790 +
  26.791 +#ifdef CPU_DISABLE_CACHE
  26.792 +	/*
  26.793 +	 * Certain K6-2 box becomes unstable when write allocation is
  26.794 +	 * enabled.
  26.795 +	 */
  26.796 +	/*
  26.797 +	 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
  26.798 +	 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
  26.799 +	 * All other bits in TR12 have no effect on the processer's operation.
  26.800 +	 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
  26.801 +	 * on the AMD-K6.
  26.802 +	 */
  26.803 +	wrmsr(0x0000000e, (u_int64_t)0x0008);
  26.804 +#endif
  26.805 +	/* Don't assume that memory size is aligned with 4M. */
  26.806 +	if (Maxmem > 0)
  26.807 +	  size = ((Maxmem >> 8) + 3) >> 2;
  26.808 +	else
  26.809 +	  size = 0;
  26.810 +
  26.811 +	/* Limit is 4092M bytes. */
  26.812 +	if (size > 0x3fff)
  26.813 +		size = 0x3ff;
  26.814 +	whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
  26.815 +
  26.816 +#if defined(PC98) || defined(NO_MEMORY_HOLE)
  26.817 +	if (whcr & (0x3ffLL << 22)) {
  26.818 +#ifdef PC98
  26.819 +		/*
  26.820 +		 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
  26.821 +		 * 15-16M range.
  26.822 +		 */
  26.823 +		if (!(inb(0x43b) & 4))
  26.824 +			whcr &= ~(1LL << 16);
  26.825 +		else
  26.826 +#endif
  26.827 +			whcr |=  1LL << 16;
  26.828 +	}
  26.829 +#else
  26.830 +	/*
  26.831 +	 * There is no way to know wheter 15-16M hole exists or not. 
  26.832 +	 * Therefore, we disable write allocate for this range.
  26.833 +	 */
  26.834 +	whcr &= ~(1LL << 16);
  26.835 +#endif
  26.836 +	wrmsr(0x0c0000082, whcr);
  26.837 +
  26.838 +	write_eflags(eflags);
  26.839 +}
  26.840 +#endif /* I585_CPU && CPU_WT_ALLOC */
  26.841 +
  26.842 +#include "opt_ddb.h"
  26.843 +#ifdef DDB
  26.844 +#include <ddb/ddb.h>
  26.845 +#if 0
  26.846 +DB_SHOW_COMMAND(cyrixreg, cyrixreg)
  26.847 +{
  26.848 +	u_long	eflags;
  26.849 +	u_int	cr0;
  26.850 +	u_char	ccr1, ccr2, ccr3;
  26.851 +	u_char	ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
  26.852 +
  26.853 +	cr0 = rcr0();
  26.854 +	if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
  26.855 +		eflags = read_eflags();
  26.856 +		disable_intr();
  26.857 +
  26.858 +
  26.859 +		if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
  26.860 +			ccr0 = read_cyrix_reg(CCR0);
  26.861 +		}
  26.862 +		ccr1 = read_cyrix_reg(CCR1);
  26.863 +		ccr2 = read_cyrix_reg(CCR2);
  26.864 +		ccr3 = read_cyrix_reg(CCR3);
  26.865 +		if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
  26.866 +			write_cyrix_reg(CCR3, CCR3_MAPEN0);
  26.867 +			ccr4 = read_cyrix_reg(CCR4);
  26.868 +			if ((cpu == CPU_M1) || (cpu == CPU_M2))
  26.869 +				ccr5 = read_cyrix_reg(CCR5);
  26.870 +			else
  26.871 +				pcr0 = read_cyrix_reg(PCR0);
  26.872 +			write_cyrix_reg(CCR3, ccr3);		/* Restore CCR3. */
  26.873 +		}
  26.874 +		write_eflags(eflags);
  26.875 +
  26.876 +		if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
  26.877 +			printf("CCR0=%x, ", (u_int)ccr0);
  26.878 +
  26.879 +		printf("CCR1=%x, CCR2=%x, CCR3=%x",
  26.880 +			(u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
  26.881 +		if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
  26.882 +			printf(", CCR4=%x, ", (u_int)ccr4);
  26.883 +			if (cpu == CPU_M1SC)
  26.884 +				printf("PCR0=%x\n", pcr0);
  26.885 +			else
  26.886 +				printf("CCR5=%x\n", ccr5);
  26.887 +		}
  26.888 +	}
  26.889 +	printf("CR0=%x\n", cr0);
  26.890 +}
  26.891 +#endif
  26.892 +#endif /* DDB */
    27.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/intr_machdep.c	Mon Mar 21 07:58:08 2005 +0000
    27.3 @@ -0,0 +1,326 @@
    27.4 +/*-
    27.5 + * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    27.6 + * All rights reserved.
    27.7 + *
    27.8 + * Redistribution and use in source and binary forms, with or without
    27.9 + * modification, are permitted provided that the following conditions
   27.10 + * are met:
   27.11 + * 1. Redistributions of source code must retain the above copyright
   27.12 + *    notice, this list of conditions and the following disclaimer.
   27.13 + * 2. Redistributions in binary form must reproduce the above copyright
   27.14 + *    notice, this list of conditions and the following disclaimer in the
   27.15 + *    documentation and/or other materials provided with the distribution.
   27.16 + * 3. Neither the name of the author nor the names of any co-contributors
   27.17 + *    may be used to endorse or promote products derived from this software
   27.18 + *    without specific prior written permission.
   27.19 + *
   27.20 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   27.21 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   27.22 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   27.23 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   27.24 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27.25 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27.26 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27.27 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27.28 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27.29 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27.30 + * SUCH DAMAGE.
   27.31 + *
   27.32 + * $FreeBSD: src/sys/i386/i386/intr_machdep.c,v 1.4 2003/11/17 06:10:14 peter Exp $
   27.33 + */
   27.34 +
   27.35 +/*
   27.36 + * Machine dependent interrupt code for i386.  For the i386, we have to
   27.37 + * deal with different PICs.  Thus, we use the passed in vector to lookup
   27.38 + * an interrupt source associated with that vector.  The interrupt source
   27.39 + * describes which PIC the source belongs to and includes methods to handle
   27.40 + * that source.
   27.41 + */
   27.42 +
   27.43 +#include "opt_ddb.h"
   27.44 +
   27.45 +#include <sys/param.h>
   27.46 +#include <sys/bus.h>
   27.47 +#include <sys/interrupt.h>
   27.48 +#include <sys/lock.h>
   27.49 +#include <sys/ktr.h>
   27.50 +#include <sys/kernel.h>
   27.51 +#include <sys/mutex.h>
   27.52 +#include <sys/proc.h>
   27.53 +#include <sys/syslog.h>
   27.54 +#include <sys/systm.h>
   27.55 +#include <machine/clock.h>
   27.56 +#include <machine/intr_machdep.h>
   27.57 +#ifdef DDB
   27.58 +#include <ddb/ddb.h>
   27.59 +#endif
   27.60 +
   27.61 +#define	MAX_STRAY_LOG	5
   27.62 +
   27.63 +typedef void (*mask_fn)(uintptr_t vector);
   27.64 +
   27.65 +static int intrcnt_index;
   27.66 +static struct intsrc *interrupt_sources[NUM_IO_INTS];
   27.67 +static struct mtx intr_table_lock;
   27.68 +
   27.69 +static void	intr_init(void *__dummy);
   27.70 +static void	intrcnt_setname(const char *name, int index);
   27.71 +static void	intrcnt_updatename(struct intsrc *is);
   27.72 +static void	intrcnt_register(struct intsrc *is);
   27.73 +
   27.74 +/*
   27.75 + * Register a new interrupt source with the global interrupt system.
   27.76 + * The global interrupts need to be disabled when this function is
   27.77 + * called.
   27.78 + */
   27.79 +int
   27.80 +intr_register_source(struct intsrc *isrc)
   27.81 +{
   27.82 +	int error, vector;
   27.83 +
   27.84 +	vector = isrc->is_pic->pic_vector(isrc);
   27.85 +	if (interrupt_sources[vector] != NULL)
   27.86 +		return (EEXIST);
   27.87 +	error = ithread_create(&isrc->is_ithread, (uintptr_t)isrc, 0,
   27.88 +	    (mask_fn)isrc->is_pic->pic_disable_source,
   27.89 +	    (mask_fn)isrc->is_pic->pic_enable_source, "irq%d:", vector);
   27.90 +	if (error)
   27.91 +		return (error);
   27.92 +	mtx_lock_spin(&intr_table_lock);
   27.93 +	if (interrupt_sources[vector] != NULL) {
   27.94 +		mtx_unlock_spin(&intr_table_lock);
   27.95 +		ithread_destroy(isrc->is_ithread);
   27.96 +		return (EEXIST);
   27.97 +	}
   27.98 +	intrcnt_register(isrc);
   27.99 +	interrupt_sources[vector] = isrc;
  27.100 +	mtx_unlock_spin(&intr_table_lock);
  27.101 +	return (0);
  27.102 +}
  27.103 +
  27.104 +struct intsrc *
  27.105 +intr_lookup_source(int vector)
  27.106 +{
  27.107 +
  27.108 +	return (interrupt_sources[vector]);
  27.109 +}
  27.110 +
  27.111 +int
  27.112 +intr_add_handler(const char *name, int vector, driver_intr_t handler,
  27.113 +    void *arg, enum intr_type flags, void **cookiep)
  27.114 +{
  27.115 +	struct intsrc *isrc;
  27.116 +	int error;
  27.117 +
  27.118 +	isrc = intr_lookup_source(vector);
  27.119 +	if (isrc == NULL)
  27.120 +		return (EINVAL);
  27.121 +
  27.122 +	error = ithread_add_handler(isrc->is_ithread, name, handler, arg,
  27.123 +	    ithread_priority(flags), flags, cookiep);
  27.124 +	if (error == 0) {
  27.125 +		intrcnt_updatename(isrc);
  27.126 +		isrc->is_pic->pic_enable_intr(isrc);
  27.127 +		isrc->is_pic->pic_enable_source(isrc);
  27.128 +	}
  27.129 +	return (error);
  27.130 +}
  27.131 +
  27.132 +int
  27.133 +intr_remove_handler(void *cookie)
  27.134 +{
  27.135 +	int error;
  27.136 +
  27.137 +	error = ithread_remove_handler(cookie);
  27.138 +#ifdef XXX
  27.139 +	if (error == 0)
  27.140 +		intrcnt_updatename(/* XXX */);
  27.141 +#endif
  27.142 +	return (error);
  27.143 +}
  27.144 +
  27.145 +int
  27.146 +intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
  27.147 +{
  27.148 +	struct intsrc *isrc;
  27.149 +
  27.150 +	isrc = intr_lookup_source(vector);
  27.151 +	if (isrc == NULL)
  27.152 +		return (EINVAL);
  27.153 +	return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
  27.154 +}
  27.155 +
  27.156 +void
  27.157 +intr_execute_handlers(struct intsrc *isrc, struct intrframe *iframe)
  27.158 +{
  27.159 +	struct thread *td;
  27.160 +	struct ithd *it;
  27.161 +	struct intrhand *ih;
  27.162 +	int error, vector;
  27.163 +
  27.164 +	td = curthread;
  27.165 +	td->td_intr_nesting_level++;
  27.166 +
  27.167 +	/*
  27.168 +	 * We count software interrupts when we process them.  The
  27.169 +	 * code here follows previous practice, but there's an
  27.170 +	 * argument for counting hardware interrupts when they're
  27.171 +	 * processed too.
  27.172 +	 */
  27.173 +	atomic_add_long(isrc->is_count, 1);
  27.174 +	atomic_add_int(&cnt.v_intr, 1);
  27.175 +
  27.176 +	it = isrc->is_ithread;
  27.177 +	if (it == NULL)
  27.178 +		ih = NULL;
  27.179 +	else
  27.180 +		ih = TAILQ_FIRST(&it->it_handlers);
  27.181 +
  27.182 +	/*
  27.183 +	 * XXX: We assume that IRQ 0 is only used for the ISA timer
  27.184 +	 * device (clk).
  27.185 +	 */
  27.186 +	vector = isrc->is_pic->pic_vector(isrc);
  27.187 +	if (vector == 0)
  27.188 +		clkintr_pending = 1;
  27.189 +
  27.190 +
  27.191 +	if (ih != NULL && ih->ih_flags & IH_FAST) {
  27.192 +		/*
  27.193 +		 * Execute fast interrupt handlers directly.
  27.194 +		 * To support clock handlers, if a handler registers
  27.195 +		 * with a NULL argument, then we pass it a pointer to
  27.196 +		 * a trapframe as its argument.
  27.197 +		 */
  27.198 +		critical_enter();
  27.199 +		TAILQ_FOREACH(ih, &it->it_handlers, ih_next) {
  27.200 +			MPASS(ih->ih_flags & IH_FAST);
  27.201 +			CTR3(KTR_INTR, "%s: executing handler %p(%p)",
  27.202 +			    __func__, ih->ih_handler,
  27.203 +			    ih->ih_argument == NULL ? iframe :
  27.204 +			    ih->ih_argument);
  27.205 +			if (ih->ih_argument == NULL)
  27.206 +				ih->ih_handler(iframe);
  27.207 +			else
  27.208 +				ih->ih_handler(ih->ih_argument);
  27.209 +		}
  27.210 +		isrc->is_pic->pic_eoi_source(isrc);
  27.211 +		error = 0;
  27.212 +		/* XXX */
  27.213 +		td->td_pflags &= ~TDP_OWEPREEMPT;
  27.214 +		critical_exit();
  27.215 +	} else {
  27.216 +		/*
  27.217 +		 * For stray and threaded interrupts, we mask and EOI the
  27.218 +		 * source.
  27.219 +		 */
  27.220 +		isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
  27.221 +		if (ih == NULL)
  27.222 +			error = EINVAL;
  27.223 +		else
  27.224 +			error = ithread_schedule(it);
  27.225 +		isrc->is_pic->pic_eoi_source(isrc);
  27.226 +	}
  27.227 +
  27.228 +	if (error == EINVAL) {
  27.229 +		atomic_add_long(isrc->is_straycount, 1);
  27.230 +		if (*isrc->is_straycount < MAX_STRAY_LOG)
  27.231 +			log(LOG_ERR, "stray irq%d\n", vector);
  27.232 +		else if (*isrc->is_straycount == MAX_STRAY_LOG)
  27.233 +			log(LOG_CRIT,
  27.234 +			    "too many stray irq %d's: not logging anymore\n",
  27.235 +			    vector);
  27.236 +	}
  27.237 +	td->td_intr_nesting_level--;
  27.238 +	
  27.239 +}
  27.240 +
  27.241 +void
  27.242 +intr_resume(void)
  27.243 +{
  27.244 +	struct intsrc **isrc;
  27.245 +	int i;
  27.246 +
  27.247 +	mtx_lock_spin(&intr_table_lock);
  27.248 +	for (i = 0, isrc = interrupt_sources; i < NUM_IO_INTS; i++, isrc++)
  27.249 +		if (*isrc != NULL && (*isrc)->is_pic->pic_resume != NULL)
  27.250 +			(*isrc)->is_pic->pic_resume(*isrc);
  27.251 +	mtx_unlock_spin(&intr_table_lock);
  27.252 +}
  27.253 +
  27.254 +void
  27.255 +intr_suspend(void)
  27.256 +{
  27.257 +	struct intsrc **isrc;
  27.258 +	int i;
  27.259 +
  27.260 +	mtx_lock_spin(&intr_table_lock);
  27.261 +	for (i = 0, isrc = interrupt_sources; i < NUM_IO_INTS; i++, isrc++)
  27.262 +		if (*isrc != NULL && (*isrc)->is_pic->pic_suspend != NULL)
  27.263 +			(*isrc)->is_pic->pic_suspend(*isrc);
  27.264 +	mtx_unlock_spin(&intr_table_lock);
  27.265 +}
  27.266 +
  27.267 +static void
  27.268 +intrcnt_setname(const char *name, int index)
  27.269 +{
  27.270 +
  27.271 +	snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
  27.272 +	    MAXCOMLEN, name);
  27.273 +}
  27.274 +
  27.275 +static void
  27.276 +intrcnt_updatename(struct intsrc *is)
  27.277 +{
  27.278 +
  27.279 +	intrcnt_setname(is->is_ithread->it_td->td_proc->p_comm, is->is_index);
  27.280 +}
  27.281 +
  27.282 +static void
  27.283 +intrcnt_register(struct intsrc *is)
  27.284 +{
  27.285 +	char straystr[MAXCOMLEN + 1];
  27.286 +
  27.287 +	/* mtx_assert(&intr_table_lock, MA_OWNED); */
  27.288 +	KASSERT(is->is_ithread != NULL, ("%s: isrc with no ithread", __func__));
  27.289 +	is->is_index = intrcnt_index;
  27.290 +	intrcnt_index += 2;
  27.291 +	snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
  27.292 +	    is->is_pic->pic_vector(is));
  27.293 +	intrcnt_updatename(is);
  27.294 +	is->is_count = &intrcnt[is->is_index];
  27.295 +	intrcnt_setname(straystr, is->is_index + 1);
  27.296 +	is->is_straycount = &intrcnt[is->is_index + 1];
  27.297 +}
  27.298 +
  27.299 +static void
  27.300 +intr_init(void *dummy __unused)
  27.301 +{
  27.302 +
  27.303 +	intrcnt_setname("???", 0);
  27.304 +	intrcnt_index = 1;
  27.305 +	mtx_init(&intr_table_lock, "intr table", NULL, MTX_SPIN);
  27.306 +}
  27.307 +SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL)
  27.308 +
  27.309 +#ifdef DDB
  27.310 +/*
  27.311 + * Dump data about interrupt handlers
  27.312 + */
  27.313 +DB_SHOW_COMMAND(irqs, db_show_irqs)
  27.314 +{
  27.315 +	struct intsrc **isrc;
  27.316 +	int i, quit, verbose;
  27.317 +
  27.318 +	quit = 0;
  27.319 +	if (strcmp(modif, "v") == 0)
  27.320 +		verbose = 1;
  27.321 +	else
  27.322 +		verbose = 0;
  27.323 +	isrc = interrupt_sources;
  27.324 +	db_setup_paging(db_simple_pager, &quit, DB_LINES_PER_PAGE);
  27.325 +	for (i = 0; i < NUM_IO_INTS && !quit; i++, isrc++)
  27.326 +		if (*isrc != NULL)
  27.327 +			db_dump_ithread((*isrc)->is_ithread, verbose);
  27.328 +}
  27.329 +#endif
    28.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    28.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/io_apic.c	Mon Mar 21 07:58:08 2005 +0000
    28.3 @@ -0,0 +1,850 @@
    28.4 +/*-
    28.5 + * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    28.6 + * All rights reserved.
    28.7 + *
    28.8 + * Redistribution and use in source and binary forms, with or without
    28.9 + * modification, are permitted provided that the following conditions
   28.10 + * are met:
   28.11 + * 1. Redistributions of source code must retain the above copyright
   28.12 + *    notice, this list of conditions and the following disclaimer.
   28.13 + * 2. Redistributions in binary form must reproduce the above copyright
   28.14 + *    notice, this list of conditions and the following disclaimer in the
   28.15 + *    documentation and/or other materials provided with the distribution.
   28.16 + * 3. Neither the name of the author nor the names of any co-contributors
   28.17 + *    may be used to endorse or promote products derived from this software
   28.18 + *    without specific prior written permission.
   28.19 + *
   28.20 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   28.21 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28.22 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   28.23 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   28.24 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28.25 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28.26 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28.27 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28.28 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28.29 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28.30 + * SUCH DAMAGE.
   28.31 + */
   28.32 +
   28.33 +#include <sys/cdefs.h>
   28.34 +__FBSDID("$FreeBSD: src/sys/i386/i386/io_apic.c,v 1.14 2004/08/02 15:31:10 scottl Exp $");
   28.35 +
   28.36 +#include "opt_isa.h"
   28.37 +#include "opt_no_mixed_mode.h"
   28.38 +
   28.39 +#include <sys/param.h>
   28.40 +#include <sys/systm.h>
   28.41 +#include <sys/bus.h>
   28.42 +#include <sys/kernel.h>
   28.43 +#include <sys/malloc.h>
   28.44 +#include <sys/lock.h>
   28.45 +#include <sys/mutex.h>
   28.46 +
   28.47 +#include <vm/vm.h>
   28.48 +#include <vm/pmap.h>
   28.49 +
   28.50 +#include <machine/apicreg.h>
   28.51 +#include <machine/frame.h>
   28.52 +#include <machine/intr_machdep.h>
   28.53 +#include <machine/apicvar.h>
   28.54 +#include <machine/segments.h>
   28.55 +
   28.56 +#define IOAPIC_ISA_INTS		16
   28.57 +#define	IOAPIC_MEM_REGION	32
   28.58 +#define	IOAPIC_REDTBL_LO(i)	(IOAPIC_REDTBL + (i) * 2)
   28.59 +#define	IOAPIC_REDTBL_HI(i)	(IOAPIC_REDTBL_LO(i) + 1)
   28.60 +
   28.61 +#define	VECTOR_EXTINT		252
   28.62 +#define	VECTOR_NMI		253
   28.63 +#define	VECTOR_SMI		254
   28.64 +#define	VECTOR_DISABLED		255
   28.65 +
   28.66 +#define	DEST_NONE		-1
   28.67 +#define	DEST_EXTINT		-2
   28.68 +
   28.69 +#define	TODO		printf("%s: not implemented!\n", __func__)
   28.70 +
   28.71 +MALLOC_DEFINE(M_IOAPIC, "I/O APIC", "I/O APIC structures");
   28.72 +
   28.73 +/*
   28.74 + * New interrupt support code..
   28.75 + *
   28.76 + * XXX: we really should have the interrupt cookie passed up from new-bus
   28.77 + * just be a int pin, and not map 1:1 to interrupt vector number but should
   28.78 + * use INTR_TYPE_FOO to set priority bands for device classes and do all the
   28.79 + * magic remapping of intpin to vector in here.  For now we just cheat as on
   28.80 + * ia64 and map intpin X to vector NRSVIDT + X.  Note that we assume that the
   28.81 + * first IO APIC has ISA interrupts on pins 1-15.  Not sure how you are
   28.82 + * really supposed to figure out which IO APIC in a system with multiple IO
   28.83 + * APIC's actually has the ISA interrupts routed to it.  As far as interrupt
   28.84 + * pin numbers, we use the ACPI System Interrupt number model where each
   28.85 + * IO APIC has a contiguous chunk of the System Interrupt address space.
   28.86 + */
   28.87 +
   28.88 +/*
   28.89 + * Direct the ExtINT pin on the first I/O APIC to a logical cluster of
   28.90 + * CPUs rather than a physical destination of just the BSP.
   28.91 + *
   28.92 + * Note: This is disabled by default as test systems seem to croak with it
   28.93 + * enabled.
   28.94 +#define ENABLE_EXTINT_LOGICAL_DESTINATION
   28.95 + */
   28.96 +
   28.97 +struct ioapic_intsrc {
   28.98 +	struct intsrc io_intsrc;
   28.99 +	u_int io_intpin:8;
  28.100 +	u_int io_vector:8;
  28.101 +	u_int io_activehi:1;
  28.102 +	u_int io_edgetrigger:1;
  28.103 +	u_int io_masked:1;
  28.104 +	int io_dest:5;
  28.105 +	int io_bus:4;
  28.106 +};
  28.107 +
  28.108 +struct ioapic {
  28.109 +	struct pic io_pic;
  28.110 +	u_int io_id:8;			/* logical ID */
  28.111 +	u_int io_apic_id:4;
  28.112 +	u_int io_intbase:8;		/* System Interrupt base */
  28.113 +	u_int io_numintr:8;
  28.114 +	volatile ioapic_t *io_addr;	/* XXX: should use bus_space */
  28.115 +	STAILQ_ENTRY(ioapic) io_next;
  28.116 +	struct ioapic_intsrc io_pins[0];
  28.117 +};
  28.118 +
  28.119 +static u_int	ioapic_read(volatile ioapic_t *apic, int reg);
  28.120 +static void	ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
  28.121 +static const char *ioapic_bus_string(int bus_type);
  28.122 +static void	ioapic_print_vector(struct ioapic_intsrc *intpin);
  28.123 +static void	ioapic_enable_source(struct intsrc *isrc);
  28.124 +static void	ioapic_disable_source(struct intsrc *isrc, int eoi);
  28.125 +static void	ioapic_eoi_source(struct intsrc *isrc);
  28.126 +static void	ioapic_enable_intr(struct intsrc *isrc);
  28.127 +static int	ioapic_vector(struct intsrc *isrc);
  28.128 +static int	ioapic_source_pending(struct intsrc *isrc);
  28.129 +static int	ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
  28.130 +		    enum intr_polarity pol);
  28.131 +static void	ioapic_suspend(struct intsrc *isrc);
  28.132 +static void	ioapic_resume(struct intsrc *isrc);
  28.133 +static void	ioapic_program_destination(struct ioapic_intsrc *intpin);
  28.134 +static void	ioapic_program_intpin(struct ioapic_intsrc *intpin);
  28.135 +static void	ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
  28.136 +
  28.137 +static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
  28.138 +struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
  28.139 +			       ioapic_eoi_source, ioapic_enable_intr,
  28.140 +			       ioapic_vector, ioapic_source_pending,
  28.141 +			       ioapic_suspend, ioapic_resume,
  28.142 +			       ioapic_config_intr };
  28.143 +	
  28.144 +static int bsp_id, current_cluster, logical_clusters, next_ioapic_base;
  28.145 +static u_int mixed_mode_enabled, next_id, program_logical_dest;
  28.146 +#ifdef NO_MIXED_MODE
  28.147 +static int mixed_mode_active = 0;
  28.148 +#else
  28.149 +static int mixed_mode_active = 1;
  28.150 +#endif
  28.151 +TUNABLE_INT("hw.apic.mixed_mode", &mixed_mode_active);
  28.152 +
  28.153 +static __inline void
  28.154 +_ioapic_eoi_source(struct intsrc *isrc)
  28.155 +{
  28.156 +	lapic_eoi();
  28.157 +}
  28.158 +
  28.159 +static u_int
  28.160 +ioapic_read(volatile ioapic_t *apic, int reg)
  28.161 +{
  28.162 +
  28.163 +	mtx_assert(&icu_lock, MA_OWNED);
  28.164 +	apic->ioregsel = reg;
  28.165 +	return (apic->iowin);
  28.166 +}
  28.167 +
  28.168 +static void
  28.169 +ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
  28.170 +{
  28.171 +
  28.172 +	mtx_assert(&icu_lock, MA_OWNED);
  28.173 +	apic->ioregsel = reg;
  28.174 +	apic->iowin = val;
  28.175 +}
  28.176 +
  28.177 +static const char *
  28.178 +ioapic_bus_string(int bus_type)
  28.179 +{
  28.180 +
  28.181 +	switch (bus_type) {
  28.182 +	case APIC_BUS_ISA:
  28.183 +		return ("ISA");
  28.184 +	case APIC_BUS_EISA:
  28.185 +		return ("EISA");
  28.186 +	case APIC_BUS_PCI:
  28.187 +		return ("PCI");
  28.188 +	default:
  28.189 +		return ("unknown");
  28.190 +	}
  28.191 +}
  28.192 +
  28.193 +static void
  28.194 +ioapic_print_vector(struct ioapic_intsrc *intpin)
  28.195 +{
  28.196 +
  28.197 +	switch (intpin->io_vector) {
  28.198 +	case VECTOR_DISABLED:
  28.199 +		printf("disabled");
  28.200 +		break;
  28.201 +	case VECTOR_EXTINT:
  28.202 +		printf("ExtINT");
  28.203 +		break;
  28.204 +	case VECTOR_NMI:
  28.205 +		printf("NMI");
  28.206 +		break;
  28.207 +	case VECTOR_SMI:
  28.208 +		printf("SMI");
  28.209 +		break;
  28.210 +	default:
  28.211 +		printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
  28.212 +		    intpin->io_vector);
  28.213 +	}
  28.214 +}
  28.215 +
  28.216 +static void
  28.217 +ioapic_enable_source(struct intsrc *isrc)
  28.218 +{
  28.219 +	struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  28.220 +	struct ioapic *io = (struct ioapic *)isrc->is_pic;
  28.221 +	uint32_t flags;
  28.222 +
  28.223 +	mtx_lock_spin(&icu_lock);
  28.224 +	if (intpin->io_masked) {
  28.225 +		flags = ioapic_read(io->io_addr,
  28.226 +		    IOAPIC_REDTBL_LO(intpin->io_intpin));
  28.227 +		flags &= ~(IOART_INTMASK);
  28.228 +		ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
  28.229 +		    flags);
  28.230 +		intpin->io_masked = 0;
  28.231 +	}
  28.232 +	mtx_unlock_spin(&icu_lock);
  28.233 +}
  28.234 +
  28.235 +static void
  28.236 +ioapic_disable_source(struct intsrc *isrc, int eoi)
  28.237 +{
  28.238 +	struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  28.239 +	struct ioapic *io = (struct ioapic *)isrc->is_pic;
  28.240 +	uint32_t flags;
  28.241 +
  28.242 +	mtx_lock_spin(&icu_lock);
  28.243 +	if (!intpin->io_masked && !intpin->io_edgetrigger) {
  28.244 +		flags = ioapic_read(io->io_addr,
  28.245 +		    IOAPIC_REDTBL_LO(intpin->io_intpin));
  28.246 +		flags |= IOART_INTMSET;
  28.247 +		ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
  28.248 +		    flags);
  28.249 +		intpin->io_masked = 1;
  28.250 +	}
  28.251 +
  28.252 +	if (eoi == PIC_EOI)
  28.253 +		_ioapic_eoi_source(isrc);
  28.254 +
  28.255 +	mtx_unlock_spin(&icu_lock);
  28.256 +}
  28.257 +
  28.258 +static void
  28.259 +ioapic_eoi_source(struct intsrc *isrc)
  28.260 +{
  28.261 +
  28.262 +	_ioapic_eoi_source(isrc);
  28.263 +}
  28.264 +
  28.265 +/*
  28.266 + * Completely program an intpin based on the data in its interrupt source
  28.267 + * structure.
  28.268 + */
  28.269 +static void
  28.270 +ioapic_program_intpin(struct ioapic_intsrc *intpin)
  28.271 +{
  28.272 +	struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
  28.273 +	uint32_t low, high, value;
  28.274 +
  28.275 +	/*
  28.276 +	 * For pins routed via mixed mode or disabled, just ensure that
  28.277 +	 * they are masked.
  28.278 +	 */
  28.279 +	if (intpin->io_dest == DEST_EXTINT ||
  28.280 +	    intpin->io_vector == VECTOR_DISABLED) {
  28.281 +		low = ioapic_read(io->io_addr,
  28.282 +		    IOAPIC_REDTBL_LO(intpin->io_intpin));
  28.283 +		if ((low & IOART_INTMASK) == IOART_INTMCLR)
  28.284 +			ioapic_write(io->io_addr,
  28.285 +			    IOAPIC_REDTBL_LO(intpin->io_intpin),
  28.286 +			    low | IOART_INTMSET);
  28.287 +		return;
  28.288 +	}
  28.289 +
  28.290 +	/* Set the destination. */
  28.291 +	if (intpin->io_dest == DEST_NONE) {
  28.292 +		low = IOART_DESTPHY;
  28.293 +		high = bsp_id << APIC_ID_SHIFT;
  28.294 +	} else {
  28.295 +		low = IOART_DESTLOG;
  28.296 +		high = (intpin->io_dest << APIC_ID_CLUSTER_SHIFT |
  28.297 +		    APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT;
  28.298 +	}
  28.299 +
  28.300 +	/* Program the rest of the low word. */
  28.301 +	if (intpin->io_edgetrigger)
  28.302 +		low |= IOART_TRGREDG;
  28.303 +	else
  28.304 +		low |= IOART_TRGRLVL;
  28.305 +	if (intpin->io_activehi)
  28.306 +		low |= IOART_INTAHI;
  28.307 +	else
  28.308 +		low |= IOART_INTALO;
  28.309 +	if (intpin->io_masked)
  28.310 +		low |= IOART_INTMSET;
  28.311 +	switch (intpin->io_vector) {
  28.312 +	case VECTOR_EXTINT:
  28.313 +		KASSERT(intpin->io_edgetrigger,
  28.314 +		    ("EXTINT not edge triggered"));
  28.315 +		low |= IOART_DELEXINT;
  28.316 +		break;
  28.317 +	case VECTOR_NMI:
  28.318 +		KASSERT(intpin->io_edgetrigger,
  28.319 +		    ("NMI not edge triggered"));
  28.320 +		low |= IOART_DELNMI;
  28.321 +		break;
  28.322 +	case VECTOR_SMI:
  28.323 +		KASSERT(intpin->io_edgetrigger,
  28.324 +		    ("SMI not edge triggered"));
  28.325 +		low |= IOART_DELSMI;
  28.326 +		break;
  28.327 +	default:
  28.328 +		low |= IOART_DELLOPRI | apic_irq_to_idt(intpin->io_vector);
  28.329 +	}
  28.330 +
  28.331 +	/* Write the values to the APIC. */
  28.332 +	mtx_lock_spin(&icu_lock);
  28.333 +	ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
  28.334 +	value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
  28.335 +	value &= ~IOART_DEST;
  28.336 +	value |= high;
  28.337 +	ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
  28.338 +	mtx_unlock_spin(&icu_lock);
  28.339 +}
  28.340 +
  28.341 +/*
  28.342 + * Program an individual intpin's logical destination.
  28.343 + */
  28.344 +static void
  28.345 +ioapic_program_destination(struct ioapic_intsrc *intpin)
  28.346 +{
  28.347 +	struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
  28.348 +
  28.349 +	KASSERT(intpin->io_dest != DEST_NONE,
  28.350 +	    ("intpin not assigned to a cluster"));
  28.351 +	KASSERT(intpin->io_dest != DEST_EXTINT,
  28.352 +	    ("intpin routed via ExtINT"));
  28.353 +	if (bootverbose) {
  28.354 +		printf("ioapic%u: routing intpin %u (", io->io_id,
  28.355 +		    intpin->io_intpin);
  28.356 +		ioapic_print_vector(intpin);
  28.357 +		printf(") to cluster %u\n", intpin->io_dest);
  28.358 +	}
  28.359 +	ioapic_program_intpin(intpin);
  28.360 +}
  28.361 +
  28.362 +static void
  28.363 +ioapic_assign_cluster(struct ioapic_intsrc *intpin)
  28.364 +{
  28.365 +
  28.366 +	/*
  28.367 +	 * Assign this intpin to a logical APIC cluster in a
  28.368 +	 * round-robin fashion.  We don't actually use the logical
  28.369 +	 * destination for this intpin until after all the CPU's
  28.370 +	 * have been started so that we don't end up with interrupts
  28.371 +	 * that don't go anywhere.  Another alternative might be to
  28.372 +	 * start up the CPU's earlier so that they can handle interrupts
  28.373 +	 * sooner.
  28.374 +	 */
  28.375 +	intpin->io_dest = current_cluster;
  28.376 +	current_cluster++;
  28.377 +	if (current_cluster >= logical_clusters)
  28.378 +		current_cluster = 0;
  28.379 +	if (program_logical_dest)
  28.380 +		ioapic_program_destination(intpin);
  28.381 +}
  28.382 +
  28.383 +static void
  28.384 +ioapic_enable_intr(struct intsrc *isrc)
  28.385 +{
  28.386 +	struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  28.387 +
  28.388 +	KASSERT(intpin->io_dest != DEST_EXTINT,
  28.389 +	    ("ExtINT pin trying to use ioapic enable_intr method"));
  28.390 +	if (intpin->io_dest == DEST_NONE) {
  28.391 +		ioapic_assign_cluster(intpin);
  28.392 +		lapic_enable_intr(intpin->io_vector);
  28.393 +	}
  28.394 +}
  28.395 +
  28.396 +static int
  28.397 +ioapic_vector(struct intsrc *isrc)
  28.398 +{
  28.399 +	struct ioapic_intsrc *pin;
  28.400 +
  28.401 +	pin = (struct ioapic_intsrc *)isrc;
  28.402 +	return (pin->io_vector);
  28.403 +}
  28.404 +
  28.405 +static int
  28.406 +ioapic_source_pending(struct intsrc *isrc)
  28.407 +{
  28.408 +	struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  28.409 +
  28.410 +	return (lapic_intr_pending(intpin->io_vector));
  28.411 +}
  28.412 +
  28.413 +static int
  28.414 +ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
  28.415 +    enum intr_polarity pol)
  28.416 +{
  28.417 +	struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  28.418 +	struct ioapic *io = (struct ioapic *)isrc->is_pic;
  28.419 +	int changed;
  28.420 +
  28.421 +	KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
  28.422 +	    ("%s: Conforming trigger or polarity\n", __func__));
  28.423 +
  28.424 +	/*
  28.425 +	 * EISA interrupts always use active high polarity, so don't allow
  28.426 +	 * them to be set to active low.
  28.427 +	 *
  28.428 +	 * XXX: Should we write to the ELCR if the trigger mode changes for
  28.429 +	 * an EISA IRQ?
  28.430 +	 */
  28.431 +	if (intpin->io_bus == APIC_BUS_EISA)
  28.432 +		pol = INTR_POLARITY_HIGH;
  28.433 +	changed = 0;
  28.434 +	if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
  28.435 +		if (bootverbose)
  28.436 +			printf("ioapic%u: Changing trigger for pin %u to %s\n",
  28.437 +			    io->io_id, intpin->io_intpin,
  28.438 +			    trig == INTR_TRIGGER_EDGE ? "edge" : "level");
  28.439 +		intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
  28.440 +		changed++;
  28.441 +	}
  28.442 +	if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
  28.443 +		if (bootverbose)
  28.444 +			printf("ioapic%u: Changing polarity for pin %u to %s\n",
  28.445 +			    io->io_id, intpin->io_intpin,
  28.446 +			    pol == INTR_POLARITY_HIGH ? "high" : "low");
  28.447 +		intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
  28.448 +		changed++;
  28.449 +	}
  28.450 +	if (changed)
  28.451 +		ioapic_program_intpin(intpin);
  28.452 +	return (0);
  28.453 +}
  28.454 +
  28.455 +static void
  28.456 +ioapic_suspend(struct intsrc *isrc)
  28.457 +{
  28.458 +
  28.459 +	TODO;
  28.460 +}
  28.461 +
  28.462 +static void
  28.463 +ioapic_resume(struct intsrc *isrc)
  28.464 +{
  28.465 +
  28.466 +	ioapic_program_intpin((struct ioapic_intsrc *)isrc);
  28.467 +}
  28.468 +
  28.469 +/*
  28.470 + * APIC enumerators call this function to indicate that the 8259A AT PICs
  28.471 + * are available and that mixed mode can be used.
  28.472 + */
  28.473 +void
  28.474 +ioapic_enable_mixed_mode(void)
  28.475 +{
  28.476 +
  28.477 +	mixed_mode_enabled = 1;
  28.478 +}
  28.479 +
  28.480 +/*
  28.481 + * Allocate and return a logical cluster ID.  Note that the first time
  28.482 + * this is called, it returns cluster 0.  ioapic_enable_intr() treats
  28.483 + * the two cases of logical_clusters == 0 and logical_clusters == 1 the
  28.484 + * same: one cluster of ID 0 exists.  The logical_clusters == 0 case is
  28.485 + * for UP kernels, which should never call this function.
  28.486 + */
  28.487 +int
  28.488 +ioapic_next_logical_cluster(void)
  28.489 +{
  28.490 +
  28.491 +	if (logical_clusters >= APIC_MAX_CLUSTER)
  28.492 +		panic("WARNING: Local APIC cluster IDs exhausted!");
  28.493 +	return (logical_clusters++);
  28.494 +}
  28.495 +
  28.496 +/*
  28.497 + * Create a plain I/O APIC object.
  28.498 + */
  28.499 +void *
  28.500 +ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
  28.501 +{
  28.502 +	struct ioapic *io;
  28.503 +	struct ioapic_intsrc *intpin;
  28.504 +	volatile ioapic_t *apic;
  28.505 +	u_int numintr, i;
  28.506 +	uint32_t value;
  28.507 +
  28.508 +	apic = (ioapic_t *)pmap_mapdev(addr, IOAPIC_MEM_REGION);
  28.509 +	mtx_lock_spin(&icu_lock);
  28.510 +	numintr = ((ioapic_read(apic, IOAPIC_VER) & IOART_VER_MAXREDIR) >>
  28.511 +	    MAXREDIRSHIFT) + 1;
  28.512 +	mtx_unlock_spin(&icu_lock);
  28.513 +	io = malloc(sizeof(struct ioapic) +
  28.514 +	    numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
  28.515 +	io->io_pic = ioapic_template;
  28.516 +	mtx_lock_spin(&icu_lock);
  28.517 +	io->io_id = next_id++;
  28.518 +	io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;	
  28.519 +	if (apic_id != -1 && io->io_apic_id != apic_id) {
  28.520 +		ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
  28.521 +		mtx_unlock_spin(&icu_lock);
  28.522 +		io->io_apic_id = apic_id;
  28.523 +		printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
  28.524 +		    apic_id);
  28.525 +	} else
  28.526 +		mtx_unlock_spin(&icu_lock);
  28.527 +	if (intbase == -1) {
  28.528 +		intbase = next_ioapic_base;
  28.529 +		printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
  28.530 +		    intbase);
  28.531 +	} else if (intbase != next_ioapic_base)
  28.532 +		printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
  28.533 +		    io->io_id, intbase, next_ioapic_base);
  28.534 +	io->io_intbase = intbase;
  28.535 +	next_ioapic_base = intbase + numintr;
  28.536 +	io->io_numintr = numintr;
  28.537 +	io->io_addr = apic;
  28.538 +
  28.539 +	/*
  28.540 +	 * Initialize pins.  Start off with interrupts disabled.  Default
  28.541 +	 * to active-hi and edge-triggered for ISA interrupts and active-lo
  28.542 +	 * and level-triggered for all others.
  28.543 +	 */
  28.544 +	bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
  28.545 +	mtx_lock_spin(&icu_lock);
  28.546 +	for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
  28.547 +		intpin->io_intsrc.is_pic = (struct pic *)io;
  28.548 +		intpin->io_intpin = i;
  28.549 +		intpin->io_vector = intbase + i;
  28.550 +
  28.551 +		/*
  28.552 +		 * Assume that pin 0 on the first I/O APIC is an ExtINT pin
  28.553 +		 * and that pins 1-15 are ISA interrupts.  Assume that all
  28.554 +		 * other pins are PCI interrupts.
  28.555 +		 */
  28.556 +		if (intpin->io_vector == 0)
  28.557 +			ioapic_set_extint(io, i);
  28.558 +		else if (intpin->io_vector < IOAPIC_ISA_INTS) {
  28.559 +			intpin->io_bus = APIC_BUS_ISA;
  28.560 +			intpin->io_activehi = 1;
  28.561 +			intpin->io_edgetrigger = 1;
  28.562 +			intpin->io_masked = 1;
  28.563 +		} else {
  28.564 +			intpin->io_bus = APIC_BUS_PCI;
  28.565 +			intpin->io_activehi = 0;
  28.566 +			intpin->io_edgetrigger = 0;
  28.567 +			intpin->io_masked = 1;
  28.568 +		}
  28.569 +
  28.570 +		/*
  28.571 +		 * Route interrupts to the BSP by default using physical
  28.572 +		 * addressing.  Vectored interrupts get readdressed using
  28.573 +		 * logical IDs to CPU clusters when they are enabled.
  28.574 +		 */
  28.575 +		intpin->io_dest = DEST_NONE;
  28.576 +		if (bootverbose && intpin->io_vector != VECTOR_DISABLED) {
  28.577 +			printf("ioapic%u: intpin %d -> ",  io->io_id, i);
  28.578 +			ioapic_print_vector(intpin);
  28.579 +			printf(" (%s, %s)\n", intpin->io_edgetrigger ?
  28.580 +			    "edge" : "level", intpin->io_activehi ? "high" :
  28.581 +			    "low");
  28.582 +		}
  28.583 +		value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
  28.584 +		ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
  28.585 +	}
  28.586 +	mtx_unlock_spin(&icu_lock);
  28.587 +
  28.588 +	return (io);
  28.589 +}
  28.590 +
  28.591 +int
  28.592 +ioapic_get_vector(void *cookie, u_int pin)
  28.593 +{
  28.594 +	struct ioapic *io;
  28.595 +
  28.596 +	io = (struct ioapic *)cookie;
  28.597 +	if (pin >= io->io_numintr)
  28.598 +		return (-1);
  28.599 +	return (io->io_pins[pin].io_vector);
  28.600 +}
  28.601 +
  28.602 +int
  28.603 +ioapic_disable_pin(void *cookie, u_int pin)
  28.604 +{
  28.605 +	struct ioapic *io;
  28.606 +
  28.607 +	io = (struct ioapic *)cookie;
  28.608 +	if (pin >= io->io_numintr)
  28.609 +		return (EINVAL);
  28.610 +	if (io->io_pins[pin].io_vector == VECTOR_DISABLED)
  28.611 +		return (EINVAL);
  28.612 +	io->io_pins[pin].io_vector = VECTOR_DISABLED;
  28.613 +	if (bootverbose)
  28.614 +		printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
  28.615 +	return (0);
  28.616 +}
  28.617 +
  28.618 +int
  28.619 +ioapic_remap_vector(void *cookie, u_int pin, int vector)
  28.620 +{
  28.621 +	struct ioapic *io;
  28.622 +
  28.623 +	io = (struct ioapic *)cookie;
  28.624 +	if (pin >= io->io_numintr || vector < 0)
  28.625 +		return (EINVAL);
  28.626 +	if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  28.627 +		return (EINVAL);
  28.628 +	io->io_pins[pin].io_vector = vector;
  28.629 +	if (bootverbose)
  28.630 +		printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
  28.631 +		    vector, pin);
  28.632 +	return (0);
  28.633 +}
  28.634 +
  28.635 +int
  28.636 +ioapic_set_bus(void *cookie, u_int pin, int bus_type)
  28.637 +{
  28.638 +	struct ioapic *io;
  28.639 +
  28.640 +	if (bus_type < 0 || bus_type > APIC_BUS_MAX)
  28.641 +		return (EINVAL);
  28.642 +	io = (struct ioapic *)cookie;
  28.643 +	if (pin >= io->io_numintr)
  28.644 +		return (EINVAL);
  28.645 +	if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  28.646 +		return (EINVAL);
  28.647 +	io->io_pins[pin].io_bus = bus_type;
  28.648 +	if (bootverbose)
  28.649 +		printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
  28.650 +		    ioapic_bus_string(bus_type));
  28.651 +	return (0);
  28.652 +}
  28.653 +
  28.654 +int
  28.655 +ioapic_set_nmi(void *cookie, u_int pin)
  28.656 +{
  28.657 +	struct ioapic *io;
  28.658 +
  28.659 +	io = (struct ioapic *)cookie;
  28.660 +	if (pin >= io->io_numintr)
  28.661 +		return (EINVAL);
  28.662 +	if (io->io_pins[pin].io_vector == VECTOR_NMI)
  28.663 +		return (0);
  28.664 +	if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  28.665 +		return (EINVAL);
  28.666 +	io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
  28.667 +	io->io_pins[pin].io_vector = VECTOR_NMI;
  28.668 +	io->io_pins[pin].io_masked = 0;
  28.669 +	io->io_pins[pin].io_edgetrigger = 1;
  28.670 +	io->io_pins[pin].io_activehi = 1;
  28.671 +	if (bootverbose)
  28.672 +		printf("ioapic%u: Routing NMI -> intpin %d\n",
  28.673 +		    io->io_id, pin);
  28.674 +	return (0);
  28.675 +}
  28.676 +
  28.677 +int
  28.678 +ioapic_set_smi(void *cookie, u_int pin)
  28.679 +{
  28.680 +	struct ioapic *io;
  28.681 +
  28.682 +	io = (struct ioapic *)cookie;
  28.683 +	if (pin >= io->io_numintr)
  28.684 +		return (EINVAL);
  28.685 +	if (io->io_pins[pin].io_vector == VECTOR_SMI)
  28.686 +		return (0);
  28.687 +	if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  28.688 +		return (EINVAL);
  28.689 +	io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
  28.690 +	io->io_pins[pin].io_vector = VECTOR_SMI;
  28.691 +	io->io_pins[pin].io_masked = 0;
  28.692 +	io->io_pins[pin].io_edgetrigger = 1;
  28.693 +	io->io_pins[pin].io_activehi = 1;
  28.694 +	if (bootverbose)
  28.695 +		printf("ioapic%u: Routing SMI -> intpin %d\n",
  28.696 +		    io->io_id, pin);
  28.697 +	return (0);
  28.698 +}
  28.699 +
  28.700 +int
  28.701 +ioapic_set_extint(void *cookie, u_int pin)
  28.702 +{
  28.703 +	struct ioapic *io;
  28.704 +
  28.705 +	io = (struct ioapic *)cookie;
  28.706 +	if (pin >= io->io_numintr)
  28.707 +		return (EINVAL);
  28.708 +	if (io->io_pins[pin].io_vector == VECTOR_EXTINT)
  28.709 +		return (0);
  28.710 +	if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  28.711 +		return (EINVAL);
  28.712 +	io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
  28.713 +	io->io_pins[pin].io_vector = VECTOR_EXTINT;
  28.714 +
  28.715 +	/* Enable this pin if mixed mode is available and active. */
  28.716 +	if (mixed_mode_enabled && mixed_mode_active)
  28.717 +		io->io_pins[pin].io_masked = 0;
  28.718 +	else
  28.719 +		io->io_pins[pin].io_masked = 1;
  28.720 +	io->io_pins[pin].io_edgetrigger = 1;
  28.721 +	io->io_pins[pin].io_activehi = 1;
  28.722 +	if (bootverbose)
  28.723 +		printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
  28.724 +		    io->io_id, pin);
  28.725 +	return (0);
  28.726 +}
  28.727 +
  28.728 +int
  28.729 +ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
  28.730 +{
  28.731 +	struct ioapic *io;
  28.732 +
  28.733 +	io = (struct ioapic *)cookie;
  28.734 +	if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
  28.735 +		return (EINVAL);
  28.736 +	if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  28.737 +		return (EINVAL);
  28.738 +	io->io_pins[pin].io_activehi = (pol == INTR_POLARITY_HIGH);
  28.739 +	if (bootverbose)
  28.740 +		printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
  28.741 +		    pol == INTR_POLARITY_HIGH ? "high" : "low");
  28.742 +	return (0);
  28.743 +}
  28.744 +
  28.745 +int
  28.746 +ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
  28.747 +{
  28.748 +	struct ioapic *io;
  28.749 +
  28.750 +	io = (struct ioapic *)cookie;
  28.751 +	if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
  28.752 +		return (EINVAL);
  28.753 +	if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  28.754 +		return (EINVAL);
  28.755 +	io->io_pins[pin].io_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
  28.756 +	if (bootverbose)
  28.757 +		printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
  28.758 +		    trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
  28.759 +	return (0);
  28.760 +}
  28.761 +
  28.762 +/*
  28.763 + * Register a complete I/O APIC object with the interrupt subsystem.
  28.764 + */
  28.765 +void
  28.766 +ioapic_register(void *cookie)
  28.767 +{
  28.768 +	struct ioapic_intsrc *pin;
  28.769 +	struct ioapic *io;
  28.770 +	volatile ioapic_t *apic;
  28.771 +	uint32_t flags;
  28.772 +	int i;
  28.773 +
  28.774 +	io = (struct ioapic *)cookie;
  28.775 +	apic = io->io_addr;
  28.776 +	mtx_lock_spin(&icu_lock);
  28.777 +	flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
  28.778 +	STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
  28.779 +	mtx_unlock_spin(&icu_lock);
  28.780 +	printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
  28.781 +	    io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
  28.782 +	    io->io_intbase + io->io_numintr - 1);
  28.783 +	bsp_id = PCPU_GET(apic_id);
  28.784 +	for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
  28.785 +		/*
  28.786 +		 * Finish initializing the pins by programming the vectors
  28.787 +		 * and delivery mode.
  28.788 +		 */
  28.789 +		if (pin->io_vector == VECTOR_DISABLED)
  28.790 +			continue;
  28.791 +		ioapic_program_intpin(pin);
  28.792 +		if (pin->io_vector >= NUM_IO_INTS)
  28.793 +			continue;
  28.794 +		/*
  28.795 +		 * Route IRQ0 via the 8259A using mixed mode if mixed mode
  28.796 +		 * is available and turned on.
  28.797 +		 */
  28.798 +		if (pin->io_vector == 0 && mixed_mode_active &&
  28.799 +		    mixed_mode_enabled)
  28.800 +			ioapic_setup_mixed_mode(pin);
  28.801 +		else
  28.802 +			intr_register_source(&pin->io_intsrc);
  28.803 +	}
  28.804 +}
  28.805 +
  28.806 +/*
  28.807 + * Program all the intpins to use logical destinations once the AP's
  28.808 + * have been launched.
  28.809 + */
  28.810 +static void
  28.811 +ioapic_set_logical_destinations(void *arg __unused)
  28.812 +{
  28.813 +	struct ioapic *io;
  28.814 +	int i;
  28.815 +
  28.816 +	program_logical_dest = 1;
  28.817 +	STAILQ_FOREACH(io, &ioapic_list, io_next)
  28.818 +	    for (i = 0; i < io->io_numintr; i++)
  28.819 +		    if (io->io_pins[i].io_dest != DEST_NONE &&
  28.820 +			io->io_pins[i].io_dest != DEST_EXTINT)
  28.821 +			    ioapic_program_destination(&io->io_pins[i]);
  28.822 +}
  28.823 +SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND,
  28.824 +    ioapic_set_logical_destinations, NULL)
  28.825 +
  28.826 +/*
  28.827 + * Support for mixed-mode interrupt sources.  These sources route an ISA
  28.828 + * IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
  28.829 + * routes the ISA interrupts.  We just ignore the intpins that use this
  28.830 + * mode and allow the atpic driver to register its interrupt source for
  28.831 + * that IRQ instead.
  28.832 + */
  28.833 +
  28.834 +static void
  28.835 +ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin)
  28.836 +{
  28.837 +	struct ioapic_intsrc *extint;
  28.838 +	struct ioapic *io;
  28.839 +
  28.840 +	/*
  28.841 +	 * Mark the associated I/O APIC intpin as being delivered via
  28.842 +	 * ExtINT and enable the ExtINT pin on the I/O APIC if needed.
  28.843 +	 */
  28.844 +	intpin->io_dest = DEST_EXTINT;
  28.845 +	io = (struct ioapic *)intpin->io_intsrc.is_pic;
  28.846 +	extint = &io->io_pins[0];
  28.847 +	if (extint->io_vector != VECTOR_EXTINT)
  28.848 +		panic("Can't find ExtINT pin to route through!");
  28.849 +#ifdef ENABLE_EXTINT_LOGICAL_DESTINATION
  28.850 +	if (extint->io_dest == DEST_NONE)
  28.851 +		ioapic_assign_cluster(extint);
  28.852 +#endif
  28.853 +}
    29.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    29.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/local_apic.c	Mon Mar 21 07:58:08 2005 +0000
    29.3 @@ -0,0 +1,762 @@
    29.4 +/*-
    29.5 + * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    29.6 + * Copyright (c) 1996, by Steve Passe
    29.7 + * All rights reserved.
    29.8 + *
    29.9 + * Redistribution and use in source and binary forms, with or without
   29.10 + * modification, are permitted provided that the following conditions
   29.11 + * are met:
   29.12 + * 1. Redistributions of source code must retain the above copyright
   29.13 + *    notice, this list of conditions and the following disclaimer.
   29.14 + * 2. The name of the developer may NOT be used to endorse or promote products
   29.15 + *    derived from this software without specific prior written permission.
   29.16 + * 3. Neither the name of the author nor the names of any co-contributors
   29.17 + *    may be used to endorse or promote products derived from this software
   29.18 + *    without specific prior written permission.
   29.19 + *
   29.20 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   29.21 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   29.22 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29.23 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   29.24 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   29.25 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29.26 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29.27 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29.28 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29.29 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29.30 + * SUCH DAMAGE.
   29.31 + */
   29.32 +
   29.33 +/*
   29.34 + * Local APIC support on Pentium and later processors.
   29.35 + */
   29.36 +
   29.37 +#include <sys/cdefs.h>
   29.38 +__FBSDID("$FreeBSD: src/sys/i386/i386/local_apic.c,v 1.9 2004/07/14 18:12:15 jhb Exp $");
   29.39 +
   29.40 +#include <sys/param.h>
   29.41 +#include <sys/systm.h>
   29.42 +#include <sys/bus.h>
   29.43 +#include <sys/kernel.h>
   29.44 +#include <sys/pcpu.h>
   29.45 +
   29.46 +#include <vm/vm.h>
   29.47 +#include <vm/pmap.h>
   29.48 +
   29.49 +#include <machine/apicreg.h>
   29.50 +#include <machine/cputypes.h>
   29.51 +#include <machine/frame.h>
   29.52 +#include <machine/intr_machdep.h>
   29.53 +#include <machine/apicvar.h>
   29.54 +#include <machine/md_var.h>
   29.55 +#include <machine/smp.h>
   29.56 +#include <machine/specialreg.h>
   29.57 +
   29.58 +/*
   29.59 + * We can handle up to 60 APICs via our logical cluster IDs, but currently
   29.60 + * the physical IDs on Intel processors up to the Pentium 4 are limited to
   29.61 + * 16.
   29.62 + */
   29.63 +#define	MAX_APICID	16
   29.64 +
   29.65 +/* Sanity checks on IDT vectors. */
   29.66 +CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS <= APIC_LOCAL_INTS);
   29.67 +CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
   29.68 +
   29.69 +/*
   29.70 + * Support for local APICs.  Local APICs manage interrupts on each
   29.71 + * individual processor as opposed to I/O APICs which receive interrupts
   29.72 + * from I/O devices and then forward them on to the local APICs.
   29.73 + *
   29.74 + * Local APICs can also send interrupts to each other thus providing the
   29.75 + * mechanism for IPIs.
   29.76 + */
   29.77 +
   29.78 +struct lvt {
   29.79 +	u_int lvt_edgetrigger:1;
   29.80 +	u_int lvt_activehi:1;
   29.81 +	u_int lvt_masked:1;
   29.82 +	u_int lvt_active:1;
   29.83 +	u_int lvt_mode:16;
   29.84 +	u_int lvt_vector:8;
   29.85 +};
   29.86 +
   29.87 +struct lapic {
   29.88 +	struct lvt la_lvts[LVT_MAX + 1];
   29.89 +	u_int la_id:8;
   29.90 +	u_int la_cluster:4;
   29.91 +	u_int la_cluster_id:2;
   29.92 +	u_int la_present:1;
   29.93 +} static lapics[MAX_APICID];
   29.94 +
   29.95 +/* XXX: should thermal be an NMI? */
   29.96 +
   29.97 +/* Global defaults for local APIC LVT entries. */
   29.98 +static struct lvt lvts[LVT_MAX + 1] = {
   29.99 +	{ 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 },	/* LINT0: masked ExtINT */
  29.100 +	{ 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 },	/* LINT1: NMI */
  29.101 +	{ 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },	/* Timer: needs a vector */
  29.102 +	{ 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },	/* Error: needs a vector */
  29.103 +	{ 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },	/* PMC */
  29.104 +	{ 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 },	/* Thermal: needs a vector */
  29.105 +};
  29.106 +
  29.107 +static inthand_t *ioint_handlers[] = {
  29.108 +	NULL,			/* 0 - 31 */
  29.109 +	IDTVEC(apic_isr1),	/* 32 - 63 */
  29.110 +	IDTVEC(apic_isr2),	/* 64 - 95 */
  29.111 +	IDTVEC(apic_isr3),	/* 96 - 127 */
  29.112 +	IDTVEC(apic_isr4),	/* 128 - 159 */
  29.113 +	IDTVEC(apic_isr5),	/* 160 - 191 */
  29.114 +	IDTVEC(apic_isr6),	/* 192 - 223 */
  29.115 +	IDTVEC(apic_isr7),	/* 224 - 255 */
  29.116 +};
  29.117 +
  29.118 +volatile lapic_t *lapic;
  29.119 +
  29.120 +static uint32_t
  29.121 +lvt_mode(struct lapic *la, u_int pin, uint32_t value)
  29.122 +{
  29.123 +	struct lvt *lvt;
  29.124 +
  29.125 +	KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
  29.126 +	if (la->la_lvts[pin].lvt_active)
  29.127 +		lvt = &la->la_lvts[pin];
  29.128 +	else
  29.129 +		lvt = &lvts[pin];
  29.130 +
  29.131 +	value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
  29.132 +	    APIC_LVT_VECTOR);
  29.133 +	if (lvt->lvt_edgetrigger == 0)
  29.134 +		value |= APIC_LVT_TM;
  29.135 +	if (lvt->lvt_activehi == 0)
  29.136 +		value |= APIC_LVT_IIPP_INTALO;
  29.137 +	if (lvt->lvt_masked)
  29.138 +		value |= APIC_LVT_M;
  29.139 +	value |= lvt->lvt_mode;
  29.140 +	switch (lvt->lvt_mode) {
  29.141 +	case APIC_LVT_DM_NMI:
  29.142 +	case APIC_LVT_DM_SMI:
  29.143 +	case APIC_LVT_DM_INIT:
  29.144 +	case APIC_LVT_DM_EXTINT:
  29.145 +		if (!lvt->lvt_edgetrigger) {
  29.146 +			printf("lapic%u: Forcing LINT%u to edge trigger\n",
  29.147 +			    la->la_id, pin);
  29.148 +			value |= APIC_LVT_TM;
  29.149 +		}
  29.150 +		/* Use a vector of 0. */
  29.151 +		break;
  29.152 +	case APIC_LVT_DM_FIXED:
  29.153 +#if 0
  29.154 +		value |= lvt->lvt_vector;
  29.155 +#else
  29.156 +		panic("Fixed LINT pins not supported");
  29.157 +#endif
  29.158 +		break;
  29.159 +	default:
  29.160 +		panic("bad APIC LVT delivery mode: %#x\n", value);
  29.161 +	}
  29.162 +	return (value);
  29.163 +}
  29.164 +
  29.165 +/*
  29.166 + * Map the local APIC and setup necessary interrupt vectors.
  29.167 + */
  29.168 +void
  29.169 +lapic_init(uintptr_t addr)
  29.170 +{
  29.171 +	u_int32_t value;
  29.172 +
  29.173 +	/* Map the local APIC and setup the spurious interrupt handler. */
  29.174 +	KASSERT(trunc_page(addr) == addr,
  29.175 +	    ("local APIC not aligned on a page boundary"));
  29.176 +	lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
  29.177 +	setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
  29.178 +	    GSEL(GCODE_SEL, SEL_KPL));
  29.179 +
  29.180 +	/* Perform basic initialization of the BSP's local APIC. */
  29.181 +	value = lapic->svr;
  29.182 +	value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
  29.183 +	value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
  29.184 +	lapic->svr = value;
  29.185 +
  29.186 +	/* Set BSP's per-CPU local APIC ID. */
  29.187 +	PCPU_SET(apic_id, lapic_id());
  29.188 +
  29.189 +	/* XXX: timer/error/thermal interrupts */
  29.190 +}
  29.191 +
  29.192 +/*
  29.193 + * Create a local APIC instance.
  29.194 + */
  29.195 +void
  29.196 +lapic_create(u_int apic_id, int boot_cpu)
  29.197 +{
  29.198 +	int i;
  29.199 +
  29.200 +	if (apic_id >= MAX_APICID) {
  29.201 +		printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
  29.202 +		if (boot_cpu)
  29.203 +			panic("Can't ignore BSP");
  29.204 +		return;
  29.205 +	}
  29.206 +	KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
  29.207 +	    apic_id));
  29.208 +
  29.209 +	/*
  29.210 +	 * Assume no local LVT overrides and a cluster of 0 and
  29.211 +	 * intra-cluster ID of 0.
  29.212 +	 */
  29.213 +	lapics[apic_id].la_present = 1;
  29.214 +	lapics[apic_id].la_id = apic_id;
  29.215 +	for (i = 0; i < LVT_MAX; i++) {
  29.216 +		lapics[apic_id].la_lvts[i] = lvts[i];
  29.217 +		lapics[apic_id].la_lvts[i].lvt_active = 0;
  29.218 +	}
  29.219 +
  29.220 +#ifdef SMP
  29.221 +	cpu_add(apic_id, boot_cpu);
  29.222 +#endif
  29.223 +}
  29.224 +
  29.225 +/*
  29.226 + * Dump contents of local APIC registers
  29.227 + */
  29.228 +void
  29.229 +lapic_dump(const char* str)
  29.230 +{
  29.231 +
  29.232 +	printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
  29.233 +	printf("     ID: 0x%08x   VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
  29.234 +	    lapic->id, lapic->version, lapic->ldr, lapic->dfr);
  29.235 +	printf("  lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
  29.236 +	    lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
  29.237 +}
  29.238 +
  29.239 +void
  29.240 +lapic_enable_intr(u_int irq)
  29.241 +{
  29.242 +	u_int vector;
  29.243 +
  29.244 +	vector = apic_irq_to_idt(irq);
  29.245 +	KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
  29.246 +	KASSERT(ioint_handlers[vector / 32] != NULL,
  29.247 +	    ("No ISR handler for IRQ %u", irq));
  29.248 +	setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL,
  29.249 +	    GSEL(GCODE_SEL, SEL_KPL));
  29.250 +}
  29.251 +
  29.252 +void
  29.253 +lapic_setup(void)
  29.254 +{
  29.255 +	struct lapic *la;
  29.256 +	u_int32_t value, maxlvt;
  29.257 +	register_t eflags;
  29.258 +
  29.259 +	la = &lapics[lapic_id()];
  29.260 +	KASSERT(la->la_present, ("missing APIC structure"));
  29.261 +	eflags = intr_disable();
  29.262 +	maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
  29.263 +
  29.264 +	/* Program LINT[01] LVT entries. */
  29.265 +	lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
  29.266 +	lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
  29.267 +
  29.268 +	/* XXX: more LVT entries */
  29.269 +
  29.270 +	/* Clear the TPR. */
  29.271 +	value = lapic->tpr;
  29.272 +	value &= ~APIC_TPR_PRIO;
  29.273 +	lapic->tpr = value;
  29.274 +
  29.275 +	/* Use the cluster model for logical IDs. */
  29.276 +	value = lapic->dfr;
  29.277 +	value &= ~APIC_DFR_MODEL_MASK;
  29.278 +	value |= APIC_DFR_MODEL_CLUSTER;
  29.279 +	lapic->dfr = value;
  29.280 +
  29.281 +	/* Set this APIC's logical ID. */
  29.282 +	value = lapic->ldr;
  29.283 +	value &= ~APIC_ID_MASK;
  29.284 +	value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT |
  29.285 +	    1 << la->la_cluster_id) << APIC_ID_SHIFT;
  29.286 +	lapic->ldr = value;
  29.287 +
  29.288 +	/* Setup spurious vector and enable the local APIC. */
  29.289 +	value = lapic->svr;
  29.290 +	value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
  29.291 +	value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
  29.292 +	lapic->svr = value;
  29.293 +	intr_restore(eflags);
  29.294 +}
  29.295 +
  29.296 +void
  29.297 +lapic_disable(void)
  29.298 +{
  29.299 +	uint32_t value;
  29.300 +
  29.301 +	/* Software disable the local APIC. */
  29.302 +	value = lapic->svr;
  29.303 +	value &= ~APIC_SVR_SWEN;
  29.304 +	lapic->svr = value;
  29.305 +}
  29.306 +
  29.307 +int
  29.308 +lapic_id(void)
  29.309 +{
  29.310 +
  29.311 +	KASSERT(lapic != NULL, ("local APIC is not mapped"));
  29.312 +	return (lapic->id >> APIC_ID_SHIFT);
  29.313 +}
  29.314 +
  29.315 +int
  29.316 +lapic_intr_pending(u_int vector)
  29.317 +{
  29.318 +	volatile u_int32_t *irr;
  29.319 +
  29.320 +	/*
  29.321 +	 * The IRR registers are an array of 128-bit registers each of
  29.322 +	 * which only describes 32 interrupts in the low 32 bits..  Thus,
  29.323 +	 * we divide the vector by 32 to get the 128-bit index.  We then
  29.324 +	 * multiply that index by 4 to get the equivalent index from
  29.325 +	 * treating the IRR as an array of 32-bit registers.  Finally, we
  29.326 +	 * modulus the vector by 32 to determine the individual bit to
  29.327 +	 * test.
  29.328 +	 */
  29.329 +	irr = &lapic->irr0;
  29.330 +	return (irr[(vector / 32) * 4] & 1 << (vector % 32));
  29.331 +}
  29.332 +
  29.333 +void
  29.334 +lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
  29.335 +{
  29.336 +	struct lapic *la;
  29.337 +
  29.338 +	KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
  29.339 +	    __func__, apic_id));
  29.340 +	KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
  29.341 +	    __func__, cluster));
  29.342 +	KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
  29.343 +	    ("%s: intra cluster id %u too big", __func__, cluster_id));
  29.344 +	la = &lapics[apic_id];
  29.345 +	la->la_cluster = cluster;
  29.346 +	la->la_cluster_id = cluster_id;
  29.347 +}
  29.348 +
  29.349 +int
  29.350 +lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
  29.351 +{
  29.352 +
  29.353 +	if (pin > LVT_MAX)
  29.354 +		return (EINVAL);
  29.355 +	if (apic_id == APIC_ID_ALL) {
  29.356 +		lvts[pin].lvt_masked = masked;
  29.357 +		if (bootverbose)
  29.358 +			printf("lapic:");
  29.359 +	} else {
  29.360 +		KASSERT(lapics[apic_id].la_present,
  29.361 +		    ("%s: missing APIC %u", __func__, apic_id));
  29.362 +		lapics[apic_id].la_lvts[pin].lvt_masked = masked;
  29.363 +		lapics[apic_id].la_lvts[pin].lvt_active = 1;
  29.364 +		if (bootverbose)
  29.365 +			printf("lapic%u:", apic_id);
  29.366 +	}
  29.367 +	if (bootverbose)
  29.368 +		printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
  29.369 +	return (0);
  29.370 +}
  29.371 +
  29.372 +int
  29.373 +lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
  29.374 +{
  29.375 +	struct lvt *lvt;
  29.376 +
  29.377 +	if (pin > LVT_MAX)
  29.378 +		return (EINVAL);
  29.379 +	if (apic_id == APIC_ID_ALL) {
  29.380 +		lvt = &lvts[pin];
  29.381 +		if (bootverbose)
  29.382 +			printf("lapic:");
  29.383 +	} else {
  29.384 +		KASSERT(lapics[apic_id].la_present,
  29.385 +		    ("%s: missing APIC %u", __func__, apic_id));
  29.386 +		lvt = &lapics[apic_id].la_lvts[pin];
  29.387 +		lvt->lvt_active = 1;
  29.388 +		if (bootverbose)
  29.389 +			printf("lapic%u:", apic_id);
  29.390 +	}
  29.391 +	lvt->lvt_mode = mode;
  29.392 +	switch (mode) {
  29.393 +	case APIC_LVT_DM_NMI:
  29.394 +	case APIC_LVT_DM_SMI:
  29.395 +	case APIC_LVT_DM_INIT:
  29.396 +	case APIC_LVT_DM_EXTINT:
  29.397 +		lvt->lvt_edgetrigger = 1;
  29.398 +		lvt->lvt_activehi = 1;
  29.399 +		if (mode == APIC_LVT_DM_EXTINT)
  29.400 +			lvt->lvt_masked = 1;
  29.401 +		else
  29.402 +			lvt->lvt_masked = 0;
  29.403 +		break;
  29.404 +	default:
  29.405 +		panic("Unsupported delivery mode: 0x%x\n", mode);
  29.406 +	}
  29.407 +	if (bootverbose) {
  29.408 +		printf(" Routing ");
  29.409 +		switch (mode) {
  29.410 +		case APIC_LVT_DM_NMI:
  29.411 +			printf("NMI");
  29.412 +			break;
  29.413 +		case APIC_LVT_DM_SMI:
  29.414 +			printf("SMI");
  29.415 +			break;
  29.416 +		case APIC_LVT_DM_INIT:
  29.417 +			printf("INIT");
  29.418 +			break;
  29.419 +		case APIC_LVT_DM_EXTINT:
  29.420 +			printf("ExtINT");
  29.421 +			break;
  29.422 +		}
  29.423 +		printf(" -> LINT%u\n", pin);
  29.424 +	}
  29.425 +	return (0);
  29.426 +}
  29.427 +
  29.428 +int
  29.429 +lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
  29.430 +{
  29.431 +
  29.432 +	if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
  29.433 +		return (EINVAL);
  29.434 +	if (apic_id == APIC_ID_ALL) {
  29.435 +		lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
  29.436 +		if (bootverbose)
  29.437 +			printf("lapic:");
  29.438 +	} else {
  29.439 +		KASSERT(lapics[apic_id].la_present,
  29.440 +		    ("%s: missing APIC %u", __func__, apic_id));
  29.441 +		lapics[apic_id].la_lvts[pin].lvt_active = 1;
  29.442 +		lapics[apic_id].la_lvts[pin].lvt_activehi =
  29.443 +		    (pol == INTR_POLARITY_HIGH);
  29.444 +		if (bootverbose)
  29.445 +			printf("lapic%u:", apic_id);
  29.446 +	}
  29.447 +	if (bootverbose)
  29.448 +		printf(" LINT%u polarity: active-%s\n", pin,
  29.449 +		    pol == INTR_POLARITY_HIGH ? "high" : "low");
  29.450 +	return (0);
  29.451 +}
  29.452 +
  29.453 +int
  29.454 +lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
  29.455 +{
  29.456 +
  29.457 +	if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
  29.458 +		return (EINVAL);
  29.459 +	if (apic_id == APIC_ID_ALL) {
  29.460 +		lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
  29.461 +		if (bootverbose)
  29.462 +			printf("lapic:");
  29.463 +	} else {
  29.464 +		KASSERT(lapics[apic_id].la_present,
  29.465 +		    ("%s: missing APIC %u", __func__, apic_id));
  29.466 +		lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
  29.467 +		    (trigger == INTR_TRIGGER_EDGE);
  29.468 +		lapics[apic_id].la_lvts[pin].lvt_active = 1;
  29.469 +		if (bootverbose)
  29.470 +			printf("lapic%u:", apic_id);
  29.471 +	}
  29.472 +	if (bootverbose)
  29.473 +		printf(" LINT%u trigger: %s\n", pin,
  29.474 +		    trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
  29.475 +	return (0);
  29.476 +}
  29.477 +
  29.478 +void
  29.479 +lapic_eoi(void)
  29.480 +{
  29.481 +
  29.482 +	lapic->eoi = 0;
  29.483 +}
  29.484 +
  29.485 +void
  29.486 +lapic_handle_intr(struct intrframe frame)
  29.487 +{
  29.488 +	struct intsrc *isrc;
  29.489 +
  29.490 +	if (frame.if_vec == -1)
  29.491 +		panic("Couldn't get vector from ISR!");
  29.492 +	isrc = intr_lookup_source(apic_idt_to_irq(frame.if_vec));
  29.493 +	intr_execute_handlers(isrc, &frame);
  29.494 +}
  29.495 +
  29.496 +/* Translate between IDT vectors and IRQ vectors. */
  29.497 +u_int
  29.498 +apic_irq_to_idt(u_int irq)
  29.499 +{
  29.500 +	u_int vector;
  29.501 +
  29.502 +	KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
  29.503 +	vector = irq + APIC_IO_INTS;
  29.504 +	if (vector >= IDT_SYSCALL)
  29.505 +		vector++;
  29.506 +	return (vector);
  29.507 +}
  29.508 +
  29.509 +u_int
  29.510 +apic_idt_to_irq(u_int vector)
  29.511 +{
  29.512 +
  29.513 +	KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
  29.514 +	    vector <= APIC_IO_INTS + NUM_IO_INTS,
  29.515 +	    ("Vector %u does not map to an IRQ line", vector));
  29.516 +	if (vector > IDT_SYSCALL)
  29.517 +		vector--;
  29.518 +	return (vector - APIC_IO_INTS);
  29.519 +}
  29.520 +
  29.521 +/*
  29.522 + * APIC probing support code.  This includes code to manage enumerators.
  29.523 + */
  29.524 +
  29.525 +static SLIST_HEAD(, apic_enumerator) enumerators =
  29.526 +	SLIST_HEAD_INITIALIZER(enumerators);
  29.527 +static struct apic_enumerator *best_enum;
  29.528 +	
  29.529 +void
  29.530 +apic_register_enumerator(struct apic_enumerator *enumerator)
  29.531 +{
  29.532 +#ifdef INVARIANTS
  29.533 +	struct apic_enumerator *apic_enum;
  29.534 +
  29.535 +	SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
  29.536 +		if (apic_enum == enumerator)
  29.537 +			panic("%s: Duplicate register of %s", __func__,
  29.538 +			    enumerator->apic_name);
  29.539 +	}
  29.540 +#endif
  29.541 +	SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
  29.542 +}
  29.543 +
  29.544 +/*
  29.545 + * Probe the APIC enumerators, enumerate CPUs, and initialize the
  29.546 + * local APIC.
  29.547 + */
  29.548 +static void
  29.549 +apic_init(void *dummy __unused)
  29.550 +{
  29.551 +	struct apic_enumerator *enumerator;
  29.552 +	uint64_t apic_base;
  29.553 +	int retval, best;
  29.554 +
  29.555 +	/* We only support built in local APICs. */
  29.556 +	if (!(cpu_feature & CPUID_APIC))
  29.557 +		return;
  29.558 +
  29.559 +	/* Don't probe if APIC mode is disabled. */
  29.560 +	if (resource_disabled("apic", 0))
  29.561 +		return;
  29.562 +
  29.563 +	/* First, probe all the enumerators to find the best match. */
  29.564 +	best_enum = NULL;
  29.565 +	best = 0;
  29.566 +	SLIST_FOREACH(enumerator, &enumerators, apic_next) {
  29.567 +		retval = enumerator->apic_probe();
  29.568 +		if (retval > 0)
  29.569 +			continue;
  29.570 +		if (best_enum == NULL || best < retval) {
  29.571 +			best_enum = enumerator;
  29.572 +			best = retval;
  29.573 +		}
  29.574 +	}
  29.575 +	if (best_enum == NULL) {
  29.576 +		if (bootverbose)
  29.577 +			printf("APIC: Could not find any APICs.\n");
  29.578 +		return;
  29.579 +	}
  29.580 +
  29.581 +	if (bootverbose)
  29.582 +		printf("APIC: Using the %s enumerator.\n",
  29.583 +		    best_enum->apic_name);
  29.584 +
  29.585 +	/*
  29.586 +	 * To work around an errata, we disable the local APIC on some
  29.587 +	 * CPUs during early startup.  We need to turn the local APIC back
  29.588 +	 * on on such CPUs now.
  29.589 +	 */
  29.590 +	if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
  29.591 +	    (cpu_id & 0xff0) == 0x610) {
  29.592 +		apic_base = rdmsr(MSR_APICBASE);
  29.593 +		apic_base |= APICBASE_ENABLED;
  29.594 +		wrmsr(MSR_APICBASE, apic_base);
  29.595 +	}
  29.596 +
  29.597 +	/* Second, probe the CPU's in the system. */
  29.598 +	retval = best_enum->apic_probe_cpus();
  29.599 +	if (retval != 0)
  29.600 +		printf("%s: Failed to probe CPUs: returned %d\n",
  29.601 +		    best_enum->apic_name, retval);
  29.602 +
  29.603 +	/* Third, initialize the local APIC. */
  29.604 +	retval = best_enum->apic_setup_local();
  29.605 +	if (retval != 0)
  29.606 +		printf("%s: Failed to setup the local APIC: returned %d\n",
  29.607 +		    best_enum->apic_name, retval);
  29.608 +#ifdef SMP
  29.609 +	/* Last, setup the cpu topology now that we have probed CPUs */
  29.610 +	mp_topology();
  29.611 +#endif
  29.612 +}
  29.613 +SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL)
  29.614 +
  29.615 +/*
  29.616 + * Setup the I/O APICs.
  29.617 + */
  29.618 +static void
  29.619 +apic_setup_io(void *dummy __unused)
  29.620 +{
  29.621 +	int retval;
  29.622 +
  29.623 +	if (best_enum == NULL)
  29.624 +		return;
  29.625 +	retval = best_enum->apic_setup_io();
  29.626 +	if (retval != 0)
  29.627 +		printf("%s: Failed to setup I/O APICs: returned %d\n",
  29.628 +		    best_enum->apic_name, retval);
  29.629 +
  29.630 +	/*
  29.631 +	 * Finish setting up the local APIC on the BSP once we know how to
  29.632 +	 * properly program the LINT pins.
  29.633 +	 */
  29.634 +	lapic_setup();
  29.635 +	if (bootverbose)
  29.636 +		lapic_dump("BSP");
  29.637 +}
  29.638 +SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
  29.639 +
  29.640 +#ifdef SMP
  29.641 +/*
  29.642 + * Inter Processor Interrupt functions.  The lapic_ipi_*() functions are
  29.643 + * private the sys/i386 code.  The public interface for the rest of the
  29.644 + * kernel is defined in mp_machdep.c.
  29.645 + */
  29.646 +
  29.647 +int
  29.648 +lapic_ipi_wait(int delay)
  29.649 +{
  29.650 +	int x, incr;
  29.651 +
  29.652 +	/*
  29.653 +	 * Wait delay loops for IPI to be sent.  This is highly bogus
  29.654 +	 * since this is sensitive to CPU clock speed.  If delay is
  29.655 +	 * -1, we wait forever.
  29.656 +	 */
  29.657 +	if (delay == -1) {
  29.658 +		incr = 0;
  29.659 +		delay = 1;
  29.660 +	} else
  29.661 +		incr = 1;
  29.662 +	for (x = 0; x < delay; x += incr) {
  29.663 +		if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
  29.664 +			return (1);
  29.665 +		ia32_pause();
  29.666 +	}
  29.667 +	return (0);
  29.668 +}
  29.669 +
  29.670 +void
  29.671 +lapic_ipi_raw(register_t icrlo, u_int dest)
  29.672 +{
  29.673 +	register_t value, eflags;
  29.674 +
  29.675 +	/* XXX: Need more sanity checking of icrlo? */
  29.676 +	KASSERT(lapic != NULL, ("%s called too early", __func__));
  29.677 +	KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
  29.678 +	    ("%s: invalid dest field", __func__));
  29.679 +	KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
  29.680 +	    ("%s: reserved bits set in ICR LO register", __func__));
  29.681 +
  29.682 +	/* Set destination in ICR HI register if it is being used. */
  29.683 +	eflags = intr_disable();
  29.684 +	if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
  29.685 +		value = lapic->icr_hi;
  29.686 +		value &= ~APIC_ID_MASK;
  29.687 +		value |= dest << APIC_ID_SHIFT;
  29.688 +		lapic->icr_hi = value;
  29.689 +	}
  29.690 +
  29.691 +	/* Program the contents of the IPI and dispatch it. */
  29.692 +	value = lapic->icr_lo;
  29.693 +	value &= APIC_ICRLO_RESV_MASK;
  29.694 +	value |= icrlo;
  29.695 +	lapic->icr_lo = value;
  29.696 +	intr_restore(eflags);
  29.697 +}
  29.698 +
  29.699 +#define	BEFORE_SPIN	1000000
  29.700 +#ifdef DETECT_DEADLOCK
  29.701 +#define	AFTER_SPIN	1000
  29.702 +#endif
  29.703 +
  29.704 +void
  29.705 +lapic_ipi_vectored(u_int vector, int dest)
  29.706 +{
  29.707 +	register_t icrlo, destfield;
  29.708 +
  29.709 +	KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
  29.710 +	    ("%s: invalid vector %d", __func__, vector));
  29.711 +
  29.712 +	icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
  29.713 +	    APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
  29.714 +	destfield = 0;
  29.715 +	switch (dest) {
  29.716 +	case APIC_IPI_DEST_SELF:
  29.717 +		icrlo |= APIC_DEST_SELF;
  29.718 +		break;
  29.719 +	case APIC_IPI_DEST_ALL:
  29.720 +		icrlo |= APIC_DEST_ALLISELF;
  29.721 +		break;
  29.722 +	case APIC_IPI_DEST_OTHERS:
  29.723 +		icrlo |= APIC_DEST_ALLESELF;
  29.724 +		break;
  29.725 +	default:
  29.726 +		KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
  29.727 +		    ("%s: invalid destination 0x%x", __func__, dest));
  29.728 +		destfield = dest;
  29.729 +	}
  29.730 +
  29.731 +	/* Wait for an earlier IPI to finish. */
  29.732 +	if (!lapic_ipi_wait(BEFORE_SPIN))
  29.733 +		panic("APIC: Previous IPI is stuck");
  29.734 +
  29.735 +	lapic_ipi_raw(icrlo, destfield);
  29.736 +
  29.737 +#ifdef DETECT_DEADLOCK
  29.738 +	/* Wait for IPI to be delivered. */
  29.739 +	if (!lapic_ipi_wait(AFTER_SPIN)) {
  29.740 +#ifdef needsattention
  29.741 +		/*
  29.742 +		 * XXX FIXME:
  29.743 +		 *
  29.744 +		 * The above function waits for the message to actually be
  29.745 +		 * delivered.  It breaks out after an arbitrary timeout
  29.746 +		 * since the message should eventually be delivered (at
  29.747 +		 * least in theory) and that if it wasn't we would catch
  29.748 +		 * the failure with the check above when the next IPI is
  29.749 +		 * sent.
  29.750 +		 *
  29.751 +		 * We could skiip this wait entirely, EXCEPT it probably
  29.752 +		 * protects us from other routines that assume that the
  29.753 +		 * message was delivered and acted upon when this function
  29.754 +		 * returns.
  29.755 +		 */
  29.756 +		printf("APIC: IPI might be stuck\n");
  29.757 +#else /* !needsattention */
  29.758 +		/* Wait until mesage is sent without a timeout. */
  29.759 +		while (lapic->icr_lo & APIC_DELSTAT_PEND)
  29.760 +			ia32_pause();
  29.761 +#endif /* needsattention */
  29.762 +	}
  29.763 +#endif /* DETECT_DEADLOCK */
  29.764 +}
  29.765 +#endif /* SMP */
    30.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    30.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/locore.s	Mon Mar 21 07:58:08 2005 +0000
    30.3 @@ -0,0 +1,949 @@
    30.4 +/*-
    30.5 + * Copyright (c) 1990 The Regents of the University of California.
    30.6 + * All rights reserved.
    30.7 + *
    30.8 + * This code is derived from software contributed to Berkeley by
    30.9 + * William Jolitz.
   30.10 + *
   30.11 + * Redistribution and use in source and binary forms, with or without
   30.12 + * modification, are permitted provided that the following conditions
   30.13 + * are met:
   30.14 + * 1. Redistributions of source code must retain the above copyright
   30.15 + *    notice, this list of conditions and the following disclaimer.
   30.16 + * 2. Redistributions in binary form must reproduce the above copyright
   30.17 + *    notice, this list of conditions and the following disclaimer in the
   30.18 + *    documentation and/or other materials provided with the distribution.
   30.19 + * 4. Neither the name of the University nor the names of its contributors
   30.20 + *    may be used to endorse or promote products derived from this software
   30.21 + *    without specific prior written permission.
   30.22 + *
   30.23 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   30.24 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   30.25 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   30.26 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   30.27 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   30.28 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   30.29 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30.30 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30.31 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30.32 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30.33 + * SUCH DAMAGE.
   30.34 + *
   30.35 + *	from: @(#)locore.s	7.3 (Berkeley) 5/13/91
   30.36 + * $FreeBSD: src/sys/i386/i386/locore.s,v 1.181 2003/11/03 21:53:37 jhb Exp $
   30.37 + *
   30.38 + *		originally from: locore.s, by William F. Jolitz
   30.39 + *
   30.40 + *		Substantially rewritten by David Greenman, Rod Grimes,
   30.41 + *			Bruce Evans, Wolfgang Solfrank, Poul-Henning Kamp
   30.42 + *			and many others.
   30.43 + */
   30.44 +
   30.45 +#include "opt_bootp.h"
   30.46 +#include "opt_compat.h"
   30.47 +#include "opt_nfsroot.h"
   30.48 +#include "opt_pmap.h"
   30.49 +
   30.50 +#include <sys/syscall.h>
   30.51 +#include <sys/reboot.h>
   30.52 +
   30.53 +#include <machine/asmacros.h>
   30.54 +#include <machine/cputypes.h>
   30.55 +#include <machine/psl.h>
   30.56 +#include <machine/pmap.h>
   30.57 +#include <machine/specialreg.h>
   30.58 +
   30.59 +#include "assym.s"
   30.60 +
   30.61 +.section __xen_guest
   30.62 +	    .asciz "LOADER=generic,GUEST_VER=5.2.1,XEN_VER=2.0,BSD_SYMTAB"
   30.63 +	
   30.64 +	
   30.65 +/*
   30.66 + *	XXX
   30.67 + *
   30.68 + * Note: This version greatly munged to avoid various assembler errors
   30.69 + * that may be fixed in newer versions of gas. Perhaps newer versions
   30.70 + * will have more pleasant appearance.
   30.71 + */
   30.72 +
   30.73 +/*
   30.74 + * PTmap is recursive pagemap at top of virtual address space.
   30.75 + * Within PTmap, the page directory can be found (third indirection).
   30.76 + */
   30.77 +	.globl	PTmap,PTD,PTDpde
   30.78 +	.set	PTmap,(PTDPTDI << PDRSHIFT)
   30.79 +	.set	PTD,PTmap + (PTDPTDI * PAGE_SIZE)
   30.80 +	.set	PTDpde,PTD + (PTDPTDI * PDESIZE)
   30.81 +
   30.82 +#ifdef SMP
   30.83 +/*
   30.84 + * Define layout of per-cpu address space.
   30.85 + * This is "constructed" in locore.s on the BSP and in mp_machdep.c
   30.86 + * for each AP.  DO NOT REORDER THESE WITHOUT UPDATING THE REST!
   30.87 + */
   30.88 +	.globl	SMP_prvspace
   30.89 +	.set	SMP_prvspace,(MPPTDI << PDRSHIFT)
   30.90 +#endif /* SMP */
   30.91 +
   30.92 +/*
   30.93 + * Compiled KERNBASE location and the kernel load address
   30.94 + */
   30.95 +	.globl	kernbase
   30.96 +	.set	kernbase,KERNBASE
   30.97 +	.globl	kernload
   30.98 +	.set	kernload,KERNLOAD
   30.99 +
  30.100 +/*
  30.101 + * Globals
  30.102 + */
  30.103 +	.data
  30.104 +	ALIGN_DATA			/* just to be sure */
  30.105 +
  30.106 +	.space	0x2000			/* space for tmpstk - temporary stack */
  30.107 +tmpstk:
  30.108 +
  30.109 +	.globl	bootinfo
  30.110 +bootinfo:	.space	BOOTINFO_SIZE	/* bootinfo that we can handle */
  30.111 +
  30.112 +		.globl KERNend
  30.113 +KERNend:	.long	0		/* phys addr end of kernel (just after bss) */
  30.114 +physfree:	.long	0		/* phys addr of next free page */
  30.115 +
  30.116 +#ifdef SMP
  30.117 +		.globl	cpu0prvpage
  30.118 +cpu0pp:		.long	0		/* phys addr cpu0 private pg */
  30.119 +cpu0prvpage:	.long	0		/* relocated version */
  30.120 +
  30.121 +		.globl	SMPpt
  30.122 +SMPptpa:	.long	0		/* phys addr SMP page table */
  30.123 +SMPpt:		.long	0		/* relocated version */
  30.124 +#endif /* SMP */
  30.125 +
  30.126 +	.globl	IdlePTD
  30.127 +IdlePTD:	.long	0		/* phys addr of kernel PTD */
  30.128 +
  30.129 +
  30.130 +	.globl	KPTphys
  30.131 +KPTphys:	.long	0		/* phys addr of kernel page tables */
  30.132 +
  30.133 +	.globl	proc0uarea, proc0kstack
  30.134 +proc0uarea:	.long	0		/* address of proc 0 uarea space */
  30.135 +proc0kstack:	.long	0		/* address of proc 0 kstack space */
  30.136 +p0upa:		.long	0		/* phys addr of proc0's UAREA */
  30.137 +p0kpa:		.long	0		/* phys addr of proc0's STACK */
  30.138 +
  30.139 +#ifdef PC98
  30.140 +	.globl	pc98_system_parameter
  30.141 +pc98_system_parameter:
  30.142 +	.space	0x240
  30.143 +#endif
  30.144 +
  30.145 +/**********************************************************************
  30.146 + *
  30.147 + * Some handy macros
  30.148 + *
  30.149 + */
  30.150 +
  30.151 +#define R(foo) ((foo))
  30.152 +
  30.153 +#define ALLOCPAGES(foo) \
  30.154 +	movl	R(physfree), %esi ; \
  30.155 +	movl	$((foo)*PAGE_SIZE), %eax ; \
  30.156 +	addl	%esi, %eax ; \
  30.157 +	movl	%eax, R(physfree) ; \
  30.158 +	movl	%esi, %edi ; \
  30.159 +	movl	$((foo)*PAGE_SIZE),%ecx ; \
  30.160 +	xorl	%eax,%eax ; \
  30.161 +	cld ; \
  30.162 +	rep ; \
  30.163 +	stosb
  30.164 +
  30.165 +/*
  30.166 + * fillkpt
  30.167 + *	eax = page frame address
  30.168 + *	ebx = index into page table
  30.169 + *	ecx = how many pages to map
  30.170 + * 	base = base address of page dir/table
  30.171 + *	prot = protection bits
  30.172 + */
  30.173 +#define	fillkpt(base, prot)		  \
  30.174 +	shll	$PTESHIFT,%ebx		; \
  30.175 +	addl	base,%ebx		; \
  30.176 +	orl	$PG_V,%eax		; \
  30.177 +	orl	prot,%eax		; \
  30.178 +1:	movl	%eax,(%ebx)		; \
  30.179 +	addl	$PAGE_SIZE,%eax		; /* increment physical address */ \
  30.180 +	addl	$PTESIZE,%ebx		; /* next pte */ \
  30.181 +	loop	1b
  30.182 +
  30.183 +/*
  30.184 + * fillkptphys(prot)
  30.185 + *	eax = physical address
  30.186 + *	ecx = how many pages to map
  30.187 + *	prot = protection bits
  30.188 + */
  30.189 +#define	fillkptphys(prot)		  \
  30.190 +	movl	%eax, %ebx		; \
  30.191 +	shrl	$PAGE_SHIFT, %ebx	; \
  30.192 +	fillkpt(R(KPTphys), prot)
  30.193 +
  30.194 +	.text
  30.195 +/**********************************************************************
  30.196 + *
  30.197 + * This is where the bootblocks start us, set the ball rolling...
  30.198 + *
  30.199 + */
  30.200 +NON_GPROF_ENTRY(btext)
  30.201 +	pushl   %esi
  30.202 +	call	initvalues	
  30.203 +	popl	%esi
  30.204 +	call	identify_cpu
  30.205 +	movl	proc0kstack,%eax
  30.206 +	leal	(KSTACK_PAGES*PAGE_SIZE-PCB_SIZE)(%eax),%esp	
  30.207 +        xorl    %ebp,%ebp               /* mark end of frames */
  30.208 +	movl    IdlePTD,%esi
  30.209 +        movl    %esi,(KSTACK_PAGES*PAGE_SIZE-PCB_SIZE+PCB_CR3)(%eax)
  30.210 +	call	init386
  30.211 +	call	mi_startup
  30.212 +	int	$3
  30.213 +
  30.214 +	
  30.215 +#ifdef PC98
  30.216 +	/* save SYSTEM PARAMETER for resume (NS/T or other) */
  30.217 +	movl	$0xa1400,%esi
  30.218 +	movl	$R(pc98_system_parameter),%edi
  30.219 +	movl	$0x0240,%ecx
  30.220 +	cld
  30.221 +	rep
  30.222 +	movsb
  30.223 +#else	/* IBM-PC */
  30.224 +/* Tell the bios to warmboot next time */
  30.225 +	movw	$0x1234,0x472
  30.226 +#endif	/* PC98 */
  30.227 +
  30.228 +/* Set up a real frame in case the double return in newboot is executed. */
  30.229 +	pushl	%ebp
  30.230 +	movl	%esp, %ebp
  30.231 +
  30.232 +/* Don't trust what the BIOS gives for eflags. */
  30.233 +	pushl	$PSL_KERNEL
  30.234 +	popfl
  30.235 +
  30.236 +/*
  30.237 + * Don't trust what the BIOS gives for %fs and %gs.  Trust the bootstrap
  30.238 + * to set %cs, %ds, %es and %ss.
  30.239 + */
  30.240 +	mov	%ds, %ax
  30.241 +	mov	%ax, %fs
  30.242 +	mov	%ax, %gs
  30.243 +
  30.244 +/*
  30.245 + * Clear the bss.  Not all boot programs do it, and it is our job anyway.
  30.246 + *
  30.247 + * XXX we don't check that there is memory for our bss and page tables
  30.248 + * before using it.
  30.249 + *
  30.250 + * Note: we must be careful to not overwrite an active gdt or idt.  They
  30.251 + * inactive from now until we switch to new ones, since we don't load any
  30.252 + * more segment registers or permit interrupts until after the switch.
  30.253 + */
  30.254 +	movl	$R(end),%ecx
  30.255 +	movl	$R(edata),%edi
  30.256 +	subl	%edi,%ecx
  30.257 +	xorl	%eax,%eax
  30.258 +	cld
  30.259 +	rep
  30.260 +	stosb
  30.261 +
  30.262 +	call	recover_bootinfo
  30.263 +
  30.264 +/* Get onto a stack that we can trust. */
  30.265 +/*
  30.266 + * XXX this step is delayed in case recover_bootinfo needs to return via
  30.267 + * the old stack, but it need not be, since recover_bootinfo actually
  30.268 + * returns via the old frame.
  30.269 + */
  30.270 +	movl	$R(tmpstk),%esp
  30.271 +
  30.272 +#ifdef PC98
  30.273 +	/* pc98_machine_type & M_EPSON_PC98 */
  30.274 +	testb	$0x02,R(pc98_system_parameter)+220
  30.275 +	jz	3f
  30.276 +	/* epson_machine_id <= 0x0b */
  30.277 +	cmpb	$0x0b,R(pc98_system_parameter)+224
  30.278 +	ja	3f
  30.279 +
  30.280 +	/* count up memory */
  30.281 +	movl	$0x100000,%eax		/* next, talley remaining memory */
  30.282 +	movl	$0xFFF-0x100,%ecx
  30.283 +1:	movl	0(%eax),%ebx		/* save location to check */
  30.284 +	movl	$0xa55a5aa5,0(%eax)	/* write test pattern */
  30.285 +	cmpl	$0xa55a5aa5,0(%eax)	/* does not check yet for rollover */
  30.286 +	jne	2f
  30.287 +	movl	%ebx,0(%eax)		/* restore memory */
  30.288 +	addl	$PAGE_SIZE,%eax
  30.289 +	loop	1b
  30.290 +2:	subl	$0x100000,%eax
  30.291 +	shrl	$17,%eax
  30.292 +	movb	%al,R(pc98_system_parameter)+1
  30.293 +3:
  30.294 +
  30.295 +	movw	R(pc98_system_parameter+0x86),%ax
  30.296 +	movw	%ax,R(cpu_id)
  30.297 +#endif
  30.298 +
  30.299 +	call	identify_cpu
  30.300 +	call	create_pagetables
  30.301 +
  30.302 +/*
  30.303 + * If the CPU has support for VME, turn it on.
  30.304 + */ 
  30.305 +	testl	$CPUID_VME, R(cpu_feature)
  30.306 +	jz	1f
  30.307 +	movl	%cr4, %eax
  30.308 +	orl	$CR4_VME, %eax
  30.309 +	movl	%eax, %cr4
  30.310 +1:
  30.311 +
  30.312 +/* Now enable paging */
  30.313 +	movl	R(IdlePTD), %eax
  30.314 +	movl	%eax,%cr3		/* load ptd addr into mmu */
  30.315 +	movl	%cr0,%eax		/* get control word */
  30.316 +	orl	$CR0_PE|CR0_PG,%eax	/* enable paging */
  30.317 +	movl	%eax,%cr0		/* and let's page NOW! */
  30.318 +
  30.319 +	pushl	$begin			/* jump to high virtualized address */
  30.320 +	ret
  30.321 +
  30.322 +/* now running relocated at KERNBASE where the system is linked to run */
  30.323 +begin:
  30.324 +	/* set up bootstrap stack */
  30.325 +	movl	proc0kstack,%eax	/* location of in-kernel stack */
  30.326 +			/* bootstrap stack end location */
  30.327 +	leal	(KSTACK_PAGES*PAGE_SIZE-PCB_SIZE)(%eax),%esp
  30.328 +
  30.329 +	xorl	%ebp,%ebp		/* mark end of frames */
  30.330 +
  30.331 +#ifdef PAE
  30.332 +	movl	IdlePDPT,%esi
  30.333 +#else
  30.334 +	movl	IdlePTD,%esi
  30.335 +#endif
  30.336 +	movl	%esi,(KSTACK_PAGES*PAGE_SIZE-PCB_SIZE+PCB_CR3)(%eax)
  30.337 +
  30.338 +	pushl	physfree		/* value of first for init386(first) */
  30.339 +	call	init386			/* wire 386 chip for unix operation */
  30.340 +
  30.341 +	/*
  30.342 +	 * Clean up the stack in a way that db_numargs() understands, so
  30.343 +	 * that backtraces in ddb don't underrun the stack.  Traps for
  30.344 +	 * inaccessible memory are more fatal than usual this early.
  30.345 +	 */
  30.346 +	addl	$4,%esp
  30.347 +
  30.348 +	call	mi_startup		/* autoconfiguration, mountroot etc */
  30.349 +	/* NOTREACHED */
  30.350 +	addl	$0,%esp			/* for db_numargs() again */
  30.351 +
  30.352 +/*
  30.353 + * Signal trampoline, copied to top of user stack
  30.354 + */
  30.355 +NON_GPROF_ENTRY(sigcode)
  30.356 +	calll	*SIGF_HANDLER(%esp)
  30.357 +	leal	SIGF_UC(%esp),%eax	/* get ucontext */
  30.358 +	pushl	%eax
  30.359 +	testl	$PSL_VM,UC_EFLAGS(%eax)
  30.360 +	jne	1f
  30.361 +	movl	UC_GS(%eax),%gs		/* restore %gs */
  30.362 +1:
  30.363 +	movl	$SYS_sigreturn,%eax
  30.364 +	pushl	%eax			/* junk to fake return addr. */
  30.365 +	int	$0x80			/* enter kernel with args */
  30.366 +					/* on stack */
  30.367 +1:
  30.368 +	jmp	1b
  30.369 +
  30.370 +#ifdef COMPAT_FREEBSD4
  30.371 +	ALIGN_TEXT
  30.372 +freebsd4_sigcode:
  30.373 +	calll	*SIGF_HANDLER(%esp)
  30.374 +	leal	SIGF_UC4(%esp),%eax	/* get ucontext */
  30.375 +	pushl	%eax
  30.376 +	testl	$PSL_VM,UC4_EFLAGS(%eax)
  30.377 +	jne	1f
  30.378 +	movl	UC4_GS(%eax),%gs	/* restore %gs */
  30.379 +1:
  30.380 +	movl	$344,%eax		/* 4.x SYS_sigreturn */
  30.381 +	pushl	%eax			/* junk to fake return addr. */
  30.382 +	int	$0x80			/* enter kernel with args */
  30.383 +					/* on stack */
  30.384 +1:
  30.385 +	jmp	1b
  30.386 +#endif
  30.387 +
  30.388 +#ifdef COMPAT_43
  30.389 +	ALIGN_TEXT
  30.390 +osigcode:
  30.391 +	call	*SIGF_HANDLER(%esp)	/* call signal handler */
  30.392 +	lea	SIGF_SC(%esp),%eax	/* get sigcontext */
  30.393 +	pushl	%eax
  30.394 +	testl	$PSL_VM,SC_PS(%eax)
  30.395 +	jne	9f
  30.396 +	movl	SC_GS(%eax),%gs		/* restore %gs */
  30.397 +9:
  30.398 +	movl	$103,%eax		/* 3.x SYS_sigreturn */
  30.399 +	pushl	%eax			/* junk to fake return addr. */
  30.400 +	int	$0x80			/* enter kernel with args */
  30.401 +0:	jmp	0b
  30.402 +#endif /* COMPAT_43 */
  30.403 +
  30.404 +	ALIGN_TEXT
  30.405 +esigcode:
  30.406 +
  30.407 +	.data
  30.408 +	.globl	szsigcode
  30.409 +szsigcode:
  30.410 +	.long	esigcode-sigcode
  30.411 +#ifdef COMPAT_FREEBSD4
  30.412 +	.globl	szfreebsd4_sigcode
  30.413 +szfreebsd4_sigcode:
  30.414 +	.long	esigcode-freebsd4_sigcode
  30.415 +#endif
  30.416 +#ifdef COMPAT_43
  30.417 +	.globl	szosigcode
  30.418 +szosigcode:
  30.419 +	.long	esigcode-osigcode
  30.420 +#endif
  30.421 +	.text
  30.422 +
  30.423 +/**********************************************************************
  30.424 + *
  30.425 + * Recover the bootinfo passed to us from the boot program
  30.426 + *
  30.427 + */
  30.428 +recover_bootinfo:
  30.429 +	/*
  30.430 +	 * This code is called in different ways depending on what loaded
  30.431 +	 * and started the kernel.  This is used to detect how we get the
  30.432 +	 * arguments from the other code and what we do with them.
  30.433 +	 *
  30.434 +	 * Old disk boot blocks:
  30.435 +	 *	(*btext)(howto, bootdev, cyloffset, esym);
  30.436 +	 *	[return address == 0, and can NOT be returned to]
  30.437 +	 *	[cyloffset was not supported by the FreeBSD boot code
  30.438 +	 *	 and always passed in as 0]
  30.439 +	 *	[esym is also known as total in the boot code, and
  30.440 +	 *	 was never properly supported by the FreeBSD boot code]
  30.441 +	 *
  30.442 +	 * Old diskless netboot code:
  30.443 +	 *	(*btext)(0,0,0,0,&nfsdiskless,0,0,0);
  30.444 +	 *	[return address != 0, and can NOT be returned to]
  30.445 +	 *	If we are being booted by this code it will NOT work,
  30.446 +	 *	so we are just going to halt if we find this case.
  30.447 +	 *
  30.448 +	 * New uniform boot code:
  30.449 +	 *	(*btext)(howto, bootdev, 0, 0, 0, &bootinfo)
  30.450 +	 *	[return address != 0, and can be returned to]
  30.451 +	 *
  30.452 +	 * There may seem to be a lot of wasted arguments in here, but
  30.453 +	 * that is so the newer boot code can still load very old kernels
  30.454 +	 * and old boot code can load new kernels.
  30.455 +	 */
  30.456 +
  30.457 +	/*
  30.458 +	 * The old style disk boot blocks fake a frame on the stack and
  30.459 +	 * did an lret to get here.  The frame on the stack has a return
  30.460 +	 * address of 0.
  30.461 +	 */
  30.462 +	cmpl	$0,4(%ebp)
  30.463 +	je	olddiskboot
  30.464 +
  30.465 +	/*
  30.466 +	 * We have some form of return address, so this is either the
  30.467 +	 * old diskless netboot code, or the new uniform code.  That can
  30.468 +	 * be detected by looking at the 5th argument, if it is 0
  30.469 +	 * we are being booted by the new uniform boot code.
  30.470 +	 */
  30.471 +	cmpl	$0,24(%ebp)
  30.472 +	je	newboot
  30.473 +
  30.474 +	/*
  30.475 +	 * Seems we have been loaded by the old diskless boot code, we
  30.476 +	 * don't stand a chance of running as the diskless structure
  30.477 +	 * changed considerably between the two, so just halt.
  30.478 +	 */
  30.479 +	 hlt
  30.480 +
  30.481 +	/*
  30.482 +	 * We have been loaded by the new uniform boot code.
  30.483 +	 * Let's check the bootinfo version, and if we do not understand
  30.484 +	 * it we return to the loader with a status of 1 to indicate this error
  30.485 +	 */
  30.486 +newboot:
  30.487 +	movl	28(%ebp),%ebx		/* &bootinfo.version */
  30.488 +	movl	BI_VERSION(%ebx),%eax
  30.489 +	cmpl	$1,%eax			/* We only understand version 1 */
  30.490 +	je	1f
  30.491 +	movl	$1,%eax			/* Return status */
  30.492 +	leave
  30.493 +	/*
  30.494 +	 * XXX this returns to our caller's caller (as is required) since
  30.495 +	 * we didn't set up a frame and our caller did.
  30.496 +	 */
  30.497 +	ret
  30.498 +
  30.499 +1:
  30.500 +	/*
  30.501 +	 * If we have a kernelname copy it in
  30.502 +	 */
  30.503 +	movl	BI_KERNELNAME(%ebx),%esi
  30.504 +	cmpl	$0,%esi
  30.505 +	je	2f			/* No kernelname */
  30.506 +	movl	$MAXPATHLEN,%ecx	/* Brute force!!! */
  30.507 +	movl	$R(kernelname),%edi
  30.508 +	cmpb	$'/',(%esi)		/* Make sure it starts with a slash */
  30.509 +	je	1f
  30.510 +	movb	$'/',(%edi)
  30.511 +	incl	%edi
  30.512 +	decl	%ecx
  30.513 +1:
  30.514 +	cld
  30.515 +	rep
  30.516 +	movsb
  30.517 +
  30.518 +2:
  30.519 +	/*
  30.520 +	 * Determine the size of the boot loader's copy of the bootinfo
  30.521 +	 * struct.  This is impossible to do properly because old versions
  30.522 +	 * of the struct don't contain a size field and there are 2 old
  30.523 +	 * versions with the same version number.
  30.524 +	 */
  30.525 +	movl	$BI_ENDCOMMON,%ecx	/* prepare for sizeless version */
  30.526 +	testl	$RB_BOOTINFO,8(%ebp)	/* bi_size (and bootinfo) valid? */
  30.527 +	je	got_bi_size		/* no, sizeless version */
  30.528 +	movl	BI_SIZE(%ebx),%ecx
  30.529 +got_bi_size:
  30.530 +
  30.531 +	/*
  30.532 +	 * Copy the common part of the bootinfo struct
  30.533 +	 */
  30.534 +	movl	%ebx,%esi
  30.535 +	movl	$R(bootinfo),%edi
  30.536 +	cmpl	$BOOTINFO_SIZE,%ecx
  30.537 +	jbe	got_common_bi_size
  30.538 +	movl	$BOOTINFO_SIZE,%ecx
  30.539 +got_common_bi_size:
  30.540 +	cld
  30.541 +	rep
  30.542 +	movsb
  30.543 +
  30.544 +#ifdef NFS_ROOT
  30.545 +#ifndef BOOTP_NFSV3
  30.546 +	/*
  30.547 +	 * If we have a nfs_diskless structure copy it in
  30.548 +	 */
  30.549 +	movl	BI_NFS_DISKLESS(%ebx),%esi
  30.550 +	cmpl	$0,%esi
  30.551 +	je	olddiskboot
  30.552 +	movl	$R(nfs_diskless),%edi
  30.553 +	movl	$NFSDISKLESS_SIZE,%ecx
  30.554 +	cld
  30.555 +	rep
  30.556 +	movsb
  30.557 +	movl	$R(nfs_diskless_valid),%edi
  30.558 +	movl	$1,(%edi)
  30.559 +#endif
  30.560 +#endif
  30.561 +
  30.562 +	/*
  30.563 +	 * The old style disk boot.
  30.564 +	 *	(*btext)(howto, bootdev, cyloffset, esym);
  30.565 +	 * Note that the newer boot code just falls into here to pick
  30.566 +	 * up howto and bootdev, cyloffset and esym are no longer used
  30.567 +	 */
  30.568 +olddiskboot:
  30.569 +	movl	8(%ebp),%eax
  30.570 +	movl	%eax,R(boothowto)
  30.571 +	movl	12(%ebp),%eax
  30.572 +	movl	%eax,R(bootdev)
  30.573 +
  30.574 +	ret
  30.575 +
  30.576 +
  30.577 +/**********************************************************************
  30.578 +	 *
  30.579 +	 * Identify the CPU and initialize anything special about it
  30.580 +	 *
  30.581 +	 */
  30.582 +identify_cpu:
  30.583 +
  30.584 +	        /* Try to toggle alignment check flag ;  does not exist on 386. */
  30.585 +	        pushfl
  30.586 +	        popl    %eax
  30.587 +	        movl    %eax,%ecx
  30.588 +	        orl     $PSL_AC,%eax
  30.589 +	        pushl   %eax
  30.590 +	        popfl
  30.591 +	        pushfl
  30.592 +	        popl    %eax
  30.593 +	        xorl    %ecx,%eax
  30.594 +	        andl    $PSL_AC,%eax
  30.595 +	        pushl   %ecx
  30.596 +	        popfl
  30.597 +
  30.598 +	        testl   %eax,%eax
  30.599 +	        jnz     try486
  30.600 +
  30.601 +	        /* NexGen CPU does not have aligment check flag. */
  30.602 +	        pushfl
  30.603 +	        movl    $0x5555, %eax
  30.604 +	        xorl    %edx, %edx
  30.605 +	        movl    $2, %ecx
  30.606 +	        clc
  30.607 +	        divl    %ecx
  30.608 +	        jz      trynexgen
  30.609 +	        popfl
  30.610 +	        movl    $CPU_386,R(cpu)
  30.611 +	        jmp     3f
  30.612 +
  30.613 +trynexgen:
  30.614 +	        popfl
  30.615 +	        movl    $CPU_NX586,R(cpu)
  30.616 +	        movl    $0x4778654e,R(cpu_vendor)       # store vendor string
  30.617 +	        movl    $0x72446e65,R(cpu_vendor+4)
  30.618 +	        movl    $0x6e657669,R(cpu_vendor+8)
  30.619 +	        movl    $0,R(cpu_vendor+12)
  30.620 +	        jmp     3f
  30.621 +
  30.622 +try486:	 /* Try to toggle identification flag ;  does not exist on early 486s. */
  30.623 +	        pushfl
  30.624 +	        popl    %eax
  30.625 +	        movl    %eax,%ecx
  30.626 +	        xorl    $PSL_ID,%eax
  30.627 +	        pushl   %eax
  30.628 +	        popfl
  30.629 +	        pushfl
  30.630 +	        popl    %eax
  30.631 +	        xorl    %ecx,%eax
  30.632 +	        andl    $PSL_ID,%eax
  30.633 +	        pushl   %ecx
  30.634 +	        popfl
  30.635 +
  30.636 +	        testl   %eax,%eax
  30.637 +	        jnz     trycpuid
  30.638 +	        movl    $CPU_486,R(cpu)
  30.639 +
  30.640 +	        /*
  30.641 +	         * Check Cyrix CPU
  30.642 +	         * Cyrix CPUs do not change the undefined flags following
  30.643 +	         * execution of the divide instruction which divides 5 by 2.
  30.644 +	         *
  30.645 +	         * Note:	 CPUID is enabled on M2, so it passes another way.
  30.646 +	         */
  30.647 +	        pushfl
  30.648 +	        movl    $0x5555, %eax
  30.649 +	        xorl    %edx, %edx
  30.650 +	        movl    $2, %ecx
  30.651 +	        clc
  30.652 +	        divl    %ecx
  30.653 +	        jnc     trycyrix
  30.654 +	        popfl
  30.655 +	        jmp     3f              /* You may use Intel CPU. */
  30.656 +
  30.657 +trycyrix:
  30.658 +	        popfl
  30.659 +	        /*
  30.660 +	         * IBM Bluelighting CPU also doesn't change the undefined flags.
  30.661 +	         * Because IBM doesn't disclose the information for Bluelighting
  30.662 +	         * CPU, we couldn't distinguish it from Cyrix's (including IBM
  30.663 +	         * brand of Cyrix CPUs).
  30.664 +	         */
  30.665 +	        movl    $0x69727943,R(cpu_vendor)       # store vendor string
  30.666 +	        movl    $0x736e4978,R(cpu_vendor+4)
  30.667 +	        movl    $0x64616574,R(cpu_vendor+8)
  30.668 +	        jmp     3f
  30.669 +
  30.670 +trycpuid:	       /* Use the `cpuid' instruction. */
  30.671 +	        xorl    %eax,%eax
  30.672 +	        cpuid                                   # cpuid 0
  30.673 +	        movl    %eax,R(cpu_high)                # highest capability
  30.674 +	        movl    %ebx,R(cpu_vendor)              # store vendor string
  30.675 +	        movl    %edx,R(cpu_vendor+4)
  30.676 +	        movl    %ecx,R(cpu_vendor+8)
  30.677 +	        movb    $0,R(cpu_vendor+12)
  30.678 +
  30.679 +	        movl    $1,%eax
  30.680 +	        cpuid                                   # cpuid 1
  30.681 +	        movl    %eax,R(cpu_id)                  # store cpu_id
  30.682 +	        movl    %ebx,R(cpu_procinfo)            # store cpu_procinfo
  30.683 +	        movl    %edx,R(cpu_feature)             # store cpu_feature
  30.684 +	        rorl    $8,%eax                         # extract family type
  30.685 +	        andl    $15,%eax
  30.686 +	        cmpl    $5,%eax
  30.687 +	        jae     1f
  30.688 +
  30.689 +	        /* less than Pentium ;  must be 486 */
  30.690 +	        movl    $CPU_486,R(cpu)
  30.691 +	        jmp     3f
  30.692 +1:
  30.693 +	        /* a Pentium? */
  30.694 +	        cmpl    $5,%eax
  30.695 +	        jne     2f
  30.696 +	        movl    $CPU_586,R(cpu)
  30.697 +	        jmp     3f
  30.698 +2:
  30.699 +	        /* Greater than Pentium...call it a Pentium Pro */
  30.700 +	        movl    $CPU_686,R(cpu)
  30.701 +3:
  30.702 +	        ret
  30.703 +	
  30.704 +/**********************************************************************
  30.705 + *
  30.706 + * Create the first page directory and its page tables.
  30.707 + *
  30.708 + */
  30.709 +
  30.710 +create_pagetables:
  30.711 +
  30.712 +/* Find end of kernel image (rounded up to a page boundary). */
  30.713 +	movl	$R(_end),%esi
  30.714 +
  30.715 +/* Include symbols, if any. */
  30.716 +	movl	R(bootinfo+BI_ESYMTAB),%edi
  30.717 +	testl	%edi,%edi
  30.718 +	je	over_symalloc
  30.719 +	movl	%edi,%esi
  30.720 +	movl	$KERNBASE,%edi
  30.721 +	addl	%edi,R(bootinfo+BI_SYMTAB)
  30.722 +	addl	%edi,R(bootinfo+BI_ESYMTAB)
  30.723 +over_symalloc:
  30.724 +
  30.725 +/* If we are told where the end of the kernel space is, believe it. */
  30.726 +	movl	R(bootinfo+BI_KERNEND),%edi
  30.727 +	testl	%edi,%edi
  30.728 +	je	no_kernend
  30.729 +	movl	%edi,%esi
  30.730 +no_kernend:
  30.731 +
  30.732 +	addl	$PDRMASK,%esi		/* Play conservative for now, and */
  30.733 +	andl	$~PDRMASK,%esi		/*   ... wrap to next 4M. */
  30.734 +	movl	%esi,R(KERNend)		/* save end of kernel */
  30.735 +	movl	%esi,R(physfree)	/* next free page is at end of kernel */
  30.736 +
  30.737 +/* Allocate Kernel Page Tables */
  30.738 +	ALLOCPAGES(NKPT)
  30.739 +	movl	%esi,R(KPTphys)
  30.740 +
  30.741 +/* Allocate Page Table Directory */
  30.742 +#ifdef PAE
  30.743 +	/* XXX only need 32 bytes (easier for now) */
  30.744 +	ALLOCPAGES(1)
  30.745 +	movl	%esi,R(IdlePDPT)
  30.746 +#endif
  30.747 +	ALLOCPAGES(NPGPTD)
  30.748 +	movl	%esi,R(IdlePTD)
  30.749 +
  30.750 +/* Allocate UPAGES */
  30.751 +	ALLOCPAGES(UAREA_PAGES)
  30.752 +	movl	%esi,R(p0upa)
  30.753 +	addl	$KERNBASE, %esi
  30.754 +	movl	%esi, R(proc0uarea)
  30.755 +
  30.756 +	ALLOCPAGES(KSTACK_PAGES)
  30.757 +	movl	%esi,R(p0kpa)
  30.758 +	addl	$KERNBASE, %esi
  30.759 +	movl	%esi, R(proc0kstack)
  30.760 +#if 0
  30.761 +	ALLOCPAGES(1)			/* vm86/bios stack */
  30.762 +	movl	%esi,R(vm86phystk)
  30.763 +
  30.764 +	ALLOCPAGES(3)			/* pgtable + ext + IOPAGES */
  30.765 +	movl	%esi,R(vm86pa)
  30.766 +	addl	$KERNBASE, %esi
  30.767 +	movl	%esi, R(vm86paddr)
  30.768 +#endif
  30.769 +#ifdef SMP
  30.770 +/* Allocate cpu0's private data page */
  30.771 +	ALLOCPAGES(1)
  30.772 +	movl	%esi,R(cpu0pp)
  30.773 +	addl	$KERNBASE, %esi
  30.774 +	movl	%esi, R(cpu0prvpage)	/* relocated to KVM space */
  30.775 +
  30.776 +/* Allocate SMP page table page */
  30.777 +	ALLOCPAGES(1)
  30.778 +	movl	%esi,R(SMPptpa)
  30.779 +	addl	$KERNBASE, %esi
  30.780 +	movl	%esi, R(SMPpt)		/* relocated to KVM space */
  30.781 +#endif	/* SMP */
  30.782 +
  30.783 +/* Map page zero read-write so bios32 calls can use it */
  30.784 +	xorl	%eax, %eax
  30.785 +	movl	$PG_RW,%edx
  30.786 +	movl	$1,%ecx
  30.787 +	fillkptphys(%edx)
  30.788 +
  30.789 +/* Map read-only from page 1 to the beginning of the kernel text section */
  30.790 +	movl	$PAGE_SIZE, %eax
  30.791 +	xorl	%edx,%edx
  30.792 +	movl	$R(btext),%ecx
  30.793 +	addl	$PAGE_MASK,%ecx
  30.794 +	subl	%eax,%ecx
  30.795 +	shrl	$PAGE_SHIFT,%ecx
  30.796 +	fillkptphys(%edx)
  30.797 +
  30.798 +/*
  30.799 + * Enable PSE and PGE.
  30.800 + */
  30.801 +#ifndef DISABLE_PSE
  30.802 +	testl	$CPUID_PSE, R(cpu_feature)
  30.803 +	jz	1f
  30.804 +	movl	$PG_PS, R(pseflag)
  30.805 +	movl	%cr4, %eax
  30.806 +	orl	$CR4_PSE, %eax
  30.807 +	movl	%eax, %cr4
  30.808 +1:
  30.809 +#endif
  30.810 +#ifndef DISABLE_PG_G
  30.811 +	testl	$CPUID_PGE, R(cpu_feature)
  30.812 +	jz	2f
  30.813 +	movl	$PG_G, R(pgeflag)
  30.814 +	movl	%cr4, %eax
  30.815 +	orl	$CR4_PGE, %eax
  30.816 +	movl	%eax, %cr4
  30.817 +2:
  30.818 +#endif
  30.819 +
  30.820 +/*
  30.821 + * Write page tables for the kernel starting at btext and
  30.822 + * until the end.  Make sure to map read+write.  We do this even
  30.823 + * if we've enabled PSE above, we'll just switch the corresponding kernel
  30.824 + * PDEs before we turn on paging.
  30.825 + *
  30.826 + * XXX: We waste some pages here in the PSE case!  DON'T BLINDLY REMOVE
  30.827 + * THIS!  SMP needs the page table to be there to map the kernel P==V.
  30.828 + */
  30.829 +	movl	$R(btext),%eax
  30.830 +	addl	$PAGE_MASK, %eax
  30.831 +	andl	$~PAGE_MASK, %eax
  30.832 +	movl	$PG_RW,%edx
  30.833 +	movl	R(KERNend),%ecx
  30.834 +	subl	%eax,%ecx
  30.835 +	shrl	$PAGE_SHIFT,%ecx
  30.836 +	fillkptphys(%edx)
  30.837 +
  30.838 +/* Map page directory. */
  30.839 +	movl	R(IdlePTD), %eax
  30.840 +	movl	$NPGPTD, %ecx
  30.841 +	fillkptphys($PG_RW)
  30.842 +
  30.843 +/* Map proc0's UPAGES in the physical way ... */
  30.844 +	movl	R(p0upa), %eax
  30.845 +	movl	$(UAREA_PAGES), %ecx
  30.846 +	fillkptphys($PG_RW)
  30.847 +
  30.848 +/* Map proc0's KSTACK in the physical way ... */
  30.849 +	movl	R(p0kpa), %eax
  30.850 +	movl	$(KSTACK_PAGES), %ecx
  30.851 +	fillkptphys($PG_RW)
  30.852 +
  30.853 +/* Map ISA hole */
  30.854 +	movl	$ISA_HOLE_START, %eax
  30.855 +	movl	$ISA_HOLE_LENGTH>>PAGE_SHIFT, %ecx
  30.856 +	fillkptphys($PG_RW)
  30.857 +#if 0
  30.858 +/* Map space for the vm86 region */
  30.859 +	movl	R(vm86phystk), %eax
  30.860 +	movl	$4, %ecx
  30.861 +	fillkptphys($PG_RW)
  30.862 +
  30.863 +/* Map page 0 into the vm86 page table */
  30.864 +	movl	$0, %eax
  30.865 +	movl	$0, %ebx
  30.866 +	movl	$1, %ecx
  30.867 +	fillkpt(R(vm86pa), $PG_RW|PG_U)
  30.868 +
  30.869 +/* ...likewise for the ISA hole */
  30.870 +	movl	$ISA_HOLE_START, %eax
  30.871 +	movl	$ISA_HOLE_START>>PAGE_SHIFT, %ebx
  30.872 +	movl	$ISA_HOLE_LENGTH>>PAGE_SHIFT, %ecx
  30.873 +	fillkpt(R(vm86pa), $PG_RW|PG_U)
  30.874 +#endif
  30.875 +#ifdef SMP
  30.876 +/* Map cpu0's private page into global kmem (4K @ cpu0prvpage) */
  30.877 +	movl	R(cpu0pp), %eax
  30.878 +	movl	$1, %ecx
  30.879 +	fillkptphys($PG_RW)
  30.880 +
  30.881 +/* Map SMP page table page into global kmem FWIW */
  30.882 +	movl	R(SMPptpa), %eax
  30.883 +	movl	$1, %ecx
  30.884 +	fillkptphys($PG_RW)
  30.885 +
  30.886 +/* Map the private page into the SMP page table */
  30.887 +	movl	R(cpu0pp), %eax
  30.888 +	movl	$0, %ebx		/* pte offset = 0 */
  30.889 +	movl	$1, %ecx		/* one private page coming right up */
  30.890 +	fillkpt(R(SMPptpa), $PG_RW)
  30.891 +
  30.892 +/* ... and put the page table table in the pde. */
  30.893 +	movl	R(SMPptpa), %eax
  30.894 +	movl	$MPPTDI, %ebx
  30.895 +	movl	$1, %ecx
  30.896 +	fillkpt(R(IdlePTD), $PG_RW)
  30.897 +
  30.898 +/* Fakeup VA for the local apic to allow early traps. */
  30.899 +	ALLOCPAGES(1)
  30.900 +	movl	%esi, %eax
  30.901 +	movl	$(NPTEPG-1), %ebx	/* pte offset = NTEPG-1 */
  30.902 +	movl	$1, %ecx		/* one private pt coming right up */
  30.903 +	fillkpt(R(SMPptpa), $PG_RW)
  30.904 +#endif	/* SMP */
  30.905 +
  30.906 +/* install a pde for temporary double map of bottom of VA */
  30.907 +	movl	R(KPTphys), %eax
  30.908 +	xorl	%ebx, %ebx
  30.909 +	movl	$NKPT, %ecx
  30.910 +	fillkpt(R(IdlePTD), $PG_RW)
  30.911 +
  30.912 +/*
  30.913 + * For the non-PSE case, install PDEs for PTs covering the kernel.
  30.914 + * For the PSE case, do the same, but clobber the ones corresponding
  30.915 + * to the kernel (from btext to KERNend) with 4M ('PS') PDEs immediately
  30.916 + * after.
  30.917 + */
  30.918 +	movl	R(KPTphys), %eax
  30.919 +	movl	$KPTDI, %ebx
  30.920 +	movl	$NKPT, %ecx
  30.921 +	fillkpt(R(IdlePTD), $PG_RW)
  30.922 +	cmpl	$0,R(pseflag)
  30.923 +	je	done_pde
  30.924 +
  30.925 +	movl	R(KERNend), %ecx
  30.926 +	movl	$KERNLOAD, %eax
  30.927 +	subl	%eax, %ecx
  30.928 +	shrl	$PDRSHIFT, %ecx
  30.929 +	movl	$(KPTDI+(KERNLOAD/(1 << PDRSHIFT))), %ebx
  30.930 +	shll	$PDESHIFT, %ebx
  30.931 +	addl	R(IdlePTD), %ebx
  30.932 +	orl	$(PG_V|PG_RW|PG_PS), %eax
  30.933 +1:	movl	%eax, (%ebx)
  30.934 +	addl	$(1 << PDRSHIFT), %eax
  30.935 +	addl	$PDESIZE, %ebx
  30.936 +	loop	1b
  30.937 +
  30.938 +done_pde:
  30.939 +/* install a pde recursively mapping page directory as a page table */
  30.940 +	movl	R(IdlePTD), %eax
  30.941 +	movl	$PTDPTDI, %ebx
  30.942 +	movl	$NPGPTD,%ecx
  30.943 +	fillkpt(R(IdlePTD), $PG_RW)
  30.944 +
  30.945 +#ifdef PAE
  30.946 +	movl	R(IdlePTD), %eax
  30.947 +	xorl	%ebx, %ebx
  30.948 +	movl	$NPGPTD, %ecx
  30.949 +	fillkpt(R(IdlePDPT), $0x0)
  30.950 +#endif
  30.951 +
  30.952 +	ret
    31.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    31.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/machdep.c	Mon Mar 21 07:58:08 2005 +0000
    31.3 @@ -0,0 +1,2396 @@
    31.4 +/*-
    31.5 + * Copyright (c) 1992 Terrence R. Lambert.
    31.6 + * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    31.7 + * All rights reserved.
    31.8 + *
    31.9 + * This code is derived from software contributed to Berkeley by
   31.10 + * William Jolitz.
   31.11 + *
   31.12 + * Redistribution and use in source and binary forms, with or without
   31.13 + * modification, are permitted provided that the following conditions
   31.14 + * are met:
   31.15 + * 1. Redistributions of source code must retain the above copyright
   31.16 + *    notice, this list of conditions and the following disclaimer.
   31.17 + * 2. Redistributions in binary form must reproduce the above copyright
   31.18 + *    notice, this list of conditions and the following disclaimer in the
   31.19 + *    documentation and/or other materials provided with the distribution.
   31.20 + * 3. All advertising materials mentioning features or use of this software
   31.21 + *    must display the following acknowledgement:
   31.22 + *	This product includes software developed by the University of
   31.23 + *	California, Berkeley and its contributors.
   31.24 + * 4. Neither the name of the University nor the names of its contributors
   31.25 + *    may be used to endorse or promote products derived from this software
   31.26 + *    without specific prior written permission.
   31.27 + *
   31.28 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   31.29 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   31.30 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   31.31 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   31.32 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31.33 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   31.34 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31.35 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31.36 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31.37 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31.38 + * SUCH DAMAGE.
   31.39 + *
   31.40 + *	from: @(#)machdep.c	7.4 (Berkeley) 6/3/91
   31.41 + */
   31.42 +
   31.43 +#include <sys/cdefs.h>
   31.44 +__FBSDID("$FreeBSD: src/sys/i386/i386/machdep.c,v 1.584 2003/12/03 21:12:09 jhb Exp $");
   31.45 +
   31.46 +#include "opt_apic.h"
   31.47 +#include "opt_atalk.h"
   31.48 +#include "opt_compat.h"
   31.49 +#include "opt_cpu.h"
   31.50 +#include "opt_ddb.h"
   31.51 +#include "opt_inet.h"
   31.52 +#include "opt_ipx.h"
   31.53 +#include "opt_isa.h"
   31.54 +#include "opt_kstack_pages.h"
   31.55 +#include "opt_maxmem.h"
   31.56 +#include "opt_msgbuf.h"
   31.57 +#include "opt_npx.h"
   31.58 +#include "opt_perfmon.h"
   31.59 +#include "opt_xen.h"
   31.60 +
   31.61 +#include <sys/param.h>
   31.62 +#include <sys/systm.h>
   31.63 +#include <sys/sysproto.h>
   31.64 +#include <sys/signalvar.h>
   31.65 +#include <sys/imgact.h>
   31.66 +#include <sys/kdb.h>
   31.67 +#include <sys/kernel.h>
   31.68 +#include <sys/ktr.h>
   31.69 +#include <sys/linker.h>
   31.70 +#include <sys/lock.h>
   31.71 +#include <sys/malloc.h>
   31.72 +#include <sys/memrange.h>
   31.73 +#include <sys/mutex.h>
   31.74 +#include <sys/pcpu.h>
   31.75 +#include <sys/proc.h>
   31.76 +#include <sys/bio.h>
   31.77 +#include <sys/buf.h>
   31.78 +#include <sys/reboot.h>
   31.79 +#includ