ia64/xen-unstable

changeset 18495:75c4a603d9cd

x86: Fix 32-bit build after AMD microcode update patch.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Sep 15 15:44:38 2008 +0100 (2008-09-15)
parents 59aba2cbbb58
children 087008dfb005
files xen/arch/x86/microcode_amd.c
line diff
     1.1 --- a/xen/arch/x86/microcode_amd.c	Mon Sep 15 11:36:20 2008 +0100
     1.2 +++ b/xen/arch/x86/microcode_amd.c	Mon Sep 15 15:44:38 2008 +0100
     1.3 @@ -170,11 +170,10 @@ out:
     1.4  static int apply_microcode_amd(int cpu)
     1.5  {
     1.6  	unsigned long flags;
     1.7 -	unsigned int eax, edx;
     1.8 -	unsigned int rev;
     1.9 +	uint32_t eax, edx, rev;
    1.10  	int cpu_num = raw_smp_processor_id();
    1.11  	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
    1.12 -	unsigned long addr;
    1.13 +	uint64_t addr;
    1.14  
    1.15  	/* We should bind the task to the CPU */
    1.16  	BUG_ON(cpu_num != cpu);
    1.17 @@ -185,8 +184,8 @@ static int apply_microcode_amd(int cpu)
    1.18  	spin_lock_irqsave(&microcode_update_lock, flags);
    1.19  
    1.20  	addr = (unsigned long)&uci->mc.mc_amd->hdr.data_code;
    1.21 -	edx = (unsigned int)((unsigned long)(addr >> 32));
    1.22 -	eax = (unsigned int)((unsigned long)(addr & 0xffffffff));
    1.23 +	edx = (uint32_t)(addr >> 32);
    1.24 +	eax = (uint32_t)addr;
    1.25  
    1.26  	asm volatile("movl %0, %%ecx; wrmsr" :
    1.27  		     : "i" (MSR_AMD_PATCHLOADER), "a" (eax), "d" (edx) : "ecx");