ia64/xen-unstable

changeset 4189:74080d40b2e9

bitkeeper revision 1.1236.36.1 (423910292v91UiEbc7EnKxjnrVFSYg)

Merge djm@kirby.fc.hp.com://home/djm/src/xen/xeno-unstable-ia64.bk
into sportsman.spdomain:/home/djm/xeno-unstable-ia64.bk
author djm@sportsman.spdomain
date Thu Mar 17 05:05:45 2005 +0000 (2005-03-17)
parents 7a5ec83c604e 863434ec7eab
children 58f33dec606f
files xen/arch/ia64/process.c xen/arch/ia64/regionreg.c
line diff
     1.1 --- a/xen/arch/ia64/process.c	Tue Mar 15 23:44:44 2005 +0000
     1.2 +++ b/xen/arch/ia64/process.c	Thu Mar 17 05:05:45 2005 +0000
     1.3 @@ -147,7 +147,7 @@ void reflect_interruption(unsigned long 
     1.4  		}
     1.5  		vector &= ~0xf;
     1.6  		if (vector != IA64_DATA_TLB_VECTOR &&
     1.7 -		    vector != IA64_DATA_TLB_VECTOR) {
     1.8 +		    vector != IA64_ALT_DATA_TLB_VECTOR) {
     1.9  panic_domain(regs,"psr.ic off, delivering fault=%lx,iip=%p,ifa=%p,isr=%p,PSCB.iip=%p\n",
    1.10  	vector,regs->cr_iip,ifa,isr,PSCB(ed,iip));
    1.11  			
     2.1 --- a/xen/arch/ia64/regionreg.c	Tue Mar 15 23:44:44 2005 +0000
     2.2 +++ b/xen/arch/ia64/regionreg.c	Thu Mar 17 05:05:45 2005 +0000
     2.3 @@ -379,37 +379,28 @@ unsigned long load_region_regs(struct ex
     2.4  		rrv.rid = ed->domain->metaphysical_rid;
     2.5  		rrv.ps = PAGE_SHIFT;
     2.6  		rrv.ve = 1;
     2.7 -		rr0 = rr1 = rr2 = rr3 = rr4 = rr5 = rrv.rrval;
     2.8 -		rrv.ve = 0;
     2.9 -		rr6 = rrv.rrval;
    2.10 +		rr0 = rrv.rrval;
    2.11  		set_rr_no_srlz(0x0000000000000000L, rr0);
    2.12 -		set_rr_no_srlz(0x2000000000000000L, rr1);
    2.13 -		set_rr_no_srlz(0x4000000000000000L, rr2);
    2.14 -		set_rr_no_srlz(0x6000000000000000L, rr3);
    2.15 -		set_rr_no_srlz(0x8000000000000000L, rr4);
    2.16 -		set_rr_no_srlz(0xa000000000000000L, rr5);
    2.17 -		set_rr_no_srlz(0xc000000000000000L, rr6);
    2.18 -		// skip rr7 when in metaphysical mode
    2.19 +		ia64_srlz_d();
    2.20  	}
    2.21  	else {
    2.22  		rr0 =  ed->vcpu_info->arch.rrs[0];
    2.23 -		rr1 =  ed->vcpu_info->arch.rrs[1];
    2.24 -		rr2 =  ed->vcpu_info->arch.rrs[2];
    2.25 -		rr3 =  ed->vcpu_info->arch.rrs[3];
    2.26 -		rr4 =  ed->vcpu_info->arch.rrs[4];
    2.27 -		rr5 =  ed->vcpu_info->arch.rrs[5];
    2.28 -		rr6 =  ed->vcpu_info->arch.rrs[6];
    2.29 -		rr7 =  ed->vcpu_info->arch.rrs[7];
    2.30  		if (!set_one_rr(0x0000000000000000L, rr0)) bad |= 1;
    2.31 -		if (!set_one_rr(0x2000000000000000L, rr1)) bad |= 2;
    2.32 -		if (!set_one_rr(0x4000000000000000L, rr2)) bad |= 4;
    2.33 -		if (!set_one_rr(0x6000000000000000L, rr3)) bad |= 8;
    2.34 -		if (!set_one_rr(0x8000000000000000L, rr4)) bad |= 0x10;
    2.35 -		if (!set_one_rr(0xa000000000000000L, rr5)) bad |= 0x20;
    2.36 -		if (!set_one_rr(0xc000000000000000L, rr6)) bad |= 0x40;
    2.37 -		if (!set_one_rr(0xe000000000000000L, rr7)) bad |= 0x80;
    2.38  	}
    2.39 -	ia64_srlz_d();
    2.40 +	rr1 =  ed->vcpu_info->arch.rrs[1];
    2.41 +	rr2 =  ed->vcpu_info->arch.rrs[2];
    2.42 +	rr3 =  ed->vcpu_info->arch.rrs[3];
    2.43 +	rr4 =  ed->vcpu_info->arch.rrs[4];
    2.44 +	rr5 =  ed->vcpu_info->arch.rrs[5];
    2.45 +	rr6 =  ed->vcpu_info->arch.rrs[6];
    2.46 +	rr7 =  ed->vcpu_info->arch.rrs[7];
    2.47 +	if (!set_one_rr(0x2000000000000000L, rr1)) bad |= 2;
    2.48 +	if (!set_one_rr(0x4000000000000000L, rr2)) bad |= 4;
    2.49 +	if (!set_one_rr(0x6000000000000000L, rr3)) bad |= 8;
    2.50 +	if (!set_one_rr(0x8000000000000000L, rr4)) bad |= 0x10;
    2.51 +	if (!set_one_rr(0xa000000000000000L, rr5)) bad |= 0x20;
    2.52 +	if (!set_one_rr(0xc000000000000000L, rr6)) bad |= 0x40;
    2.53 +	if (!set_one_rr(0xe000000000000000L, rr7)) bad |= 0x80;
    2.54  	if (bad) {
    2.55  		panic_domain(0,"load_region_regs: can't set! bad=%lx\n",bad);
    2.56  	}