ia64/xen-unstable

changeset 9861:70b7d520bda4

[IA64] Fix RSE issue in VTI-domain

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Mon May 08 12:49:53 2006 -0600 (2006-05-08)
parents 3ab5ab4d6d75
children cf66d644b4d6
files xen/arch/ia64/vmx/vmx_entry.S xen/arch/ia64/vmx/vmx_interrupt.c xen/arch/ia64/vmx/vmx_ivt.S
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_entry.S	Mon May 08 12:47:54 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_entry.S	Mon May 08 12:49:53 2006 -0600
     1.3 @@ -315,7 +315,9 @@ vmx_dorfirfi_back:
     1.4      adds r18=IA64_VPD_BASE_OFFSET,r21
     1.5      ;;
     1.6      ld8 r18=[r18]   //vpd
     1.7 +    adds r17=IA64_VCPU_ISR_OFFSET,r21
     1.8      ;;
     1.9 +    ld8 r17=[r17]
    1.10      adds r19=VPD(VPSR),r18
    1.11      ;;
    1.12      ld8 r19=[r19]        //vpsr
    1.13 @@ -337,6 +339,7 @@ GLOBAL_ENTRY(ia64_vmm_entry)
    1.14  /*
    1.15   *  must be at bank 0
    1.16   *  parameter:
    1.17 + *  r17:cr.isr
    1.18   *  r18:vpd
    1.19   *  r19:vpsr
    1.20   *  r20:__vsa_base
    1.21 @@ -348,8 +351,14 @@ GLOBAL_ENTRY(ia64_vmm_entry)
    1.22      tbit.nz p1,p2 = r19,IA64_PSR_IC_BIT        // p1=vpsr.ic
    1.23      ;;
    1.24      (p1) add r29=PAL_VPS_RESUME_NORMAL,r20
    1.25 +    (p1) br.sptk.many ia64_vmm_entry_out
    1.26 +    ;;
    1.27 +    tbit.nz p1,p2 = r17,IA64_ISR_IR_BIT		//p1=cr.isr.ir
    1.28 +    ;;
    1.29 +    (p1) add r29=PAL_VPS_RESUME_NORMAL,r20
    1.30      (p2) add r29=PAL_VPS_RESUME_HANDLER,r20
    1.31      ;;
    1.32 +ia64_vmm_entry_out:    
    1.33      mov pr=r23,-2
    1.34      mov b0=r29
    1.35      ;;
     2.1 --- a/xen/arch/ia64/vmx/vmx_interrupt.c	Mon May 08 12:47:54 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_interrupt.c	Mon May 08 12:49:53 2006 -0600
     2.3 @@ -91,8 +91,12 @@ inject_guest_interruption(VCPU *vcpu, u6
     2.4  {
     2.5      u64 viva;
     2.6      REGS *regs;
     2.7 +    ISR pt_isr;
     2.8      regs=vcpu_regs(vcpu);
     2.9 -
    2.10 +    // clear cr.isr.ri 
    2.11 +    pt_isr.val = VMX(vcpu,cr_isr);
    2.12 +    pt_isr.ir = 0;
    2.13 +    VMX(vcpu,cr_isr) = pt_isr.val;
    2.14      collect_interruption(vcpu);
    2.15  
    2.16      vmx_vcpu_get_iva(vcpu,&viva);
     3.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Mon May 08 12:47:54 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Mon May 08 12:49:53 2006 -0600
     3.3 @@ -172,6 +172,7 @@ vmx_itlb_loop:
     3.4      ;;
     3.5      srlz.i
     3.6      ;;
     3.7 +    mov r17=cr.isr
     3.8      mov r23=r31
     3.9      mov r22=b0
    3.10      adds r16=IA64_VPD_BASE_OFFSET,r21
    3.11 @@ -237,6 +238,7 @@ vmx_dtlb_loop:
    3.12      ;;
    3.13      srlz.d;
    3.14      ;;
    3.15 +    mov r17=cr.isr
    3.16      mov r23=r31
    3.17      mov r22=b0
    3.18      adds r16=IA64_VPD_BASE_OFFSET,r21