ia64/xen-unstable

changeset 12928:6ff313c841db

[XEN][POWERPC] go ultra conservative on CI IO routines
The following patch contains:
- Code that uses SLBIE for ERAT flush rather than TLBIE. Erratum #16
says to use SLBIE bit a TLBIE should do it and is "less
distruptive".
- Machine Check issues
- Track CI mode while cache is still enabled
- Use r7 to indicate that the IO is still pending while CI is on
- The right sync for the right reasons
Signed-off-by: Jimi Xenidis <jimix@watson.ibm.com>
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
author Jimi Xenidis <jimix@watson.ibm.com>
date Mon Oct 02 11:04:00 2006 -0400 (2006-10-02)
parents 2bf4257944f4
children 24fd59787982
files xen/arch/powerpc/powerpc64/io.S
line diff
     1.1 --- a/xen/arch/powerpc/powerpc64/io.S	Sun Oct 01 20:40:44 2006 -0400
     1.2 +++ b/xen/arch/powerpc/powerpc64/io.S	Mon Oct 02 11:04:00 2006 -0400
     1.3 @@ -23,6 +23,11 @@
     1.4  #include <asm/processor.h>
     1.5  #include <asm/percpu.h>
     1.6  
     1.7 +/* There is no reason why I can't use a tlbie, which should be less
     1.8 + * "destructive" but useing SLBIE proves to be more stable result.
     1.9 + */
    1.10 +#define INVALIDATE_ERAT_WITH_SLBIE
    1.11 +
    1.12  /* Xen runs in real mode (i.e. untranslated, MMU disabled). This avoids TLB
    1.13   * flushes and also makes it easy to access all domains' memory. However, on
    1.14   * PowerPC real mode accesses are cacheable, which is good for general
    1.15 @@ -34,12 +39,14 @@
    1.16   * make the access, then re-enable it...
    1.17   */
    1.18  
    1.19 +#ifdef INVALIDATE_ERAT_WITH_SLBIE
    1.20  /* Not all useful assemblers understand 'tlbiel'.
    1.21   * 'addr' is a GPR containing the address being accessed.
    1.22   */
    1.23  .macro tlbiel addr
    1.24  	.long 0x7c000224 | (\addr << 11)
    1.25  .endm
    1.26 +#endif
    1.27  
    1.28  .macro DISABLE_DCACHE addr
    1.29  	mfmsr r8
    1.30 @@ -48,29 +55,53 @@
    1.31  	ori r6, r6, MSR_EE
    1.32  	andc r5, r8, r6
    1.33  	mtmsr r5
    1.34 +	sync
    1.35  
    1.36 -	/* set HID4.RM_CI */
    1.37 +#ifdef INVALIDATE_ERAT_WITH_SLBIE 
    1.38 +	/* create an slbie entry for the io setting a high order bit
    1.39 +	 * to avoid any important SLBs */
    1.40 +	extldi r0, \addr, 36, 0 
    1.41 +#endif
    1.42 +	/* setup HID4.RM_CI */
    1.43  	mfspr r9, SPRN_HID4
    1.44  	li r6, 0x100
    1.45  	sldi r6, r6, 32
    1.46 -	or r5, r9, r6
    1.47 -	tlbiel \addr /* invalidate the ERAT entry */
    1.48 -	sync
    1.49 -	mtspr SPRN_HID4, r5
    1.50 +	or r10, r9, r6
    1.51 +
    1.52 +	/* Mark the processor as "in CI mode" */
    1.53 +	li r7,0
    1.54 +	mfspr r5, SPRN_PIR
    1.55 +	li r6, MCK_CPU_STAT_CI
    1.56 +	/* store that we are in a CI routine */
    1.57 +	stb r6, MCK_CPU_STAT_BASE(r5)
    1.58 +	/* r7 = MCK_CPU_STAT_CI IO in progress */
    1.59 +	mr r7, r5
    1.60 +	lwsync
    1.61 +
    1.62 +	/* switch modes */
    1.63 +	mtspr SPRN_HID4, r10
    1.64 +	/* invalidate the ERAT entry */
    1.65 +#ifdef INVALIDATE_ERAT_WITH_SLBIE
    1.66 +	slbie r0
    1.67 +#else
    1.68 +	tlbiel \addr
    1.69 +#endif
    1.70  	isync
    1.71  
    1.72 -	/* Mark the processor as "in CI mode" */
    1.73 -	mfspr r5, SPRN_PIR
    1.74 -	li r6, MCK_CPU_STAT_CI
    1.75 -	stb r6, MCK_CPU_STAT_BASE(r5)
    1.76 -	sync
    1.77  .endm
    1.78  
    1.79  .macro ENABLE_DCACHE addr
    1.80 -	/* re-zero HID4.RM_CI */
    1.81 +	/* r7 = 0, IO is complete */
    1.82 +	li r7, 0
    1.83 +	lwsync
    1.84 +	/* restore HID4.RM_CI */
    1.85 +	mtspr SPRN_HID4, r9
    1.86 +	/* invalidate the ERAT entry */
    1.87 +#ifdef INVALIDATE_ERAT_WITH_SLBIE
    1.88 +	slbie r0
    1.89 +#else
    1.90  	tlbiel \addr /* invalidate the ERAT entry */
    1.91 -	sync
    1.92 -	mtspr SPRN_HID4, r9
    1.93 +#endif
    1.94  	isync
    1.95  
    1.96  	/* Mark the processor as "out of CI mode" */
    1.97 @@ -83,9 +114,13 @@
    1.98  	mtmsr r8
    1.99  .endm
   1.100  
   1.101 -/* The following assembly cannot use r8 or r9 since they hold original
   1.102 - * values of msr and hid4 repectively
   1.103 +/* The following assembly cannot use some registers since they hold original
   1.104 + * values of we need to keep
   1.105   */
   1.106 +#undef r0
   1.107 +#define r0 do_not_use_r0
   1.108 +#undef r7
   1.109 +#define r7 do_not_use_r7
   1.110  #undef r8
   1.111  #define r8 do_not_use_r8
   1.112  #undef r9