1.1 --- a/xen/arch/ia64/xen/flushd.S	Mon Aug 14 13:42:00 2006 -0600
     1.2 +++ b/xen/arch/ia64/xen/flushd.S	Mon Aug 14 13:43:31 2006 -0600
     1.3 @@ -16,8 +16,9 @@
     1.4  	 *
     1.5  	 *	Flush cache.
     1.6  	 *
     1.7 -	 *	Must deal with range from start to end-1 but nothing else (need to
     1.8 -	 *	be careful not to touch addresses that may be unmapped).
     1.9 +	 *	Must deal with range from start to end-1 but nothing else 
    1.10 +	 *	(need to be careful not to touch addresses that may be 
    1.11 +	 *	unmapped).
    1.12  	 *
    1.13  	 *	Note: "in0" and "in1" are preserved for debugging purposes.
    1.14  	 */
    1.15 @@ -37,7 +38,8 @@ GLOBAL_ENTRY(flush_dcache_range)
    1.16  	;;
    1.17  	sub	r8=r22,r23		// number of strides - 1
    1.18  	shl	r24=r23,r20		// r24: addresses for "fc" =
    1.19 -					//	"start" rounded down to stride boundary
    1.20 +					//	"start" rounded down to stride 
    1.21 +					//	boundary
    1.22  	.save	ar.lc,r3
    1.23  	mov	r3=ar.lc		// save ar.lc
    1.24  	;;
    1.25 @@ -49,7 +51,8 @@ GLOBAL_ENTRY(flush_dcache_range)
    1.26  	 * 32 byte aligned loop, even number of (actually 2) bundles
    1.27  	 */
    1.28  .Loop:	fc	r24			// issuable on M0 only
    1.29 -	add	r24=r21,r24		// we flush "stride size" bytes per iteration
    1.30 +	add	r24=r21,r24		// we flush "stride size" bytes per
    1.31 +					//   iteration
    1.32  	nop.i	0
    1.33  	br.cloop.sptk.few .Loop
    1.34  	;;