ia64/xen-unstable

changeset 3507:6b76ae4b9ea7

bitkeeper revision 1.1159.212.30 (41f5268cMEdHLMEMs4o0SWqVEHZvuw)

Minor cleanup. Removed some duplicate MSRs, fixed some MSR names,
added a few new MSRs and MSR bit fields.
Signed-off-by: michael.fetterman@cl.cam.ac.uk
author mafetter@fleming.research
date Mon Jan 24 16:47:08 2005 +0000 (2005-01-24)
parents 09041bbc0e2c
children ba0bfd97ed0f
files xen/arch/x86/nmi.c xen/include/asm-x86/cpufeature.h xen/include/asm-x86/fixmap.h xen/include/asm-x86/irq.h xen/include/asm-x86/msr.h
line diff
     1.1 --- a/xen/arch/x86/nmi.c	Mon Jan 24 16:46:25 2005 +0000
     1.2 +++ b/xen/arch/x86/nmi.c	Mon Jan 24 16:47:08 2005 +0000
     1.3 @@ -48,9 +48,6 @@ extern int logical_proc_id[];
     1.4  #define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
     1.5  #define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED
     1.6  
     1.7 -#define MSR_P4_MISC_ENABLE	0x1A0
     1.8 -#define MSR_P4_MISC_ENABLE_PERF_AVAIL	(1<<7)
     1.9 -#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL	(1<<12)
    1.10  #define MSR_P4_PERFCTR0		0x300
    1.11  #define MSR_P4_CCCR0		0x360
    1.12  #define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
    1.13 @@ -186,15 +183,15 @@ static int __pminit setup_p4_watchdog(vo
    1.14  {
    1.15      unsigned int misc_enable, dummy;
    1.16  
    1.17 -    rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
    1.18 -    if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
    1.19 +    rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
    1.20 +    if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
    1.21          return 0;
    1.22  
    1.23      nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
    1.24  
    1.25      if ( logical_proc_id[smp_processor_id()] == 0 )
    1.26      {
    1.27 -        if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
    1.28 +        if (!(misc_enable & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
    1.29              clear_msr_range(0x3F1, 2);
    1.30          /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
    1.31             docs doesn't fully define it, so leave it alone for now. */
     2.1 --- a/xen/include/asm-x86/cpufeature.h	Mon Jan 24 16:46:25 2005 +0000
     2.2 +++ b/xen/include/asm-x86/cpufeature.h	Mon Jan 24 16:47:08 2005 +0000
     2.3 @@ -8,7 +8,7 @@
     2.4  #define __ASM_X86_CPUFEATURE_H
     2.5  
     2.6  /* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
     2.7 -#define CPU_FEATURE_P(CAP, FEATURE) test_bit(CAP, X86_FEATURE_##FEATURE ##_BIT)
     2.8 +#define CPU_FEATURE_P(CAP, FEATURE) test_bit(CAP, X86_FEATURE_##FEATURE)
     2.9  
    2.10  #define NCAPINTS	6	/* Currently we have 6 32-bit words worth of info */
    2.11  
     3.1 --- a/xen/include/asm-x86/fixmap.h	Mon Jan 24 16:46:25 2005 +0000
     3.2 +++ b/xen/include/asm-x86/fixmap.h	Mon Jan 24 16:47:08 2005 +0000
     3.3 @@ -26,7 +26,7 @@
     3.4   */
     3.5  enum fixed_addresses {
     3.6  #ifdef CONFIG_X86_LOCAL_APIC
     3.7 -    FIX_APIC_BASE,	/* local (CPU) APIC) -- required for SMP or not */
     3.8 +    FIX_APIC_BASE,	/* local (CPU) APIC -- required for SMP or not */
     3.9  #endif
    3.10  #ifdef CONFIG_X86_IO_APIC
    3.11      FIX_IO_APIC_BASE_0,
     4.1 --- a/xen/include/asm-x86/irq.h	Mon Jan 24 16:46:25 2005 +0000
     4.2 +++ b/xen/include/asm-x86/irq.h	Mon Jan 24 16:47:08 2005 +0000
     4.3 @@ -134,11 +134,6 @@ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\
     4.4  	"push"__OS" $"#nr"<<16\n\t" \
     4.5  	"jmp common_interrupt");
     4.6  
     4.7 -extern unsigned long prof_cpu_mask;
     4.8 -extern unsigned int *prof_buffer;
     4.9 -extern unsigned long prof_len;
    4.10 -extern unsigned long prof_shift;
    4.11 -
    4.12  #include <xen/irq.h>
    4.13  
    4.14  static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
     5.1 --- a/xen/include/asm-x86/msr.h	Mon Jan 24 16:46:25 2005 +0000
     5.2 +++ b/xen/include/asm-x86/msr.h	Mon Jan 24 16:47:08 2005 +0000
     5.3 @@ -95,12 +95,6 @@
     5.4  #define MSR_IA32_EVNTSEL0      0x186
     5.5  #define MSR_IA32_EVNTSEL1      0x187
     5.6  
     5.7 -#define MSR_IA32_DEBUGCTLMSR       0x1d9
     5.8 -#define MSR_IA32_LASTBRANCHFROMIP  0x1db
     5.9 -#define MSR_IA32_LASTBRANCHTOIP        0x1dc
    5.10 -#define MSR_IA32_LASTINTFROMIP     0x1dd
    5.11 -#define MSR_IA32_LASTINTTOIP       0x1de
    5.12 -
    5.13  #define MSR_MTRRfix64K_00000	0x250
    5.14  #define MSR_MTRRfix16K_80000	0x258
    5.15  #define MSR_MTRRfix16K_A0000	0x259
    5.16 @@ -119,6 +113,8 @@
    5.17  #define MSR_IA32_MC0_ADDR      0x402
    5.18  #define MSR_IA32_MC0_MISC      0x403
    5.19  
    5.20 +#define MSR_IA32_DS_AREA	0x600
    5.21 +
    5.22  #define MSR_IA32_APICBASE		0x1b
    5.23  #define MSR_IA32_APICBASE_BSP		(1<<8)
    5.24  #define MSR_IA32_APICBASE_ENABLE	(1<<11)
    5.25 @@ -138,11 +134,22 @@
    5.26  #define MSR_IA32_THERM_STATUS		0x19c
    5.27  #define MSR_IA32_MISC_ENABLE		0x1a0
    5.28  
    5.29 +#define MSR_IA32_MISC_ENABLE_PERF_AVAIL   (1<<7)
    5.30 +#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL  (1<<11)
    5.31 +#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
    5.32 +
    5.33  #define MSR_IA32_DEBUGCTLMSR		0x1d9
    5.34 -#define MSR_IA32_LASTBRANCHFROMIP	0x1db
    5.35 -#define MSR_IA32_LASTBRANCHTOIP		0x1dc
    5.36 -#define MSR_IA32_LASTINTFROMIP		0x1dd
    5.37 -#define MSR_IA32_LASTINTTOIP		0x1de
    5.38 +#define MSR_IA32_DEBUGCTLMSR_LBR        (1<<0)
    5.39 +#define MSR_IA32_DEBUGCTLMSR_BTF        (1<<1)
    5.40 +#define MSR_IA32_DEBUGCTLMSR_TR		(1<<2)
    5.41 +#define MSR_IA32_DEBUGCTLMSR_BTS        (1<<3)
    5.42 +#define MSR_IA32_DEBUGCTLMSR_BTINT      (1<<4)
    5.43 +
    5.44 +#define MSR_IA32_LASTBRANCH_TOS         0x1da
    5.45 +#define MSR_IA32_LASTBRANCH_0		0x1db
    5.46 +#define MSR_IA32_LASTBRANCH_1		0x1dc
    5.47 +#define MSR_IA32_LASTBRANCH_2		0x1dd
    5.48 +#define MSR_IA32_LASTBRANCH_3		0x1de
    5.49  
    5.50  #define MSR_IA32_MC0_CTL		0x400
    5.51  #define MSR_IA32_MC0_STATUS		0x401
    5.52 @@ -154,6 +161,7 @@
    5.53  #define MSR_P6_EVNTSEL0			0x186
    5.54  #define MSR_P6_EVNTSEL1			0x187
    5.55  
    5.56 +
    5.57  /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
    5.58  #define MSR_K7_EVNTSEL0            0xC0010000
    5.59  #define MSR_K7_PERFCTR0            0xC0010004