ia64/xen-unstable

changeset 15345:65956e1d1aec

[IA64] RBS is now in vcpu_guest_context_regs.

As there is not anymore local variable of type vcpu_guest_context_regs in
the hypervisor the rbs field (16KB) can be put in the structure.
Code to read/write the field added.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Fri Jun 15 12:36:04 2007 -0600 (2007-06-15)
parents fd0103b55504
children fe42519fb10e
files xen/arch/ia64/xen/domain.c xen/include/public/arch-ia64.h xen/include/public/foreign/reference.size
line diff
     1.1 --- a/xen/arch/ia64/xen/domain.c	Fri Jun 15 11:34:34 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/domain.c	Fri Jun 15 12:36:04 2007 -0600
     1.3 @@ -361,6 +361,10 @@ void startup_cpu_idle_loop(void)
     1.4  # error "XMAPPEDREGS_SHIFT doesn't match sizeof(mapped_regs_t)."
     1.5  #endif
     1.6  
     1.7 +#if (IA64_RBS_OFFSET % 512) != IA64_GUEST_CONTEXT_RBS_OFFSET
     1.8 +# error "arch-ia64.h: IA64_GUEST_CONTEXT_RBS_OFFSET must be adjusted."
     1.9 +#endif
    1.10 +
    1.11  void hlt_timer_fn(void *data)
    1.12  {
    1.13  	struct vcpu *v = data;
    1.14 @@ -610,6 +614,7 @@ void arch_get_info_guest(struct vcpu *v,
    1.15  	struct vcpu_tr_regs *tr = &c.nat->regs.tr;
    1.16  	struct cpu_user_regs *uregs = vcpu_regs(v);
    1.17  	int is_hvm = VMX_DOMAIN(v);
    1.18 +	unsigned int rbs_size;
    1.19  
    1.20  	c.nat->regs.b[6] = uregs->b6;
    1.21  	c.nat->regs.b[7] = uregs->b7;
    1.22 @@ -638,7 +643,8 @@ void arch_get_info_guest(struct vcpu *v,
    1.23  
    1.24  	c.nat->regs.pr = uregs->pr;
    1.25  	c.nat->regs.b[0] = uregs->b0;
    1.26 -	c.nat->regs.ar.bsp = uregs->ar_bspstore + (uregs->loadrs >> 16);
    1.27 +	rbs_size = uregs->loadrs >> 16;
    1.28 +	c.nat->regs.ar.bsp = uregs->ar_bspstore + rbs_size;
    1.29  
    1.30  	c.nat->regs.r[1] = uregs->r1;
    1.31  	c.nat->regs.r[12] = uregs->r12;
    1.32 @@ -683,6 +689,9 @@ void arch_get_info_guest(struct vcpu *v,
    1.33  	/* FIXME: to be reordered.  */
    1.34  	c.nat->regs.nats = uregs->eml_unat;
    1.35  
    1.36 +	if (rbs_size < sizeof (c.nat->regs.rbs))
    1.37 +		memcpy (c.nat->regs.rbs, (char *)v + IA64_RBS_OFFSET, rbs_size);
    1.38 +
    1.39   	c.nat->privregs_pfn = get_gpfn_from_mfn
    1.40  		(virt_to_maddr(v->arch.privregs) >> PAGE_SHIFT);
    1.41  
    1.42 @@ -713,10 +722,12 @@ int arch_set_info_guest(struct vcpu *v, 
    1.43  {
    1.44  	struct cpu_user_regs *uregs = vcpu_regs(v);
    1.45  	struct domain *d = v->domain;
    1.46 +	int was_initialised = v->is_initialised;
    1.47 +	unsigned int rbs_size;
    1.48  	int rc;
    1.49  
    1.50  	/* Finish vcpu initialization.  */
    1.51 -	if (!v->is_initialised) {
    1.52 +	if (!was_initialised) {
    1.53  		if (d->arch.is_vti)
    1.54  			rc = vmx_final_setup_guest(v);
    1.55  		else
    1.56 @@ -761,7 +772,12 @@ int arch_set_info_guest(struct vcpu *v, 
    1.57  	
    1.58  	uregs->pr = c.nat->regs.pr;
    1.59  	uregs->b0 = c.nat->regs.b[0];
    1.60 -	uregs->loadrs = (c.nat->regs.ar.bsp - c.nat->regs.ar.bspstore) << 16;
    1.61 +	rbs_size = c.nat->regs.ar.bsp - c.nat->regs.ar.bspstore;
    1.62 +	/* Protection against crazy user code.  */
    1.63 +	if (!was_initialised)
    1.64 +		uregs->loadrs = (rbs_size) << 16;
    1.65 +	if (rbs_size == (uregs->loadrs >> 16))
    1.66 +		memcpy ((char *)v + IA64_RBS_OFFSET, c.nat->regs.rbs, rbs_size);
    1.67  
    1.68  	uregs->r1 = c.nat->regs.r[1];
    1.69  	uregs->r12 = c.nat->regs.r[12];
     2.1 --- a/xen/include/public/arch-ia64.h	Fri Jun 15 11:34:34 2007 -0600
     2.2 +++ b/xen/include/public/arch-ia64.h	Fri Jun 15 12:36:04 2007 -0600
     2.3 @@ -451,7 +451,8 @@ struct vcpu_guest_context_regs {
     2.4          unsigned long psr;
     2.5          unsigned long cfm;
     2.6          unsigned long pr;
     2.7 -        unsigned long nats; /* NaT bits for r1-r31.  */
     2.8 +        unsigned int nats; /* NaT bits for r1-r31.  */
     2.9 +        unsigned int bnats; /* Nat bits for banked registers.  */
    2.10          union vcpu_ar_regs ar;
    2.11          union vcpu_cr_regs cr;
    2.12          struct pt_fpreg f[128];
    2.13 @@ -469,18 +470,17 @@ struct vcpu_guest_context_regs {
    2.14  
    2.15          struct vcpu_tr_regs tr;
    2.16  
    2.17 -#if 0
    2.18 -	/*
    2.19 -	 * The vcpu_guest_context structure is allocated on the stack in
    2.20 -	 * a few places.  With this array for RBS storage, that structure
    2.21 -	 * is a bit over 21k.  It looks like maybe we're blowing the stack
    2.22 -	 * and causing rather random looking failures on a couple systems.
    2.23 -	 * Remove since we're not actually using it for now.
    2.24 -	 */
    2.25 -
    2.26 +        /*
    2.27 +         * The rbs is intended to be the image of the stacked registers still
    2.28 +         * in the cpu (not yet stored in memory).  It is laid out as if it
    2.29 +         * were written in memory at an 512 (64*8) * aligned address + offset.
    2.30 +         * The offset is IA64_RBS_OFFSET % 512.
    2.31 +         * rbs_nat contains NaT bits for the remaining rbs registers.
    2.32 +         */
    2.33          /* Note: loadrs is 2**14 bytes == 2**11 slots.  */
    2.34 +#define IA64_GUEST_CONTEXT_RBS_OFFSET 448
    2.35          unsigned long rbs[2048];
    2.36 -#endif
    2.37 +        unsigned long rbs_nat;
    2.38  };
    2.39  
    2.40  struct vcpu_guest_context {
     3.1 --- a/xen/include/public/foreign/reference.size	Fri Jun 15 11:34:34 2007 -0600
     3.2 +++ b/xen/include/public/foreign/reference.size	Fri Jun 15 12:36:04 2007 -0600
     3.3 @@ -8,8 +8,8 @@ cpu_user_regs             |      68     
     3.4  xen_ia64_boot_param       |       -       -      96
     3.5  ia64_tr_entry             |       -       -      32
     3.6  vcpu_tr_regs              |       -       -     512
     3.7 -vcpu_guest_context_regs   |       -       -    5488
     3.8 -vcpu_guest_context        |    2800    5168    5520
     3.9 +vcpu_guest_context_regs   |       -       -   21872
    3.10 +vcpu_guest_context        |    2800    5168   21904
    3.11  arch_vcpu_info            |      24      16       0
    3.12  vcpu_time_info            |      32      32      32
    3.13  vcpu_info                 |      64      64      48