ia64/xen-unstable

changeset 16262:63bfed7b662b

x86, hvm: Clean up code style in stdvga code and do not compile for
32-bit hypervisor (it doesn't work).
Signed-off-by: Keir Fraser <keir@xensource.com>
author Keir Fraser <keir@xensource.com>
date Mon Oct 29 09:17:38 2007 +0000 (2007-10-29)
parents 03b006b02995
children 23582bcda6e1
files xen/arch/x86/hvm/Makefile xen/arch/x86/hvm/stdvga.c xen/include/asm-x86/hvm/io.h
line diff
     1.1 --- a/xen/arch/x86/hvm/Makefile	Mon Oct 29 09:16:59 2007 +0000
     1.2 +++ b/xen/arch/x86/hvm/Makefile	Mon Oct 29 09:17:38 2007 +0000
     1.3 @@ -17,4 +17,5 @@ obj-y += vioapic.o
     1.4  obj-y += vlapic.o
     1.5  obj-y += vpic.o
     1.6  obj-y += save.o
     1.7 -obj-y += stdvga.o
     1.8 +
     1.9 +obj-$(x86_64) += stdvga.o
     2.1 --- a/xen/arch/x86/hvm/stdvga.c	Mon Oct 29 09:16:59 2007 +0000
     2.2 +++ b/xen/arch/x86/hvm/stdvga.c	Mon Oct 29 09:17:38 2007 +0000
     2.3 @@ -7,8 +7,6 @@
     2.4   *  License, version 2.1 and not any later version of the GPL, as published
     2.5   *  by the Free Software Foundation. 
     2.6   *
     2.7 - *
     2.8 - *
     2.9   *  This improves the performance of Standard VGA,
    2.10   *  the mode used during Windows boot and by the Linux
    2.11   *  splash screen.
    2.12 @@ -24,7 +22,7 @@
    2.13   *  PIO input ops are satisfied from cached state without
    2.14   *  bothering QEMU.
    2.15   *
    2.16 -    PIO output and mmio ops are passed through to QEMU, including
    2.17 + *  PIO output and mmio ops are passed through to QEMU, including
    2.18   *  mmio read ops.  This is necessary because mmio reads
    2.19   *  can have side effects.
    2.20   */
    2.21 @@ -34,15 +32,12 @@
    2.22  #include <xen/sched.h>
    2.23  #include <asm/hvm/support.h>
    2.24  
    2.25 -#define vram_b(_s, _a) (((uint8_t*) (_s)->vram_ptr[((_a)>>12)&0x3f])[(_a)&0xfff])
    2.26 -#define vram_w(_s, _a) (((uint16_t*)(_s)->vram_ptr[((_a)>>11)&0x3f])[(_a)&0x7ff])
    2.27 -#define vram_l(_s, _a) (((uint32_t*)(_s)->vram_ptr[((_a)>>10)&0x3f])[(_a)&0x3ff])
    2.28 -
    2.29 -#ifdef STDVGA_STATS
    2.30 -#define UPDATE_STATS(x) x
    2.31 -#else
    2.32 -#define UPDATE_STATS(x)
    2.33 -#endif
    2.34 +#define vram_b(_s, _a) \
    2.35 +    (((uint8_t*) (_s)->vram_ptr[((_a)>>12)&0x3f])[(_a)&0xfff])
    2.36 +#define vram_w(_s, _a) \
    2.37 +    (((uint16_t*)(_s)->vram_ptr[((_a)>>11)&0x3f])[(_a)&0x7ff])
    2.38 +#define vram_l(_s, _a) \
    2.39 +    (((uint32_t*)(_s)->vram_ptr[((_a)>>10)&0x3f])[(_a)&0x3ff])
    2.40  
    2.41  #define PAT(x) (x)
    2.42  static const uint32_t mask16[16] = {
    2.43 @@ -92,13 +87,15 @@ static uint64_t stdvga_inb(uint64_t addr
    2.44  {
    2.45      struct hvm_hw_stdvga *s = &current->domain->arch.hvm_domain.stdvga;
    2.46      uint8_t val = 0;
    2.47 -    switch (addr) {
    2.48 +
    2.49 +    switch ( addr )
    2.50 +    {
    2.51      case 0x3c4:                 /* sequencer address register */
    2.52          val = s->sr_index;
    2.53          break;
    2.54  
    2.55      case 0x3c5:                 /* sequencer data register */
    2.56 -        if (s->sr_index < sizeof(s->sr))
    2.57 +        if ( s->sr_index < sizeof(s->sr) )
    2.58              val = s->sr[s->sr_index];
    2.59          break;
    2.60  
    2.61 @@ -113,6 +110,7 @@ static uint64_t stdvga_inb(uint64_t addr
    2.62      default:
    2.63          gdprintk(XENLOG_WARNING, "unexpected io addr 0x%04x\n", (int)addr);
    2.64      }
    2.65 +
    2.66      return val;
    2.67  }
    2.68  
    2.69 @@ -120,7 +118,9 @@ static uint64_t stdvga_in(ioreq_t *p)
    2.70  {
    2.71      /* Satisfy reads from sequence and graphics registers using local values */
    2.72      uint64_t data = 0;
    2.73 -    switch (p->size) {
    2.74 +
    2.75 +    switch ( p->size )
    2.76 +    {
    2.77      case 1:
    2.78          data = stdvga_inb(p->addr);
    2.79          break;
    2.80 @@ -151,6 +151,7 @@ static uint64_t stdvga_in(ioreq_t *p)
    2.81      default:
    2.82          gdprintk(XENLOG_WARNING, "invalid io size:%d\n", (int)p->size);
    2.83      }
    2.84 +
    2.85      return data;
    2.86  }
    2.87  
    2.88 @@ -161,13 +162,15 @@ static void stdvga_outb(uint64_t addr, u
    2.89      struct hvm_hw_stdvga *s = &current->domain->arch.hvm_domain.stdvga;
    2.90      int prev_stdvga = s->stdvga;
    2.91  
    2.92 -    switch (addr) {
    2.93 +    switch ( addr )
    2.94 +    {
    2.95      case 0x3c4:                 /* sequencer address register */
    2.96          s->sr_index = val;
    2.97          break;
    2.98  
    2.99      case 0x3c5:                 /* sequencer data register */
   2.100 -        switch (s->sr_index) {
   2.101 +        switch ( s->sr_index )
   2.102 +        {
   2.103          case 0x00 ... 0x05:
   2.104          case 0x07:
   2.105              s->sr[s->sr_index] = val & sr_mask[s->sr_index];
   2.106 @@ -176,7 +179,7 @@ static void stdvga_outb(uint64_t addr, u
   2.107              s->sr[s->sr_index] = ((val & 0x17) == 0x12) ? 0x12 : 0x0f;
   2.108              break;
   2.109          default:
   2.110 -            if (s->sr_index < sizeof(s->sr))
   2.111 +            if ( s->sr_index < sizeof(s->sr) )
   2.112                  s->sr[s->sr_index] = val;
   2.113              break;
   2.114          }
   2.115 @@ -187,37 +190,43 @@ static void stdvga_outb(uint64_t addr, u
   2.116          break;
   2.117  
   2.118      case 0x3cf:                 /* graphics data register */
   2.119 -        if (s->gr_index < sizeof(gr_mask)) {
   2.120 +        if ( s->gr_index < sizeof(gr_mask) )
   2.121 +        {
   2.122              s->gr[s->gr_index] = val & gr_mask[s->gr_index];
   2.123          }
   2.124 -        else if (s->gr_index == 0xff && s->vram_ptr != NULL) {
   2.125 +        else if ( (s->gr_index == 0xff) && (s->vram_ptr != NULL) )
   2.126 +        {
   2.127              uint32_t addr;
   2.128 -            for (addr = 0xa0000; addr < 0xa4000; addr += 2)
   2.129 +            for ( addr = 0xa0000; addr < 0xa4000; addr += 2 )
   2.130                  vram_w(s, addr) = (val << 8) | s->gr[0xfe];
   2.131          }
   2.132          else
   2.133 +        {
   2.134              s->gr[s->gr_index] = val;
   2.135 +        }
   2.136          break;
   2.137      }
   2.138  
   2.139      /* When in standard vga mode, emulate here all writes to the vram buffer
   2.140       * so we can immediately satisfy reads without waiting for qemu. */
   2.141      s->stdvga =
   2.142 -        s->sr[0x07] == 0 &&          /* standard vga mode */
   2.143 -        s->gr[6] == 0x05;            /* misc graphics register w/ MemoryMapSelect=1  0xa0000-0xaffff (64K region) and AlphaDis=1 */
   2.144 +        (s->sr[0x07] == 0) &&  /* standard vga mode */
   2.145 +        (s->gr[6] == 0x05);    /* misc graphics register w/ MemoryMapSelect=1
   2.146 +                                * 0xa0000-0xaffff (64k region), AlphaDis=1 */
   2.147  
   2.148 -    if (!prev_stdvga && s->stdvga) {
   2.149 +    if ( !prev_stdvga && s->stdvga )
   2.150 +    {
   2.151          s->cache = 1;       /* (re)start caching video buffer */
   2.152          gdprintk(XENLOG_INFO, "entering stdvga and caching modes\n");
   2.153      }
   2.154 -    else
   2.155 -    if (prev_stdvga && !s->stdvga)
   2.156 -        gdprintk(XENLOG_INFO, "leaving  stdvga\n");
   2.157 +    else if ( prev_stdvga && !s->stdvga )
   2.158 +        gdprintk(XENLOG_INFO, "leaving stdvga\n");
   2.159  }
   2.160  
   2.161  static void stdvga_outv(uint64_t addr, uint64_t data, uint32_t size)
   2.162  {
   2.163 -    switch (size) {
   2.164 +    switch ( size )
   2.165 +    {
   2.166      case 1:
   2.167          stdvga_outb(addr, data);
   2.168          break;
   2.169 @@ -252,10 +261,12 @@ static void stdvga_outv(uint64_t addr, u
   2.170  
   2.171  static void stdvga_out(ioreq_t *p)
   2.172  {
   2.173 -    if (p->data_is_ptr) {
   2.174 +    if ( p->data_is_ptr )
   2.175 +    {
   2.176          int i, sign = p->df ? -1 : 1;
   2.177          uint64_t addr = p->addr, data = p->data, tmp;
   2.178 -        for (i = 0; i < p->count; i++) {
   2.179 +        for ( i = 0; i < p->count; i++ )
   2.180 +        {
   2.181              hvm_copy_from_guest_phys(&tmp, data, p->size);
   2.182              stdvga_outv(addr, tmp, p->size);
   2.183              data += sign * p->size;
   2.184 @@ -263,45 +274,46 @@ static void stdvga_out(ioreq_t *p)
   2.185          }
   2.186      }
   2.187      else
   2.188 +    {
   2.189          stdvga_outv(p->addr, p->data, p->size);
   2.190 +    }
   2.191  }
   2.192  
   2.193  int stdvga_intercept_pio(ioreq_t *p)
   2.194  {
   2.195      struct hvm_hw_stdvga *s = &current->domain->arch.hvm_domain.stdvga;
   2.196 -    int buf = 0;
   2.197 +    int buf = 0, rc;
   2.198  
   2.199 -    if (p->size > 8) {
   2.200 +    if ( p->size > 8 )
   2.201 +    {
   2.202          gdprintk(XENLOG_WARNING, "stdvga bad access size %d\n", (int)p->size);
   2.203          return 0;
   2.204      }
   2.205  
   2.206      spin_lock(&s->lock);
   2.207 -    if ( p->dir == IOREQ_READ ) {
   2.208 -        if (p->size != 1)
   2.209 +
   2.210 +    if ( p->dir == IOREQ_READ )
   2.211 +    {
   2.212 +        if ( p->size != 1 )
   2.213              gdprintk(XENLOG_WARNING, "unexpected io size:%d\n", (int)p->size);
   2.214 -        if (!(p->addr == 0x3c5 && s->sr_index >= sizeof(sr_mask)) &&
   2.215 -            !(p->addr == 0x3cf && s->gr_index >= sizeof(gr_mask)))
   2.216 +        if ( !((p->addr == 0x3c5) && (s->sr_index >= sizeof(sr_mask))) &&
   2.217 +             !((p->addr == 0x3cf) && (s->gr_index >= sizeof(gr_mask))) )
   2.218          {
   2.219              p->data = stdvga_in(p);
   2.220              buf = 1;
   2.221          }
   2.222      }
   2.223 -    else {
   2.224 +    else
   2.225 +    {
   2.226          stdvga_out(p);
   2.227          buf = 1;
   2.228      }
   2.229  
   2.230 -    if (buf && hvm_buffered_io_send(p)) {
   2.231 -        UPDATE_STATS(s->stats.nr_pio_buffered_wr++);
   2.232 -        spin_unlock(&s->lock);
   2.233 -        return 1;
   2.234 -    }
   2.235 -    else {
   2.236 -        UPDATE_STATS(s->stats.nr_pio_unbuffered_wr++);
   2.237 -        spin_unlock(&s->lock);
   2.238 -        return 0;
   2.239 -    }
   2.240 +    rc = (buf && hvm_buffered_io_send(p));
   2.241 +
   2.242 +    spin_unlock(&s->lock);
   2.243 +
   2.244 +    return rc;
   2.245  }
   2.246  
   2.247  #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
   2.248 @@ -313,25 +325,33 @@ static uint8_t stdvga_mem_readb(uint64_t
   2.249      uint32_t ret;
   2.250  
   2.251      addr &= 0x1ffff;
   2.252 -    if (addr >= 0x10000)
   2.253 +    if ( addr >= 0x10000 )
   2.254          return 0xff;
   2.255  
   2.256 -    if (s->sr[4] & 0x08) {
   2.257 +    if ( s->sr[4] & 0x08 )
   2.258 +    {
   2.259          /* chain 4 mode : simplest access */
   2.260          ret = vram_b(s, addr);
   2.261 -    } else if (s->gr[5] & 0x10) {
   2.262 +    }
   2.263 +    else if ( s->gr[5] & 0x10 )
   2.264 +    {
   2.265          /* odd/even mode (aka text mode mapping) */
   2.266          plane = (s->gr[4] & 2) | (addr & 1);
   2.267          ret = vram_b(s, ((addr & ~1) << 1) | plane);
   2.268 -    } else {
   2.269 +    }
   2.270 +    else
   2.271 +    {
   2.272          /* standard VGA latched access */
   2.273          s->latch = vram_l(s, addr);
   2.274  
   2.275 -        if (!(s->gr[5] & 0x08)) {
   2.276 +        if ( !(s->gr[5] & 0x08) )
   2.277 +        {
   2.278              /* read mode 0 */
   2.279              plane = s->gr[4];
   2.280              ret = GET_PLANE(s->latch, plane);
   2.281 -        } else {
   2.282 +        }
   2.283 +        else
   2.284 +        {
   2.285              /* read mode 1 */
   2.286              ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
   2.287              ret |= ret >> 16;
   2.288 @@ -339,6 +359,7 @@ static uint8_t stdvga_mem_readb(uint64_t
   2.289              ret = (~ret) & 0xff;
   2.290          }
   2.291      }
   2.292 +
   2.293      return ret;
   2.294  }
   2.295  
   2.296 @@ -346,7 +367,8 @@ static uint32_t stdvga_mem_read(uint32_t
   2.297  {
   2.298      uint32_t data = 0;
   2.299  
   2.300 -    switch (size) {
   2.301 +    switch ( size )
   2.302 +    {
   2.303      case 1:
   2.304          data = stdvga_mem_readb(addr);
   2.305          break;
   2.306 @@ -365,7 +387,9 @@ static uint32_t stdvga_mem_read(uint32_t
   2.307  
   2.308      default:
   2.309          gdprintk(XENLOG_WARNING, "invalid io size:%d\n", size);
   2.310 +        break;
   2.311      }
   2.312 +
   2.313      return data;
   2.314  }
   2.315  
   2.316 @@ -376,27 +400,32 @@ static void stdvga_mem_writeb(uint64_t a
   2.317      uint32_t write_mask, bit_mask, set_mask;
   2.318  
   2.319      addr &= 0x1ffff;
   2.320 -    if (addr >= 0x10000)
   2.321 +    if ( addr >= 0x10000 )
   2.322          return;
   2.323  
   2.324 -    if (s->sr[4] & 0x08) {
   2.325 +    if ( s->sr[4] & 0x08 )
   2.326 +    {
   2.327          /* chain 4 mode : simplest access */
   2.328          plane = addr & 3;
   2.329          mask = (1 << plane);
   2.330 -        if (s->sr[2] & mask) {
   2.331 +        if ( s->sr[2] & mask )
   2.332              vram_b(s, addr) = val;
   2.333 -        }
   2.334 -    } else if (s->gr[5] & 0x10) {
   2.335 +    } else if ( s->gr[5] & 0x10 )
   2.336 +    {
   2.337          /* odd/even mode (aka text mode mapping) */
   2.338          plane = (s->gr[4] & 2) | (addr & 1);
   2.339          mask = (1 << plane);
   2.340 -        if (s->sr[2] & mask) {
   2.341 +        if ( s->sr[2] & mask )
   2.342 +        {
   2.343              addr = ((addr & ~1) << 1) | plane;
   2.344              vram_b(s, addr) = val;
   2.345          }
   2.346 -    } else {
   2.347 +    }
   2.348 +    else
   2.349 +    {
   2.350          write_mode = s->gr[5] & 3;
   2.351 -        switch(write_mode) {
   2.352 +        switch ( write_mode )
   2.353 +        {
   2.354          default:
   2.355          case 0:
   2.356              /* rotate */
   2.357 @@ -429,7 +458,8 @@ static void stdvga_mem_writeb(uint64_t a
   2.358  
   2.359          /* apply logical operation */
   2.360          func_select = s->gr[3] >> 3;
   2.361 -        switch(func_select) {
   2.362 +        switch ( func_select )
   2.363 +        {
   2.364          case 0:
   2.365          default:
   2.366              /* nothing to do */
   2.367 @@ -466,7 +496,8 @@ static void stdvga_mem_writeb(uint64_t a
   2.368  static void stdvga_mem_write(uint32_t addr, uint32_t data, uint32_t size)
   2.369  {
   2.370      /* Intercept mmio write */
   2.371 -    switch (size) {
   2.372 +    switch ( size )
   2.373 +    {
   2.374      case 1:
   2.375          stdvga_mem_writeb(addr, (data >>  0) & 0xff);
   2.376          break;
   2.377 @@ -485,6 +516,7 @@ static void stdvga_mem_write(uint32_t ad
   2.378  
   2.379      default:
   2.380          gdprintk(XENLOG_WARNING, "invalid io size:%d\n", size);
   2.381 +        break;
   2.382      }
   2.383  }
   2.384  
   2.385 @@ -495,19 +527,24 @@ static int mmio_move(struct hvm_hw_stdvg
   2.386      int i;
   2.387      int sign = p->df ? -1 : 1;
   2.388  
   2.389 -    if (p->data_is_ptr) {
   2.390 -        if (p->dir == IOREQ_READ ) {
   2.391 +    if ( p->data_is_ptr )
   2.392 +    {
   2.393 +        if ( p->dir == IOREQ_READ )
   2.394 +        {
   2.395              uint32_t addr = p->addr, data = p->data, tmp;
   2.396 -            for (i = 0; i < p->count; i++) {
   2.397 +            for ( i = 0; i < p->count; i++ ) 
   2.398 +            {
   2.399                  tmp = stdvga_mem_read(addr, p->size);
   2.400                  hvm_copy_to_guest_phys(data, &tmp, p->size);
   2.401                  data += sign * p->size;
   2.402                  addr += sign * p->size;
   2.403              }
   2.404          }
   2.405 -        else {
   2.406 +        else
   2.407 +        {
   2.408              uint32_t addr = p->addr, data = p->data, tmp;
   2.409 -            for (i = 0; i < p->count; i++) {
   2.410 +            for ( i = 0; i < p->count; i++ )
   2.411 +            {
   2.412                  hvm_copy_from_guest_phys(&tmp, data, p->size);
   2.413                  stdvga_mem_write(addr, tmp, p->size);
   2.414                  data += sign * p->size;
   2.415 @@ -515,17 +552,22 @@ static int mmio_move(struct hvm_hw_stdvg
   2.416              }
   2.417          }
   2.418      }
   2.419 -    else {
   2.420 -        if (p->dir == IOREQ_READ ) {
   2.421 +    else
   2.422 +    {
   2.423 +        if ( p->dir == IOREQ_READ )
   2.424 +        {
   2.425              uint32_t addr = p->addr;
   2.426 -            for (i = 0; i < p->count; i++) {
   2.427 +            for ( i = 0; i < p->count; i++ )
   2.428 +            {
   2.429                  p->data = stdvga_mem_read(addr, p->size);
   2.430                  addr += sign * p->size;
   2.431              }
   2.432          }
   2.433 -        else {
   2.434 +        else
   2.435 +        {
   2.436              uint32_t addr = p->addr;
   2.437 -            for (i = 0; i < p->count; i++) {
   2.438 +            for ( i = 0; i < p->count; i++ )
   2.439 +            {
   2.440                  stdvga_mem_write(addr, p->data, p->size);
   2.441                  addr += sign * p->size;
   2.442              }
   2.443 @@ -553,11 +595,13 @@ static int mmio_op(struct hvm_hw_stdvga 
   2.444  {
   2.445      uint32_t orig, mod = 0;
   2.446      orig = stdvga_mem_read(p->addr, p->size);
   2.447 -    if (p->dir == IOREQ_WRITE) {
   2.448 +
   2.449 +    if ( p->dir == IOREQ_WRITE )
   2.450 +    {
   2.451          mod = (op_array[p->type])(orig, p->data);
   2.452          stdvga_mem_write(p->addr, mod, p->size);
   2.453      }
   2.454 -    // p->data = orig; // Can't modify p->data yet.  QEMU still needs to use it.  So return zero below.
   2.455 +
   2.456      return 0; /* Don't try to buffer these operations */
   2.457  }
   2.458  
   2.459 @@ -565,17 +609,20 @@ int stdvga_intercept_mmio(ioreq_t *p)
   2.460  {
   2.461      struct domain *d = current->domain;
   2.462      struct hvm_hw_stdvga *s = &d->arch.hvm_domain.stdvga;
   2.463 -    int buf = 0;
   2.464 +    int buf = 0, rc;
   2.465  
   2.466 -    if (p->size > 8) {
   2.467 +    if ( p->size > 8 )
   2.468 +    {
   2.469          gdprintk(XENLOG_WARNING, "invalid mmio size %d\n", (int)p->size);
   2.470          return 0;
   2.471      }
   2.472  
   2.473      spin_lock(&s->lock);
   2.474  
   2.475 -    if (s->stdvga && s->cache) {
   2.476 -        switch (p->type) {
   2.477 +    if ( s->stdvga && s->cache )
   2.478 +    {
   2.479 +        switch ( p->type )
   2.480 +        {
   2.481          case IOREQ_TYPE_COPY:
   2.482              buf = mmio_move(s, p);
   2.483              break;
   2.484 @@ -588,23 +635,20 @@ int stdvga_intercept_mmio(ioreq_t *p)
   2.485              break;
   2.486          default:
   2.487              gdprintk(XENLOG_ERR, "unsupported mmio request type:%d "
   2.488 -                     "addr:0x%04x data:0x%04x size:%d count:%d state:%d isptr:%d dir:%d df:%d\n",
   2.489 -                     p->type,
   2.490 -                     (int)p->addr, (int)p->data, (int)p->size, (int)p->count, p->state,
   2.491 +                     "addr:0x%04x data:0x%04x size:%d count:%d state:%d "
   2.492 +                     "isptr:%d dir:%d df:%d\n",
   2.493 +                     p->type, (int)p->addr, (int)p->data, (int)p->size,
   2.494 +                     (int)p->count, p->state,
   2.495                       p->data_is_ptr, p->dir, p->df);
   2.496              s->cache = 0;
   2.497          }
   2.498      }
   2.499 -    if (buf && hvm_buffered_io_send(p)) {
   2.500 -        UPDATE_STATS(p->dir == IOREQ_READ ? s->stats.nr_mmio_buffered_rd++ : s->stats.nr_mmio_buffered_wr++);
   2.501 -        spin_unlock(&s->lock);
   2.502 -        return 1;
   2.503 -    }
   2.504 -    else {
   2.505 -        UPDATE_STATS(p->dir == IOREQ_READ ? s->stats.nr_mmio_unbuffered_rd++ : s->stats.nr_mmio_unbuffered_wr++);
   2.506 -        spin_unlock(&s->lock);
   2.507 -        return 0;
   2.508 -    }
   2.509 +
   2.510 +    rc = (buf && hvm_buffered_io_send(p));
   2.511 +
   2.512 +    spin_unlock(&s->lock);
   2.513 +
   2.514 +    return rc;
   2.515  }
   2.516  
   2.517  void stdvga_init(struct domain *d)
   2.518 @@ -614,18 +658,25 @@ void stdvga_init(struct domain *d)
   2.519      memset(s, 0, sizeof(*s));
   2.520      spin_lock_init(&s->lock);
   2.521      
   2.522 -    for (i = 0; i != ARRAY_SIZE(s->vram_ptr); i++) {
   2.523 +    for ( i = 0; i != ARRAY_SIZE(s->vram_ptr); i++ )
   2.524 +    {
   2.525          struct page_info *vram_page;
   2.526          vram_page = alloc_domheap_page(NULL);
   2.527 -        if (!vram_page)
   2.528 +        if ( vram_page == NULL )
   2.529              break;
   2.530          s->vram_ptr[i] = page_to_virt(vram_page);
   2.531          memset(s->vram_ptr[i], 0, PAGE_SIZE);
   2.532      }
   2.533 -    if (i == ARRAY_SIZE(s->vram_ptr)) {
   2.534 -        register_portio_handler(d, 0x3c4, 2, stdvga_intercept_pio); /* sequencer registers */
   2.535 -        register_portio_handler(d, 0x3ce, 2, stdvga_intercept_pio); /* graphics registers */
   2.536 -        register_buffered_io_handler(d, 0xa0000, 0x10000, stdvga_intercept_mmio); /* mmio */
   2.537 +
   2.538 +    if ( i == ARRAY_SIZE(s->vram_ptr) )
   2.539 +    {
   2.540 +        /* Sequencer registers. */
   2.541 +        register_portio_handler(d, 0x3c4, 2, stdvga_intercept_pio);
   2.542 +        /* Graphics registers. */
   2.543 +        register_portio_handler(d, 0x3ce, 2, stdvga_intercept_pio);
   2.544 +        /* MMIO. */
   2.545 +        register_buffered_io_handler(d, 0xa0000, 0x10000,
   2.546 +                                     stdvga_intercept_mmio);
   2.547      }
   2.548  }
   2.549  
   2.550 @@ -633,80 +684,14 @@ void stdvga_deinit(struct domain *d)
   2.551  {
   2.552      struct hvm_hw_stdvga *s = &d->arch.hvm_domain.stdvga;
   2.553      int i;
   2.554 -    for (i = 0; i != ARRAY_SIZE(s->vram_ptr); i++) {
   2.555 +
   2.556 +    for ( i = 0; i != ARRAY_SIZE(s->vram_ptr); i++ )
   2.557 +    {
   2.558          struct page_info *vram_page;
   2.559 -        if (s->vram_ptr[i] == NULL)
   2.560 +        if ( s->vram_ptr[i] == NULL )
   2.561              continue;
   2.562          vram_page = virt_to_page(s->vram_ptr[i]);
   2.563          free_domheap_page(vram_page);
   2.564          s->vram_ptr[i] = NULL;
   2.565      }
   2.566  }
   2.567 -
   2.568 -#ifdef STDVGA_STATS
   2.569 -static void stdvga_stats_dump(unsigned char key)
   2.570 -{
   2.571 -    struct domain *d;
   2.572 -
   2.573 -    printk("%s: key '%c' pressed\n", __FUNCTION__, key);
   2.574 -
   2.575 -    rcu_read_lock(&domlist_read_lock);
   2.576 -
   2.577 -    for_each_domain ( d )
   2.578 -    {
   2.579 -        struct hvm_hw_stdvga *s;
   2.580 -        int i;
   2.581 -
   2.582 -        if ( !is_hvm_domain(d) )
   2.583 -            continue;
   2.584 -
   2.585 -        s = &d->arch.hvm_domain.stdvga;
   2.586 -        spin_lock(&s->lock);
   2.587 -        printk("\n>>> Domain %d <<<\n", d->domain_id);
   2.588 -        printk("    modes: stdvga:%d caching:%d\n", s->stdvga, s->cache);
   2.589 -        printk("                       %8s %8s\n", "read", "write");
   2.590 -        printk("    nr_mmio_buffered:  %8u %8u\n", s->stats.nr_mmio_buffered_rd, s->stats.nr_mmio_buffered_wr);
   2.591 -        printk("    nr_mmio_unbuffered:%8u %8u\n", s->stats.nr_mmio_unbuffered_rd, s->stats.nr_mmio_unbuffered_wr);
   2.592 -        printk("    nr_pio_buffered:   %8u %8u\n", s->stats.nr_pio_buffered_rd, s->stats.nr_pio_buffered_wr);
   2.593 -        printk("    nr_pio_unbuffered: %8u %8u\n", s->stats.nr_pio_unbuffered_rd, s->stats.nr_pio_unbuffered_wr);
   2.594 -
   2.595 -        for (i = 0; i != sizeof(s->sr); i++) {
   2.596 -            if (i % 8 == 0)
   2.597 -                printk("    sr[0x%02x] ", i);
   2.598 -            printk("%02x ", s->sr[i]);
   2.599 -            if (i % 8 == 7)
   2.600 -                printk("\n");
   2.601 -        }
   2.602 -        if (i % 8 != 7)
   2.603 -            printk("\n");
   2.604 -
   2.605 -        for (i = 0; i != sizeof(s->gr); i++) {
   2.606 -            if (i % 8 == 0)
   2.607 -                printk("    gr[0x%02x] ", i);
   2.608 -            printk("%02x ", s->gr[i]);
   2.609 -            if (i % 8 == 7)
   2.610 -                printk("\n");
   2.611 -        }
   2.612 -        if (i % 8 != 7)
   2.613 -            printk("\n");
   2.614 -
   2.615 -        memset(&s->stats, 0, sizeof(s->stats));
   2.616 -
   2.617 -        spin_unlock(&s->lock);
   2.618 -    }
   2.619 -
   2.620 -    rcu_read_unlock(&domlist_read_lock);
   2.621 -}
   2.622 -
   2.623 -#include <xen/keyhandler.h>
   2.624 -
   2.625 -static int __init setup_stdvga_stats_dump(void)
   2.626 -{
   2.627 -    register_keyhandler('<', stdvga_stats_dump, "dump stdvga stats");
   2.628 -    return 0;
   2.629 -}
   2.630 -
   2.631 -__initcall(setup_stdvga_stats_dump);
   2.632 -
   2.633 -#endif
   2.634 -
     3.1 --- a/xen/include/asm-x86/hvm/io.h	Mon Oct 29 09:16:59 2007 +0000
     3.2 +++ b/xen/include/asm-x86/hvm/io.h	Mon Oct 29 09:17:38 2007 +0000
     3.3 @@ -166,9 +166,7 @@ extern void hvm_io_assist(void);
     3.4  extern void hvm_dpci_eoi(struct domain *d, unsigned int guest_irq,
     3.5                           union vioapic_redir_entry *ent);
     3.6  
     3.7 -
     3.8 -#undef  STDVGA_STATS /* #define to enable stdvga statistics */
     3.9 -#undef  STDVGA_CHECK /* debug: ensure cached value matches qemu value */
    3.10 +#ifdef __x86_64__
    3.11  
    3.12  struct hvm_hw_stdvga {
    3.13      uint8_t sr_index;
    3.14 @@ -180,24 +178,18 @@ struct hvm_hw_stdvga {
    3.15      int cache;
    3.16      uint8_t *vram_ptr[64];  /* shadow of 0xa0000-0xaffff */
    3.17      spinlock_t lock;
    3.18 -    
    3.19 -#ifdef STDVGA_STATS
    3.20 -    struct {
    3.21 -        uint32_t nr_mmio_buffered_rd;
    3.22 -        uint32_t nr_mmio_buffered_wr;
    3.23 -        uint32_t nr_mmio_unbuffered_rd;
    3.24 -        uint32_t nr_mmio_unbuffered_wr;
    3.25 -        uint32_t nr_pio_buffered_rd;
    3.26 -        uint32_t nr_pio_buffered_wr;
    3.27 -        uint32_t nr_pio_unbuffered_rd;
    3.28 -        uint32_t nr_pio_unbuffered_wr;
    3.29 -    } stats;
    3.30 -#endif
    3.31  };
    3.32  
    3.33 -extern void stdvga_init(struct domain *d);
    3.34 -extern void stdvga_deinit(struct domain *d);
    3.35 -extern void stdvga_check_cached_value(ioreq_t *p);
    3.36 +void stdvga_init(struct domain *d);
    3.37 +void stdvga_deinit(struct domain *d);
    3.38 +
    3.39 +#else /* __i386__ */
    3.40 +
    3.41 +struct hvm_hw_stdvga {};
    3.42 +#define stdvga_init(d)   ((void)0)
    3.43 +#define stdvga_deinit(d) ((void)0)
    3.44 +
    3.45 +#endif
    3.46  
    3.47  #endif /* __ASM_X86_HVM_IO_H__ */
    3.48