ia64/xen-unstable

changeset 11279:61eea55dce65

[TOOLS] Remove the 'cpuperf' misc tool. Xenoprof is the
correct tool to use for hardware perfctr monitoring now.
Also remove unused xc_msr MSR accessor functions from libxenctrl.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Wed Aug 23 15:02:55 2006 +0100 (2006-08-23)
parents 58b5141c8309
children 26b673aeff8b
files tools/libxc/xc_misc.c tools/libxc/xenctrl.h tools/misc/Makefile tools/misc/cpuperf/Makefile tools/misc/cpuperf/README.txt tools/misc/cpuperf/cpuperf.c tools/misc/cpuperf/cpuperf_perfcntr.h tools/misc/cpuperf/cpuperf_xeno.h tools/misc/cpuperf/module/Makefile tools/misc/cpuperf/module/perfcntr.c tools/misc/cpuperf/p4perf.h
line diff
     1.1 --- a/tools/libxc/xc_misc.c	Wed Aug 23 14:43:48 2006 +0100
     1.2 +++ b/tools/libxc/xc_misc.c	Wed Aug 23 15:02:55 2006 +0100
     1.3 @@ -91,40 +91,6 @@ int xc_perfc_control(int xc_handle,
     1.4      return rc;
     1.5  }
     1.6  
     1.7 -long long xc_msr_read(int xc_handle, int cpu_mask, int msr)
     1.8 -{
     1.9 -    int rc;
    1.10 -    DECLARE_DOM0_OP;
    1.11 -
    1.12 -    op.cmd = DOM0_MSR;
    1.13 -    op.u.msr.write = 0;
    1.14 -    op.u.msr.msr = msr;
    1.15 -    op.u.msr.cpu_mask = cpu_mask;
    1.16 -
    1.17 -    rc = do_dom0_op(xc_handle, &op);
    1.18 -
    1.19 -    return (((unsigned long long)op.u.msr.out2)<<32) | op.u.msr.out1 ;
    1.20 -}
    1.21 -
    1.22 -int xc_msr_write(int xc_handle, int cpu_mask, int msr, unsigned int low,
    1.23 -                  unsigned int high)
    1.24 -{
    1.25 -    int rc;
    1.26 -    DECLARE_DOM0_OP;
    1.27 -
    1.28 -    op.cmd = DOM0_MSR;
    1.29 -    op.u.msr.write = 1;
    1.30 -    op.u.msr.msr = msr;
    1.31 -    op.u.msr.cpu_mask = cpu_mask;
    1.32 -    op.u.msr.in1 = low;
    1.33 -    op.u.msr.in2 = high;
    1.34 -
    1.35 -    rc = do_dom0_op(xc_handle, &op);
    1.36 -
    1.37 -    return rc;
    1.38 -}
    1.39 -
    1.40 -
    1.41  /*
    1.42   * Local variables:
    1.43   * mode: C
     2.1 --- a/tools/libxc/xenctrl.h	Wed Aug 23 14:43:48 2006 +0100
     2.2 +++ b/tools/libxc/xenctrl.h	Wed Aug 23 15:02:55 2006 +0100
     2.3 @@ -471,11 +471,6 @@ int xc_perfc_control(int xc_handle,
     2.4                       int *nbr_desc,
     2.5                       int *nbr_val);
     2.6  
     2.7 -/* read/write msr */
     2.8 -long long xc_msr_read(int xc_handle, int cpu_mask, int msr);
     2.9 -int xc_msr_write(int xc_handle, int cpu_mask, int msr, unsigned int low,
    2.10 -                  unsigned int high);
    2.11 -
    2.12  /**
    2.13   * Memory maps a range within one domain to a local address range.  Mappings
    2.14   * should be unmapped with munmap and should follow the same rules as mmap
     3.1 --- a/tools/misc/Makefile	Wed Aug 23 14:43:48 2006 +0100
     3.2 +++ b/tools/misc/Makefile	Wed Aug 23 15:02:55 2006 +0100
     3.3 @@ -24,7 +24,6 @@ all: build
     3.4  .PHONY: build
     3.5  build: $(TARGETS)
     3.6  	$(MAKE) -C miniterm
     3.7 -	$(MAKE) -C cpuperf
     3.8  ifeq ($(CONFIG_MBOOTPACK),y)
     3.9  	$(MAKE) -C mbootpack
    3.10  endif
    3.11 @@ -36,7 +35,6 @@ install: build
    3.12  	[ -d $(DESTDIR)/usr/sbin ] || $(INSTALL_DIR) $(DESTDIR)/usr/sbin
    3.13  	$(INSTALL_PROG) $(INSTALL_BIN) $(DESTDIR)/usr/bin
    3.14  	$(INSTALL_PROG) $(INSTALL_SBIN) $(DESTDIR)/usr/sbin
    3.15 -	$(MAKE) -C cpuperf install
    3.16  	$(MAKE) -C lomount install
    3.17  #       No sense in installing miniterm on the Xen box.
    3.18  #	$(MAKE) -C miniterm install
    3.19 @@ -47,7 +45,6 @@ install: build
    3.20  clean:
    3.21  	$(RM) *.o $(TARGETS) *~
    3.22  	$(MAKE) -C miniterm clean
    3.23 -	$(MAKE) -C cpuperf clean
    3.24  	$(MAKE) -C mbootpack clean
    3.25  	$(MAKE) -C lomount clean
    3.26  
     4.1 --- a/tools/misc/cpuperf/Makefile	Wed Aug 23 14:43:48 2006 +0100
     4.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.3 @@ -1,51 +0,0 @@
     4.4 -#
     4.5 -# Make Performance counter tool
     4.6 -#
     4.7 -# $Id: Makefile,v 1.1 2003/10/13 16:49:44 jrb44 Exp $
     4.8 -#
     4.9 -# $Log: Makefile,v $
    4.10 -# Revision 1.1  2003/10/13 16:49:44  jrb44
    4.11 -# Initial revision
    4.12 -#
    4.13 -#
    4.14 -
    4.15 -INSTALL		= install
    4.16 -INSTALL_PROG	= $(INSTALL) -m0755
    4.17 -INSTALL_DIR	= $(INSTALL) -d -m0755
    4.18 -
    4.19 -# these are for Xen
    4.20 -XEN_ROOT=../../..
    4.21 -include $(XEN_ROOT)/tools/Rules.mk
    4.22 -
    4.23 -HDRS         = $(wildcard *.h)
    4.24 -SRCS         = $(wildcard *.c)
    4.25 -OBJS         = $(patsubst %.c,%.o,$(SRCS))
    4.26 -
    4.27 -TARGETS      = cpuperf-xen cpuperf-perfcntr
    4.28 -
    4.29 -INSTALL_BIN  = $(TARGETS)
    4.30 -
    4.31 -
    4.32 -.PHONY: all
    4.33 -all: $(TARGETS)
    4.34 -
    4.35 -.PHONY: clean
    4.36 -clean:
    4.37 -	$(RM) *.o $(TARGETS)
    4.38 -
    4.39 -%: %.c $(HDRS) Makefile
    4.40 -	$(CC) $(CFLAGS) -o $@ $<
    4.41 -
    4.42 -cpuperf-xen: cpuperf.c $(HDRS) Makefile
    4.43 -	$(CC) $(CFLAGS) -I $(XEN_LIBXC) -L$(XEN_LIBXC) -lxenctrl -DXENO -o $@ $<
    4.44 -
    4.45 -cpuperf-perfcntr: cpuperf.c $(HDRS) Makefile
    4.46 -	$(CC) $(CFLAGS) -DPERFCNTR -o $@ $<
    4.47 -
    4.48 -.PHONY: install
    4.49 -install: all
    4.50 -	$(INSTALL_PROG) $(INSTALL_BIN) $(DESTDIR)/usr/bin
    4.51 -
    4.52 -
    4.53 -# End of $RCSfile: Makefile,v $
    4.54 -
     5.1 --- a/tools/misc/cpuperf/README.txt	Wed Aug 23 14:43:48 2006 +0100
     5.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.3 @@ -1,371 +0,0 @@
     5.4 -Usage
     5.5 -=====
     5.6 -
     5.7 -Use either xen-cpuperf, cpuperf-perfcntr as appropriate to the system
     5.8 -in use.
     5.9 -
    5.10 -To write:
    5.11 -
    5.12 -    cpuperf -E <escr> -C <cccr> 
    5.13 -
    5.14 -        optional: all numbers in base 10 unless specified
    5.15 -
    5.16 -        -d             Debug mode
    5.17 -        -c <cpu>       CPU number
    5.18 -        -t <thread>    ESCR thread bits - default is 12 (Thread 0 all rings)
    5.19 -                         bit 0: Thread 1 in rings 1,2,3
    5.20 -                         bit 1: Thread 1 in ring 0
    5.21 -                         bit 2: Thread 0 in rings 1,2,3
    5.22 -                         bit 3: Thread 0 in ring 0
    5.23 -        -e <eventsel>  Event selection number
    5.24 -        -m <eventmask> Event mask bits
    5.25 -        -T <value>     ESCR tag value
    5.26 -        -k             Sets CCCR 'compare' bit
    5.27 -        -n             Sets CCCR 'complement' bit
    5.28 -        -g             Sets CCCR 'edge' bit
    5.29 -        -P <bit>       Set the specified bit in MSR_P4_PEBS_ENABLE
    5.30 -        -V <bit>       Set the specified bit in MSR_P4_PEBS_MATRIX_VERT
    5.31 -        (-V and -P may be used multiple times to set multiple bits.)
    5.32 -
    5.33 -To read:
    5.34 -
    5.35 -    cpuperf -r    
    5.36 -
    5.37 -        optional: all numbers in base 10 unless specified
    5.38 -    
    5.39 -        -c <cpu>       CPU number
    5.40 -
    5.41 -<cccr> values:
    5.42 -
    5.43 -    BPU_CCCR0
    5.44 -    BPU_CCCR1
    5.45 -    BPU_CCCR2
    5.46 -    BPU_CCCR3
    5.47 -    MS_CCCR0
    5.48 -    MS_CCCR1
    5.49 -    MS_CCCR2
    5.50 -    MS_CCCR3
    5.51 -    FLAME_CCCR0
    5.52 -    FLAME_CCCR1
    5.53 -    FLAME_CCCR2
    5.54 -    FLAME_CCCR3
    5.55 -    IQ_CCCR0
    5.56 -    IQ_CCCR1
    5.57 -    IQ_CCCR2
    5.58 -    IQ_CCCR3
    5.59 -    IQ_CCCR4
    5.60 -    IQ_CCCR5
    5.61 -    NONE - do not program any CCCR, used when setting up an ESCR for tagging
    5.62 -
    5.63 -<escr> values:
    5.64 -
    5.65 -    BSU_ESCR0
    5.66 -    BSU_ESCR1
    5.67 -    FSB_ESCR0
    5.68 -    FSB_ESCR1
    5.69 -    MOB_ESCR0
    5.70 -    MOB_ESCR1
    5.71 -    PMH_ESCR0
    5.72 -    PMH_ESCR1
    5.73 -    BPU_ESCR0
    5.74 -    BPU_ESCR1
    5.75 -    IS_ESCR0
    5.76 -    IS_ESCR1
    5.77 -    ITLB_ESCR0
    5.78 -    ITLB_ESCR1
    5.79 -    IX_ESCR0
    5.80 -    IX_ESCR1
    5.81 -    MS_ESCR0
    5.82 -    MS_ESCR1
    5.83 -    TBPU_ESCR0
    5.84 -    TBPU_ESCR1
    5.85 -    TC_ESCR0
    5.86 -    TC_ESCR1
    5.87 -    FIRM_ESCR0
    5.88 -    FIRM_ESCR1
    5.89 -    FLAME_ESCR0
    5.90 -    FLAME_ESCR1
    5.91 -    DAC_ESCR0
    5.92 -    DAC_ESCR1
    5.93 -    SAAT_ESCR0
    5.94 -    SAAT_ESCR1
    5.95 -    U2L_ESCR0
    5.96 -    U2L_ESCR1
    5.97 -    CRU_ESCR0
    5.98 -    CRU_ESCR1
    5.99 -    CRU_ESCR2
   5.100 -    CRU_ESCR3
   5.101 -    CRU_ESCR4
   5.102 -    CRU_ESCR5
   5.103 -    IQ_ESCR0
   5.104 -    IQ_ESCR1
   5.105 -    RAT_ESCR0
   5.106 -    RAT_ESCR1
   5.107 -    SSU_ESCR0
   5.108 -    SSU_ESCR1
   5.109 -    ALF_ESCR0
   5.110 -    ALF_ESCR1
   5.111 -
   5.112 -
   5.113 -Example configurations
   5.114 -======================
   5.115 -
   5.116 -Note than in most cases there is a choice of ESCRs and CCCRs for
   5.117 -each metric although not all combinations are allowed. Each ESCR and
   5.118 -counter/CCCR can be used only once.
   5.119 -
   5.120 -Mispredicted branches retired
   5.121 -=============================
   5.122 -
   5.123 -cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 3 -m 1
   5.124 -cpuperf -E CRU_ESCR0 -C IQ_CCCR1 -e 3 -m 1
   5.125 -cpuperf -E CRU_ESCR0 -C IQ_CCCR4 -e 3 -m 1
   5.126 -cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 3 -m 1
   5.127 -cpuperf -E CRU_ESCR1 -C IQ_CCCR3 -e 3 -m 1
   5.128 -cpuperf -E CRU_ESCR1 -C IQ_CCCR5 -e 3 -m 1
   5.129 -
   5.130 -Tracecache misses
   5.131 -=================
   5.132 -
   5.133 -cpuperf -E BPU_ESCR0 -C BPU_CCCR0 -e 3 -m 1
   5.134 -cpuperf -E BPU_ESCR0 -C BPU_CCCR1 -e 3 -m 1
   5.135 -cpuperf -E BPU_ESCR1 -C BPU_CCCR2 -e 3 -m 1
   5.136 -cpuperf -E BPU_ESCR1 -C BPU_CCCR3 -e 3 -m 1
   5.137 -
   5.138 -I-TLB
   5.139 -=====
   5.140 -
   5.141 -cpuperf -E ITLB_ESCR0 -C BPU_CCCR0 -e 24 
   5.142 -cpuperf -E ITLB_ESCR0 -C BPU_CCCR1 -e 24 
   5.143 -cpuperf -E ITLB_ESCR1 -C BPU_CCCR2 -e 24 
   5.144 -cpuperf -E ITLB_ESCR1 -C BPU_CCCR3 -e 24 
   5.145 -
   5.146 - -m <n> : bit 0 count HITS, bit 1 MISSES, bit 2 uncacheable hit
   5.147 -
   5.148 - e.g. all ITLB misses -m 2
   5.149 -
   5.150 -Load replays
   5.151 -============
   5.152 -
   5.153 -cpuperf -E MOB_ESCR0 -C BPU_CCCR0 -e 3
   5.154 -cpuperf -E MOB_ESCR0 -C BPU_CCCR1 -e 3
   5.155 -cpuperf -E MOB_ESCR1 -C BPU_CCCR2 -e 3
   5.156 -cpuperf -E MOB_ESCR1 -C BPU_CCCR3 -e 3
   5.157 -
   5.158 - -m <n> : bit mask, replay due to...
   5.159 -           1: unknown store address
   5.160 -           3: unknown store data
   5.161 -           4: partially overlapped data access between LD/ST
   5.162 -           5: unaligned address between LD/ST
   5.163 -
   5.164 -Page walks
   5.165 -==========
   5.166 -
   5.167 -cpuperf -E PMH_ESCR0 -C BPU_CCCR0 -e 1
   5.168 -cpuperf -E PMH_ESCR0 -C BPU_CCCR1 -e 1
   5.169 -cpuperf -E PMH_ESCR1 -C BPU_CCCR2 -e 1
   5.170 -cpuperf -E PMH_ESCR1 -C BPU_CCCR3 -e 1
   5.171 -
   5.172 - -m <n> : bit 0 counts walks for a D-TLB miss, bit 1 for I-TLB miss
   5.173 -
   5.174 -L2/L3 cache accesses
   5.175 -====================
   5.176 -
   5.177 -cpuperf -E BSU_ESCR0 -C BPU_CCCR0 -e 12
   5.178 -cpuperf -E BSU_ESCR0 -C BPU_CCCR1 -e 12
   5.179 -cpuperf -E BSU_ESCR1 -C BPU_CCCR2 -e 12
   5.180 -cpuperf -E BSU_ESCR1 -C BPU_CCCR3 -e 12
   5.181 -
   5.182 - -m <n> : where the bit mask is:
   5.183 -           0: Read L2 HITS Shared
   5.184 -           1: Read L2 HITS Exclusive
   5.185 -           2: Read L2 HITS Modified
   5.186 -           3: Read L3 HITS Shared
   5.187 -           4: Read L3 HITS Exclusive
   5.188 -           5: Read L3 HITS Modified
   5.189 -           8: Read L2 MISS
   5.190 -           9: Read L3 MISS
   5.191 -          10: Write L2 MISS
   5.192 -
   5.193 -Front side bus activity
   5.194 -=======================
   5.195 -
   5.196 -cpuperf -E FSB_ESCR0 -C BPU_CCCR0 -e 23 -k -g
   5.197 -cpuperf -E FSB_ESCR0 -C BPU_CCCR1 -e 23 -k -g
   5.198 -cpuperf -E FSB_ESCR1 -C BPU_CCCR2 -e 23 -k -g
   5.199 -cpuperf -E FSB_ESCR1 -C BPU_CCCR3 -e 23 -k -g
   5.200 -
   5.201 - -m <n> : where the bit mask is for bus events:
   5.202 -           0: DRDY_DRV    Processor drives bus
   5.203 -           1: DRDY_OWN    Processor reads bus
   5.204 -           2: DRDY_OTHER  Data on bus not being sampled by processor
   5.205 -           3: DBSY_DRV    Processor reserves bus for driving
   5.206 -           4: DBSY_OWN    Other entity reserves bus for sending to processor
   5.207 -           5: DBSY_OTHER  Other entity reserves bus for sending elsewhere
   5.208 -
   5.209 - e.g. -m 3 to get cycles bus actually in use.
   5.210 -
   5.211 -Pipeline clear (entire)
   5.212 -=======================
   5.213 -
   5.214 -cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 2
   5.215 -cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 2
   5.216 -cpuperf -E CRU_ESCR2 -C IQ_CCCR4 -e 2
   5.217 -cpuperf -E CRU_ESCR3 -C IQ_CCCR2 -e 2
   5.218 -cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 2
   5.219 -cpuperf -E CRU_ESCR3 -C IQ_CCCR5 -e 2
   5.220 -
   5.221 - -m <n> : bit mask:
   5.222 -           0: counts a portion of cycles while clear (use -g for edge trigger)
   5.223 -           1: counts each time machine clears for memory ordering issues
   5.224 -           2: counts each time machine clears for self modifying code
   5.225 -
   5.226 -Instructions retired
   5.227 -====================
   5.228 -
   5.229 -cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 2
   5.230 -cpuperf -E CRU_ESCR0 -C IQ_CCCR1 -e 2
   5.231 -cpuperf -E CRU_ESCR0 -C IQ_CCCR4 -e 2
   5.232 -cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 2
   5.233 -cpuperf -E CRU_ESCR1 -C IQ_CCCR3 -e 2
   5.234 -cpuperf -E CRU_ESCR1 -C IQ_CCCR5 -e 2
   5.235 -
   5.236 - -m <n> : bit mask:
   5.237 -           0: counts non-bogus, not tagged instructions
   5.238 -           1: counts non-bogus, tagged instructions
   5.239 -           2: counts bogus, not tagged instructions
   5.240 -           3: counts bogus, tagged instructions
   5.241 -
   5.242 - e.g. -m 3 to count legit retirements
   5.243 -
   5.244 -Uops retired
   5.245 -============
   5.246 -
   5.247 -cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 1
   5.248 -cpuperf -E CRU_ESCR0 -C IQ_CCCR1 -e 1
   5.249 -cpuperf -E CRU_ESCR0 -C IQ_CCCR4 -e 1
   5.250 -cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 1
   5.251 -cpuperf -E CRU_ESCR1 -C IQ_CCCR3 -e 1
   5.252 -cpuperf -E CRU_ESCR1 -C IQ_CCCR5 -e 1
   5.253 -
   5.254 - -m <n> : bit mask:
   5.255 -           0: Non-bogus
   5.256 -           1: Bogus
   5.257 -
   5.258 -x87 FP uops
   5.259 -===========
   5.260 -
   5.261 -cpuperf -E FIRM_ESCR0 -C FLAME_CCCR0 -e 4 -m 32768
   5.262 -cpuperf -E FIRM_ESCR0 -C FLAME_CCCR1 -e 4 -m 32768
   5.263 -cpuperf -E FIRM_ESCR1 -C FLAME_CCCR2 -e 4 -m 32768
   5.264 -cpuperf -E FIRM_ESCR1 -C FLAME_CCCR3 -e 4 -m 32768
   5.265 -
   5.266 -Replay tagging mechanism
   5.267 -========================
   5.268 -
   5.269 -Counts retirement of uops tagged with the replay tagging mechanism
   5.270 -
   5.271 -cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 9
   5.272 -cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 9
   5.273 -cpuperf -E CRU_ESCR2 -C IQ_CCCR4 -e 9
   5.274 -cpuperf -E CRU_ESCR3 -C IQ_CCCR2 -e 9
   5.275 -cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 9
   5.276 -cpuperf -E CRU_ESCR3 -C IQ_CCCR5 -e 9
   5.277 -
   5.278 - -m <n> : bit mask:
   5.279 -           0: Non-bogus (set this bit for all events listed below)
   5.280 -           1: Bogus
   5.281 -
   5.282 -Set replay tagging mechanism bits with -P and -V:
   5.283 -
   5.284 -  L1 cache load miss retired:      -P 0 -P 24 -P 25 -V 0
   5.285 -  L2 cache load miss retired:      -P 1 -P 24 -P 25 -V 0  (read manual)
   5.286 -  DTLB load miss retired:          -P 2 -P 24 -P 25 -V 0
   5.287 -  DTLB store miss retired:         -P 2 -P 24 -P 25 -V 1
   5.288 -  DTLB all miss retired:           -P 2 -P 24 -P 25 -V 0 -V 1
   5.289 -
   5.290 -e.g. to count all DTLB misses
   5.291 -
   5.292 - cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 9 -m 1 P 2 -P 24 -P 25 -V 0 -V 1
   5.293 -
   5.294 -Front end event
   5.295 -===============
   5.296 -
   5.297 -To count tagged uops:
   5.298 -
   5.299 -cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 8
   5.300 -cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 8
   5.301 -cpuperf -E CRU_ESCR2 -C IQ_CCCR4 -e 8
   5.302 -cpuperf -E CRU_ESCR3 -C IQ_CCCR2 -e 8
   5.303 -cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 8
   5.304 -cpuperf -E CRU_ESCR3 -C IQ_CCCR5 -e 8
   5.305 -
   5.306 - -m <n> : bit 0 for non-bogus uops, bit 1 for bogus uops
   5.307 -
   5.308 -Must have another ESCR programmed to tag uops as required
   5.309 -
   5.310 -cpuperf -E RAT_ESCR0 -C NONE -e 2
   5.311 -cpuperf -E RAT_ESCR1 -C NONE -e 2
   5.312 -
   5.313 - -m <n> : bit 1 for LOADs, bit 2 for STOREs
   5.314 -
   5.315 -An example set of counters
   5.316 -===========================
   5.317 -
   5.318 -# instructions retired
   5.319 -cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 2 -m 3
   5.320 -
   5.321 -# trace cache misses
   5.322 -cpuperf -E BPU_ESCR0 -C BPU_CCCR0 -e 3 -m 1
   5.323 -
   5.324 -# L1 D cache misses (load misses retired)
   5.325 -cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 9 -m 1 -P 0 -P 24 -P 25 -V 0
   5.326 -
   5.327 -# L2 misses (load and store)
   5.328 -cpuperf -E BSU_ESCR0 -C BPU_CCCR1 -e 12 -m 1280
   5.329 -
   5.330 -# I-TLB misses
   5.331 -cpuperf -E ITLB_ESCR1 -C BPU_CCCR2 -e 24 -m 2
   5.332 -
   5.333 -# D-TLB misses (as PT walks)
   5.334 -cpuperf -E PMH_ESCR1 -C BPU_CCCR3 -e 1 -m 1
   5.335 -
   5.336 -# Other 'bonus' counters would be:
   5.337 -#   number of loads executed - need both command lines
   5.338 -cpuperf -E RAT_ESCR0 -C NONE -e 2 -m 2
   5.339 -cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 8 -m 3
   5.340 -
   5.341 -#   number of mispredicted branches
   5.342 -cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 3 -m 1
   5.343 -
   5.344 -# x87 FP uOps
   5.345 -cpuperf -E FIRM_ESCR0 -C FLAME_CCCR0 -e 4 -m 32768
   5.346 -
   5.347 -The above has counter assignments
   5.348 -
   5.349 -0  Trace cache misses
   5.350 -1  L2 Misses
   5.351 -2  I-TLB misses
   5.352 -3  D-TLB misses
   5.353 -4  
   5.354 -5  
   5.355 -6  
   5.356 -7  
   5.357 -8  x87 FP uOps 
   5.358 -9  
   5.359 -10 
   5.360 -11 
   5.361 -12 Instructions retired
   5.362 -13 L1 D cache misses
   5.363 -14 Mispredicted branches
   5.364 -15 Loads executed
   5.365 -16 
   5.366 -17 
   5.367 -
   5.368 -Counting instructions retired on each logical CPU
   5.369 -=================================================
   5.370 -
   5.371 -cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 2 -m 3 -t 12
   5.372 -cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 2 -m 3 -t 3
   5.373 -
   5.374 -Cannot count mispred branches as well due to CRU_ESCR1 use.
     6.1 --- a/tools/misc/cpuperf/cpuperf.c	Wed Aug 23 14:43:48 2006 +0100
     6.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.3 @@ -1,296 +0,0 @@
     6.4 -/*
     6.5 - * User mode program to program performance counters.
     6.6 - *
     6.7 - * JRB/IAP October 2003.
     6.8 - *
     6.9 - * $Id: cpuperf.c,v 1.2 2003/10/14 11:00:59 jrb44 Exp $
    6.10 - *
    6.11 - * $Log: cpuperf.c,v $
    6.12 - * Revision 1.2  2003/10/14 11:00:59  jrb44
    6.13 - * Added dcefault CPU. Added NONE CCCR.
    6.14 - *
    6.15 - * Revision 1.1  2003/10/13 16:49:44  jrb44
    6.16 - * Initial revision
    6.17 - *
    6.18 - */
    6.19 -
    6.20 -#include <sys/types.h>
    6.21 -#include <sched.h>
    6.22 -#include <stdio.h>
    6.23 -#include <unistd.h>
    6.24 -#include <stdlib.h>
    6.25 -#include <string.h>
    6.26 -#include <errno.h>
    6.27 -
    6.28 -#include "p4perf.h"
    6.29 -
    6.30 -static inline void cpus_wrmsr(int cpu_mask,
    6.31 -                              int msr,
    6.32 -                              unsigned int low,
    6.33 -                              unsigned int high )
    6.34 -{
    6.35 -    fprintf(stderr, "No backend to write MSR 0x%x <= 0x%08x%08x on %08x\n",
    6.36 -            msr, high, low, cpu_mask);
    6.37 -}
    6.38 -
    6.39 -static inline unsigned long long cpus_rdmsr( int cpu_mask, int msr )
    6.40 -{
    6.41 -    fprintf(stderr, "No backend to read MSR 0x%x on %08x\n", msr, cpu_mask);
    6.42 -    return 0;
    6.43 -}
    6.44 -
    6.45 -#ifdef PERFCNTR
    6.46 -#include "cpuperf_perfcntr.h"
    6.47 -#define cpus_wrmsr perfcntr_wrmsr
    6.48 -#define cpus_rdmsr perfcntr_rdmsr
    6.49 -#endif
    6.50 -
    6.51 -#ifdef XENO
    6.52 -#include "cpuperf_xeno.h"
    6.53 -#define cpus_wrmsr dom0_wrmsr
    6.54 -#define cpus_rdmsr dom0_rdmsr
    6.55 -#endif
    6.56 -
    6.57 -struct macros {
    6.58 -    char         *name;
    6.59 -    unsigned long msr_addr;
    6.60 -    int           number;
    6.61 -};
    6.62 -
    6.63 -#define NO_CCCR 0xfffffffe
    6.64 -
    6.65 -struct macros msr[] = {
    6.66 -    {"BPU_COUNTER0", 0x300, 0},
    6.67 -    {"BPU_COUNTER1", 0x301, 1},
    6.68 -    {"BPU_COUNTER2", 0x302, 2},
    6.69 -    {"BPU_COUNTER3", 0x303, 3},
    6.70 -    {"MS_COUNTER0", 0x304, 4},
    6.71 -    {"MS_COUNTER1", 0x305, 5},
    6.72 -    {"MS_COUNTER2", 0x306, 6},
    6.73 -    {"MS_COUNTER3", 0x307, 7},
    6.74 -    {"FLAME_COUNTER0", 0x308, 8},
    6.75 -    {"FLAME_COUNTER1", 0x309, 9},
    6.76 -    {"FLAME_COUNTER2", 0x30a, 10},
    6.77 -    {"FLAME_COUNTER3", 0x30b, 11},
    6.78 -    {"IQ_COUNTER0", 0x30c, 12},
    6.79 -    {"IQ_COUNTER1", 0x30d, 13},
    6.80 -    {"IQ_COUNTER2", 0x30e, 14},
    6.81 -    {"IQ_COUNTER3", 0x30f, 15},
    6.82 -    {"IQ_COUNTER4", 0x310, 16},
    6.83 -    {"IQ_COUNTER5", 0x311, 17},
    6.84 -    {"BPU_CCCR0", 0x360, 0},
    6.85 -    {"BPU_CCCR1", 0x361, 1},
    6.86 -    {"BPU_CCCR2", 0x362, 2},
    6.87 -    {"BPU_CCCR3", 0x363, 3},
    6.88 -    {"MS_CCCR0", 0x364, 4},
    6.89 -    {"MS_CCCR1", 0x365, 5},
    6.90 -    {"MS_CCCR2", 0x366, 6},
    6.91 -    {"MS_CCCR3", 0x367, 7},
    6.92 -    {"FLAME_CCCR0", 0x368, 8},
    6.93 -    {"FLAME_CCCR1", 0x369, 9},
    6.94 -    {"FLAME_CCCR2", 0x36a, 10},
    6.95 -    {"FLAME_CCCR3", 0x36b, 11},
    6.96 -    {"IQ_CCCR0", 0x36c, 12},
    6.97 -    {"IQ_CCCR1", 0x36d, 13},
    6.98 -    {"IQ_CCCR2", 0x36e, 14},
    6.99 -    {"IQ_CCCR3", 0x36f, 15},
   6.100 -    {"IQ_CCCR4", 0x370, 16},
   6.101 -    {"IQ_CCCR5", 0x371, 17},
   6.102 -    {"BSU_ESCR0", 0x3a0, 7},
   6.103 -    {"BSU_ESCR1", 0x3a1, 7},
   6.104 -    {"FSB_ESCR0", 0x3a2, 6},
   6.105 -    {"FSB_ESCR1", 0x3a3, 6},
   6.106 -    {"MOB_ESCR0", 0x3aa, 2},
   6.107 -    {"MOB_ESCR1", 0x3ab, 2},
   6.108 -    {"PMH_ESCR0", 0x3ac, 4},
   6.109 -    {"PMH_ESCR1", 0x3ad, 4},
   6.110 -    {"BPU_ESCR0", 0x3b2, 0},
   6.111 -    {"BPU_ESCR1", 0x3b3, 0},
   6.112 -    {"IS_ESCR0", 0x3b4, 1},
   6.113 -    {"IS_ESCR1", 0x3b5, 1},
   6.114 -    {"ITLB_ESCR0", 0x3b6, 3},
   6.115 -    {"ITLB_ESCR1", 0x3b7, 3},
   6.116 -    {"IX_ESCR0", 0x3c8, 5},
   6.117 -    {"IX_ESCR1", 0x3c9, 5},
   6.118 -    {"MS_ESCR0", 0x3c0, 0},
   6.119 -    {"MS_ESCR1", 0x3c1, 0},
   6.120 -    {"TBPU_ESCR0", 0x3c2, 2},
   6.121 -    {"TBPU_ESCR1", 0x3c3, 2},
   6.122 -    {"TC_ESCR0", 0x3c4, 1},
   6.123 -    {"TC_ESCR1", 0x3c5, 1},
   6.124 -    {"FIRM_ESCR0", 0x3a4, 1},
   6.125 -    {"FIRM_ESCR1", 0x3a5, 1},
   6.126 -    {"FLAME_ESCR0", 0x3a6, 0},
   6.127 -    {"FLAME_ESCR1", 0x3a7, 0},
   6.128 -    {"DAC_ESCR0", 0x3a8, 5},
   6.129 -    {"DAC_ESCR1", 0x3a9, 5},
   6.130 -    {"SAAT_ESCR0", 0x3ae, 2},
   6.131 -    {"SAAT_ESCR1", 0x3af, 2},
   6.132 -    {"U2L_ESCR0", 0x3b0, 3},
   6.133 -    {"U2L_ESCR1", 0x3b1, 3},
   6.134 -    {"CRU_ESCR0", 0x3b8, 4},
   6.135 -    {"CRU_ESCR1", 0x3b9, 4},
   6.136 -    {"CRU_ESCR2", 0x3cc, 5},
   6.137 -    {"CRU_ESCR3", 0x3cd, 5},
   6.138 -    {"CRU_ESCR4", 0x3e0, 6},
   6.139 -    {"CRU_ESCR5", 0x3e1, 6},
   6.140 -    {"IQ_ESCR0", 0x3ba, 0},
   6.141 -    {"IQ_ESCR1", 0x3bb, 0},
   6.142 -    {"RAT_ESCR0", 0x3bc, 2},
   6.143 -    {"RAT_ESCR1", 0x3bd, 2},
   6.144 -    {"SSU_ESCR0", 0x3be, 3},
   6.145 -    {"SSU_ESCR1", 0x3bf, 3},
   6.146 -    {"ALF_ESCR0", 0x3ca, 1},
   6.147 -    {"ALF_ESCR1", 0x3cb, 1},
   6.148 -    {"PEBS_ENABLE", 0x3f1, 0},
   6.149 -    {"PEBS_MATRIX_VERT", 0x3f2, 0},
   6.150 -    {"NONE", NO_CCCR, 0},
   6.151 -    {NULL, 0, 0}
   6.152 -};
   6.153 -
   6.154 -struct macros *lookup_macro(char *str)
   6.155 -{
   6.156 -    struct macros *m;
   6.157 -
   6.158 -    m = msr;
   6.159 -    while (m->name) {
   6.160 -        if (strcmp(m->name, str) == 0)
   6.161 -            return m;
   6.162 -        m++;
   6.163 -    }
   6.164 -    return NULL;
   6.165 -}
   6.166 -
   6.167 -int main(int argc, char **argv)
   6.168 -{
   6.169 -    int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
   6.170 -    unsigned int cpu_mask = 1;
   6.171 -    struct macros *escr = NULL, *cccr = NULL;
   6.172 -    unsigned long escr_val, cccr_val;
   6.173 -    int debug = 0;
   6.174 -    unsigned long pebs = 0, pebs_vert = 0;
   6.175 -    int pebs_x = 0, pebs_vert_x = 0;
   6.176 -    int read = 0;
   6.177 -    int compare = 0;
   6.178 -    int complement = 0;
   6.179 -    int edge = 0;
   6.180 -    
   6.181 -#ifdef XENO
   6.182 -    xen_init();
   6.183 -#endif
   6.184 -
   6.185 -
   6.186 -    while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:rkng")) != -1) {
   6.187 -        switch((char)c) {
   6.188 -        case 'P':
   6.189 -            pebs |= 1 << atoi(optarg);
   6.190 -            pebs_x = 1;
   6.191 -            break;
   6.192 -        case 'V':
   6.193 -            pebs_vert |= 1 << atoi(optarg);
   6.194 -            pebs_vert_x = 1;
   6.195 -            break;
   6.196 -        case 'd':
   6.197 -            debug = 1;
   6.198 -            break;
   6.199 -        case 'c':
   6.200 -            {
   6.201 -                int cpu = atoi(optarg);
   6.202 -                cpu_mask  = (cpu == -1)?(~0):(1<<cpu);
   6.203 -            }
   6.204 -            break;
   6.205 -        case 't': // ESCR thread bits
   6.206 -            t = atoi(optarg);
   6.207 -            break;
   6.208 -        case 'e': // eventsel
   6.209 -            es = atoi(optarg);
   6.210 -            break;
   6.211 -        case 'm': // eventmask
   6.212 -            em = atoi(optarg);
   6.213 -            break;
   6.214 -        case 'T': // tag value
   6.215 -            tv = atoi(optarg);
   6.216 -            te = 1;
   6.217 -            break;
   6.218 -        case 'E':
   6.219 -            escr = lookup_macro(optarg);
   6.220 -            if (!escr) {
   6.221 -                fprintf(stderr, "Macro '%s' not found.\n", optarg);
   6.222 -                exit(1);
   6.223 -            }
   6.224 -            break;
   6.225 -        case 'C':
   6.226 -            cccr = lookup_macro(optarg);
   6.227 -            if (!cccr) {
   6.228 -                fprintf(stderr, "Macro '%s' not found.\n", optarg);
   6.229 -                exit(1);
   6.230 -            }
   6.231 -            break;
   6.232 -        case 'r':
   6.233 -            read = 1;
   6.234 -            break;
   6.235 -        case 'k':
   6.236 -            compare = 1;
   6.237 -            break;
   6.238 -        case 'n':
   6.239 -            complement = 1;
   6.240 -            break;
   6.241 -        case 'g':
   6.242 -            edge = 1;
   6.243 -            break;
   6.244 -        }
   6.245 -    }
   6.246 -
   6.247 -    if (read) {
   6.248 -        int i;
   6.249 -        for (i=0x300;i<0x312;i++)
   6.250 -            printf("%010llu ",cpus_rdmsr( cpu_mask, i ) );
   6.251 -        printf("\n");
   6.252 -        exit(1);
   6.253 -    }
   6.254 -    
   6.255 -    if (!escr) {
   6.256 -        fprintf(stderr, "Need an ESCR.\n");
   6.257 -        exit(1);
   6.258 -    }
   6.259 -    if (!cccr) {
   6.260 -        fprintf(stderr, "Need a counter number.\n");
   6.261 -        exit(1);
   6.262 -    }
   6.263 -
   6.264 -    escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
   6.265 -        P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
   6.266 -    cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
   6.267 -        ((compare)?P4_CCCR_COMPARE:0) |
   6.268 -        ((complement)?P4_CCCR_COMPLEMENT:0) |
   6.269 -        ((edge)?P4_CCCR_EDGE:0) |
   6.270 -        P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
   6.271 -
   6.272 -    if (debug) {
   6.273 -        fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
   6.274 -        if (cccr->msr_addr != NO_CCCR)
   6.275 -            fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
   6.276 -                    cccr->msr_addr, cccr_val, cccr->number);
   6.277 -        if (pebs_x)
   6.278 -            fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
   6.279 -                    MSR_P4_PEBS_ENABLE, pebs);
   6.280 -        if (pebs_vert_x)
   6.281 -            fprintf(stderr, "PMV  0x%x <= 0x%08lx\n",
   6.282 -                    MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
   6.283 -    }
   6.284 -    
   6.285 -    cpus_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
   6.286 -    if (cccr->msr_addr != NO_CCCR)
   6.287 -        cpus_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
   6.288 -    
   6.289 -    if (pebs_x)
   6.290 -        cpus_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
   6.291 -    
   6.292 -    if (pebs_vert_x)
   6.293 -        cpus_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
   6.294 -    
   6.295 -    return 0;
   6.296 -}
   6.297 -
   6.298 -// End of $RCSfile: cpuperf.c,v $
   6.299 -
     7.1 --- a/tools/misc/cpuperf/cpuperf_perfcntr.h	Wed Aug 23 14:43:48 2006 +0100
     7.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.3 @@ -1,41 +0,0 @@
     7.4 -/*
     7.5 - * Interface to JRB44's /proc/perfcntr interface.
     7.6 - *
     7.7 - * $Id: cpuperf_perfcntr.h,v 1.1 2003/10/13 16:49:44 jrb44 Exp $
     7.8 - *
     7.9 - * $Log: cpuperf_perfcntr.h,v $
    7.10 - * Revision 1.1  2003/10/13 16:49:44  jrb44
    7.11 - * Initial revision
    7.12 - *
    7.13 - */
    7.14 -
    7.15 -#define  PROC_PERFCNTR "/proc/perfcntr"
    7.16 -
    7.17 -static inline void perfcntr_wrmsr(int cpu_mask,
    7.18 -                                  int msr,
    7.19 -                                  unsigned int low,
    7.20 -                                  unsigned int high )
    7.21 -{
    7.22 -    FILE *fd;
    7.23 -    unsigned long long value = low | (((unsigned long long)high) << 32);
    7.24 -
    7.25 -    fd = fopen(PROC_PERFCNTR, "w");
    7.26 -    if (fd == NULL)
    7.27 -    {
    7.28 -        perror("open " PROC_PERFCNTR);
    7.29 -        exit(1);
    7.30 -    }
    7.31 -    
    7.32 -    fprintf(fd, "%x %x %llx \n", cpu_mask, msr, value);
    7.33 -    fprintf(stderr, "%x %x %llx \n", cpu_mask, msr, value);
    7.34 -    fclose(fd);
    7.35 -}
    7.36 -
    7.37 -static inline unsigned long long perfcntr_rdmsr( int cpu_mask, int msr )
    7.38 -{
    7.39 -    fprintf(stderr, "WARNING: rdmsr not yet implemented for perfcntr.\n");
    7.40 -    return 0;
    7.41 -}
    7.42 -
    7.43 -// End of $RCSfile: cpuperf_perfcntr.h,v $
    7.44 -
     8.1 --- a/tools/misc/cpuperf/cpuperf_xeno.h	Wed Aug 23 14:43:48 2006 +0100
     8.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.3 @@ -1,38 +0,0 @@
     8.4 -/*
     8.5 - * Interface to Xen MSR hypercalls.
     8.6 - * 
     8.7 - * $Id: cpuperf_xeno.h,v 1.1 2003/10/13 16:49:44 jrb44 Exp $
     8.8 - * 
     8.9 - * $Log: cpuperf_xeno.h,v $
    8.10 - * Revision 1.1  2003/10/13 16:49:44  jrb44
    8.11 - * Initial revision
    8.12 - *
    8.13 - */
    8.14 -
    8.15 -#include <xenctrl.h>
    8.16 -
    8.17 -static int xc_handle;
    8.18 -
    8.19 -void xen_init(void)
    8.20 -{
    8.21 -    if ( (xc_handle = xc_interface_open()) == -1 )
    8.22 -    {
    8.23 -        fprintf(stderr, "Error opening xc interface: %d (%s)\n",
    8.24 -                errno, strerror(errno));
    8.25 -        exit(-1);
    8.26 -    }
    8.27 -
    8.28 -}
    8.29 -
    8.30 -void dom0_wrmsr(int cpu_mask, int msr, unsigned int low, unsigned int high)
    8.31 -{
    8.32 -    xc_msr_write (xc_handle, cpu_mask, msr, low, high);
    8.33 -}
    8.34 -
    8.35 -unsigned long long dom0_rdmsr(int cpu_mask, int msr)
    8.36 -{
    8.37 -    return xc_msr_read(xc_handle, cpu_mask, msr);
    8.38 -}
    8.39 -
    8.40 -// End of $RCSfile: cpuperf_xeno.h,v $
    8.41 -
     9.1 --- a/tools/misc/cpuperf/module/Makefile	Wed Aug 23 14:43:48 2006 +0100
     9.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.3 @@ -1,16 +0,0 @@
     9.4 -#############################################################################
     9.5 -# (C) 2005 - Rolf Neugebauer - Intel Research Cambridge
     9.6 -#############################################################################
     9.7 -#
     9.8 -#        File: Makefile
     9.9 -#      Author: Rolf Neugebauer (rolf.neugebauer@intel.com)
    9.10 -#        Date: Mar 2005
    9.11 -# 
    9.12 -# Environment: 
    9.13 -#
    9.14 -
    9.15 -# invoke:
    9.16 -# make -C /lib/modules/`uname -r`/build SUBDIRS=`pwd` modules_install
    9.17 -
    9.18 -obj-m    := perfcntr.o
    9.19 -
    10.1 --- a/tools/misc/cpuperf/module/perfcntr.c	Wed Aug 23 14:43:48 2006 +0100
    10.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.3 @@ -1,730 +0,0 @@
    10.4 -/*
    10.5 - * Linux loadable kernel module to use P4 performance counters.
    10.6 - *
    10.7 - * James Bulpin, Feb 2003.
    10.8 - *
    10.9 - * $Id$
   10.10 - *
   10.11 - * $Log$
   10.12 - */
   10.13 -
   10.14 -#define DRV_NAME        "perfcntr"
   10.15 -#define DRV_VERSION     "0.2"
   10.16 -#define DRV_RELDATE     "02 Jun 2004"
   10.17 -
   10.18 -
   10.19 -#include <linux/module.h>
   10.20 -#include <linux/kernel.h>
   10.21 -#include <linux/init.h>
   10.22 -#include <linux/types.h>
   10.23 -#include <linux/proc_fs.h>
   10.24 -#include <linux/seq_file.h>
   10.25 -
   10.26 -#include <asm/uaccess.h>
   10.27 -#include <asm/pgtable.h>
   10.28 -#include <asm/io.h>
   10.29 -#include <asm/processor.h>
   10.30 -
   10.31 -#define NOHT
   10.32 -
   10.33 -#include "../p4perf.h"
   10.34 -
   10.35 -#ifdef NOHT
   10.36 -# define CPUMASK 0x00000003
   10.37 -#else
   10.38 -# define CPUMASK 0x00000005
   10.39 -#endif
   10.40 -
   10.41 -/*****************************************************************************
   10.42 - * Module admin                                                              *
   10.43 - *****************************************************************************/
   10.44 -
   10.45 -MODULE_AUTHOR("James Bulpin <James.Bulpin@cl.cam.ac.uk>");
   10.46 -MODULE_DESCRIPTION("P4 Performance Counters access "
   10.47 -                   DRV_VERSION " " DRV_RELDATE);
   10.48 -MODULE_LICENSE("GPL");
   10.49 -
   10.50 -static char version[] __devinitdata =
   10.51 -DRV_NAME ": James Bulpin.\n";
   10.52 -
   10.53 -static unsigned char foobar[4];
   10.54 -
   10.55 -/* rpcc: get full 64-bit Pentium TSC value
   10.56 - */
   10.57 -static __inline__ unsigned long long int rpcc(void) 
   10.58 -{
   10.59 -    unsigned int __h, __l;
   10.60 -    __asm__ __volatile__ ("rdtsc" :"=a" (__l), "=d" (__h));
   10.61 -    return (((unsigned long long)__h) << 32) + __l;
   10.62 -}
   10.63 -
   10.64 -/*****************************************************************************
   10.65 - * Display the counters                                                      *
   10.66 - *****************************************************************************/
   10.67 -
   10.68 -//#define processor cpu // post 2.4.16
   10.69 -
   10.70 -typedef union {
   10.71 -    struct {
   10.72 -        unsigned long lo;
   10.73 -        unsigned long hi;
   10.74 -    };
   10.75 -    unsigned long long cnt;
   10.76 -} cpu_perfcntr_t;
   10.77 -
   10.78 -typedef struct counters_t_struct {
   10.79 -    int                processor;
   10.80 -    unsigned long long tsc;
   10.81 -    cpu_perfcntr_t     counters[18];
   10.82 -} counters_t;
   10.83 -
   10.84 -typedef struct perfcntr_t_struct {
   10.85 -    unsigned long cpu_mask;
   10.86 -    counters_t    cpus[4]; // Actually for each cpu in system
   10.87 -} perfcntr_t;
   10.88 -
   10.89 -#ifdef HUMAN_READABLE
   10.90 -# define SHOW_COUNTER(c) rdmsr (c, l, h);\
   10.91 -    seq_printf(m, "0x%03x: 0x%08x%08x\n", c, h, l)
   10.92 -#else
   10.93 -# define SHOW_COUNTER(c) rdmsr (c, l, h);\
   10.94 -    seq_printf(m, " %llu", \
   10.95 -               (unsigned long long)h << 32 | (unsigned long long)l)
   10.96 -#endif
   10.97 -
   10.98 -#if 0
   10.99 -static unsigned long last_l = 0, last_h = 0, last_msr = 0;
  10.100 -static int last_cpu = 0;
  10.101 -#endif
  10.102 -
  10.103 -#define READ_COUNTER(_i, _msr) rdmsr((_msr), l, h); c->counters[_i].lo = l; \
  10.104 -    c->counters[_i].hi = h;
  10.105 -
  10.106 -static perfcntr_t perfcntrs;
  10.107 -
  10.108 -static void show_perfcntr_for(void *v)
  10.109 -{
  10.110 -    unsigned int l, h;
  10.111 -
  10.112 -    perfcntr_t *p = &perfcntrs;
  10.113 -    counters_t *c;
  10.114 -
  10.115 -    if (!((1 << smp_processor_id()) & p->cpu_mask))
  10.116 -        return;
  10.117 -
  10.118 -    c = &p->cpus[smp_processor_id()];
  10.119 -
  10.120 -    c->processor = smp_processor_id();
  10.121 -    c->tsc = rpcc();
  10.122 -
  10.123 -    READ_COUNTER(0,  MSR_P4_BPU_COUNTER0);
  10.124 -    READ_COUNTER(1,  MSR_P4_BPU_COUNTER1);
  10.125 -    READ_COUNTER(2,  MSR_P4_BPU_COUNTER2);
  10.126 -    READ_COUNTER(3,  MSR_P4_BPU_COUNTER3);
  10.127 -
  10.128 -    READ_COUNTER(4,  MSR_P4_MS_COUNTER0);
  10.129 -    READ_COUNTER(5,  MSR_P4_MS_COUNTER1);
  10.130 -    READ_COUNTER(6,  MSR_P4_MS_COUNTER2);
  10.131 -    READ_COUNTER(7,  MSR_P4_MS_COUNTER3);
  10.132 -
  10.133 -    READ_COUNTER(8,  MSR_P4_FLAME_COUNTER0);
  10.134 -    READ_COUNTER(9,  MSR_P4_FLAME_COUNTER1);
  10.135 -    READ_COUNTER(10, MSR_P4_FLAME_COUNTER2);
  10.136 -    READ_COUNTER(11, MSR_P4_FLAME_COUNTER3);
  10.137 -
  10.138 -    READ_COUNTER(12, MSR_P4_IQ_COUNTER0);
  10.139 -    READ_COUNTER(13, MSR_P4_IQ_COUNTER1);
  10.140 -    READ_COUNTER(14, MSR_P4_IQ_COUNTER2);
  10.141 -    READ_COUNTER(15, MSR_P4_IQ_COUNTER3);
  10.142 -    READ_COUNTER(16, MSR_P4_IQ_COUNTER4);
  10.143 -    READ_COUNTER(17, MSR_P4_IQ_COUNTER5);
  10.144 -
  10.145 -    return;    
  10.146 -}
  10.147 -
  10.148 -static int show_perfcntr(struct seq_file *m, void *v)
  10.149 -{
  10.150 -    int i, j;
  10.151 -
  10.152 -    // Get each physical cpu to read counters
  10.153 -    perfcntrs.cpu_mask = CPUMASK;
  10.154 -
  10.155 -    smp_call_function(show_perfcntr_for, NULL, 1, 1);
  10.156 -    show_perfcntr_for(NULL);
  10.157 -
  10.158 -    for (i = 0; i < 32; i++) {
  10.159 -        if (((1 << i) & (perfcntrs.cpu_mask = CPUMASK))) {
  10.160 -            counters_t *c = &perfcntrs.cpus[i];
  10.161 -            seq_printf(m, "%u %llu", c->processor, c->tsc);
  10.162 -            for (j = 0; j < 18; j++) {
  10.163 -                seq_printf(m, " %llu", c->counters[j].cnt);
  10.164 -            }
  10.165 -            seq_printf(m, "\n");
  10.166 -        }
  10.167 -    }
  10.168 -
  10.169 -#if 0
  10.170 -    unsigned long long t;
  10.171 -    unsigned int l, h;
  10.172 -
  10.173 -    t = rpcc();
  10.174 -
  10.175 -
  10.176 -
  10.177 -#ifdef HUMAN_READABLE
  10.178 -    seq_printf(m,
  10.179 -               "show_perfcntr\nprocessor: %u\ntime: %llu\n"
  10.180 -               "last write: 0x%08lx%08lx -> 0x%lx (CPU%u)\n",
  10.181 -               smp_processor_id(),
  10.182 -               t,
  10.183 -               last_h,
  10.184 -               last_l,
  10.185 -               last_msr,
  10.186 -               last_cpu);
  10.187 -#else
  10.188 -    seq_printf(m, "%u %llu", smp_processor_id(), t);
  10.189 -#endif
  10.190 -
  10.191 -    SHOW_COUNTER(MSR_P4_BPU_COUNTER0);
  10.192 -    SHOW_COUNTER(MSR_P4_BPU_COUNTER1);
  10.193 -    SHOW_COUNTER(MSR_P4_BPU_COUNTER2);
  10.194 -    SHOW_COUNTER(MSR_P4_BPU_COUNTER3);
  10.195 -
  10.196 -    SHOW_COUNTER(MSR_P4_MS_COUNTER0);
  10.197 -    SHOW_COUNTER(MSR_P4_MS_COUNTER1);
  10.198 -    SHOW_COUNTER(MSR_P4_MS_COUNTER2);
  10.199 -    SHOW_COUNTER(MSR_P4_MS_COUNTER3);
  10.200 -
  10.201 -    SHOW_COUNTER(MSR_P4_FLAME_COUNTER0);
  10.202 -    SHOW_COUNTER(MSR_P4_FLAME_COUNTER1);
  10.203 -    SHOW_COUNTER(MSR_P4_FLAME_COUNTER2);
  10.204 -    SHOW_COUNTER(MSR_P4_FLAME_COUNTER3);
  10.205 -
  10.206 -    SHOW_COUNTER(MSR_P4_IQ_COUNTER0);
  10.207 -    SHOW_COUNTER(MSR_P4_IQ_COUNTER1);
  10.208 -    SHOW_COUNTER(MSR_P4_IQ_COUNTER2);
  10.209 -    SHOW_COUNTER(MSR_P4_IQ_COUNTER3);
  10.210 -    SHOW_COUNTER(MSR_P4_IQ_COUNTER4);
  10.211 -    SHOW_COUNTER(MSR_P4_IQ_COUNTER5);
  10.212 -
  10.213 -#ifndef HUMAN_READBLE
  10.214 -    seq_printf(m, "\n");
  10.215 -#endif
  10.216 -
  10.217 -#endif
  10.218 -
  10.219 -    return 0;
  10.220 -}
  10.221 -
  10.222 -/*****************************************************************************
  10.223 - * Show counter configuration                                                *
  10.224 - *****************************************************************************/
  10.225 -
  10.226 -typedef union {
  10.227 -    struct {
  10.228 -        unsigned long lo;
  10.229 -        unsigned long hi;
  10.230 -    };
  10.231 -    unsigned long long cnt;
  10.232 -} cpu_perfcfg_t;
  10.233 -
  10.234 -typedef struct configs_t_struct {
  10.235 -    int                processor;
  10.236 -    unsigned long long tsc;
  10.237 -    cpu_perfcfg_t      cccr[18];
  10.238 -    cpu_perfcfg_t      escr[0x42];
  10.239 -} configs_t;
  10.240 -
  10.241 -typedef struct perfcfg_t_struct {
  10.242 -    unsigned long cpu_mask;
  10.243 -    configs_t     cpus[4]; // Actually for each cpu in system
  10.244 -} perfcfg_t;
  10.245 -
  10.246 -static perfcfg_t perfcfgs;
  10.247 -
  10.248 -#define READ_CCCR(_i, _msr) rdmsr((_msr), l, h); c->cccr[_i].lo = l; \
  10.249 -    c->cccr[_i].hi = h;
  10.250 -#define READ_ESCR(_i, _msr) rdmsr((_msr), l, h); c->escr[_i].lo = l; \
  10.251 -    c->escr[_i].hi = h;
  10.252 -
  10.253 -static void show_perfcfg_for(void *v)
  10.254 -{
  10.255 -    unsigned int l, h;
  10.256 -
  10.257 -    perfcfg_t *p = &perfcfgs;
  10.258 -    configs_t *c;
  10.259 -
  10.260 -    if (!((1 << smp_processor_id()) & p->cpu_mask))
  10.261 -        return;
  10.262 -
  10.263 -    c = &p->cpus[smp_processor_id()];
  10.264 -
  10.265 -    c->processor = smp_processor_id();
  10.266 -    c->tsc = rpcc();
  10.267 -
  10.268 -    READ_CCCR(0,  MSR_P4_BPU_CCCR0);
  10.269 -    READ_CCCR(1,  MSR_P4_BPU_CCCR1);
  10.270 -    READ_CCCR(2,  MSR_P4_BPU_CCCR2);
  10.271 -    READ_CCCR(3,  MSR_P4_BPU_CCCR3);
  10.272 -
  10.273 -    READ_CCCR(4,  MSR_P4_MS_CCCR0);
  10.274 -    READ_CCCR(5,  MSR_P4_MS_CCCR1);
  10.275 -    READ_CCCR(6,  MSR_P4_MS_CCCR2);
  10.276 -    READ_CCCR(7,  MSR_P4_MS_CCCR3);
  10.277 -
  10.278 -    READ_CCCR(8,  MSR_P4_FLAME_CCCR0);
  10.279 -    READ_CCCR(9,  MSR_P4_FLAME_CCCR1);
  10.280 -    READ_CCCR(10, MSR_P4_FLAME_CCCR2);
  10.281 -    READ_CCCR(11, MSR_P4_FLAME_CCCR3);
  10.282 -
  10.283 -    READ_CCCR(12, MSR_P4_IQ_CCCR0);
  10.284 -    READ_CCCR(13, MSR_P4_IQ_CCCR1);
  10.285 -    READ_CCCR(14, MSR_P4_IQ_CCCR2);
  10.286 -    READ_CCCR(15, MSR_P4_IQ_CCCR3);
  10.287 -    READ_CCCR(16, MSR_P4_IQ_CCCR4);
  10.288 -    READ_CCCR(17, MSR_P4_IQ_CCCR5);
  10.289 -
  10.290 -    READ_ESCR(0x00, MSR_P4_BSU_ESCR0);
  10.291 -    READ_ESCR(0x02, MSR_P4_FSB_ESCR0);
  10.292 -    READ_ESCR(0x0a, MSR_P4_MOB_ESCR0);
  10.293 -    READ_ESCR(0x0c, MSR_P4_PMH_ESCR0);
  10.294 -    READ_ESCR(0x12, MSR_P4_BPU_ESCR0);
  10.295 -    READ_ESCR(0x14, MSR_P4_IS_ESCR0);
  10.296 -    READ_ESCR(0x16, MSR_P4_ITLB_ESCR0);
  10.297 -    READ_ESCR(0x28, MSR_P4_IX_ESCR0);
  10.298 -    READ_ESCR(0x01, MSR_P4_BSU_ESCR1);
  10.299 -    READ_ESCR(0x03, MSR_P4_FSB_ESCR1);
  10.300 -    READ_ESCR(0x0b, MSR_P4_MOB_ESCR1);
  10.301 -    READ_ESCR(0x0d, MSR_P4_PMH_ESCR1);
  10.302 -    READ_ESCR(0x13, MSR_P4_BPU_ESCR1);
  10.303 -    READ_ESCR(0x15, MSR_P4_IS_ESCR1);
  10.304 -    READ_ESCR(0x17, MSR_P4_ITLB_ESCR1);
  10.305 -    READ_ESCR(0x29, MSR_P4_IX_ESCR1);
  10.306 -    READ_ESCR(0x20, MSR_P4_MS_ESCR0);
  10.307 -    READ_ESCR(0x22, MSR_P4_TBPU_ESCR0);
  10.308 -    READ_ESCR(0x24, MSR_P4_TC_ESCR0);
  10.309 -    READ_ESCR(0x21, MSR_P4_MS_ESCR1);
  10.310 -    READ_ESCR(0x23, MSR_P4_TBPU_ESCR1);
  10.311 -    READ_ESCR(0x25, MSR_P4_TC_ESCR1);
  10.312 -    READ_ESCR(0x04, MSR_P4_FIRM_ESCR0);
  10.313 -    READ_ESCR(0x06, MSR_P4_FLAME_ESCR0);
  10.314 -    READ_ESCR(0x08, MSR_P4_DAC_ESCR0);
  10.315 -    READ_ESCR(0x0e, MSR_P4_SAAT_ESCR0);
  10.316 -    READ_ESCR(0x10, MSR_P4_U2L_ESCR0);
  10.317 -    READ_ESCR(0x05, MSR_P4_FIRM_ESCR1);
  10.318 -    READ_ESCR(0x07, MSR_P4_FLAME_ESCR1);
  10.319 -    READ_ESCR(0x09, MSR_P4_DAC_ESCR1);
  10.320 -    READ_ESCR(0x0f, MSR_P4_SAAT_ESCR1);
  10.321 -    READ_ESCR(0x11, MSR_P4_U2L_ESCR1);
  10.322 -    READ_ESCR(0x18, MSR_P4_CRU_ESCR0);
  10.323 -    READ_ESCR(0x2c, MSR_P4_CRU_ESCR2);
  10.324 -    READ_ESCR(0x40, MSR_P4_CRU_ESCR4);
  10.325 -    READ_ESCR(0x1a, MSR_P4_IQ_ESCR0);
  10.326 -    READ_ESCR(0x1c, MSR_P4_RAT_ESCR0);
  10.327 -    READ_ESCR(0x1e, MSR_P4_SSU_ESCR0);
  10.328 -    READ_ESCR(0x2a, MSR_P4_ALF_ESCR0);
  10.329 -    READ_ESCR(0x19, MSR_P4_CRU_ESCR1);
  10.330 -    READ_ESCR(0x2d, MSR_P4_CRU_ESCR3);
  10.331 -    READ_ESCR(0x41, MSR_P4_CRU_ESCR5);
  10.332 -    READ_ESCR(0x1b, MSR_P4_IQ_ESCR1);
  10.333 -    READ_ESCR(0x1d, MSR_P4_RAT_ESCR1);
  10.334 -    READ_ESCR(0x2b, MSR_P4_ALF_ESCR1);
  10.335 -
  10.336 -    return;    
  10.337 -}
  10.338 -
  10.339 -static char *escr_names[] = {
  10.340 -    "BSU_ESCR0",
  10.341 -    "BSU_ESCR1",
  10.342 -    "FSB_ESCR0",
  10.343 -    "FSB_ESCR1",
  10.344 -    "FIRM_ESCR0",
  10.345 -    "FIRM_ESCR1",
  10.346 -    "FLAME_ESCR0",
  10.347 -    "FLAME_ESCR1",
  10.348 -    "DAC_ESCR0",
  10.349 -    "DAC_ESCR1",
  10.350 -    "MOB_ESCR0",
  10.351 -    "MOB_ESCR1",
  10.352 -    "PMH_ESCR0",
  10.353 -    "PMH_ESCR1",
  10.354 -    "SAAT_ESCR0",
  10.355 -    "SAAT_ESCR1",
  10.356 -    "U2L_ESCR0",
  10.357 -    "U2L_ESCR1",
  10.358 -    "BPU_ESCR0",
  10.359 -    "BPU_ESCR1",
  10.360 -    "IS_ESCR0",
  10.361 -    "IS_ESCR1",
  10.362 -    "ITLB_ESCR0",
  10.363 -    "ITLB_ESCR1",
  10.364 -    "CRU_ESCR0",
  10.365 -    "CRU_ESCR1",
  10.366 -    "IQ_ESCR0",
  10.367 -    "IQ_ESCR1",
  10.368 -    "RAT_ESCR0",
  10.369 -    "RAT_ESCR1",
  10.370 -    "SSU_ESCR0",
  10.371 -    "SSU_ESCR1",
  10.372 -    "MS_ESCR0",
  10.373 -    "MS_ESCR1",
  10.374 -    "TBPU_ESCR0",
  10.375 -    "TBPU_ESCR1",
  10.376 -    "TC_ESCR0",
  10.377 -    "TC_ESCR1",
  10.378 -    "0x3c6",
  10.379 -    "0x3c7",
  10.380 -    "IX_ESCR0",
  10.381 -    "IX_ESCR1",
  10.382 -    "ALF_ESCR0",
  10.383 -    "ALF_ESCR1",
  10.384 -    "CRU_ESCR2",
  10.385 -    "CRU_ESCR3",
  10.386 -    "0x3ce",
  10.387 -    "0x3cf",
  10.388 -    "0x3d0",
  10.389 -    "0x3d1",
  10.390 -    "0x3d2",
  10.391 -    "0x3d3",
  10.392 -    "0x3d4",
  10.393 -    "0x3d5",
  10.394 -    "0x3d6",
  10.395 -    "0x3d7",
  10.396 -    "0x3d8",
  10.397 -    "0x3d9",
  10.398 -    "0x3da",
  10.399 -    "0x3db",
  10.400 -    "0x3dc",
  10.401 -    "0x3dd",
  10.402 -    "0x3de",
  10.403 -    "0x3df",
  10.404 -    "CRU_ESCR4",
  10.405 -    "CRU_ESCR5"
  10.406 -};
  10.407 -
  10.408 -static unsigned long escr_map_0[] = 
  10.409 -{MSR_P4_BPU_ESCR0, MSR_P4_IS_ESCR0,
  10.410 - MSR_P4_MOB_ESCR0, MSR_P4_ITLB_ESCR0,
  10.411 - MSR_P4_PMH_ESCR0, MSR_P4_IX_ESCR0,
  10.412 - MSR_P4_FSB_ESCR0, MSR_P4_BSU_ESCR0}; //BPU even
  10.413 -static unsigned long escr_map_1[] = 
  10.414 -    {MSR_P4_BPU_ESCR1, MSR_P4_IS_ESCR1,
  10.415 -     MSR_P4_MOB_ESCR1, MSR_P4_ITLB_ESCR1,
  10.416 -     MSR_P4_PMH_ESCR1, MSR_P4_IX_ESCR1,
  10.417 -     MSR_P4_FSB_ESCR1, MSR_P4_BSU_ESCR1}; //BPU odd
  10.418 -static unsigned long escr_map_2[] = 
  10.419 -    {MSR_P4_MS_ESCR0, MSR_P4_TC_ESCR0, MSR_P4_TBPU_ESCR0,
  10.420 -     0, 0, 0, 0, 0}; //MS even
  10.421 -static unsigned long escr_map_3[] = 
  10.422 -    {MSR_P4_MS_ESCR1, MSR_P4_TC_ESCR1, MSR_P4_TBPU_ESCR1,
  10.423 -     0, 0, 0, 0, 0}; //MS odd
  10.424 -static unsigned long escr_map_4[] = 
  10.425 -    {MSR_P4_FLAME_ESCR0, MSR_P4_FIRM_ESCR0, MSR_P4_SAAT_ESCR0,
  10.426 -     MSR_P4_U2L_ESCR0, 0, MSR_P4_DAC_ESCR0, 0, 0}; //FLAME even
  10.427 -static unsigned long escr_map_5[] = 
  10.428 -    {MSR_P4_FLAME_ESCR1, MSR_P4_FIRM_ESCR1, MSR_P4_SAAT_ESCR1,
  10.429 -     MSR_P4_U2L_ESCR1, 0, MSR_P4_DAC_ESCR1, 0, 0}; //FLAME odd
  10.430 -static unsigned long escr_map_6[] = 
  10.431 -    {MSR_P4_IQ_ESCR0, MSR_P4_ALF_ESCR0,
  10.432 -     MSR_P4_RAT_ESCR0, MSR_P4_SSU_ESCR0,
  10.433 -     MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR4, 0}; //IQ even
  10.434 -static unsigned long escr_map_7[] = 
  10.435 -    {MSR_P4_IQ_ESCR1, MSR_P4_ALF_ESCR1,
  10.436 -     MSR_P4_RAT_ESCR1, 0,
  10.437 -     MSR_P4_CRU_ESCR1, MSR_P4_CRU_ESCR3, MSR_P4_CRU_ESCR5, 0}; //IQ odd
  10.438 -
  10.439 -static unsigned long *escr_map[] = {
  10.440 -    escr_map_0,
  10.441 -    escr_map_1,
  10.442 -    escr_map_2,
  10.443 -    escr_map_3,
  10.444 -    escr_map_4,
  10.445 -    escr_map_5,
  10.446 -    escr_map_6,
  10.447 -    escr_map_7,
  10.448 -};
  10.449 -
  10.450 -unsigned long get_escr_msr(int c, int e)
  10.451 -{
  10.452 -    int index = -1;
  10.453 -
  10.454 -    // Get the ESCR MSR address from the counter number and the ESCR number.
  10.455 -    switch (c) {
  10.456 -    case P4_BPU_COUNTER0_NUMBER:
  10.457 -    case P4_BPU_COUNTER1_NUMBER:
  10.458 -	index = 0;
  10.459 -	break;
  10.460 -    case P4_BPU_COUNTER2_NUMBER:
  10.461 -    case P4_BPU_COUNTER3_NUMBER:	
  10.462 -	index = 1;
  10.463 -	break;
  10.464 -    case P4_MS_COUNTER0_NUMBER:
  10.465 -    case P4_MS_COUNTER1_NUMBER:
  10.466 -	index = 2; // probably !
  10.467 -	break;
  10.468 -    case P4_MS_COUNTER2_NUMBER:
  10.469 -    case P4_MS_COUNTER3_NUMBER:
  10.470 -	index = 3; // probably !
  10.471 -	break;
  10.472 -    case P4_FLAME_COUNTER0_NUMBER:
  10.473 -    case P4_FLAME_COUNTER1_NUMBER:
  10.474 -	index = 4; // probably !
  10.475 -	break;
  10.476 -    case P4_FLAME_COUNTER2_NUMBER:
  10.477 -    case P4_FLAME_COUNTER3_NUMBER:
  10.478 -	index = 5; // probably !
  10.479 -	break;
  10.480 -    case P4_IQ_COUNTER0_NUMBER:
  10.481 -    case P4_IQ_COUNTER1_NUMBER:
  10.482 -    case P4_IQ_COUNTER4_NUMBER:
  10.483 -	index = 6;
  10.484 -	break;
  10.485 -    case P4_IQ_COUNTER2_NUMBER:
  10.486 -    case P4_IQ_COUNTER3_NUMBER:
  10.487 -    case P4_IQ_COUNTER5_NUMBER:
  10.488 -	index = 7;
  10.489 -	break;
  10.490 -    }
  10.491 -
  10.492 -    if (index != -1) {
  10.493 -	return escr_map[index][e];
  10.494 -    }
  10.495 -
  10.496 -    return 0;
  10.497 -}
  10.498 -
  10.499 -static char null_string[] = "";
  10.500 -static char *get_escr(int c, int e)
  10.501 -{
  10.502 -    unsigned long msr = get_escr_msr(c, e);
  10.503 -
  10.504 -    if ((msr >= 0x3a0) && (msr <= 0x3e1))
  10.505 -	return escr_names[(int)(msr - 0x3a0)];
  10.506 -    return null_string;
  10.507 -}
  10.508 -
  10.509 -static int show_perfcfg(struct seq_file *m, void *v)
  10.510 -{
  10.511 -    int i, j;
  10.512 -
  10.513 -    // Get each physical cpu to read configs
  10.514 -    perfcfgs.cpu_mask = CPUMASK;
  10.515 -
  10.516 -    smp_call_function(show_perfcfg_for, NULL, 1, 1);
  10.517 -    show_perfcfg_for(NULL);
  10.518 -
  10.519 -    for (i = 0; i < 32; i++) {
  10.520 -        if (((1 << i) & (perfcfgs.cpu_mask = CPUMASK))) {
  10.521 -            configs_t *c = &perfcfgs.cpus[i];
  10.522 -            seq_printf(m, "----------------------------------------\n");
  10.523 -            seq_printf(m, "%u %llu\n", c->processor, c->tsc);
  10.524 -            for (j = 0; j < 18; j++) {
  10.525 -                seq_printf(m, "%08lx", c->cccr[j].lo);
  10.526 -
  10.527 -		if (!(c->cccr[j].lo & P4_CCCR_ENABLE))
  10.528 -		    seq_printf(m, " DISABLED");
  10.529 -		else {
  10.530 -		    unsigned long escr_msr =
  10.531 -			get_escr_msr(i, (int)((c->cccr[j].lo >> 13)&7));
  10.532 -		    seq_printf(m, " ESCR=%s",
  10.533 -			       get_escr(i, (int)((c->cccr[j].lo >> 13)&7)));
  10.534 -		    if ((escr_msr >= 0x3a0) && (escr_msr <= 0x3e1)) {
  10.535 -			unsigned long e = c->escr[(int)(escr_msr - 0x3a0)].lo;
  10.536 -			seq_printf(m, "(%08lx es=%lx mask=%lx", e,
  10.537 -				   (e >> 25) & 0x7f,
  10.538 -				   (e >> 9) & 0xffff);
  10.539 -			if ((e & P4_ESCR_T0_USR))
  10.540 -			    seq_printf(m, " T(0)USR");
  10.541 -			if ((e & P4_ESCR_T0_OS))
  10.542 -			    seq_printf(m, " T(0)OS");
  10.543 -			if ((e & P4_ESCR_T1_USR))
  10.544 -			    seq_printf(m, " T1USR");
  10.545 -			if ((e & P4_ESCR_T1_OS))
  10.546 -			    seq_printf(m, " T1OS");
  10.547 -			seq_printf(m, ")");
  10.548 -		    }
  10.549 -		    seq_printf(m, " AT=%u", (int)((c->cccr[j].lo >> 16)&3));
  10.550 -
  10.551 -		    if ((c->cccr[j].lo & P4_CCCR_OVF))
  10.552 -			seq_printf(m, " OVF");
  10.553 -		    if ((c->cccr[j].lo & P4_CCCR_CASCADE))
  10.554 -			seq_printf(m, " CASC");
  10.555 -		    if ((c->cccr[j].lo & P4_CCCR_FORCE_OVF))
  10.556 -			seq_printf(m, " F-OVF");
  10.557 -		    if ((c->cccr[j].lo & P4_CCCR_EDGE))
  10.558 -			seq_printf(m, " EDGE");
  10.559 -		    if ((c->cccr[j].lo & P4_CCCR_COMPLEMENT))
  10.560 -			seq_printf(m, " COMPL");
  10.561 -		    if ((c->cccr[j].lo & P4_CCCR_COMPARE))
  10.562 -			seq_printf(m, " CMP");
  10.563 -		    if ((c->cccr[j].lo & P4_CCCR_OVF_PMI_T0))
  10.564 -			seq_printf(m, " OVF_PMI(_T0)");
  10.565 -		    if ((c->cccr[j].lo & P4_CCCR_OVF_PMI_T1))
  10.566 -			seq_printf(m, " OVF_PMI_T1");
  10.567 -		}
  10.568 -		seq_printf(m, "\n");
  10.569 -            }
  10.570 -        }
  10.571 -    }
  10.572 -
  10.573 -    return 0;
  10.574 -}
  10.575 -
  10.576 -/*****************************************************************************
  10.577 - * Handle writes                                                             *
  10.578 - *****************************************************************************/
  10.579 -
  10.580 -static int set_msr_cpu_mask;
  10.581 -static unsigned long set_msr_addr;
  10.582 -static unsigned long set_msr_lo;
  10.583 -static unsigned long set_msr_hi;
  10.584 -
  10.585 -static void perfcntr_write_for(void *unused)
  10.586 -{
  10.587 -#ifdef NOHT
  10.588 -    if (((1 << smp_processor_id()) & set_msr_cpu_mask)) {
  10.589 -#endif
  10.590 -        //printk("perfcntr: wrmsr(%08lx, %08lx, %08lx)\n",
  10.591 -        //     set_msr_addr, set_msr_lo, set_msr_hi);
  10.592 -        wrmsr(set_msr_addr, set_msr_lo, set_msr_hi);
  10.593 -#ifdef NOHT
  10.594 -    }
  10.595 -#endif
  10.596 -}
  10.597 -
  10.598 -ssize_t perfcntr_write(struct file *f,
  10.599 -                       const  char *data,
  10.600 -                       size_t       size,
  10.601 -                       loff_t      *pos)
  10.602 -{
  10.603 -    char         *endp;
  10.604 -    ssize_t       ret = 0;
  10.605 -    //unsigned long l, h, msr;
  10.606 -    unsigned long long v;
  10.607 -
  10.608 -    set_msr_cpu_mask = (int)simple_strtoul(data, &endp, 16);
  10.609 -    endp++; // skip past space
  10.610 -    if ((endp - data) >= size) {
  10.611 -        ret = -EINVAL;
  10.612 -        goto out;
  10.613 -    }
  10.614 -
  10.615 -    set_msr_addr = simple_strtoul(endp, &endp, 16);
  10.616 -    endp++; // skip past space
  10.617 -    if ((endp - data) >= size) {
  10.618 -        ret = -EINVAL;
  10.619 -        goto out;
  10.620 -    }
  10.621 -    
  10.622 -    v = simple_strtoul(endp, &endp, 16);
  10.623 -    set_msr_lo = (unsigned long)(v & 0xffffffffULL);
  10.624 -    set_msr_hi = (unsigned long)(v >> 32);
  10.625 -
  10.626 -    smp_call_function(perfcntr_write_for, NULL, 1, 1);
  10.627 -    perfcntr_write_for(NULL);    
  10.628 -
  10.629 -#if 0
  10.630 -    wrmsr(msr, l, h);
  10.631 -    last_l   = l;
  10.632 -    last_h   = h;
  10.633 -    last_msr = msr;
  10.634 -    last_cpu = smp_processor_id();
  10.635 -#endif
  10.636 -    ret = size;
  10.637 -
  10.638 - out:
  10.639 -    return ret;
  10.640 -}
  10.641 -
  10.642 -/*****************************************************************************
  10.643 - * /proc stuff                                                               *
  10.644 - *****************************************************************************/
  10.645 -
  10.646 -static void *c_start(struct seq_file *m, loff_t *pos)
  10.647 -{
  10.648 -    //return *pos < NR_CPUS ? cpu_data + *pos : NULL;
  10.649 -    return *pos == 0 ? foobar : NULL;
  10.650 -}
  10.651 -
  10.652 -static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  10.653 -{
  10.654 -    ++*pos;
  10.655 -    return c_start(m, pos);
  10.656 -}
  10.657 -
  10.658 -static void c_stop(struct seq_file *m, void *v)
  10.659 -{
  10.660 -}
  10.661 -
  10.662 -struct seq_operations perfcntr_op = {
  10.663 -    start:  c_start,
  10.664 -    next:   c_next,
  10.665 -    stop:   c_stop,
  10.666 -    show:   show_perfcntr,
  10.667 -};
  10.668 -
  10.669 -struct seq_operations perfcfg_op = {
  10.670 -    start:  c_start,
  10.671 -    next:   c_next,
  10.672 -    stop:   c_stop,
  10.673 -    show:   show_perfcfg,
  10.674 -};
  10.675 -
  10.676 -static int perfcntr_open(struct inode *inode, struct file *file)
  10.677 -{
  10.678 -    return seq_open(file, &perfcntr_op);
  10.679 -}
  10.680 -
  10.681 -static int perfcfg_open(struct inode *inode, struct file *file)
  10.682 -{
  10.683 -    return seq_open(file, &perfcfg_op);
  10.684 -}
  10.685 -
  10.686 -static struct file_operations proc_perfcntr_operations = {
  10.687 -    open:           perfcntr_open,
  10.688 -    read:           seq_read,
  10.689 -    write:          perfcntr_write,
  10.690 -    llseek:         seq_lseek,
  10.691 -    release:        seq_release,
  10.692 -};
  10.693 -
  10.694 -static struct file_operations proc_perfcfg_operations = {
  10.695 -    open:           perfcfg_open,
  10.696 -    read:           seq_read,
  10.697 -    write:          perfcntr_write,
  10.698 -    llseek:         seq_lseek,
  10.699 -    release:        seq_release,
  10.700 -};
  10.701 -
  10.702 -static void create_seq_entry(char *name, mode_t mode, struct file_operations *f)
  10.703 -{
  10.704 -    struct proc_dir_entry *entry;
  10.705 -    entry = create_proc_entry(name, mode, NULL);
  10.706 -    if (entry)
  10.707 -        entry->proc_fops = f;
  10.708 -}
  10.709 -
  10.710 -/*****************************************************************************
  10.711 - * Module init and cleanup                                                   *
  10.712 - *****************************************************************************/
  10.713 -
  10.714 -static int __init perfcntr_init(void)
  10.715 -{
  10.716 -    printk(version);
  10.717 -
  10.718 -    create_seq_entry("perfcntr", 0777, &proc_perfcntr_operations);
  10.719 -    create_seq_entry("perfcntr_config", 0777, &proc_perfcfg_operations);
  10.720 -
  10.721 -    return 0;
  10.722 -}
  10.723 -
  10.724 -static void __exit perfcntr_exit(void)
  10.725 -{
  10.726 -    remove_proc_entry("perfcntr", NULL);
  10.727 -    remove_proc_entry("perfcntr_config", NULL);
  10.728 -}
  10.729 -
  10.730 -module_init(perfcntr_init);
  10.731 -module_exit(perfcntr_exit);
  10.732 -
  10.733 -/* End of $RCSfile$ */
    11.1 --- a/tools/misc/cpuperf/p4perf.h	Wed Aug 23 14:43:48 2006 +0100
    11.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.3 @@ -1,382 +0,0 @@
    11.4 -/*
    11.5 - * P4 Performance counter stuff.
    11.6 - *
    11.7 - * P4 Xeon with Hyperthreading has counters per physical package which can
    11.8 - * count events from either logical CPU. However, in many cases more than
    11.9 - * ECSR and CCCR/counter can be used to count the same event. For instr or
   11.10 - * uops retired, use either ESCR0/IQ_CCCR0 ESCR1/IQ_CCCR2.
   11.11 - *
   11.12 - * $Id: p4perf.h,v 1.2 2003/10/13 16:51:41 jrb44 Exp $
   11.13 - *
   11.14 - * $Log: p4perf.h,v $
   11.15 - * Revision 1.2  2003/10/13 16:51:41  jrb44
   11.16 - * *** empty log message ***
   11.17 - *
   11.18 - */
   11.19 -
   11.20 -#ifndef P4PERF_H
   11.21 -#define P4PERF_H
   11.22 -
   11.23 -#ifdef __KERNEL__
   11.24 -#include <asm/msr.h>
   11.25 -#endif
   11.26 -
   11.27 -/*****************************************************************************
   11.28 - * Performance counter configuration.                                        *
   11.29 - *****************************************************************************/
   11.30 -
   11.31 -#ifndef P6_EVNTSEL_OS
   11.32 -# define P6_EVNTSEL_OS     (1 << 17)
   11.33 -# define P6_EVNTSEL_USR    (1 << 16)
   11.34 -# define P6_EVNTSEL_E      (1 << 18)
   11.35 -# define P6_EVNTSEL_EN     (1 << 22)
   11.36 -#endif
   11.37 -#define P6_PERF_INST_RETIRED 0xc0
   11.38 -#define P6_PERF_UOPS_RETIRED 0xc2
   11.39 -
   11.40 -#define P4_ESCR_USR                    (1 << 2)
   11.41 -#define P4_ESCR_OS                     (1 << 3)
   11.42 -#define P4_ESCR_T0_USR                 (1 << 2) /* First logical CPU  */
   11.43 -#define P4_ESCR_T0_OS                  (1 << 3)
   11.44 -#define P4_ESCR_T1_USR                 (1 << 0) /* Second logical CPU */
   11.45 -#define P4_ESCR_T1_OS                  (1 << 1)
   11.46 -#define P4_ESCR_TE                     (1 << 4)
   11.47 -#define P4_ESCR_THREADS(t)             (t)
   11.48 -#define P4_ESCR_TV(tag)                (tag << 5)
   11.49 -#define P4_ESCR_EVNTSEL(e)             (e << 25)
   11.50 -#define P4_ESCR_EVNTMASK(e)            (e << 9)
   11.51 -
   11.52 -#define P4_ESCR_EVNTSEL_FRONT_END      0x08
   11.53 -#define P4_ESCR_EVNTSEL_EXECUTION      0x0c
   11.54 -#define P4_ESCR_EVNTSEL_REPLAY         0x09
   11.55 -#define P4_ESCR_EVNTSEL_INSTR_RETIRED  0x02
   11.56 -#define P4_ESCR_EVNTSEL_UOPS_RETIRED   0x01
   11.57 -#define P4_ESCR_EVNTSEL_UOP_TYPE       0x02
   11.58 -#define P4_ESCR_EVNTSEL_RET_MBR_TYPE   0x05
   11.59 -//#define P4_ESCR_EVNTSEL_RET_MBR_TYPE   0x04
   11.60 -
   11.61 -#define P4_ESCR_EVNTMASK_FE_NBOGUS     0x01
   11.62 -#define P4_ESCR_EVNTMASK_FE_BOGUS      0x02
   11.63 -
   11.64 -#define P4_ESCR_EVNTMASK_EXEC_NBOGUS0  0x01
   11.65 -#define P4_ESCR_EVNTMASK_EXEC_NBOGUS1  0x02
   11.66 -#define P4_ESCR_EVNTMASK_EXEC_NBOGUS2  0x04
   11.67 -#define P4_ESCR_EVNTMASK_EXEC_NBOGUS3  0x08
   11.68 -#define P4_ESCR_EVNTMASK_EXEC_BOGUS0   0x10
   11.69 -#define P4_ESCR_EVNTMASK_EXEC_BOGUS1   0x20
   11.70 -#define P4_ESCR_EVNTMASK_EXEC_BOGUS2   0x40
   11.71 -#define P4_ESCR_EVNTMASK_EXEC_BOGUS3   0x80
   11.72 -
   11.73 -#define P4_ESCR_EVNTMASK_REPLAY_NBOGUS 0x01
   11.74 -#define P4_ESCR_EVNTMASK_REPLAY_BOGUS  0x02
   11.75 -
   11.76 -#define P4_ESCR_EVNTMASK_IRET_NB_NTAG  0x01
   11.77 -#define P4_ESCR_EVNTMASK_IRET_NB_TAG   0x02
   11.78 -#define P4_ESCR_EVNTMASK_IRET_B_NTAG   0x04
   11.79 -#define P4_ESCR_EVNTMASK_IRET_B_TAG    0x08
   11.80 -
   11.81 -#define P4_ESCR_EVNTMASK_URET_NBOGUS   0x01
   11.82 -#define P4_ESCR_EVNTMASK_URET_BOGUS    0x02
   11.83 -
   11.84 -#define P4_ESCR_EVNTMASK_UOP_LOADS     0x02
   11.85 -#define P4_ESCR_EVNTMASK_UOP_STORES    0x04
   11.86 -
   11.87 -#define P4_ESCR_EVNTMASK_RMBRT_COND    0x02
   11.88 -#define P4_ESCR_EVNTMASK_RMBRT_CALL    0x04
   11.89 -#define P4_ESCR_EVNTMASK_RMBRT_RETURN  0x08
   11.90 -#define P4_ESCR_EVNTMASK_RMBRT_INDIR   0x10
   11.91 -
   11.92 -#define P4_ESCR_EVNTMASK_RBRT_COND     0x02
   11.93 -#define P4_ESCR_EVNTMASK_RBRT_CALL     0x04
   11.94 -#define P4_ESCR_EVNTMASK_RBRT_RETURN   0x08
   11.95 -#define P4_ESCR_EVNTMASK_RBRT_INDIR    0x10
   11.96 -
   11.97 -//#define P4_ESCR_EVNTMASK_INSTR_RETIRED 0x01  /* Non bogus, not tagged */
   11.98 -//#define P4_ESCR_EVNTMASK_UOPS_RETIRED  0x01  /* Non bogus             */
   11.99 -
  11.100 -#define P4_CCCR_OVF                    (1 << 31)
  11.101 -#define P4_CCCR_CASCADE                (1 << 30)
  11.102 -#define P4_CCCR_FORCE_OVF              (1 << 25)
  11.103 -#define P4_CCCR_EDGE                   (1 << 24)
  11.104 -#define P4_CCCR_COMPLEMENT             (1 << 19)
  11.105 -#define P4_CCCR_COMPARE                (1 << 18)
  11.106 -#define P4_CCCR_THRESHOLD(t)           (t << 20)
  11.107 -#define P4_CCCR_ENABLE                 (1 << 12)
  11.108 -#define P4_CCCR_ESCR(escr)             (escr << 13)
  11.109 -#define P4_CCCR_ACTIVE_THREAD(t)       (t << 16)   /* Set to 11 */
  11.110 -#define P4_CCCR_OVF_PMI_T0             (1 << 26)
  11.111 -#define P4_CCCR_OVF_PMI_T1             (1 << 27)
  11.112 -#define P4_CCCR_RESERVED               (3 << 16)
  11.113 -#define P4_CCCR_OVF_PMI                (1 << 26)
  11.114 -
  11.115 -// BPU
  11.116 -#define MSR_P4_BPU_COUNTER0            0x300
  11.117 -#define MSR_P4_BPU_COUNTER1            0x301
  11.118 -#define MSR_P4_BPU_CCCR0               0x360
  11.119 -#define MSR_P4_BPU_CCCR1               0x361
  11.120 -
  11.121 -#define MSR_P4_BPU_COUNTER2            0x302
  11.122 -#define MSR_P4_BPU_COUNTER3            0x303
  11.123 -#define MSR_P4_BPU_CCCR2               0x362
  11.124 -#define MSR_P4_BPU_CCCR3               0x363
  11.125 -
  11.126 -#define MSR_P4_BSU_ESCR0               0x3a0
  11.127 -#define MSR_P4_FSB_ESCR0               0x3a2
  11.128 -#define MSR_P4_MOB_ESCR0               0x3aa
  11.129 -#define MSR_P4_PMH_ESCR0               0x3ac
  11.130 -#define MSR_P4_BPU_ESCR0               0x3b2
  11.131 -#define MSR_P4_IS_ESCR0                0x3b4
  11.132 -#define MSR_P4_ITLB_ESCR0              0x3b6
  11.133 -#define MSR_P4_IX_ESCR0                0x3c8
  11.134 -
  11.135 -#define P4_BSU_ESCR0_NUMBER            7
  11.136 -#define P4_FSB_ESCR0_NUMBER            6
  11.137 -#define P4_MOB_ESCR0_NUMBER            2
  11.138 -#define P4_PMH_ESCR0_NUMBER            4
  11.139 -#define P4_BPU_ESCR0_NUMBER            0
  11.140 -#define P4_IS_ESCR0_NUMBER             1
  11.141 -#define P4_ITLB_ESCR0_NUMBER           3
  11.142 -#define P4_IX_ESCR0_NUMBER             5
  11.143 -
  11.144 -#define MSR_P4_BSU_ESCR1               0x3a1
  11.145 -#define MSR_P4_FSB_ESCR1               0x3a3
  11.146 -#define MSR_P4_MOB_ESCR1               0x3ab
  11.147 -#define MSR_P4_PMH_ESCR1               0x3ad
  11.148 -#define MSR_P4_BPU_ESCR1               0x3b3
  11.149 -#define MSR_P4_IS_ESCR1                0x3b5
  11.150 -#define MSR_P4_ITLB_ESCR1              0x3b7
  11.151 -#define MSR_P4_IX_ESCR1                0x3c9
  11.152 -
  11.153 -#define P4_BSU_ESCR1_NUMBER            7
  11.154 -#define P4_FSB_ESCR1_NUMBER            6
  11.155 -#define P4_MOB_ESCR1_NUMBER            2
  11.156 -#define P4_PMH_ESCR1_NUMBER            4
  11.157 -#define P4_BPU_ESCR1_NUMBER            0
  11.158 -#define P4_IS_ESCR1_NUMBER             1
  11.159 -#define P4_ITLB_ESCR1_NUMBER           3
  11.160 -#define P4_IX_ESCR1_NUMBER             5
  11.161 -
  11.162 -// MS
  11.163 -#define MSR_P4_MS_COUNTER0             0x304
  11.164 -#define MSR_P4_MS_COUNTER1             0x305
  11.165 -#define MSR_P4_MS_CCCR0                0x364
  11.166 -#define MSR_P4_MS_CCCR1                0x365
  11.167 -
  11.168 -#define MSR_P4_MS_COUNTER2             0x306
  11.169 -#define MSR_P4_MS_COUNTER3             0x307
  11.170 -#define MSR_P4_MS_CCCR2                0x366
  11.171 -#define MSR_P4_MS_CCCR3                0x367
  11.172 -
  11.173 -#define MSR_P4_MS_ESCR0                0x3c0
  11.174 -#define MSR_P4_TBPU_ESCR0              0x3c2
  11.175 -#define MSR_P4_TC_ESCR0                0x3c4
  11.176 -
  11.177 -#define P4_MS_ESCR0_NUMBER             0
  11.178 -#define P4_TBPU_ESCR0_NUMBER           2
  11.179 -#define P4_TC_ESCR0_NUMBER             1
  11.180 -
  11.181 -#define MSR_P4_MS_ESCR1                0x3c1
  11.182 -#define MSR_P4_TBPU_ESCR1              0x3c3
  11.183 -#define MSR_P4_TC_ESCR1                0x3c5
  11.184 -
  11.185 -#define P4_MS_ESCR1_NUMBER             0
  11.186 -#define P4_TBPU_ESCR1_NUMBER           2
  11.187 -#define P4_TC_ESCR1_NUMBER             1
  11.188 -
  11.189 -// FLAME
  11.190 -#define MSR_P4_FLAME_COUNTER0          0x308
  11.191 -#define MSR_P4_FLAME_COUNTER1          0x309
  11.192 -#define MSR_P4_FLAME_CCCR0             0x368
  11.193 -#define MSR_P4_FLAME_CCCR1             0x369
  11.194 -
  11.195 -#define MSR_P4_FLAME_COUNTER2          0x30a
  11.196 -#define MSR_P4_FLAME_COUNTER3          0x30b
  11.197 -#define MSR_P4_FLAME_CCCR2             0x36a
  11.198 -#define MSR_P4_FLAME_CCCR3             0x36b
  11.199 -
  11.200 -#define MSR_P4_FIRM_ESCR0              0x3a4
  11.201 -#define MSR_P4_FLAME_ESCR0             0x3a6
  11.202 -#define MSR_P4_DAC_ESCR0               0x3a8
  11.203 -#define MSR_P4_SAAT_ESCR0              0x3ae
  11.204 -#define MSR_P4_U2L_ESCR0               0x3b0
  11.205 -
  11.206 -#define P4_FIRM_ESCR0_NUMBER           1
  11.207 -#define P4_FLAME_ESCR0_NUMBER          0
  11.208 -#define P4_DAC_ESCR0_NUMBER            5
  11.209 -#define P4_SAAT_ESCR0_NUMBER           2
  11.210 -#define P4_U2L_ESCR0_NUMBER            3
  11.211 -
  11.212 -#define MSR_P4_FIRM_ESCR1              0x3a5
  11.213 -#define MSR_P4_FLAME_ESCR1             0x3a7
  11.214 -#define MSR_P4_DAC_ESCR1               0x3a9
  11.215 -#define MSR_P4_SAAT_ESCR1              0x3af
  11.216 -#define MSR_P4_U2L_ESCR1               0x3b1
  11.217 -
  11.218 -#define P4_FIRM_ESCR1_NUMBER           1
  11.219 -#define P4_FLAME_ESCR1_NUMBER          0
  11.220 -#define P4_DAC_ESCR1_NUMBER            5
  11.221 -#define P4_SAAT_ESCR1_NUMBER           2
  11.222 -#define P4_U2L_ESCR1_NUMBER            3
  11.223 -
  11.224 -// IQ
  11.225 -#define MSR_P4_IQ_COUNTER0             0x30c
  11.226 -#define MSR_P4_IQ_COUNTER1             0x30d
  11.227 -#define MSR_P4_IQ_CCCR0                0x36c
  11.228 -#define MSR_P4_IQ_CCCR1                0x36d
  11.229 -
  11.230 -#define MSR_P4_IQ_COUNTER2             0x30e
  11.231 -#define MSR_P4_IQ_COUNTER3             0x30f
  11.232 -#define MSR_P4_IQ_CCCR2                0x36e
  11.233 -#define MSR_P4_IQ_CCCR3                0x36f
  11.234 -
  11.235 -#define MSR_P4_IQ_COUNTER4             0x310
  11.236 -#define MSR_P4_IQ_COUNTER5             0x311
  11.237 -#define MSR_P4_IQ_CCCR4                0x370
  11.238 -#define MSR_P4_IQ_CCCR5                0x371
  11.239 -
  11.240 -#define MSR_P4_CRU_ESCR0               0x3b8
  11.241 -#define MSR_P4_CRU_ESCR2               0x3cc
  11.242 -#define MSR_P4_CRU_ESCR4               0x3e0
  11.243 -#define MSR_P4_IQ_ESCR0                0x3ba
  11.244 -#define MSR_P4_RAT_ESCR0               0x3bc
  11.245 -#define MSR_P4_SSU_ESCR0               0x3be
  11.246 -#define MSR_P4_ALF_ESCR0               0x3ca
  11.247 -
  11.248 -#define P4_CRU_ESCR0_NUMBER            4
  11.249 -#define P4_CRU_ESCR2_NUMBER            5
  11.250 -#define P4_CRU_ESCR4_NUMBER            6
  11.251 -#define P4_IQ_ESCR0_NUMBER             0
  11.252 -#define P4_RAT_ESCR0_NUMBER            2
  11.253 -#define P4_SSU_ESCR0_NUMBER            3
  11.254 -#define P4_ALF_ESCR0_NUMBER            1
  11.255 -
  11.256 -#define MSR_P4_CRU_ESCR1               0x3b9
  11.257 -#define MSR_P4_CRU_ESCR3               0x3cd
  11.258 -#define MSR_P4_CRU_ESCR5               0x3e1
  11.259 -#define MSR_P4_IQ_ESCR1                0x3bb
  11.260 -#define MSR_P4_RAT_ESCR1               0x3bd
  11.261 -#define MSR_P4_ALF_ESCR1               0x3cb
  11.262 -
  11.263 -#define P4_CRU_ESCR1_NUMBER            4
  11.264 -#define P4_CRU_ESCR3_NUMBER            5
  11.265 -#define P4_CRU_ESCR5_NUMBER            6
  11.266 -#define P4_IQ_ESCR1_NUMBER             0
  11.267 -#define P4_RAT_ESCR1_NUMBER            2
  11.268 -#define P4_ALF_ESCR1_NUMBER            1
  11.269 -
  11.270 -#define P4_BPU_COUNTER0_NUMBER         0
  11.271 -#define P4_BPU_COUNTER1_NUMBER         1
  11.272 -#define P4_BPU_COUNTER2_NUMBER         2
  11.273 -#define P4_BPU_COUNTER3_NUMBER         3
  11.274 -
  11.275 -#define P4_MS_COUNTER0_NUMBER          4
  11.276 -#define P4_MS_COUNTER1_NUMBER          5
  11.277 -#define P4_MS_COUNTER2_NUMBER          6
  11.278 -#define P4_MS_COUNTER3_NUMBER          7
  11.279 -
  11.280 -#define P4_FLAME_COUNTER0_NUMBER       8
  11.281 -#define P4_FLAME_COUNTER1_NUMBER       9
  11.282 -#define P4_FLAME_COUNTER2_NUMBER       10
  11.283 -#define P4_FLAME_COUNTER3_NUMBER       11
  11.284 -
  11.285 -#define P4_IQ_COUNTER0_NUMBER          12
  11.286 -#define P4_IQ_COUNTER1_NUMBER          13
  11.287 -#define P4_IQ_COUNTER2_NUMBER          14
  11.288 -#define P4_IQ_COUNTER3_NUMBER          15
  11.289 -#define P4_IQ_COUNTER4_NUMBER          16
  11.290 -#define P4_IQ_COUNTER5_NUMBER          17
  11.291 -
  11.292 -/* PEBS
  11.293 - */
  11.294 -#define MSR_P4_PEBS_ENABLE             0x3F1
  11.295 -#define MSR_P4_PEBS_MATRIX_VERT        0x3F2
  11.296 -
  11.297 -#define P4_PEBS_ENABLE_MY_THR          (1 << 25)
  11.298 -#define P4_PEBS_ENABLE_OTH_THR         (1 << 26)
  11.299 -#define P4_PEBS_ENABLE                 (1 << 24)
  11.300 -#define P4_PEBS_BIT0                   (1 << 0)
  11.301 -#define P4_PEBS_BIT1                   (1 << 1)
  11.302 -#define P4_PEBS_BIT2                   (1 << 2)
  11.303 -
  11.304 -#define P4_PEBS_MATRIX_VERT_BIT0       (1 << 0)
  11.305 -#define P4_PEBS_MATRIX_VERT_BIT1       (1 << 1)
  11.306 -#define P4_PEBS_MATRIX_VERT_BIT2       (1 << 2)
  11.307 -
  11.308 -/* Replay tagging.
  11.309 - */
  11.310 -#define P4_REPLAY_TAGGING_PEBS_L1LMR   P4_PEBS_BIT0
  11.311 -#define P4_REPLAY_TAGGING_PEBS_L2LMR   P4_PEBS_BIT1
  11.312 -#define P4_REPLAY_TAGGING_PEBS_DTLMR   P4_PEBS_BIT2
  11.313 -#define P4_REPLAY_TAGGING_PEBS_DTSMR   P4_PEBS_BIT2
  11.314 -#define P4_REPLAY_TAGGING_PEBS_DTAMR   P4_PEBS_BIT2
  11.315 -
  11.316 -#define P4_REPLAY_TAGGING_VERT_L1LMR   P4_PEBS_MATRIX_VERT_BIT0
  11.317 -#define P4_REPLAY_TAGGING_VERT_L2LMR   P4_PEBS_MATRIX_VERT_BIT0
  11.318 -#define P4_REPLAY_TAGGING_VERT_DTLMR   P4_PEBS_MATRIX_VERT_BIT0
  11.319 -#define P4_REPLAY_TAGGING_VERT_DTSMR   P4_PEBS_MATRIX_VERT_BIT1
  11.320 -#define P4_REPLAY_TAGGING_VERT_DTAMR   P4_PEBS_MATRIX_VERT_BIT0 | P4_PEBS_MATRIX_VERT_BIT1
  11.321 -
  11.322 -
  11.323 -
  11.324 -
  11.325 -/*****************************************************************************
  11.326 - *                                                                           *
  11.327 - *****************************************************************************/
  11.328 -
  11.329 -// x87_FP_uop
  11.330 -#define EVENT_SEL_x87_FP_uop                0x04
  11.331 -#define EVENT_MASK_x87_FP_uop_ALL           (1 << 15)
  11.332 -
  11.333 -// execution event (at retirement)
  11.334 -#define EVENT_SEL_execution_event           0x0C
  11.335 -
  11.336 -// scalar_SP_uop
  11.337 -#define EVENT_SEL_scalar_SP_uop             0x0a
  11.338 -#define EVENT_MASK_scalar_SP_uop_ALL        (1 << 15)
  11.339 -
  11.340 -// scalar_DP_uop
  11.341 -#define EVENT_SEL_scalar_DP_uop             0x0e
  11.342 -#define EVENT_MASK_scalar_DP_uop_ALL        (1 << 15)
  11.343 -
  11.344 -// Instruction retired
  11.345 -#define EVENT_SEL_instr_retired             0x02
  11.346 -#define EVENT_MASK_instr_retired_ALL        0x0f
  11.347 -
  11.348 -// uOps retired
  11.349 -#define EVENT_SEL_uops_retired              0x01
  11.350 -#define EVENT_MASK_uops_retired_ALL         0x03
  11.351 -
  11.352 -// L1 misses retired
  11.353 -#define EVENT_SEL_replay_event              0x09
  11.354 -#define EVENT_MASK_replay_event_ALL         0x03
  11.355 -
  11.356 -// Trace cache
  11.357 -#define EVENT_SEL_BPU_fetch_request         0x03
  11.358 -#define EVENT_MASK_BPU_fetch_request_TCMISS 0x01
  11.359 -
  11.360 -// Bus activity
  11.361 -#define EVENT_SEL_FSB_data_activity               0x17
  11.362 -#define EVENT_MASK_FSB_data_activity_DRDY_DRV     0x01
  11.363 -#define EVENT_MASK_FSB_data_activity_DRDY_OWN     0x02
  11.364 -#define EVENT_MASK_FSB_data_activity_DRDY_OOTHER  0x04
  11.365 -#define EVENT_MASK_FSB_data_activity_DBSY_DRV     0x08
  11.366 -#define EVENT_MASK_FSB_data_activity_DBSY_OWN     0x10
  11.367 -#define EVENT_MASK_FSB_data_activity_DBSY_OOTHER  0x20
  11.368 -
  11.369 -// Cache L2
  11.370 -#define EVENT_SEL_BSQ_cache_reference             0x0c
  11.371 -#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITS 0x001
  11.372 -#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITE 0x002
  11.373 -#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITM 0x004
  11.374 -
  11.375 -#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITS 0x008
  11.376 -#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITE 0x010
  11.377 -#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITM 0x020
  11.378 -
  11.379 -#define EVENT_MASK_BSQ_cache_reference_RD_L2_MISS 0x100
  11.380 -#define EVENT_MASK_BSQ_cache_reference_RD_L3_MISS 0x200
  11.381 -#define EVENT_MASK_BSQ_cache_reference_WR_L2_MISS 0x400
  11.382 -
  11.383 -#endif
  11.384 -
  11.385 -/* End of $RCSfile: p4perf.h,v $ */