ia64/xen-unstable

changeset 10702:614deef19299

[IA64] vDSO paravirtualization: import linux files

import gate.S, gate.ld.S and patch.c which are needed to
paravirtualize vdso area.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@xenbuild.aw
date Mon Jul 24 13:04:40 2006 -0600 (2006-07-24)
parents 70ee75d5c12c
children 8d501f39286c
files linux-2.6-xen-sparse/arch/ia64/kernel/gate.S linux-2.6-xen-sparse/arch/ia64/kernel/gate.lds.S linux-2.6-xen-sparse/arch/ia64/kernel/patch.c
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/linux-2.6-xen-sparse/arch/ia64/kernel/gate.S	Mon Jul 24 13:04:40 2006 -0600
     1.3 @@ -0,0 +1,376 @@
     1.4 +/*
     1.5 + * This file contains the code that gets mapped at the upper end of each task's text
     1.6 + * region.  For now, it contains the signal trampoline code only.
     1.7 + *
     1.8 + * Copyright (C) 1999-2003 Hewlett-Packard Co
     1.9 + * 	David Mosberger-Tang <davidm@hpl.hp.com>
    1.10 + */
    1.11 +
    1.12 +#include <linux/config.h>
    1.13 +
    1.14 +#include <asm/asmmacro.h>
    1.15 +#include <asm/errno.h>
    1.16 +#include <asm/asm-offsets.h>
    1.17 +#include <asm/sigcontext.h>
    1.18 +#include <asm/system.h>
    1.19 +#include <asm/unistd.h>
    1.20 +
    1.21 +/*
    1.22 + * We can't easily refer to symbols inside the kernel.  To avoid full runtime relocation,
    1.23 + * complications with the linker (which likes to create PLT stubs for branches
    1.24 + * to targets outside the shared object) and to avoid multi-phase kernel builds, we
    1.25 + * simply create minimalistic "patch lists" in special ELF sections.
    1.26 + */
    1.27 +	.section ".data.patch.fsyscall_table", "a"
    1.28 +	.previous
    1.29 +#define LOAD_FSYSCALL_TABLE(reg)			\
    1.30 +[1:]	movl reg=0;					\
    1.31 +	.xdata4 ".data.patch.fsyscall_table", 1b-.
    1.32 +
    1.33 +	.section ".data.patch.brl_fsys_bubble_down", "a"
    1.34 +	.previous
    1.35 +#define BRL_COND_FSYS_BUBBLE_DOWN(pr)			\
    1.36 +[1:](pr)brl.cond.sptk 0;				\
    1.37 +	.xdata4 ".data.patch.brl_fsys_bubble_down", 1b-.
    1.38 +
    1.39 +GLOBAL_ENTRY(__kernel_syscall_via_break)
    1.40 +	.prologue
    1.41 +	.altrp b6
    1.42 +	.body
    1.43 +	/*
    1.44 +	 * Note: for (fast) syscall restart to work, the break instruction must be
    1.45 +	 *	 the first one in the bundle addressed by syscall_via_break.
    1.46 +	 */
    1.47 +{ .mib
    1.48 +	break 0x100000
    1.49 +	nop.i 0
    1.50 +	br.ret.sptk.many b6
    1.51 +}
    1.52 +END(__kernel_syscall_via_break)
    1.53 +
    1.54 +/*
    1.55 + * On entry:
    1.56 + *	r11 = saved ar.pfs
    1.57 + *	r15 = system call #
    1.58 + *	b0  = saved return address
    1.59 + *	b6  = return address
    1.60 + * On exit:
    1.61 + *	r11 = saved ar.pfs
    1.62 + *	r15 = system call #
    1.63 + *	b0  = saved return address
    1.64 + *	all other "scratch" registers:	undefined
    1.65 + *	all "preserved" registers:	same as on entry
    1.66 + */
    1.67 +
    1.68 +GLOBAL_ENTRY(__kernel_syscall_via_epc)
    1.69 +	.prologue
    1.70 +	.altrp b6
    1.71 +	.body
    1.72 +{
    1.73 +	/*
    1.74 +	 * Note: the kernel cannot assume that the first two instructions in this
    1.75 +	 * bundle get executed.  The remaining code must be safe even if
    1.76 +	 * they do not get executed.
    1.77 +	 */
    1.78 +	adds r17=-1024,r15			// A
    1.79 +	mov r10=0				// A    default to successful syscall execution
    1.80 +	epc					// B	causes split-issue
    1.81 +}
    1.82 +	;;
    1.83 +	rsm psr.be | psr.i			// M2 (5 cyc to srlz.d)
    1.84 +	LOAD_FSYSCALL_TABLE(r14)		// X
    1.85 +	;;
    1.86 +	mov r16=IA64_KR(CURRENT)		// M2 (12 cyc)
    1.87 +	shladd r18=r17,3,r14			// A
    1.88 +	mov r19=NR_syscalls-1			// A
    1.89 +	;;
    1.90 +	lfetch [r18]				// M0|1
    1.91 +	mov r29=psr				// M2 (12 cyc)
    1.92 +	// If r17 is a NaT, p6 will be zero
    1.93 +	cmp.geu p6,p7=r19,r17			// A    (sysnr > 0 && sysnr < 1024+NR_syscalls)?
    1.94 +	;;
    1.95 +	mov r21=ar.fpsr				// M2 (12 cyc)
    1.96 +	tnat.nz p10,p9=r15			// I0
    1.97 +	mov.i r26=ar.pfs			// I0 (would stall anyhow due to srlz.d...)
    1.98 +	;;
    1.99 +	srlz.d					// M0 (forces split-issue) ensure PSR.BE==0
   1.100 +(p6)	ld8 r18=[r18]				// M0|1
   1.101 +	nop.i 0
   1.102 +	;;
   1.103 +	nop.m 0
   1.104 +(p6)	tbit.z.unc p8,p0=r18,0			// I0 (dual-issues with "mov b7=r18"!)
   1.105 +	nop.i 0
   1.106 +	;;
   1.107 +(p8)	ssm psr.i
   1.108 +(p6)	mov b7=r18				// I0
   1.109 +(p8)	br.dptk.many b7				// B
   1.110 +
   1.111 +	mov r27=ar.rsc				// M2 (12 cyc)
   1.112 +/*
   1.113 + * brl.cond doesn't work as intended because the linker would convert this branch
   1.114 + * into a branch to a PLT.  Perhaps there will be a way to avoid this with some
   1.115 + * future version of the linker.  In the meantime, we just use an indirect branch
   1.116 + * instead.
   1.117 + */
   1.118 +#ifdef CONFIG_ITANIUM
   1.119 +(p6)	add r14=-8,r14				// r14 <- addr of fsys_bubble_down entry
   1.120 +	;;
   1.121 +(p6)	ld8 r14=[r14]				// r14 <- fsys_bubble_down
   1.122 +	;;
   1.123 +(p6)	mov b7=r14
   1.124 +(p6)	br.sptk.many b7
   1.125 +#else
   1.126 +	BRL_COND_FSYS_BUBBLE_DOWN(p6)
   1.127 +#endif
   1.128 +	ssm psr.i
   1.129 +	mov r10=-1
   1.130 +(p10)	mov r8=EINVAL
   1.131 +(p9)	mov r8=ENOSYS
   1.132 +	FSYS_RETURN
   1.133 +END(__kernel_syscall_via_epc)
   1.134 +
   1.135 +#	define ARG0_OFF		(16 + IA64_SIGFRAME_ARG0_OFFSET)
   1.136 +#	define ARG1_OFF		(16 + IA64_SIGFRAME_ARG1_OFFSET)
   1.137 +#	define ARG2_OFF		(16 + IA64_SIGFRAME_ARG2_OFFSET)
   1.138 +#	define SIGHANDLER_OFF	(16 + IA64_SIGFRAME_HANDLER_OFFSET)
   1.139 +#	define SIGCONTEXT_OFF	(16 + IA64_SIGFRAME_SIGCONTEXT_OFFSET)
   1.140 +
   1.141 +#	define FLAGS_OFF	IA64_SIGCONTEXT_FLAGS_OFFSET
   1.142 +#	define CFM_OFF		IA64_SIGCONTEXT_CFM_OFFSET
   1.143 +#	define FR6_OFF		IA64_SIGCONTEXT_FR6_OFFSET
   1.144 +#	define BSP_OFF		IA64_SIGCONTEXT_AR_BSP_OFFSET
   1.145 +#	define RNAT_OFF		IA64_SIGCONTEXT_AR_RNAT_OFFSET
   1.146 +#	define UNAT_OFF		IA64_SIGCONTEXT_AR_UNAT_OFFSET
   1.147 +#	define FPSR_OFF		IA64_SIGCONTEXT_AR_FPSR_OFFSET
   1.148 +#	define PR_OFF		IA64_SIGCONTEXT_PR_OFFSET
   1.149 +#	define RP_OFF		IA64_SIGCONTEXT_IP_OFFSET
   1.150 +#	define SP_OFF		IA64_SIGCONTEXT_R12_OFFSET
   1.151 +#	define RBS_BASE_OFF	IA64_SIGCONTEXT_RBS_BASE_OFFSET
   1.152 +#	define LOADRS_OFF	IA64_SIGCONTEXT_LOADRS_OFFSET
   1.153 +#	define base0		r2
   1.154 +#	define base1		r3
   1.155 +	/*
   1.156 +	 * When we get here, the memory stack looks like this:
   1.157 +	 *
   1.158 +	 *   +===============================+
   1.159 +       	 *   |				     |
   1.160 +       	 *   //	    struct sigframe          //
   1.161 +       	 *   |				     |
   1.162 +	 *   +-------------------------------+ <-- sp+16
   1.163 +	 *   |      16 byte of scratch       |
   1.164 +	 *   |            space              |
   1.165 +	 *   +-------------------------------+ <-- sp
   1.166 +	 *
   1.167 +	 * The register stack looks _exactly_ the way it looked at the time the signal
   1.168 +	 * occurred.  In other words, we're treading on a potential mine-field: each
   1.169 +	 * incoming general register may be a NaT value (including sp, in which case the
   1.170 +	 * process ends up dying with a SIGSEGV).
   1.171 +	 *
   1.172 +	 * The first thing need to do is a cover to get the registers onto the backing
   1.173 +	 * store.  Once that is done, we invoke the signal handler which may modify some
   1.174 +	 * of the machine state.  After returning from the signal handler, we return
   1.175 +	 * control to the previous context by executing a sigreturn system call.  A signal
   1.176 +	 * handler may call the rt_sigreturn() function to directly return to a given
   1.177 +	 * sigcontext.  However, the user-level sigreturn() needs to do much more than
   1.178 +	 * calling the rt_sigreturn() system call as it needs to unwind the stack to
   1.179 +	 * restore preserved registers that may have been saved on the signal handler's
   1.180 +	 * call stack.
   1.181 +	 */
   1.182 +
   1.183 +#define SIGTRAMP_SAVES										\
   1.184 +	.unwabi 3, 's';		/* mark this as a sigtramp handler (saves scratch regs) */	\
   1.185 +	.unwabi @svr4, 's'; /* backwards compatibility with old unwinders (remove in v2.7) */	\
   1.186 +	.savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF;						\
   1.187 +	.savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF;						\
   1.188 +	.savesp pr, PR_OFF+SIGCONTEXT_OFF;     							\
   1.189 +	.savesp rp, RP_OFF+SIGCONTEXT_OFF;							\
   1.190 +	.savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF;							\
   1.191 +	.vframesp SP_OFF+SIGCONTEXT_OFF
   1.192 +
   1.193 +GLOBAL_ENTRY(__kernel_sigtramp)
   1.194 +	// describe the state that is active when we get here:
   1.195 +	.prologue
   1.196 +	SIGTRAMP_SAVES
   1.197 +	.body
   1.198 +
   1.199 +	.label_state 1
   1.200 +
   1.201 +	adds base0=SIGHANDLER_OFF,sp
   1.202 +	adds base1=RBS_BASE_OFF+SIGCONTEXT_OFF,sp
   1.203 +	br.call.sptk.many rp=1f
   1.204 +1:
   1.205 +	ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF)	// get pointer to signal handler's plabel
   1.206 +	ld8 r15=[base1]					// get address of new RBS base (or NULL)
   1.207 +	cover				// push args in interrupted frame onto backing store
   1.208 +	;;
   1.209 +	cmp.ne p1,p0=r15,r0		// do we need to switch rbs? (note: pr is saved by kernel)
   1.210 +	mov.m r9=ar.bsp			// fetch ar.bsp
   1.211 +	.spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
   1.212 +(p1)	br.cond.spnt setup_rbs		// yup -> (clobbers p8, r14-r16, and r18-r20)
   1.213 +back_from_setup_rbs:
   1.214 +	alloc r8=ar.pfs,0,0,3,0
   1.215 +	ld8 out0=[base0],16		// load arg0 (signum)
   1.216 +	adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
   1.217 +	;;
   1.218 +	ld8 out1=[base1]		// load arg1 (siginfop)
   1.219 +	ld8 r10=[r17],8			// get signal handler entry point
   1.220 +	;;
   1.221 +	ld8 out2=[base0]		// load arg2 (sigcontextp)
   1.222 +	ld8 gp=[r17]			// get signal handler's global pointer
   1.223 +	adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
   1.224 +	;;
   1.225 +	.spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
   1.226 +	st8 [base0]=r9			// save sc_ar_bsp
   1.227 +	adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
   1.228 +	adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
   1.229 +	;;
   1.230 +	stf.spill [base0]=f6,32
   1.231 +	stf.spill [base1]=f7,32
   1.232 +	;;
   1.233 +	stf.spill [base0]=f8,32
   1.234 +	stf.spill [base1]=f9,32
   1.235 +	mov b6=r10
   1.236 +	;;
   1.237 +	stf.spill [base0]=f10,32
   1.238 +	stf.spill [base1]=f11,32
   1.239 +	;;
   1.240 +	stf.spill [base0]=f12,32
   1.241 +	stf.spill [base1]=f13,32
   1.242 +	;;
   1.243 +	stf.spill [base0]=f14,32
   1.244 +	stf.spill [base1]=f15,32
   1.245 +	br.call.sptk.many rp=b6			// call the signal handler
   1.246 +.ret0:	adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
   1.247 +	;;
   1.248 +	ld8 r15=[base0]				// fetch sc_ar_bsp
   1.249 +	mov r14=ar.bsp
   1.250 +	;;
   1.251 +	cmp.ne p1,p0=r14,r15			// do we need to restore the rbs?
   1.252 +(p1)	br.cond.spnt restore_rbs		// yup -> (clobbers r14-r18, f6 & f7)
   1.253 +	;;
   1.254 +back_from_restore_rbs:
   1.255 +	adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
   1.256 +	adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
   1.257 +	;;
   1.258 +	ldf.fill f6=[base0],32
   1.259 +	ldf.fill f7=[base1],32
   1.260 +	;;
   1.261 +	ldf.fill f8=[base0],32
   1.262 +	ldf.fill f9=[base1],32
   1.263 +	;;
   1.264 +	ldf.fill f10=[base0],32
   1.265 +	ldf.fill f11=[base1],32
   1.266 +	;;
   1.267 +	ldf.fill f12=[base0],32
   1.268 +	ldf.fill f13=[base1],32
   1.269 +	;;
   1.270 +	ldf.fill f14=[base0],32
   1.271 +	ldf.fill f15=[base1],32
   1.272 +	mov r15=__NR_rt_sigreturn
   1.273 +	.restore sp				// pop .prologue
   1.274 +	break __BREAK_SYSCALL
   1.275 +
   1.276 +	.prologue
   1.277 +	SIGTRAMP_SAVES
   1.278 +setup_rbs:
   1.279 +	mov ar.rsc=0				// put RSE into enforced lazy mode
   1.280 +	;;
   1.281 +	.save ar.rnat, r19
   1.282 +	mov r19=ar.rnat				// save RNaT before switching backing store area
   1.283 +	adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp
   1.284 +
   1.285 +	mov r18=ar.bspstore
   1.286 +	mov ar.bspstore=r15			// switch over to new register backing store area
   1.287 +	;;
   1.288 +
   1.289 +	.spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
   1.290 +	st8 [r14]=r19				// save sc_ar_rnat
   1.291 +	.body
   1.292 +	mov.m r16=ar.bsp			// sc_loadrs <- (new bsp - new bspstore) << 16
   1.293 +	adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp
   1.294 +	;;
   1.295 +	invala
   1.296 +	sub r15=r16,r15
   1.297 +	extr.u r20=r18,3,6
   1.298 +	;;
   1.299 +	mov ar.rsc=0xf				// set RSE into eager mode, pl 3
   1.300 +	cmp.eq p8,p0=63,r20
   1.301 +	shl r15=r15,16
   1.302 +	;;
   1.303 +	st8 [r14]=r15				// save sc_loadrs
   1.304 +(p8)	st8 [r18]=r19		// if bspstore points at RNaT slot, store RNaT there now
   1.305 +	.restore sp				// pop .prologue
   1.306 +	br.cond.sptk back_from_setup_rbs
   1.307 +
   1.308 +	.prologue
   1.309 +	SIGTRAMP_SAVES
   1.310 +	.spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
   1.311 +	.body
   1.312 +restore_rbs:
   1.313 +	// On input:
   1.314 +	//	r14 = bsp1 (bsp at the time of return from signal handler)
   1.315 +	//	r15 = bsp0 (bsp at the time the signal occurred)
   1.316 +	//
   1.317 +	// Here, we need to calculate bspstore0, the value that ar.bspstore needs
   1.318 +	// to be set to, based on bsp0 and the size of the dirty partition on
   1.319 +	// the alternate stack (sc_loadrs >> 16).  This can be done with the
   1.320 +	// following algorithm:
   1.321 +	//
   1.322 +	//  bspstore0 = rse_skip_regs(bsp0, -rse_num_regs(bsp1 - (loadrs >> 19), bsp1));
   1.323 +	//
   1.324 +	// This is what the code below does.
   1.325 +	//
   1.326 +	alloc r2=ar.pfs,0,0,0,0			// alloc null frame
   1.327 +	adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp
   1.328 +	adds r18=(RNAT_OFF+SIGCONTEXT_OFF),sp
   1.329 +	;;
   1.330 +	ld8 r17=[r16]
   1.331 +	ld8 r16=[r18]			// get new rnat
   1.332 +	extr.u r18=r15,3,6	// r18 <- rse_slot_num(bsp0)
   1.333 +	;;
   1.334 +	mov ar.rsc=r17			// put RSE into enforced lazy mode
   1.335 +	shr.u r17=r17,16
   1.336 +	;;
   1.337 +	sub r14=r14,r17		// r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16)
   1.338 +	shr.u r17=r17,3		// r17 <- (sc_loadrs >> 19)
   1.339 +	;;
   1.340 +	loadrs			// restore dirty partition
   1.341 +	extr.u r14=r14,3,6	// r14 <- rse_slot_num(bspstore1)
   1.342 +	;;
   1.343 +	add r14=r14,r17		// r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19)
   1.344 +	;;
   1.345 +	shr.u r14=r14,6		// r14 <- (rse_slot_num(bspstore1) + (sc_loadrs >> 19))/0x40
   1.346 +	;;
   1.347 +	sub r14=r14,r17		// r14 <- -rse_num_regs(bspstore1, bsp1)
   1.348 +	movl r17=0x8208208208208209
   1.349 +	;;
   1.350 +	add r18=r18,r14		// r18 (delta) <- rse_slot_num(bsp0) - rse_num_regs(bspstore1,bsp1)
   1.351 +	setf.sig f7=r17
   1.352 +	cmp.lt p7,p0=r14,r0	// p7 <- (r14 < 0)?
   1.353 +	;;
   1.354 +(p7)	adds r18=-62,r18	// delta -= 62
   1.355 +	;;
   1.356 +	setf.sig f6=r18
   1.357 +	;;
   1.358 +	xmpy.h f6=f6,f7
   1.359 +	;;
   1.360 +	getf.sig r17=f6
   1.361 +	;;
   1.362 +	add r17=r17,r18
   1.363 +	shr r18=r18,63
   1.364 +	;;
   1.365 +	shr r17=r17,5
   1.366 +	;;
   1.367 +	sub r17=r17,r18		// r17 = delta/63
   1.368 +	;;
   1.369 +	add r17=r14,r17		// r17 <- delta/63 - rse_num_regs(bspstore1, bsp1)
   1.370 +	;;
   1.371 +	shladd r15=r17,3,r15	// r15 <- bsp0 + 8*(delta/63 - rse_num_regs(bspstore1, bsp1))
   1.372 +	;;
   1.373 +	mov ar.bspstore=r15			// switch back to old register backing store area
   1.374 +	;;
   1.375 +	mov ar.rnat=r16				// restore RNaT
   1.376 +	mov ar.rsc=0xf				// (will be restored later on from sc_ar_rsc)
   1.377 +	// invala not necessary as that will happen when returning to user-mode
   1.378 +	br.cond.sptk back_from_restore_rbs
   1.379 +END(__kernel_sigtramp)
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/linux-2.6-xen-sparse/arch/ia64/kernel/gate.lds.S	Mon Jul 24 13:04:40 2006 -0600
     2.3 @@ -0,0 +1,95 @@
     2.4 +/*
     2.5 + * Linker script for gate DSO.  The gate pages are an ELF shared object prelinked to its
     2.6 + * virtual address, with only one read-only segment and one execute-only segment (both fit
     2.7 + * in one page).  This script controls its layout.
     2.8 + */
     2.9 +
    2.10 +#include <linux/config.h>
    2.11 +
    2.12 +#include <asm/system.h>
    2.13 +
    2.14 +SECTIONS
    2.15 +{
    2.16 +  . = GATE_ADDR + SIZEOF_HEADERS;
    2.17 +
    2.18 +  .hash				: { *(.hash) }				:readable
    2.19 +  .dynsym			: { *(.dynsym) }
    2.20 +  .dynstr			: { *(.dynstr) }
    2.21 +  .gnu.version			: { *(.gnu.version) }
    2.22 +  .gnu.version_d		: { *(.gnu.version_d) }
    2.23 +  .gnu.version_r		: { *(.gnu.version_r) }
    2.24 +  .dynamic			: { *(.dynamic) }			:readable :dynamic
    2.25 +
    2.26 +  /*
    2.27 +   * This linker script is used both with -r and with -shared.  For the layouts to match,
    2.28 +   * we need to skip more than enough space for the dynamic symbol table et al.  If this
    2.29 +   * amount is insufficient, ld -shared will barf.  Just increase it here.
    2.30 +   */
    2.31 +  . = GATE_ADDR + 0x500;
    2.32 +
    2.33 +  .data.patch			: {
    2.34 +				    __start_gate_mckinley_e9_patchlist = .;
    2.35 +				    *(.data.patch.mckinley_e9)
    2.36 +				    __end_gate_mckinley_e9_patchlist = .;
    2.37 +
    2.38 +				    __start_gate_vtop_patchlist = .;
    2.39 +				    *(.data.patch.vtop)
    2.40 +				    __end_gate_vtop_patchlist = .;
    2.41 +
    2.42 +				    __start_gate_fsyscall_patchlist = .;
    2.43 +				    *(.data.patch.fsyscall_table)
    2.44 +				    __end_gate_fsyscall_patchlist = .;
    2.45 +
    2.46 +				    __start_gate_brl_fsys_bubble_down_patchlist = .;
    2.47 +				    *(.data.patch.brl_fsys_bubble_down)
    2.48 +				    __end_gate_brl_fsys_bubble_down_patchlist = .;
    2.49 +  }									:readable
    2.50 +  .IA_64.unwind_info		: { *(.IA_64.unwind_info*) }
    2.51 +  .IA_64.unwind			: { *(.IA_64.unwind*) }			:readable :unwind
    2.52 +#ifdef HAVE_BUGGY_SEGREL
    2.53 +  .text (GATE_ADDR + PAGE_SIZE)	: { *(.text) *(.text.*) }		:readable
    2.54 +#else
    2.55 +  . = ALIGN (PERCPU_PAGE_SIZE) + (. & (PERCPU_PAGE_SIZE - 1));
    2.56 +  .text				: { *(.text) *(.text.*) }		:epc
    2.57 +#endif
    2.58 +
    2.59 +  /DISCARD/			: {
    2.60 +  	*(.got.plt) *(.got)
    2.61 +	*(.data .data.* .gnu.linkonce.d.*)
    2.62 +	*(.dynbss)
    2.63 +	*(.bss .bss.* .gnu.linkonce.b.*)
    2.64 +	*(__ex_table)
    2.65 +  }
    2.66 +}
    2.67 +
    2.68 +/*
    2.69 + * We must supply the ELF program headers explicitly to get just one
    2.70 + * PT_LOAD segment, and set the flags explicitly to make segments read-only.
    2.71 + */
    2.72 +PHDRS
    2.73 +{
    2.74 +  readable  PT_LOAD	FILEHDR	PHDRS	FLAGS(4);	/* PF_R */
    2.75 +#ifndef HAVE_BUGGY_SEGREL
    2.76 +  epc	    PT_LOAD	FILEHDR PHDRS	FLAGS(1);	/* PF_X */
    2.77 +#endif
    2.78 +  dynamic   PT_DYNAMIC			FLAGS(4);	/* PF_R */
    2.79 +  unwind    0x70000001; /* PT_IA_64_UNWIND, but ld doesn't match the name */
    2.80 +}
    2.81 +
    2.82 +/*
    2.83 + * This controls what symbols we export from the DSO.
    2.84 + */
    2.85 +VERSION
    2.86 +{
    2.87 +  LINUX_2.5 {
    2.88 +    global:
    2.89 +	__kernel_syscall_via_break;
    2.90 +	__kernel_syscall_via_epc;
    2.91 +	__kernel_sigtramp;
    2.92 +
    2.93 +    local: *;
    2.94 +  };
    2.95 +}
    2.96 +
    2.97 +/* The ELF entry point can be used to set the AT_SYSINFO value.  */
    2.98 +ENTRY(__kernel_syscall_via_epc)
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/linux-2.6-xen-sparse/arch/ia64/kernel/patch.c	Mon Jul 24 13:04:40 2006 -0600
     3.3 @@ -0,0 +1,197 @@
     3.4 +/*
     3.5 + * Instruction-patching support.
     3.6 + *
     3.7 + * Copyright (C) 2003 Hewlett-Packard Co
     3.8 + *	David Mosberger-Tang <davidm@hpl.hp.com>
     3.9 + */
    3.10 +#include <linux/init.h>
    3.11 +#include <linux/string.h>
    3.12 +
    3.13 +#include <asm/patch.h>
    3.14 +#include <asm/processor.h>
    3.15 +#include <asm/sections.h>
    3.16 +#include <asm/system.h>
    3.17 +#include <asm/unistd.h>
    3.18 +
    3.19 +/*
    3.20 + * This was adapted from code written by Tony Luck:
    3.21 + *
    3.22 + * The 64-bit value in a "movl reg=value" is scattered between the two words of the bundle
    3.23 + * like this:
    3.24 + *
    3.25 + * 6  6         5         4         3         2         1
    3.26 + * 3210987654321098765432109876543210987654321098765432109876543210
    3.27 + * ABBBBBBBBBBBBBBBBBBBBBBBCCCCCCCCCCCCCCCCCCDEEEEEFFFFFFFFFGGGGGGG
    3.28 + *
    3.29 + * CCCCCCCCCCCCCCCCCCxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
    3.30 + * xxxxAFFFFFFFFFEEEEEDxGGGGGGGxxxxxxxxxxxxxBBBBBBBBBBBBBBBBBBBBBBB
    3.31 + */
    3.32 +static u64
    3.33 +get_imm64 (u64 insn_addr)
    3.34 +{
    3.35 +	u64 *p = (u64 *) (insn_addr & -16);	/* mask out slot number */
    3.36 +
    3.37 +	return ( (p[1] & 0x0800000000000000UL) << 4)  | /*A*/
    3.38 +		((p[1] & 0x00000000007fffffUL) << 40) | /*B*/
    3.39 +		((p[0] & 0xffffc00000000000UL) >> 24) | /*C*/
    3.40 +		((p[1] & 0x0000100000000000UL) >> 23) | /*D*/
    3.41 +		((p[1] & 0x0003e00000000000UL) >> 29) | /*E*/
    3.42 +		((p[1] & 0x07fc000000000000UL) >> 43) | /*F*/
    3.43 +		((p[1] & 0x000007f000000000UL) >> 36);  /*G*/
    3.44 +}
    3.45 +
    3.46 +/* Patch instruction with "val" where "mask" has 1 bits. */
    3.47 +void
    3.48 +ia64_patch (u64 insn_addr, u64 mask, u64 val)
    3.49 +{
    3.50 +	u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16);
    3.51 +#	define insn_mask ((1UL << 41) - 1)
    3.52 +	unsigned long shift;
    3.53 +
    3.54 +	b0 = b[0]; b1 = b[1];
    3.55 +	shift = 5 + 41 * (insn_addr % 16); /* 5 bits of template, then 3 x 41-bit instructions */
    3.56 +	if (shift >= 64) {
    3.57 +		m1 = mask << (shift - 64);
    3.58 +		v1 = val << (shift - 64);
    3.59 +	} else {
    3.60 +		m0 = mask << shift; m1 = mask >> (64 - shift);
    3.61 +		v0 = val  << shift; v1 = val >> (64 - shift);
    3.62 +		b[0] = (b0 & ~m0) | (v0 & m0);
    3.63 +	}
    3.64 +	b[1] = (b1 & ~m1) | (v1 & m1);
    3.65 +}
    3.66 +
    3.67 +void
    3.68 +ia64_patch_imm64 (u64 insn_addr, u64 val)
    3.69 +{
    3.70 +	/* The assembler may generate offset pointing to either slot 1
    3.71 +	   or slot 2 for a long (2-slot) instruction, occupying slots 1
    3.72 +	   and 2.  */
    3.73 +  	insn_addr &= -16UL;
    3.74 +	ia64_patch(insn_addr + 2,
    3.75 +		   0x01fffefe000UL, (  ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
    3.76 +				     | ((val & 0x0000000000200000UL) <<  0) /* bit 21 -> 21 */
    3.77 +				     | ((val & 0x00000000001f0000UL) <<  6) /* bit 16 -> 22 */
    3.78 +				     | ((val & 0x000000000000ff80UL) << 20) /* bit  7 -> 27 */
    3.79 +				     | ((val & 0x000000000000007fUL) << 13) /* bit  0 -> 13 */));
    3.80 +	ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
    3.81 +}
    3.82 +
    3.83 +void
    3.84 +ia64_patch_imm60 (u64 insn_addr, u64 val)
    3.85 +{
    3.86 +	/* The assembler may generate offset pointing to either slot 1
    3.87 +	   or slot 2 for a long (2-slot) instruction, occupying slots 1
    3.88 +	   and 2.  */
    3.89 +  	insn_addr &= -16UL;
    3.90 +	ia64_patch(insn_addr + 2,
    3.91 +		   0x011ffffe000UL, (  ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
    3.92 +				     | ((val & 0x00000000000fffffUL) << 13) /* bit  0 -> 13 */));
    3.93 +	ia64_patch(insn_addr + 1, 0x1fffffffffcUL, val >> 18);
    3.94 +}
    3.95 +
    3.96 +/*
    3.97 + * We need sometimes to load the physical address of a kernel
    3.98 + * object.  Often we can convert the virtual address to physical
    3.99 + * at execution time, but sometimes (either for performance reasons
   3.100 + * or during error recovery) we cannot to this.  Patch the marked
   3.101 + * bundles to load the physical address.
   3.102 + */
   3.103 +void __init
   3.104 +ia64_patch_vtop (unsigned long start, unsigned long end)
   3.105 +{
   3.106 +	s32 *offp = (s32 *) start;
   3.107 +	u64 ip;
   3.108 +
   3.109 +	while (offp < (s32 *) end) {
   3.110 +		ip = (u64) offp + *offp;
   3.111 +
   3.112 +		/* replace virtual address with corresponding physical address: */
   3.113 +		ia64_patch_imm64(ip, ia64_tpa(get_imm64(ip)));
   3.114 +		ia64_fc((void *) ip);
   3.115 +		++offp;
   3.116 +	}
   3.117 +	ia64_sync_i();
   3.118 +	ia64_srlz_i();
   3.119 +}
   3.120 +
   3.121 +void
   3.122 +ia64_patch_mckinley_e9 (unsigned long start, unsigned long end)
   3.123 +{
   3.124 +	static int first_time = 1;
   3.125 +	int need_workaround;
   3.126 +	s32 *offp = (s32 *) start;
   3.127 +	u64 *wp;
   3.128 +
   3.129 +	need_workaround = (local_cpu_data->family == 0x1f && local_cpu_data->model == 0);
   3.130 +
   3.131 +	if (first_time) {
   3.132 +		first_time = 0;
   3.133 +		if (need_workaround)
   3.134 +			printk(KERN_INFO "Leaving McKinley Errata 9 workaround enabled\n");
   3.135 +		else
   3.136 +			printk(KERN_INFO "McKinley Errata 9 workaround not needed; "
   3.137 +			       "disabling it\n");
   3.138 +	}
   3.139 +	if (need_workaround)
   3.140 +		return;
   3.141 +
   3.142 +	while (offp < (s32 *) end) {
   3.143 +		wp = (u64 *) ia64_imva((char *) offp + *offp);
   3.144 +		wp[0] = 0x0000000100000000UL; /* nop.m 0; nop.i 0; nop.i 0 */
   3.145 +		wp[1] = 0x0004000000000200UL;
   3.146 +		wp[2] = 0x0000000100000011UL; /* nop.m 0; nop.i 0; br.ret.sptk.many b6 */
   3.147 +		wp[3] = 0x0084006880000200UL;
   3.148 +		ia64_fc(wp); ia64_fc(wp + 2);
   3.149 +		++offp;
   3.150 +	}
   3.151 +	ia64_sync_i();
   3.152 +	ia64_srlz_i();
   3.153 +}
   3.154 +
   3.155 +static void
   3.156 +patch_fsyscall_table (unsigned long start, unsigned long end)
   3.157 +{
   3.158 +	extern unsigned long fsyscall_table[NR_syscalls];
   3.159 +	s32 *offp = (s32 *) start;
   3.160 +	u64 ip;
   3.161 +
   3.162 +	while (offp < (s32 *) end) {
   3.163 +		ip = (u64) ia64_imva((char *) offp + *offp);
   3.164 +		ia64_patch_imm64(ip, (u64) fsyscall_table);
   3.165 +		ia64_fc((void *) ip);
   3.166 +		++offp;
   3.167 +	}
   3.168 +	ia64_sync_i();
   3.169 +	ia64_srlz_i();
   3.170 +}
   3.171 +
   3.172 +static void
   3.173 +patch_brl_fsys_bubble_down (unsigned long start, unsigned long end)
   3.174 +{
   3.175 +	extern char fsys_bubble_down[];
   3.176 +	s32 *offp = (s32 *) start;
   3.177 +	u64 ip;
   3.178 +
   3.179 +	while (offp < (s32 *) end) {
   3.180 +		ip = (u64) offp + *offp;
   3.181 +		ia64_patch_imm60((u64) ia64_imva((void *) ip),
   3.182 +				 (u64) (fsys_bubble_down - (ip & -16)) / 16);
   3.183 +		ia64_fc((void *) ip);
   3.184 +		++offp;
   3.185 +	}
   3.186 +	ia64_sync_i();
   3.187 +	ia64_srlz_i();
   3.188 +}
   3.189 +
   3.190 +void
   3.191 +ia64_patch_gate (void)
   3.192 +{
   3.193 +#	define START(name)	((unsigned long) __start_gate_##name##_patchlist)
   3.194 +#	define END(name)	((unsigned long)__end_gate_##name##_patchlist)
   3.195 +
   3.196 +	patch_fsyscall_table(START(fsyscall), END(fsyscall));
   3.197 +	patch_brl_fsys_bubble_down(START(brl_fsys_bubble_down), END(brl_fsys_bubble_down));
   3.198 +	ia64_patch_vtop(START(vtop), END(vtop));
   3.199 +	ia64_patch_mckinley_e9(START(mckinley_e9), END(mckinley_e9));
   3.200 +}