ia64/xen-unstable

changeset 16424:5e85709e998b

[SVM] handle MC threshold registers for Barcelona
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Nov 22 15:10:47 2007 +0000 (2007-11-22)
parents 66a7ff355762
children d3041196ae69
files xen/arch/x86/hvm/svm/svm.c
line diff
     1.1 --- a/xen/arch/x86/hvm/svm/svm.c	Thu Nov 22 14:16:25 2007 +0000
     1.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Thu Nov 22 15:10:47 2007 +0000
     1.3 @@ -133,6 +133,7 @@ static enum handler_return long_mode_do_
     1.4          break;
     1.5  
     1.6      case MSR_IA32_MC4_MISC: /* Threshold register */
     1.7 +    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
     1.8          /*
     1.9           * MCA/MCE: Threshold register is reported to be locked, so we ignore
    1.10           * all write accesses. This behaviour matches real HW, so guests should
    1.11 @@ -1777,6 +1778,7 @@ static void svm_do_msr_access(
    1.12              break;
    1.13  
    1.14          case MSR_IA32_MC4_MISC: /* Threshold register */
    1.15 +        case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
    1.16              /*
    1.17               * MCA/MCE: We report that the threshold register is unavailable
    1.18               * for OS use (locked by the BIOS).