ia64/xen-unstable

changeset 5461:5da30c7f9999

bitkeeper revision 1.1709.2.2 (42b056d09MvzQ-iWZrqZywIwiprXlw)

Enable VHPT for region 7
Signed-off-by: Dan Magenheimer <dan.magenheimer@hp.com>
author djm@kirby.fc.hp.com
date Wed Jun 15 16:26:56 2005 +0000 (2005-06-15)
parents e9bf6cebd37d
children cb924d6ba79d
files xen/arch/ia64/ivt.S xen/arch/ia64/regionreg.c xen/arch/ia64/vcpu.c xen/arch/ia64/vhpt.c xen/include/asm-ia64/vhpt.h
line diff
     1.1 --- a/xen/arch/ia64/ivt.S	Wed Jun 15 16:22:31 2005 +0000
     1.2 +++ b/xen/arch/ia64/ivt.S	Wed Jun 15 16:26:56 2005 +0000
     1.3 @@ -348,12 +348,23 @@ ENTRY(alt_itlb_miss)
     1.4  //	;;
     1.5  //#endif
     1.6  #endif
     1.7 +#ifdef XEN
     1.8 +	mov r31=pr
     1.9 +	mov r16=cr.ifa		// get address that caused the TLB miss
    1.10 +	;;
    1.11 +late_alt_itlb_miss:
    1.12 +	movl r17=PAGE_KERNEL
    1.13 +	mov r21=cr.ipsr
    1.14 +	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.15 +	;;
    1.16 +#else
    1.17  	mov r16=cr.ifa		// get address that caused the TLB miss
    1.18  	movl r17=PAGE_KERNEL
    1.19  	mov r21=cr.ipsr
    1.20  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.21  	mov r31=pr
    1.22  	;;
    1.23 +#endif
    1.24  #ifdef CONFIG_DISABLE_VHPT
    1.25  	shr.u r22=r16,61			// get the region number into r21
    1.26  	;;
    1.27 @@ -399,13 +410,18 @@ ENTRY(alt_dtlb_miss)
    1.28  //	;;
    1.29  //#endif
    1.30  #endif
    1.31 +#ifdef XEN
    1.32 +	mov r31=pr
    1.33  	mov r16=cr.ifa		// get address that caused the TLB miss
    1.34 +	;;
    1.35 +late_alt_dtlb_miss:
    1.36  	movl r17=PAGE_KERNEL
    1.37  	mov r20=cr.isr
    1.38  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.39  	mov r21=cr.ipsr
    1.40 -	mov r31=pr
    1.41  	;;
    1.42 +#else
    1.43 +#endif
    1.44  #ifdef CONFIG_DISABLE_VHPT
    1.45  	shr.u r22=r16,61			// get the region number into r21
    1.46  	;;
     2.1 --- a/xen/arch/ia64/regionreg.c	Wed Jun 15 16:22:31 2005 +0000
     2.2 +++ b/xen/arch/ia64/regionreg.c	Wed Jun 15 16:26:56 2005 +0000
     2.3 @@ -274,6 +274,7 @@ int set_one_rr(unsigned long rr, unsigne
     2.4  		return 0;
     2.5  	}
     2.6  
     2.7 +#ifdef CONFIG_VTI
     2.8  	memrrv.rrval = rrv.rrval;
     2.9  	if (rreg == 7) {
    2.10  		newrrv.rid = newrid;
    2.11 @@ -290,6 +291,15 @@ int set_one_rr(unsigned long rr, unsigne
    2.12  		if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval;
    2.13  		set_rr(rr,newrrv.rrval);
    2.14  	}
    2.15 +#else
    2.16 +	memrrv.rrval = rrv.rrval;
    2.17 +	newrrv.rid = newrid;
    2.18 +	newrrv.ve = 1;  // VHPT now enabled for region 7!!
    2.19 +	newrrv.ps = PAGE_SHIFT;
    2.20 +	if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval;
    2.21 +	if (rreg == 7) ia64_new_rr7(vmMangleRID(newrrv.rrval),v->vcpu_info);
    2.22 +	else set_rr(rr,newrrv.rrval);
    2.23 +#endif
    2.24  	return 1;
    2.25  }
    2.26  
     3.1 --- a/xen/arch/ia64/vcpu.c	Wed Jun 15 16:22:31 2005 +0000
     3.2 +++ b/xen/arch/ia64/vcpu.c	Wed Jun 15 16:26:56 2005 +0000
     3.3 @@ -1589,7 +1589,8 @@ void vcpu_itc_no_srlz(VCPU *vcpu, UINT64
     3.4  		// addresses never get flushed.  More work needed if this
     3.5  		// ever happens.
     3.6  //printf("vhpt_insert(%p,%p,%p)\n",vaddr,pte,1L<<logps);
     3.7 -		vhpt_insert(vaddr,pte,logps<<2);
     3.8 +		if (logps > PAGE_SHIFT) vhpt_multiple_insert(vaddr,pte,logps);
     3.9 +		else vhpt_insert(vaddr,pte,logps<<2);
    3.10  	}
    3.11  	// even if domain pagesize is larger than PAGE_SIZE, just put
    3.12  	// PAGE_SIZE mapping in the vhpt for now, else purging is complicated
     4.1 --- a/xen/arch/ia64/vhpt.c	Wed Jun 15 16:22:31 2005 +0000
     4.2 +++ b/xen/arch/ia64/vhpt.c	Wed Jun 15 16:26:56 2005 +0000
     4.3 @@ -87,6 +87,37 @@ void vhpt_map(void)
     4.4  	ia64_srlz_i();
     4.5  }
     4.6  
     4.7 +void vhpt_multiple_insert(unsigned long vaddr, unsigned long pte, unsigned long logps)
     4.8 +{
     4.9 +	unsigned long mask = (1L << logps) - 1;
    4.10 +	int i;
    4.11 +
    4.12 +	if (logps-PAGE_SHIFT > 10) {
    4.13 +		// if this happens, we may want to revisit this algorithm
    4.14 +		printf("vhpt_multiple_insert:logps-PAGE_SHIFT>10,spinning..\n");
    4.15 +		while(1);
    4.16 +	}
    4.17 +	if (logps-PAGE_SHIFT > 2) {
    4.18 +		// FIXME: Should add counter here to see how often this
    4.19 +		//  happens (e.g. for 16MB pages!) and determine if it
    4.20 +		//  is a performance problem.  On a quick look, it takes
    4.21 +		//  about 39000 instrs for a 16MB page and it seems to occur
    4.22 +		//  only a few times/second, so OK for now.
    4.23 +		//  An alternate solution would be to just insert the one
    4.24 +		//  16KB in the vhpt (but with the full mapping)?
    4.25 +		//printf("vhpt_multiple_insert: logps-PAGE_SHIFT==%d,"
    4.26 +			//"va=%p, pa=%p, pa-masked=%p\n",
    4.27 +			//logps-PAGE_SHIFT,vaddr,pte&_PFN_MASK,
    4.28 +			//(pte&_PFN_MASK)&~mask);
    4.29 +	}
    4.30 +	vaddr &= ~mask;
    4.31 +	pte = ((pte & _PFN_MASK) & ~mask) | (pte & ~_PFN_MASK);
    4.32 +	for (i = 1L << (logps-PAGE_SHIFT); i > 0; i--) {
    4.33 +		vhpt_insert(vaddr,pte,logps<<2);
    4.34 +		vaddr += PAGE_SIZE;
    4.35 +	}
    4.36 +}
    4.37 +
    4.38  void vhpt_init(void)
    4.39  {
    4.40  	unsigned long vhpt_total_size, vhpt_alignment, vhpt_imva;
     5.1 --- a/xen/include/asm-ia64/vhpt.h	Wed Jun 15 16:22:31 2005 +0000
     5.2 +++ b/xen/include/asm-ia64/vhpt.h	Wed Jun 15 16:26:56 2005 +0000
     5.3 @@ -140,12 +140,20 @@ CC_##Name:;							\
     5.4  	mov r16 = cr.ifa;					\
     5.5  	movl r30 = int_counts;					\
     5.6  	;;							\
     5.7 +	extr.u r17=r16,59,5					\
     5.8 +	;;							\
     5.9 +	cmp.eq p6,p0=0x1e,r17;					\
    5.10 +(p6)	br.cond.spnt	.Alt_##Name				\
    5.11 +	;;							\
    5.12 +	cmp.eq p6,p0=0x1d,r17;					\
    5.13 +(p6)	br.cond.spnt	.Alt_##Name				\
    5.14 +	;;							\
    5.15  	thash r28 = r16;					\
    5.16  	adds  r30 = CAUSE_VHPT_CC_HANDLED << 3, r30;		\
    5.17  	;;							\
    5.18  	ttag r19 = r16;						\
    5.19 -	ld8 r27 = [r30];					\
    5.20 -	adds r17 = VLE_CCHAIN_OFFSET, r28;			\
    5.21 +ld8 r27 = [r30];					\
    5.22 +adds r17 = VLE_CCHAIN_OFFSET, r28;			\
    5.23  	;;							\
    5.24  	ld8 r17 = [r17];					\
    5.25  	;;							\
    5.26 @@ -192,6 +200,11 @@ CC_##Name:;							\
    5.27  	rfi;							\
    5.28  	;;							\
    5.29  								\
    5.30 +.Alt_##Name:;							\
    5.31 +	mov pr = r31, 0x1ffff;					\
    5.32 +	;;							\
    5.33 +	br.cond.sptk late_alt_##Name				\
    5.34 +	;;							\
    5.35  .Out_##Name:;							\
    5.36  	mov pr = r31, 0x1ffff;					\
    5.37  	;;							\