ia64/xen-unstable

changeset 15872:5ccf8bbf8628

x86: Clean up asm keyword usage (asm volatile rather than __asm__
__volatile__ in most places) and ensure we use volatile keyword
wherever we have an asm stmt that produces outputs but has other
unspecified side effects or dependencies other than the
explicitly-stated inputs.

Also added volatile in a few places where its not strictly necessary
but where it's unlikely to produce worse code and it makes our
intentions perfectly clear.

The original problem this patch fixes was tracked down by Joseph
Cihula <joseph.cihula@intel.com>.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Tue Sep 11 12:14:38 2007 +0100 (2007-09-11)
parents a657ebf8e418
children 7dfc9a7a0d4e
files xen/arch/x86/bitops.c xen/arch/x86/cpu/common.c xen/arch/x86/domain.c xen/arch/x86/time.c xen/arch/x86/traps.c xen/arch/x86/x86_64/traps.c xen/arch/x86/x86_emulate.c xen/include/asm-x86/bitops.h xen/include/asm-x86/byteorder.h xen/include/asm-x86/div64.h xen/include/asm-x86/processor.h
line diff
     1.1 --- a/xen/arch/x86/bitops.c	Tue Sep 11 11:21:44 2007 +0100
     1.2 +++ b/xen/arch/x86/bitops.c	Tue Sep 11 12:14:38 2007 +0100
     1.3 @@ -7,7 +7,7 @@ unsigned int __find_first_bit(
     1.4  {
     1.5      unsigned long d0, d1, res;
     1.6  
     1.7 -    __asm__ __volatile__ (
     1.8 +    asm volatile (
     1.9          "   xor %%eax,%%eax\n\t" /* also ensures ZF==1 if size==0 */
    1.10          "   repe; scas"__OS"\n\t"
    1.11          "   je 1f\n\t"
    1.12 @@ -34,8 +34,8 @@ unsigned int __find_next_bit(
    1.13      if ( bit != 0 )
    1.14      {
    1.15          /* Look for a bit in the first word. */
    1.16 -        __asm__ ( "bsf %1,%%"__OP"ax"
    1.17 -                  : "=a" (set) : "r" (*p >> bit), "0" (BITS_PER_LONG) );
    1.18 +        asm ( "bsf %1,%%"__OP"ax"
    1.19 +              : "=a" (set) : "r" (*p >> bit), "0" (BITS_PER_LONG) );
    1.20          if ( set < (BITS_PER_LONG - bit) )
    1.21              return (offset + set);
    1.22          offset += BITS_PER_LONG - bit;
    1.23 @@ -55,7 +55,7 @@ unsigned int __find_first_zero_bit(
    1.24  {
    1.25      unsigned long d0, d1, d2, res;
    1.26  
    1.27 -    __asm__ (
    1.28 +    asm volatile (
    1.29          "   xor %%edx,%%edx\n\t" /* also ensures ZF==1 if size==0 */
    1.30          "   repe; scas"__OS"\n\t"
    1.31          "   je 1f\n\t"
    1.32 @@ -83,7 +83,7 @@ unsigned int __find_next_zero_bit(
    1.33      if ( bit != 0 )
    1.34      {
    1.35          /* Look for zero in the first word. */
    1.36 -        __asm__ ( "bsf %1,%%"__OP"ax" : "=a" (set) : "r" (~(*p >> bit)) );
    1.37 +        asm ( "bsf %1,%%"__OP"ax" : "=a" (set) : "r" (~(*p >> bit)) );
    1.38          if ( set < (BITS_PER_LONG - bit) )
    1.39              return (offset + set);
    1.40          offset += BITS_PER_LONG - bit;
     2.1 --- a/xen/arch/x86/cpu/common.c	Tue Sep 11 11:21:44 2007 +0100
     2.2 +++ b/xen/arch/x86/cpu/common.c	Tue Sep 11 12:14:38 2007 +0100
     2.3 @@ -557,10 +557,10 @@ void __devinit cpu_init(void)
     2.4  
     2.5  	*(unsigned short *)(&gdt_load[0]) = LAST_RESERVED_GDT_BYTE;
     2.6  	*(unsigned long  *)(&gdt_load[2]) = GDT_VIRT_START(current);
     2.7 -	__asm__ __volatile__ ( "lgdt %0" : "=m" (gdt_load) );
     2.8 +	asm volatile ( "lgdt %0" : "=m" (gdt_load) );
     2.9  
    2.10  	/* No nested task. */
    2.11 -	__asm__("pushf ; andw $0xbfff,(%"__OP"sp) ; popf");
    2.12 +	asm volatile ("pushf ; andw $0xbfff,(%"__OP"sp) ; popf" );
    2.13  
    2.14  	/* Ensure FPU gets initialised for each domain. */
    2.15  	stts();
    2.16 @@ -579,10 +579,10 @@ void __devinit cpu_init(void)
    2.17  #endif
    2.18  	set_tss_desc(cpu,t);
    2.19  	load_TR(cpu);
    2.20 -	__asm__ __volatile__ ( "lldt %%ax" : : "a" (0) );
    2.21 +	asm volatile ( "lldt %%ax" : : "a" (0) );
    2.22  
    2.23  	/* Clear all 6 debug registers: */
    2.24 -#define CD(register) __asm__("mov %0,%%db" #register ::"r"(0UL) );
    2.25 +#define CD(register) asm volatile ( "mov %0,%%db" #register : : "r"(0UL) );
    2.26  	CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
    2.27  #undef CD
    2.28  
     3.1 --- a/xen/arch/x86/domain.c	Tue Sep 11 11:21:44 2007 +0100
     3.2 +++ b/xen/arch/x86/domain.c	Tue Sep 11 12:14:38 2007 +0100
     3.3 @@ -930,7 +930,7 @@ arch_do_vcpu_op(
     3.4  
     3.5  #define loadsegment(seg,value) ({               \
     3.6      int __r = 1;                                \
     3.7 -    __asm__ __volatile__ (                      \
     3.8 +    asm volatile (                              \
     3.9          "1: movl %k1,%%" #seg "\n2:\n"          \
    3.10          ".section .fixup,\"ax\"\n"              \
    3.11          "3: xorl %k0,%k0\n"                     \
    3.12 @@ -1017,7 +1017,7 @@ static void load_segments(struct vcpu *n
    3.13  
    3.14          /* If in kernel mode then switch the GS bases around. */
    3.15          if ( (n->arch.flags & TF_kernel_mode) )
    3.16 -            __asm__ __volatile__ ( "swapgs" );
    3.17 +            asm volatile ( "swapgs" );
    3.18      }
    3.19  
    3.20      if ( unlikely(!all_segs_okay) )
    3.21 @@ -1190,7 +1190,7 @@ static void paravirt_ctxt_switch_to(stru
    3.22  }
    3.23  
    3.24  #define loaddebug(_v,_reg) \
    3.25 -    __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
    3.26 +    asm volatile ( "mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]) )
    3.27  
    3.28  static void __context_switch(void)
    3.29  {
    3.30 @@ -1242,7 +1242,7 @@ static void __context_switch(void)
    3.31          char gdt_load[10];
    3.32          *(unsigned short *)(&gdt_load[0]) = LAST_RESERVED_GDT_BYTE;
    3.33          *(unsigned long  *)(&gdt_load[2]) = GDT_VIRT_START(n);
    3.34 -        __asm__ __volatile__ ( "lgdt %0" : "=m" (gdt_load) );
    3.35 +        asm volatile ( "lgdt %0" : "=m" (gdt_load) );
    3.36      }
    3.37  
    3.38      if ( p->domain != n->domain )
     4.1 --- a/xen/arch/x86/time.c	Tue Sep 11 11:21:44 2007 +0100
     4.2 +++ b/xen/arch/x86/time.c	Tue Sep 11 12:14:38 2007 +0100
     4.3 @@ -89,7 +89,7 @@ static inline u32 div_frac(u32 dividend,
     4.4  {
     4.5      u32 quotient, remainder;
     4.6      ASSERT(dividend < divisor);
     4.7 -    __asm__ ( 
     4.8 +    asm ( 
     4.9          "divl %4"
    4.10          : "=a" (quotient), "=d" (remainder)
    4.11          : "0" (0), "1" (dividend), "r" (divisor) );
    4.12 @@ -103,7 +103,7 @@ static inline u32 div_frac(u32 dividend,
    4.13  static inline u32 mul_frac(u32 multiplicand, u32 multiplier)
    4.14  {
    4.15      u32 product_int, product_frac;
    4.16 -    __asm__ (
    4.17 +    asm (
    4.18          "mul %3"
    4.19          : "=a" (product_frac), "=d" (product_int)
    4.20          : "0" (multiplicand), "r" (multiplier) );
    4.21 @@ -127,7 +127,7 @@ static inline u64 scale_delta(u64 delta,
    4.22          delta <<= scale->shift;
    4.23  
    4.24  #ifdef CONFIG_X86_32
    4.25 -    __asm__ (
    4.26 +    asm (
    4.27          "mul  %5       ; "
    4.28          "mov  %4,%%eax ; "
    4.29          "mov  %%edx,%4 ; "
    4.30 @@ -138,7 +138,7 @@ static inline u64 scale_delta(u64 delta,
    4.31          : "=A" (product), "=r" (tmp1), "=r" (tmp2)
    4.32          : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (scale->mul_frac) );
    4.33  #else
    4.34 -    __asm__ (
    4.35 +    asm (
    4.36          "mul %%rdx ; shrd $32,%%rdx,%%rax"
    4.37          : "=a" (product) : "0" (delta), "d" ((u64)scale->mul_frac) );
    4.38  #endif
     5.1 --- a/xen/arch/x86/traps.c	Tue Sep 11 11:21:44 2007 +0100
     5.2 +++ b/xen/arch/x86/traps.c	Tue Sep 11 12:14:38 2007 +0100
     5.3 @@ -597,7 +597,7 @@ static int emulate_forced_invalid_op(str
     5.4          return 0;
     5.5      eip += sizeof(instr);
     5.6  
     5.7 -    __asm__ ( 
     5.8 +    asm ( 
     5.9          "cpuid"
    5.10          : "=a" (a), "=b" (b), "=c" (c), "=d" (d)
    5.11          : "0" (a), "1" (b), "2" (c), "3" (d) );
    5.12 @@ -1090,20 +1090,25 @@ static int read_descriptor(unsigned int 
    5.13      *ar = desc.b & 0x00f0ff00;
    5.14      if ( !(desc.b & _SEGMENT_L) )
    5.15      {
    5.16 -        *base = (desc.a >> 16) + ((desc.b & 0xff) << 16) + (desc.b & 0xff000000);
    5.17 +        *base = ((desc.a >> 16) + ((desc.b & 0xff) << 16) +
    5.18 +                 (desc.b & 0xff000000));
    5.19          *limit = (desc.a & 0xffff) | (desc.b & 0x000f0000);
    5.20          if ( desc.b & _SEGMENT_G )
    5.21              *limit = ((*limit + 1) << 12) - 1;
    5.22  #ifndef NDEBUG
    5.23 -        if ( !vm86_mode(regs) && sel > 3 )
    5.24 +        if ( !vm86_mode(regs) && (sel > 3) )
    5.25          {
    5.26              unsigned int a, l;
    5.27              unsigned char valid;
    5.28  
    5.29 -            __asm__("larl %2, %0\n\tsetz %1" : "=r" (a), "=rm" (valid) : "rm" (sel));
    5.30 -            BUG_ON(valid && (a & 0x00f0ff00) != *ar);
    5.31 -            __asm__("lsll %2, %0\n\tsetz %1" : "=r" (l), "=rm" (valid) : "rm" (sel));
    5.32 -            BUG_ON(valid && l != *limit);
    5.33 +            asm volatile (
    5.34 +                "larl %2,%0 ; setz %1"
    5.35 +                : "=r" (a), "=rm" (valid) : "rm" (sel));
    5.36 +            BUG_ON(valid && ((a & 0x00f0ff00) != *ar));
    5.37 +            asm volatile (
    5.38 +                "lsll %2,%0 ; setz %1"
    5.39 +                : "=r" (l), "=rm" (valid) : "rm" (sel));
    5.40 +            BUG_ON(valid && (l != *limit));
    5.41          }
    5.42  #endif
    5.43      }
    5.44 @@ -2011,13 +2016,13 @@ asmlinkage int do_debug(struct cpu_user_
    5.45      unsigned long condition;
    5.46      struct vcpu *v = current;
    5.47  
    5.48 -    __asm__ __volatile__("mov %%db6,%0" : "=r" (condition));
    5.49 +    asm volatile ( "mov %%db6,%0" : "=r" (condition) );
    5.50  
    5.51      /* Mask out spurious debug traps due to lazy DR7 setting */
    5.52      if ( (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)) &&
    5.53           (v->arch.guest_context.debugreg[7] == 0) )
    5.54      {
    5.55 -        __asm__("mov %0,%%db7" : : "r" (0UL));
    5.56 +        asm volatile ( "mov %0,%%db7" : : "r" (0UL) );
    5.57          goto out;
    5.58      }
    5.59  
    5.60 @@ -2186,25 +2191,25 @@ long set_debugreg(struct vcpu *p, int re
    5.61          if ( !access_ok(value, sizeof(long)) )
    5.62              return -EPERM;
    5.63          if ( p == current ) 
    5.64 -            __asm__ ( "mov %0, %%db0" : : "r" (value) );
    5.65 +            asm volatile ( "mov %0, %%db0" : : "r" (value) );
    5.66          break;
    5.67      case 1: 
    5.68          if ( !access_ok(value, sizeof(long)) )
    5.69              return -EPERM;
    5.70          if ( p == current ) 
    5.71 -            __asm__ ( "mov %0, %%db1" : : "r" (value) );
    5.72 +            asm volatile ( "mov %0, %%db1" : : "r" (value) );
    5.73          break;
    5.74      case 2: 
    5.75          if ( !access_ok(value, sizeof(long)) )
    5.76              return -EPERM;
    5.77          if ( p == current ) 
    5.78 -            __asm__ ( "mov %0, %%db2" : : "r" (value) );
    5.79 +            asm volatile ( "mov %0, %%db2" : : "r" (value) );
    5.80          break;
    5.81      case 3:
    5.82          if ( !access_ok(value, sizeof(long)) )
    5.83              return -EPERM;
    5.84          if ( p == current ) 
    5.85 -            __asm__ ( "mov %0, %%db3" : : "r" (value) );
    5.86 +            asm volatile ( "mov %0, %%db3" : : "r" (value) );
    5.87          break;
    5.88      case 6:
    5.89          /*
    5.90 @@ -2214,7 +2219,7 @@ long set_debugreg(struct vcpu *p, int re
    5.91          value &= 0xffffefff; /* reserved bits => 0 */
    5.92          value |= 0xffff0ff0; /* reserved bits => 1 */
    5.93          if ( p == current ) 
    5.94 -            __asm__ ( "mov %0, %%db6" : : "r" (value) );
    5.95 +            asm volatile ( "mov %0, %%db6" : : "r" (value) );
    5.96          break;
    5.97      case 7:
    5.98          /*
    5.99 @@ -2235,7 +2240,7 @@ long set_debugreg(struct vcpu *p, int re
   5.100                  if ( ((value >> (i+16)) & 3) == 2 ) return -EPERM;
   5.101          }
   5.102          if ( p == current ) 
   5.103 -            __asm__ ( "mov %0, %%db7" : : "r" (value) );
   5.104 +            asm volatile ( "mov %0, %%db7" : : "r" (value) );
   5.105          break;
   5.106      default:
   5.107          return -EINVAL;
     6.1 --- a/xen/arch/x86/x86_64/traps.c	Tue Sep 11 11:21:44 2007 +0100
     6.2 +++ b/xen/arch/x86/x86_64/traps.c	Tue Sep 11 12:14:38 2007 +0100
     6.3 @@ -149,7 +149,7 @@ asmlinkage void do_double_fault(struct c
     6.4  {
     6.5      unsigned int cpu, tr;
     6.6  
     6.7 -    asm ( "str %0" : "=r" (tr) );
     6.8 +    asm volatile ( "str %0" : "=r" (tr) );
     6.9      cpu = ((tr >> 3) - __FIRST_TSS_ENTRY) >> 2;
    6.10  
    6.11      watchdog_disable();
    6.12 @@ -185,11 +185,11 @@ void toggle_guest_mode(struct vcpu *v)
    6.13      if ( is_pv_32bit_vcpu(v) )
    6.14          return;
    6.15      v->arch.flags ^= TF_kernel_mode;
    6.16 -    __asm__ __volatile__ ( "swapgs" );
    6.17 +    asm volatile ( "swapgs" );
    6.18      update_cr3(v);
    6.19  #ifdef USER_MAPPINGS_ARE_GLOBAL
    6.20      /* Don't flush user global mappings from the TLB. Don't tick TLB clock. */
    6.21 -    __asm__ __volatile__ ( "mov %0, %%cr3" : : "r" (v->arch.cr3) : "memory" );
    6.22 +    asm volatile ( "mov %0, %%cr3" : : "r" (v->arch.cr3) : "memory" );
    6.23  #else
    6.24      write_ptbase(v);
    6.25  #endif
     7.1 --- a/xen/arch/x86/x86_emulate.c	Tue Sep 11 11:21:44 2007 +0100
     7.2 +++ b/xen/arch/x86/x86_emulate.c	Tue Sep 11 12:14:38 2007 +0100
     7.3 @@ -329,7 +329,7 @@ do{ unsigned long _tmp;                 
     7.4      switch ( (_dst).bytes )                                                \
     7.5      {                                                                      \
     7.6      case 2:                                                                \
     7.7 -        __asm__ __volatile__ (                                             \
     7.8 +        asm volatile (                                                     \
     7.9              _PRE_EFLAGS("0","4","2")                                       \
    7.10              _op"w %"_wx"3,%1; "                                            \
    7.11              _POST_EFLAGS("0","4","2")                                      \
    7.12 @@ -338,7 +338,7 @@ do{ unsigned long _tmp;                 
    7.13                "m" (_eflags), "m" ((_dst).val) );                           \
    7.14          break;                                                             \
    7.15      case 4:                                                                \
    7.16 -        __asm__ __volatile__ (                                             \
    7.17 +        asm volatile (                                                     \
    7.18              _PRE_EFLAGS("0","4","2")                                       \
    7.19              _op"l %"_lx"3,%1; "                                            \
    7.20              _POST_EFLAGS("0","4","2")                                      \
    7.21 @@ -356,7 +356,7 @@ do{ unsigned long _tmp;                 
    7.22      switch ( (_dst).bytes )                                                \
    7.23      {                                                                      \
    7.24      case 1:                                                                \
    7.25 -        __asm__ __volatile__ (                                             \
    7.26 +        asm volatile (                                                     \
    7.27              _PRE_EFLAGS("0","4","2")                                       \
    7.28              _op"b %"_bx"3,%1; "                                            \
    7.29              _POST_EFLAGS("0","4","2")                                      \
    7.30 @@ -388,7 +388,7 @@ do{ unsigned long _tmp;                 
    7.31      switch ( (_dst).bytes )                                                \
    7.32      {                                                                      \
    7.33      case 1:                                                                \
    7.34 -        __asm__ __volatile__ (                                             \
    7.35 +        asm volatile (                                                     \
    7.36              _PRE_EFLAGS("0","3","2")                                       \
    7.37              _op"b %1; "                                                    \
    7.38              _POST_EFLAGS("0","3","2")                                      \
    7.39 @@ -396,7 +396,7 @@ do{ unsigned long _tmp;                 
    7.40              : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) );        \
    7.41          break;                                                             \
    7.42      case 2:                                                                \
    7.43 -        __asm__ __volatile__ (                                             \
    7.44 +        asm volatile (                                                     \
    7.45              _PRE_EFLAGS("0","3","2")                                       \
    7.46              _op"w %1; "                                                    \
    7.47              _POST_EFLAGS("0","3","2")                                      \
    7.48 @@ -404,7 +404,7 @@ do{ unsigned long _tmp;                 
    7.49              : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) );        \
    7.50          break;                                                             \
    7.51      case 4:                                                                \
    7.52 -        __asm__ __volatile__ (                                             \
    7.53 +        asm volatile (                                                     \
    7.54              _PRE_EFLAGS("0","3","2")                                       \
    7.55              _op"l %1; "                                                    \
    7.56              _POST_EFLAGS("0","3","2")                                      \
    7.57 @@ -420,7 +420,7 @@ do{ unsigned long _tmp;                 
    7.58  /* Emulate an instruction with quadword operands (x86/64 only). */
    7.59  #if defined(__x86_64__)
    7.60  #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)         \
    7.61 -do{ __asm__ __volatile__ (                                              \
    7.62 +do{ asm volatile (                                                      \
    7.63          _PRE_EFLAGS("0","4","2")                                        \
    7.64          _op"q %"_qx"3,%1; "                                             \
    7.65          _POST_EFLAGS("0","4","2")                                       \
    7.66 @@ -429,7 +429,7 @@ do{ __asm__ __volatile__ (              
    7.67            "m" (_eflags), "m" ((_dst).val) );                            \
    7.68  } while (0)
    7.69  #define __emulate_1op_8byte(_op, _dst, _eflags)                         \
    7.70 -do{ __asm__ __volatile__ (                                              \
    7.71 +do{ asm volatile (                                                      \
    7.72          _PRE_EFLAGS("0","3","2")                                        \
    7.73          _op"q %1; "                                                     \
    7.74          _POST_EFLAGS("0","3","2")                                       \
    7.75 @@ -480,7 +480,7 @@ do {                                    
    7.76  /* Given byte has even parity (even number of 1s)? */
    7.77  static int even_parity(uint8_t v)
    7.78  {
    7.79 -    __asm__ ( "test %%al,%%al; setp %%al"
    7.80 +    asm ( "test %%al,%%al; setp %%al"
    7.81                : "=a" (v) : "0" (v) );
    7.82      return v;
    7.83  }
    7.84 @@ -2402,11 +2402,11 @@ x86_emulate(
    7.85              break;
    7.86          case 4:
    7.87  #ifdef __x86_64__
    7.88 -            __asm__ ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) );
    7.89 +            asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) );
    7.90              break;
    7.91          case 8:
    7.92  #endif
    7.93 -            __asm__ ( "bswap %0" : "=r" (dst.val) : "0" (*dst.reg) );
    7.94 +            asm ( "bswap %0" : "=r" (dst.val) : "0" (*dst.reg) );
    7.95              break;
    7.96          }
    7.97          break;
     8.1 --- a/xen/include/asm-x86/bitops.h	Tue Sep 11 11:21:44 2007 +0100
     8.2 +++ b/xen/include/asm-x86/bitops.h	Tue Sep 11 12:14:38 2007 +0100
     8.3 @@ -164,7 +164,7 @@ static __inline__ int __test_and_set_bit
     8.4  {
     8.5  	int oldbit;
     8.6  
     8.7 -	__asm__(
     8.8 +	__asm__ __volatile__(
     8.9  		"btsl %2,%1\n\tsbbl %0,%0"
    8.10  		:"=r" (oldbit),"=m" (ADDR)
    8.11  		:"dIr" (nr), "m" (ADDR) : "memory");
    8.12 @@ -203,7 +203,7 @@ static __inline__ int __test_and_clear_b
    8.13  {
    8.14  	int oldbit;
    8.15  
    8.16 -	__asm__(
    8.17 +	__asm__ __volatile__(
    8.18  		"btrl %2,%1\n\tsbbl %0,%0"
    8.19  		:"=r" (oldbit),"=m" (ADDR)
    8.20  		:"dIr" (nr), "m" (ADDR) : "memory");
     9.1 --- a/xen/include/asm-x86/byteorder.h	Tue Sep 11 11:21:44 2007 +0100
     9.2 +++ b/xen/include/asm-x86/byteorder.h	Tue Sep 11 12:14:38 2007 +0100
     9.3 @@ -20,7 +20,7 @@ static inline __attribute_const__ __u64 
     9.4      asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1" 
     9.5          : "=r" (v.s.a), "=r" (v.s.b) 
     9.6          : "0" (v.s.a), "1" (v.s.b)); 
     9.7 -    return v.u;	
     9.8 +    return v.u;
     9.9  } 
    9.10  
    9.11  /* Do not define swab16.  Gcc is smart enough to recognize "C" version and
    10.1 --- a/xen/include/asm-x86/div64.h	Tue Sep 11 11:21:44 2007 +0100
    10.2 +++ b/xen/include/asm-x86/div64.h	Tue Sep 11 12:14:38 2007 +0100
    10.3 @@ -5,13 +5,13 @@
    10.4  
    10.5  #if BITS_PER_LONG == 64
    10.6  
    10.7 -# define do_div(n,base) ({					\
    10.8 -	uint32_t __base = (base);				\
    10.9 -	uint32_t __rem;						\
   10.10 -	__rem = ((uint64_t)(n)) % __base;			\
   10.11 -	(n) = ((uint64_t)(n)) / __base;				\
   10.12 -	__rem;							\
   10.13 - })
   10.14 +#define do_div(n,base) ({                       \
   10.15 +    uint32_t __base = (base);                   \
   10.16 +    uint32_t __rem;                             \
   10.17 +    __rem = ((uint64_t)(n)) % __base;           \
   10.18 +    (n) = ((uint64_t)(n)) / __base;             \
   10.19 +    __rem;                                      \
   10.20 +})
   10.21  
   10.22  #else
   10.23  
   10.24 @@ -27,18 +27,21 @@
   10.25   * This ends up being the most efficient "calling
   10.26   * convention" on x86.
   10.27   */
   10.28 -#define do_div(n,base) ({ \
   10.29 -	unsigned long __upper, __low, __high, __mod, __base; \
   10.30 -	__base = (base); \
   10.31 -	asm("":"=a" (__low), "=d" (__high):"A" (n)); \
   10.32 -	__upper = __high; \
   10.33 -	if (__high) { \
   10.34 -		__upper = __high % (__base); \
   10.35 -		__high = __high / (__base); \
   10.36 -	} \
   10.37 -	asm("divl %2":"=a" (__low), "=d" (__mod):"rm" (__base), "0" (__low), "1" (__upper)); \
   10.38 -	asm("":"=A" (n):"a" (__low),"d" (__high)); \
   10.39 -	__mod; \
   10.40 +#define do_div(n,base) ({                                       \
   10.41 +    unsigned long __upper, __low, __high, __mod, __base;        \
   10.42 +    __base = (base);                                            \
   10.43 +    asm ( "" : "=a" (__low), "=d" (__high) : "A" (n) );         \
   10.44 +    __upper = __high;                                           \
   10.45 +    if ( __high )                                               \
   10.46 +    {                                                           \
   10.47 +        __upper = __high % (__base);                            \
   10.48 +        __high = __high / (__base);                             \
   10.49 +    }                                                           \
   10.50 +    asm ( "divl %2"                                             \
   10.51 +          : "=a" (__low), "=d" (__mod)                          \
   10.52 +          : "rm" (__base), "0" (__low), "1" (__upper) );        \
   10.53 +    asm ( "" : "=A" (n) : "a" (__low), "d" (__high) );          \
   10.54 +    __mod;                                                      \
   10.55  })
   10.56  
   10.57  #endif
    11.1 --- a/xen/include/asm-x86/processor.h	Tue Sep 11 11:21:44 2007 +0100
    11.2 +++ b/xen/include/asm-x86/processor.h	Tue Sep 11 12:14:38 2007 +0100
    11.3 @@ -146,10 +146,17 @@ struct vcpu;
    11.4   * instruction pointer ("program counter").
    11.5   */
    11.6  #ifdef __x86_64__
    11.7 -#define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
    11.8 +#define current_text_addr() ({                      \
    11.9 +    void *pc;                                       \
   11.10 +    asm ( "leaq 1f(%%rip),%0\n1:" : "=r" (pc) );    \
   11.11 +    pc;                                             \
   11.12 +})
   11.13  #else
   11.14 -#define current_text_addr() \
   11.15 -  ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
   11.16 +#define current_text_addr() ({                  \
   11.17 +    void *pc;                                   \
   11.18 +    asm ( "movl $1f,%0\n1:" : "=g" (pc) );      \
   11.19 +    pc;                                         \
   11.20 +})
   11.21  #endif
   11.22  
   11.23  struct cpuinfo_x86 {
   11.24 @@ -211,12 +218,12 @@ static always_inline void detect_ht(stru
   11.25   * resulting in stale register contents being returned.
   11.26   */
   11.27  #define cpuid(_op,_eax,_ebx,_ecx,_edx)          \
   11.28 -    __asm__("cpuid"                             \
   11.29 -            : "=a" (*(int *)(_eax)),            \
   11.30 -              "=b" (*(int *)(_ebx)),            \
   11.31 -              "=c" (*(int *)(_ecx)),            \
   11.32 -              "=d" (*(int *)(_edx))             \
   11.33 -            : "0" (_op), "2" (0))
   11.34 +    asm ( "cpuid"                               \
   11.35 +          : "=a" (*(int *)(_eax)),              \
   11.36 +            "=b" (*(int *)(_ebx)),              \
   11.37 +            "=c" (*(int *)(_ecx)),              \
   11.38 +            "=d" (*(int *)(_edx))               \
   11.39 +          : "0" (_op), "2" (0) )
   11.40  
   11.41  /* Some CPUID calls want 'count' to be placed in ecx */
   11.42  static inline void cpuid_count(
   11.43 @@ -227,9 +234,9 @@ static inline void cpuid_count(
   11.44      unsigned int *ecx,
   11.45      unsigned int *edx)
   11.46  {
   11.47 -    __asm__("cpuid"
   11.48 -            : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
   11.49 -            : "0" (op), "c" (count));
   11.50 +    asm ( "cpuid"
   11.51 +          : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
   11.52 +          : "0" (op), "c" (count) );
   11.53  }
   11.54  
   11.55  /*
   11.56 @@ -239,81 +246,81 @@ static always_inline unsigned int cpuid_
   11.57  {
   11.58      unsigned int eax;
   11.59  
   11.60 -    __asm__("cpuid"
   11.61 -            : "=a" (eax)
   11.62 -            : "0" (op)
   11.63 -            : "bx", "cx", "dx");
   11.64 +    asm ( "cpuid"
   11.65 +          : "=a" (eax)
   11.66 +          : "0" (op)
   11.67 +          : "bx", "cx", "dx" );
   11.68      return eax;
   11.69  }
   11.70 +
   11.71  static always_inline unsigned int cpuid_ebx(unsigned int op)
   11.72  {
   11.73      unsigned int eax, ebx;
   11.74  
   11.75 -    __asm__("cpuid"
   11.76 -            : "=a" (eax), "=b" (ebx)
   11.77 -            : "0" (op)
   11.78 -            : "cx", "dx" );
   11.79 +    asm ( "cpuid"
   11.80 +          : "=a" (eax), "=b" (ebx)
   11.81 +          : "0" (op)
   11.82 +          : "cx", "dx" );
   11.83      return ebx;
   11.84  }
   11.85 +
   11.86  static always_inline unsigned int cpuid_ecx(unsigned int op)
   11.87  {
   11.88      unsigned int eax, ecx;
   11.89  
   11.90 -    __asm__("cpuid"
   11.91 -            : "=a" (eax), "=c" (ecx)
   11.92 -            : "0" (op)
   11.93 -            : "bx", "dx" );
   11.94 +    asm ( "cpuid"
   11.95 +          : "=a" (eax), "=c" (ecx)
   11.96 +          : "0" (op)
   11.97 +          : "bx", "dx" );
   11.98      return ecx;
   11.99  }
  11.100 +
  11.101  static always_inline unsigned int cpuid_edx(unsigned int op)
  11.102  {
  11.103      unsigned int eax, edx;
  11.104  
  11.105 -    __asm__("cpuid"
  11.106 -            : "=a" (eax), "=d" (edx)
  11.107 -            : "0" (op)
  11.108 -            : "bx", "cx");
  11.109 +    asm ( "cpuid"
  11.110 +          : "=a" (eax), "=d" (edx)
  11.111 +          : "0" (op)
  11.112 +          : "bx", "cx" );
  11.113      return edx;
  11.114  }
  11.115  
  11.116 -
  11.117 -
  11.118  static inline unsigned long read_cr0(void)
  11.119  {
  11.120 -    unsigned long __cr0;
  11.121 -    __asm__("mov %%cr0,%0\n\t" :"=r" (__cr0));
  11.122 -    return __cr0;
  11.123 +    unsigned long cr0;
  11.124 +    asm volatile ( "mov %%cr0,%0\n\t" : "=r" (cr0) );
  11.125 +    return cr0;
  11.126  } 
  11.127  
  11.128  static inline void write_cr0(unsigned long val)
  11.129  {
  11.130 -	__asm__("mov %0,%%cr0": :"r" ((unsigned long)val));
  11.131 +    asm volatile ( "mov %0,%%cr0" : : "r" ((unsigned long)val) );
  11.132  }
  11.133  
  11.134  static inline unsigned long read_cr2(void)
  11.135  {
  11.136 -    unsigned long __cr2;
  11.137 -    __asm__("mov %%cr2,%0\n\t" :"=r" (__cr2));
  11.138 -    return __cr2;
  11.139 +    unsigned long cr2;
  11.140 +    asm volatile ( "mov %%cr2,%0\n\t" : "=r" (cr2) );
  11.141 +    return cr2;
  11.142  }
  11.143  
  11.144  static inline unsigned long read_cr4(void)
  11.145  {
  11.146 -    unsigned long __cr4;
  11.147 -    __asm__("mov %%cr4,%0\n\t" :"=r" (__cr4));
  11.148 -    return __cr4;
  11.149 +    unsigned long cr4;
  11.150 +    asm volatile ( "mov %%cr4,%0\n\t" : "=r" (cr4) );
  11.151 +    return cr4;
  11.152  } 
  11.153      
  11.154  static inline void write_cr4(unsigned long val)
  11.155  {
  11.156 -	__asm__("mov %0,%%cr4": :"r" ((unsigned long)val));
  11.157 +    asm volatile ( "mov %0,%%cr4" : : "r" ((unsigned long)val) );
  11.158  }
  11.159  
  11.160 -
  11.161  /* Clear and set 'TS' bit respectively */
  11.162  static inline void clts(void) 
  11.163  {
  11.164 -    __asm__ __volatile__ ("clts");
  11.165 +    asm volatile ( "clts" );
  11.166  }
  11.167  
  11.168  static inline void stts(void) 
  11.169 @@ -321,7 +328,6 @@ static inline void stts(void)
  11.170      write_cr0(X86_CR0_TS|read_cr0());
  11.171  }
  11.172  
  11.173 -
  11.174  /*
  11.175   * Save the cr4 feature set we're using (ie
  11.176   * Pentium 4MB enable and PPro Global page
  11.177 @@ -363,32 +369,36 @@ static always_inline void set_in_cr4 (un
  11.178  #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
  11.179  
  11.180  #define setCx86(reg, data) do { \
  11.181 -	outb((reg), 0x22); \
  11.182 -	outb((data), 0x23); \
  11.183 +    outb((reg), 0x22); \
  11.184 +    outb((data), 0x23); \
  11.185  } while (0)
  11.186  
  11.187  /* Stop speculative execution */
  11.188  static inline void sync_core(void)
  11.189  {
  11.190      int tmp;
  11.191 -    asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
  11.192 +    asm volatile (
  11.193 +        "cpuid"
  11.194 +        : "=a" (tmp)
  11.195 +        : "0" (1)
  11.196 +        : "ebx","ecx","edx","memory" );
  11.197  }
  11.198  
  11.199  static always_inline void __monitor(const void *eax, unsigned long ecx,
  11.200 -		unsigned long edx)
  11.201 +                                    unsigned long edx)
  11.202  {
  11.203 -	/* "monitor %eax,%ecx,%edx;" */
  11.204 -	asm volatile(
  11.205 -		".byte 0x0f,0x01,0xc8;"
  11.206 -		: :"a" (eax), "c" (ecx), "d"(edx));
  11.207 +    /* "monitor %eax,%ecx,%edx;" */
  11.208 +    asm volatile (
  11.209 +        ".byte 0x0f,0x01,0xc8;"
  11.210 +        : : "a" (eax), "c" (ecx), "d"(edx) );
  11.211  }
  11.212  
  11.213  static always_inline void __mwait(unsigned long eax, unsigned long ecx)
  11.214  {
  11.215 -	/* "mwait %eax,%ecx;" */
  11.216 -	asm volatile(
  11.217 -		".byte 0x0f,0x01,0xc9;"
  11.218 -		: :"a" (eax), "c" (ecx));
  11.219 +    /* "mwait %eax,%ecx;" */
  11.220 +    asm volatile (
  11.221 +        ".byte 0x0f,0x01,0xc9;"
  11.222 +        : : "a" (eax), "c" (ecx) );
  11.223  }
  11.224  
  11.225  #define IOBMP_BYTES             8192
  11.226 @@ -509,7 +519,7 @@ struct extended_sigtable {
  11.227  /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
  11.228  static always_inline void rep_nop(void)
  11.229  {
  11.230 -    __asm__ __volatile__ ( "rep;nop" : : : "memory" );
  11.231 +    asm volatile ( "rep;nop" : : : "memory" );
  11.232  }
  11.233  
  11.234  #define cpu_relax() rep_nop()
  11.235 @@ -520,7 +530,7 @@ static always_inline void rep_nop(void)
  11.236  #define ARCH_HAS_PREFETCH
  11.237  extern always_inline void prefetch(const void *x)
  11.238  {
  11.239 -    __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
  11.240 +    asm volatile ( "prefetchnta (%0)" : : "r"(x) );
  11.241  }
  11.242  
  11.243  #elif CONFIG_X86_USE_3DNOW
  11.244 @@ -531,12 +541,12 @@ extern always_inline void prefetch(const
  11.245  
  11.246  extern always_inline void prefetch(const void *x)
  11.247  {
  11.248 -    __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
  11.249 +    asm volatile ( "prefetch (%0)" : : "r"(x) );
  11.250  }
  11.251  
  11.252  extern always_inline void prefetchw(const void *x)
  11.253  {
  11.254 -    __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
  11.255 +    asm volatile ( "prefetchw (%0)" : : "r"(x) );
  11.256  }
  11.257  #define spin_lock_prefetch(x)	prefetchw(x)
  11.258