1.1 --- a/xen/arch/ia64/xen/ivt.S	Tue Jul 22 12:15:02 2008 +0900
     1.2 +++ b/xen/arch/ia64/xen/ivt.S	Tue Jul 22 12:15:02 2008 +0900
     1.3 @@ -207,17 +207,37 @@ late_alt_dtlb_miss:
     1.4  (p8)	br.cond.sptk frametable_miss ;;
     1.5  #endif
     1.6  	// If it is not a Xen address, handle it via page_fault.
     1.7 +	//    !( ((r22 == 0x18 || r22 == 0x1c) && rr7 == XEN_EFI_RR) ||
     1.8 +	//	 r22 == 0x1e )
     1.9 +	// Note that rr7 == XEN_EFI_RR implies rr6 == XEN_EFI_RR
    1.10  	extr.u r22=r16,59,5
    1.11  	;;
    1.12  	dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN	// clear the key
    1.13 -	cmp.ne p8,p0=0x1e,r22
    1.14 -(p8)	br.cond.sptk page_fault
    1.15 +	movl r23=7 << 61
    1.16 +	;;
    1.17 +	mov r23=rr[r23]
    1.18 +	;;
    1.19 +	mov r25=XEN_EFI_RR
    1.20 +	cmp.eq p8,p0=0x18,r22		// 0xc...
    1.21  	;;
    1.22 +	cmp.eq.or p8,p0=0x1c,r22	// 0xe...
    1.23 +	;;
    1.24 +	cmp.eq.and p8,p0=r25,r23	// rr7 == XEN_EFI_RR
    1.25 +	;;
    1.26 +	cmp.eq.or p8,p0=0x1e,r22	// 0xf...
    1.27 +(p8)	br.cond.spnt alt_dtlb_miss_identity_map
    1.28 +	br.cond.spnt page_fault
    1.29 +	;;
    1.30 +alt_dtlb_miss_identity_map:
    1.31  	dep r21=-1,r21,IA64_PSR_ED_BIT,1
    1.32  	or r19=r19,r17		// insert PTE control bits into r19
    1.33  	mov cr.itir=r20		// set itir with cleared key
    1.34  	;;
    1.35 -	dep r19=r18,r19,4,1	// set bit 4 (uncached) if access to UC area
    1.36 +	cmp.ne p8,p0=r0,r18		// Xen UC bit set
    1.37 +	;;
    1.38 +	cmp.eq.or p8,p0=0x18,r22	// Region 6 is UC for EFI
    1.39 +	;;
    1.40 +(p8)	dep r19=-1,r19,4,1	// set bit 4 (uncached) if access to UC area
    1.41  (p6)	mov cr.ipsr=r21
    1.42  	;;
    1.43  (p7)	itc.d r19		// insert the TLB entry