ia64/xen-unstable

changeset 3596:578b6c14e635

bitkeeper revision 1.1159.212.61 (41ff4ae9QGwwPUv_OONjfk2SaSj0dw)

Merge scramble.cl.cam.ac.uk:/local/scratch/kaf24/xen-2.0-testing.bk
into scramble.cl.cam.ac.uk:/local/scratch/kaf24/xen-unstable.bk
author kaf24@scramble.cl.cam.ac.uk
date Tue Feb 01 09:24:57 2005 +0000 (2005-02-01)
parents fec8b1778268 a5f1a6abfc46
children ed902e5c4b49
files xen/arch/x86/traps.c xen/arch/x86/x86_32/asm-offsets.c xen/arch/x86/x86_32/entry.S xen/include/asm-x86/apicdef.h xen/include/asm-x86/processor.h
line diff
     1.1 --- a/xen/arch/x86/traps.c	Mon Jan 31 23:16:27 2005 +0000
     1.2 +++ b/xen/arch/x86/traps.c	Tue Feb 01 09:24:57 2005 +0000
     1.3 @@ -946,6 +946,7 @@ void __init trap_init(void)
     1.4      set_intr_gate(TRAP_alignment_check,&alignment_check);
     1.5      set_intr_gate(TRAP_machine_check,&machine_check);
     1.6      set_intr_gate(TRAP_simd_error,&simd_coprocessor_error);
     1.7 +    set_intr_gate(TRAP_deferred_nmi,&nmi);
     1.8  
     1.9      /* Only ring 1 can access Xen services. */
    1.10      _set_gate(idt_table+HYPERCALL_VECTOR,14,1,&hypercall);
     2.1 --- a/xen/arch/x86/x86_32/asm-offsets.c	Mon Jan 31 23:16:27 2005 +0000
     2.2 +++ b/xen/arch/x86/x86_32/asm-offsets.c	Tue Feb 01 09:24:57 2005 +0000
     2.3 @@ -65,4 +65,7 @@ void __dummy__(void)
     2.4      OFFSET(MULTICALL_arg3, multicall_entry_t, args[3]);
     2.5      OFFSET(MULTICALL_arg4, multicall_entry_t, args[4]);
     2.6      OFFSET(MULTICALL_result, multicall_entry_t, args[5]);
     2.7 +    BLANK();
     2.8 +
     2.9 +    DEFINE(FIXMAP_apic_base, fix_to_virt(FIX_APIC_BASE));
    2.10  }
     3.1 --- a/xen/arch/x86/x86_32/entry.S	Mon Jan 31 23:16:27 2005 +0000
     3.2 +++ b/xen/arch/x86/x86_32/entry.S	Tue Feb 01 09:24:57 2005 +0000
     3.3 @@ -57,6 +57,7 @@
     3.4  #include <xen/errno.h>
     3.5  #include <xen/softirq.h>
     3.6  #include <asm/asm_defns.h>
     3.7 +#include <asm/apicdef.h>
     3.8  #include <public/xen.h>
     3.9  
    3.10  #define GET_CURRENT(reg)   \
    3.11 @@ -605,10 +606,10 @@ ENTRY(nmi)
    3.12          jnz   do_watchdog_tick
    3.13          movl  %ds,%eax
    3.14          cmpw  $(__HYPERVISOR_DS),%ax
    3.15 -        jne   restore_all_xen
    3.16 +        jne   defer_nmi
    3.17          movl  %es,%eax
    3.18          cmpw  $(__HYPERVISOR_DS),%ax
    3.19 -        jne   restore_all_xen
    3.20 +        jne   defer_nmi
    3.21  
    3.22  do_watchdog_tick:
    3.23          movl  $(__HYPERVISOR_DS),%edx
    3.24 @@ -626,6 +627,17 @@ do_watchdog_tick:
    3.25          GET_CURRENT(%ebx)
    3.26          jmp   restore_all_guest
    3.27  
    3.28 +defer_nmi:
    3.29 +        movl  $FIXMAP_apic_base,%eax
    3.30 +        # apic_wait_icr_idle()
    3.31 +1:      movl  APIC_ICR(%eax),%ebx
    3.32 +        testl $APIC_ICR_BUSY,%ebx
    3.33 +        jnz   1b
    3.34 +        # __send_IPI_shortcut(APIC_DEST_SELF, TRAP_deferred_nmi)
    3.35 +        movl  $(APIC_DM_FIXED | APIC_DEST_SELF | APIC_DEST_LOGICAL | \
    3.36 +                TRAP_deferred_nmi),APIC_ICR(%eax)
    3.37 +        jmp   restore_all_xen
    3.38 +
    3.39  nmi_parity_err:
    3.40          # Clear and disable the parity-error line
    3.41          andb $0xf,%al
     4.1 --- a/xen/include/asm-x86/apicdef.h	Mon Jan 31 23:16:27 2005 +0000
     4.2 +++ b/xen/include/asm-x86/apicdef.h	Tue Feb 01 09:24:57 2005 +0000
     4.3 @@ -125,255 +125,4 @@
     4.4  #define APIC_BROADCAST_ID_XAPIC (0xFF)
     4.5  #define APIC_BROADCAST_ID_APIC  (0x0F)
     4.6  
     4.7 -/*
     4.8 - * the local APIC register structure, memory mapped. Not terribly well
     4.9 - * tested, but we might eventually use this one in the future - the
    4.10 - * problem why we cannot use it right now is the P5 APIC, it has an
    4.11 - * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
    4.12 - */
    4.13 -#define u32 unsigned int
    4.14 -
    4.15 -#define lapic ((volatile struct local_apic *)APIC_BASE)
    4.16 -
    4.17 -struct local_apic {
    4.18 -
    4.19 -/*000*/	struct { u32 __reserved[4]; } __reserved_01;
    4.20 -
    4.21 -/*010*/	struct { u32 __reserved[4]; } __reserved_02;
    4.22 -
    4.23 -/*020*/	struct { /* APIC ID Register */
    4.24 -		u32   __reserved_1	: 24,
    4.25 -			phys_apic_id	:  4,
    4.26 -			__reserved_2	:  4;
    4.27 -		u32 __reserved[3];
    4.28 -	} id;
    4.29 -
    4.30 -/*030*/	const
    4.31 -	struct { /* APIC Version Register */
    4.32 -		u32   version		:  8,
    4.33 -			__reserved_1	:  8,
    4.34 -			max_lvt		:  8,
    4.35 -			__reserved_2	:  8;
    4.36 -		u32 __reserved[3];
    4.37 -	} version;
    4.38 -
    4.39 -/*040*/	struct { u32 __reserved[4]; } __reserved_03;
    4.40 -
    4.41 -/*050*/	struct { u32 __reserved[4]; } __reserved_04;
    4.42 -
    4.43 -/*060*/	struct { u32 __reserved[4]; } __reserved_05;
    4.44 -
    4.45 -/*070*/	struct { u32 __reserved[4]; } __reserved_06;
    4.46 -
    4.47 -/*080*/	struct { /* Task Priority Register */
    4.48 -		u32   priority	:  8,
    4.49 -			__reserved_1	: 24;
    4.50 -		u32 __reserved_2[3];
    4.51 -	} tpr;
    4.52 -
    4.53 -/*090*/	const
    4.54 -	struct { /* Arbitration Priority Register */
    4.55 -		u32   priority	:  8,
    4.56 -			__reserved_1	: 24;
    4.57 -		u32 __reserved_2[3];
    4.58 -	} apr;
    4.59 -
    4.60 -/*0A0*/	const
    4.61 -	struct { /* Processor Priority Register */
    4.62 -		u32   priority	:  8,
    4.63 -			__reserved_1	: 24;
    4.64 -		u32 __reserved_2[3];
    4.65 -	} ppr;
    4.66 -
    4.67 -/*0B0*/	struct { /* End Of Interrupt Register */
    4.68 -		u32   eoi;
    4.69 -		u32 __reserved[3];
    4.70 -	} eoi;
    4.71 -
    4.72 -/*0C0*/	struct { u32 __reserved[4]; } __reserved_07;
    4.73 -
    4.74 -/*0D0*/	struct { /* Logical Destination Register */
    4.75 -		u32   __reserved_1	: 24,
    4.76 -			logical_dest	:  8;
    4.77 -		u32 __reserved_2[3];
    4.78 -	} ldr;
    4.79 -
    4.80 -/*0E0*/	struct { /* Destination Format Register */
    4.81 -		u32   __reserved_1	: 28,
    4.82 -			model		:  4;
    4.83 -		u32 __reserved_2[3];
    4.84 -	} dfr;
    4.85 -
    4.86 -/*0F0*/	struct { /* Spurious Interrupt Vector Register */
    4.87 -		u32	spurious_vector	:  8,
    4.88 -			apic_enabled	:  1,
    4.89 -			focus_cpu	:  1,
    4.90 -			__reserved_2	: 22;
    4.91 -		u32 __reserved_3[3];
    4.92 -	} svr;
    4.93 -
    4.94 -/*100*/	struct { /* In Service Register */
    4.95 -/*170*/		u32 bitfield;
    4.96 -		u32 __reserved[3];
    4.97 -	} isr [8];
    4.98 -
    4.99 -/*180*/	struct { /* Trigger Mode Register */
   4.100 -/*1F0*/		u32 bitfield;
   4.101 -		u32 __reserved[3];
   4.102 -	} tmr [8];
   4.103 -
   4.104 -/*200*/	struct { /* Interrupt Request Register */
   4.105 -/*270*/		u32 bitfield;
   4.106 -		u32 __reserved[3];
   4.107 -	} irr [8];
   4.108 -
   4.109 -/*280*/	union { /* Error Status Register */
   4.110 -		struct {
   4.111 -			u32   send_cs_error			:  1,
   4.112 -				receive_cs_error		:  1,
   4.113 -				send_accept_error		:  1,
   4.114 -				receive_accept_error		:  1,
   4.115 -				__reserved_1			:  1,
   4.116 -				send_illegal_vector		:  1,
   4.117 -				receive_illegal_vector		:  1,
   4.118 -				illegal_register_address	:  1,
   4.119 -				__reserved_2			: 24;
   4.120 -			u32 __reserved_3[3];
   4.121 -		} error_bits;
   4.122 -		struct {
   4.123 -			u32 errors;
   4.124 -			u32 __reserved_3[3];
   4.125 -		} all_errors;
   4.126 -	} esr;
   4.127 -
   4.128 -/*290*/	struct { u32 __reserved[4]; } __reserved_08;
   4.129 -
   4.130 -/*2A0*/	struct { u32 __reserved[4]; } __reserved_09;
   4.131 -
   4.132 -/*2B0*/	struct { u32 __reserved[4]; } __reserved_10;
   4.133 -
   4.134 -/*2C0*/	struct { u32 __reserved[4]; } __reserved_11;
   4.135 -
   4.136 -/*2D0*/	struct { u32 __reserved[4]; } __reserved_12;
   4.137 -
   4.138 -/*2E0*/	struct { u32 __reserved[4]; } __reserved_13;
   4.139 -
   4.140 -/*2F0*/	struct { u32 __reserved[4]; } __reserved_14;
   4.141 -
   4.142 -/*300*/	struct { /* Interrupt Command Register 1 */
   4.143 -		u32   vector			:  8,
   4.144 -			delivery_mode		:  3,
   4.145 -			destination_mode	:  1,
   4.146 -			delivery_status		:  1,
   4.147 -			__reserved_1		:  1,
   4.148 -			level			:  1,
   4.149 -			trigger			:  1,
   4.150 -			__reserved_2		:  2,
   4.151 -			shorthand		:  2,
   4.152 -			__reserved_3		:  12;
   4.153 -		u32 __reserved_4[3];
   4.154 -	} icr1;
   4.155 -
   4.156 -/*310*/	struct { /* Interrupt Command Register 2 */
   4.157 -		union {
   4.158 -			u32   __reserved_1	: 24,
   4.159 -				phys_dest	:  4,
   4.160 -				__reserved_2	:  4;
   4.161 -			u32   __reserved_3	: 24,
   4.162 -				logical_dest	:  8;
   4.163 -		} dest;
   4.164 -		u32 __reserved_4[3];
   4.165 -	} icr2;
   4.166 -
   4.167 -/*320*/	struct { /* LVT - Timer */
   4.168 -		u32   vector		:  8,
   4.169 -			__reserved_1	:  4,
   4.170 -			delivery_status	:  1,
   4.171 -			__reserved_2	:  3,
   4.172 -			mask		:  1,
   4.173 -			timer_mode	:  1,
   4.174 -			__reserved_3	: 14;
   4.175 -		u32 __reserved_4[3];
   4.176 -	} lvt_timer;
   4.177 -
   4.178 -/*330*/	struct { u32 __reserved[4]; } __reserved_15;
   4.179 -
   4.180 -/*340*/	struct { /* LVT - Performance Counter */
   4.181 -		u32   vector		:  8,
   4.182 -			delivery_mode	:  3,
   4.183 -			__reserved_1	:  1,
   4.184 -			delivery_status	:  1,
   4.185 -			__reserved_2	:  3,
   4.186 -			mask		:  1,
   4.187 -			__reserved_3	: 15;
   4.188 -		u32 __reserved_4[3];
   4.189 -	} lvt_pc;
   4.190 -
   4.191 -/*350*/	struct { /* LVT - LINT0 */
   4.192 -		u32   vector		:  8,
   4.193 -			delivery_mode	:  3,
   4.194 -			__reserved_1	:  1,
   4.195 -			delivery_status	:  1,
   4.196 -			polarity	:  1,
   4.197 -			remote_irr	:  1,
   4.198 -			trigger		:  1,
   4.199 -			mask		:  1,
   4.200 -			__reserved_2	: 15;
   4.201 -		u32 __reserved_3[3];
   4.202 -	} lvt_lint0;
   4.203 -
   4.204 -/*360*/	struct { /* LVT - LINT1 */
   4.205 -		u32   vector		:  8,
   4.206 -			delivery_mode	:  3,
   4.207 -			__reserved_1	:  1,
   4.208 -			delivery_status	:  1,
   4.209 -			polarity	:  1,
   4.210 -			remote_irr	:  1,
   4.211 -			trigger		:  1,
   4.212 -			mask		:  1,
   4.213 -			__reserved_2	: 15;
   4.214 -		u32 __reserved_3[3];
   4.215 -	} lvt_lint1;
   4.216 -
   4.217 -/*370*/	struct { /* LVT - Error */
   4.218 -		u32   vector		:  8,
   4.219 -			__reserved_1	:  4,
   4.220 -			delivery_status	:  1,
   4.221 -			__reserved_2	:  3,
   4.222 -			mask		:  1,
   4.223 -			__reserved_3	: 15;
   4.224 -		u32 __reserved_4[3];
   4.225 -	} lvt_error;
   4.226 -
   4.227 -/*380*/	struct { /* Timer Initial Count Register */
   4.228 -		u32   initial_count;
   4.229 -		u32 __reserved_2[3];
   4.230 -	} timer_icr;
   4.231 -
   4.232 -/*390*/	const
   4.233 -	struct { /* Timer Current Count Register */
   4.234 -		u32   curr_count;
   4.235 -		u32 __reserved_2[3];
   4.236 -	} timer_ccr;
   4.237 -
   4.238 -/*3A0*/	struct { u32 __reserved[4]; } __reserved_16;
   4.239 -
   4.240 -/*3B0*/	struct { u32 __reserved[4]; } __reserved_17;
   4.241 -
   4.242 -/*3C0*/	struct { u32 __reserved[4]; } __reserved_18;
   4.243 -
   4.244 -/*3D0*/	struct { u32 __reserved[4]; } __reserved_19;
   4.245 -
   4.246 -/*3E0*/	struct { /* Timer Divide Configuration Register */
   4.247 -		u32   divisor		:  4,
   4.248 -			__reserved_1	: 28;
   4.249 -		u32 __reserved_2[3];
   4.250 -	} timer_dcr;
   4.251 -
   4.252 -/*3F0*/	struct { u32 __reserved[4]; } __reserved_20;
   4.253 -
   4.254 -} __attribute__ ((packed));
   4.255 -
   4.256 -#undef u32
   4.257 -
   4.258  #endif
     5.1 --- a/xen/include/asm-x86/processor.h	Mon Jan 31 23:16:27 2005 +0000
     5.2 +++ b/xen/include/asm-x86/processor.h	Tue Feb 01 09:24:57 2005 +0000
     5.3 @@ -110,6 +110,7 @@
     5.4  #define TRAP_alignment_check 17
     5.5  #define TRAP_machine_check   18
     5.6  #define TRAP_simd_error      19
     5.7 +#define TRAP_deferred_nmi    31
     5.8  
     5.9  /*
    5.10   * Non-fatal fault/trap handlers return an error code to the caller. If the