ia64/xen-unstable

changeset 5059:569173be116f

bitkeeper revision 1.1494 (428e647cwMGQpFEvYX5LZ0S3SXAZVQ)

Read VMX configuration details from architectural registers.
Signed-off-by: Nitin Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Fri May 20 22:28:12 2005 +0000 (2005-05-20)
parents 85fcf3b1b7a5
children 2562daa95e37
files xen/arch/x86/vmx.c xen/arch/x86/vmx_vmcs.c xen/include/asm-x86/msr.h xen/include/asm-x86/vmx_vmcs.h
line diff
     1.1 --- a/xen/arch/x86/vmx.c	Fri May 20 22:18:38 2005 +0000
     1.2 +++ b/xen/arch/x86/vmx.c	Fri May 20 22:28:12 2005 +0000
     1.3 @@ -51,10 +51,10 @@ void do_nmi(struct cpu_user_regs *, unsi
     1.4  int start_vmx()
     1.5  {
     1.6      struct vmcs_struct *vmcs;
     1.7 -    unsigned long ecx;
     1.8 +    u32 ecx;
     1.9 +    u32 eax, edx;
    1.10      u64 phys_vmcs;      /* debugging */
    1.11  
    1.12 -    vmcs_size = VMCS_SIZE;
    1.13      /*
    1.14       * Xen does not fill x86_capability words except 0.
    1.15       */
    1.16 @@ -63,6 +63,18 @@ int start_vmx()
    1.17  
    1.18      if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
    1.19          return 0;
    1.20 + 
    1.21 +    rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
    1.22 +
    1.23 +    if (eax & IA32_FEATURE_CONTROL_MSR_LOCK) {
    1.24 +        if ((eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0) {
    1.25 +                printk("VMX disabled by Feature Control MSR.\n");
    1.26 +		return 0;
    1.27 +        }
    1.28 +    }
    1.29 +    else 
    1.30 +        wrmsr(IA32_FEATURE_CONTROL_MSR, 
    1.31 +              IA32_FEATURE_CONTROL_MSR_LOCK | IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
    1.32  
    1.33      set_in_cr4(X86_CR4_VMXE);   /* Enable VMXE */
    1.34  
     2.1 --- a/xen/arch/x86/vmx_vmcs.c	Fri May 20 22:18:38 2005 +0000
     2.2 +++ b/xen/arch/x86/vmx_vmcs.c	Fri May 20 22:28:12 2005 +0000
     2.3 @@ -37,12 +37,14 @@
     2.4  struct vmcs_struct *alloc_vmcs(void) 
     2.5  {
     2.6      struct vmcs_struct *vmcs;
     2.7 -    unsigned int cpu_sig = cpuid_eax(0x00000001);
     2.8 +    u32 vmx_msr_low, vmx_msr_high;
     2.9  
    2.10 +    rdmsr(MSR_IA32_VMX_BASIC_MSR, vmx_msr_low, vmx_msr_high);
    2.11 +    vmcs_size = vmx_msr_high & 0x1fff;
    2.12      vmcs = (struct vmcs_struct *) alloc_xenheap_pages(get_order(vmcs_size)); 
    2.13      memset((char *) vmcs, 0, vmcs_size); /* don't remove this */
    2.14  
    2.15 -    vmcs->vmcs_revision_id = (cpu_sig > 0xf41)? 3 : 1;
    2.16 +    vmcs->vmcs_revision_id = vmx_msr_low;
    2.17      return vmcs;
    2.18  } 
    2.19  
     3.1 --- a/xen/include/asm-x86/msr.h	Fri May 20 22:18:38 2005 +0000
     3.2 +++ b/xen/include/asm-x86/msr.h	Fri May 20 22:28:12 2005 +0000
     3.3 @@ -79,6 +79,12 @@
     3.4  #define MSR_IA32_PLATFORM_ID		0x17
     3.5  #define MSR_IA32_EBL_CR_POWERON		0x2a
     3.6  
     3.7 +/* MSRs & bits used for VMX enabling */
     3.8 +#define MSR_IA32_VMX_BASIC_MSR                  0x480
     3.9 +#define IA32_FEATURE_CONTROL_MSR                0x3a
    3.10 +#define IA32_FEATURE_CONTROL_MSR_LOCK           0x1
    3.11 +#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON   0x4
    3.12 +
    3.13  /* AMD/K8 specific MSRs */ 
    3.14  #define MSR_EFER 0xc0000080		/* extended feature register */
    3.15  #define MSR_STAR 0xc0000081		/* legacy mode SYSCALL target */
     4.1 --- a/xen/include/asm-x86/vmx_vmcs.h	Fri May 20 22:18:38 2005 +0000
     4.2 +++ b/xen/include/asm-x86/vmx_vmcs.h	Fri May 20 22:28:12 2005 +0000
     4.3 @@ -31,7 +31,6 @@ void vmx_enter_scheduler(void);
     4.4  
     4.5  #define VMX_CPU_STATE_PG_ENABLED        0       
     4.6  #define	VMX_CPU_STATE_ASSIST_ENABLED	1
     4.7 -#define VMCS_SIZE                       0x1000
     4.8  
     4.9  struct vmcs_struct {
    4.10      u32 vmcs_revision_id;