IA64: Rationalize VMM mode alignment checking

This is the xen port of ia64 linux chageset of
b704882e70d87d7f56db5ff17e2253f3fa90e4f3

[IA64] Rationalize kernel mode alignment checking

Itanium processors can handle some misaligned data accesses. They
also provide a mode where all such accesses are forced to trap. The
kernel was schizophrenic about use of this mode:

* Base kernel code ran in permissive mode where the only traps
generated were from those cases that the h/w could not handle.
* Interrupt, syscall and trap code ran in strict mode where all
unaligned accesses caused traps to the 0x5a00 unaligned reference
vector.

Use strict alignment checking throughout the kernel, but make
sure that we continue to let user mode use more relaxed mode
as the default.

Signed-off-by: Tony Luck <tony.luck@intel.com>

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

     1.1 --- a/xen/arch/ia64/linux-xen/head.S	Wed Nov 26 10:23:49 2008 +0900
     1.2 +++ b/xen/arch/ia64/linux-xen/head.S	Wed Dec 03 11:43:54 2008 +0900
     1.3 @@ -267,8 +267,13 @@ start_ap:
     1.4  	/*
     1.5  	 * Switch into virtual mode:
     1.6  	 */
     1.7 +#ifdef XEN
     1.8 +		movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
     1.9 +		  |IA64_PSR_DI|IA64_PSR_AC)
    1.10 +#else
    1.11  	movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
    1.12  		  |IA64_PSR_DI)
    1.13 +#endif
    1.14  	;;
    1.15  	mov cr.ipsr=r16
    1.16  	movl r17=1f