ia64/xen-unstable

changeset 3900:53af0ad97d93

bitkeeper revision 1.1236.1.4 (421d33ccU_69hAlhQIokqDt-5pIheg)

[PATCH] Disable VHPT for Region 6

- Disable VHPT for region 6.
- Initialize the reserved bits in the region regs to 0. Otherwise it
could result in a reserved register/field fault.

Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author arun.sharma@intel.com[adsharma]
date Thu Feb 24 01:54:20 2005 +0000 (2005-02-24)
parents 74583df8e6c6
children 89cabb316ba2
files BitKeeper/etc/logging_ok xen/arch/ia64/regionreg.c
line diff
     1.1 --- a/BitKeeper/etc/logging_ok	Tue Feb 22 23:46:11 2005 +0000
     1.2 +++ b/BitKeeper/etc/logging_ok	Thu Feb 24 01:54:20 2005 +0000
     1.3 @@ -6,6 +6,7 @@ akw27@arcadians.cl.cam.ac.uk
     1.4  akw27@boulderdash.cl.cam.ac.uk
     1.5  akw27@labyrinth.cl.cam.ac.uk
     1.6  akw27@plucky.localdomain
     1.7 +arun.sharma@intel.com
     1.8  bd240@boulderdash.cl.cam.ac.uk
     1.9  bd240@labyrinth.cl.cam.ac.uk
    1.10  br260@br260.wolfson.cam.ac.uk
     2.1 --- a/xen/arch/ia64/regionreg.c	Tue Feb 22 23:46:11 2005 +0000
     2.2 +++ b/xen/arch/ia64/regionreg.c	Thu Feb 24 01:54:20 2005 +0000
     2.3 @@ -325,6 +325,7 @@ if (!ed->vcpu_info) { printf("Stopping i
     2.4  	ed->vcpu_info->arch.rrs[3] = rrv.rrval;
     2.5  	ed->vcpu_info->arch.rrs[4] = rrv.rrval;
     2.6  	ed->vcpu_info->arch.rrs[5] = rrv.rrval;
     2.7 +	rrv.ve = 0; 
     2.8  	ed->vcpu_info->arch.rrs[6] = rrv.rrval;
     2.9  //	ed->shared_info->arch.rrs[7] = rrv.rrval;
    2.10  }
    2.11 @@ -367,10 +368,13 @@ unsigned long load_region_regs(struct ex
    2.12  	if (ed->vcpu_info->arch.metaphysical_mode) {
    2.13  		ia64_rr rrv;
    2.14  
    2.15 +		rrv.rrval = 0;
    2.16  		rrv.rid = ed->domain->metaphysical_rid;
    2.17  		rrv.ps = PAGE_SHIFT;
    2.18  		rrv.ve = 1;
    2.19 -		rr0 = rr1 = rr2 = rr3 = rr4 = rr5 = rr6 = newrr7 = rrv.rrval;
    2.20 +		rr0 = rr1 = rr2 = rr3 = rr4 = rr5 = newrr7 = rrv.rrval;
    2.21 +		rrv.ve = 0;
    2.22 +		rr6 = rrv.rrval;
    2.23  	}
    2.24  	else {
    2.25  		rr0 = physicalize_rid(ed, ed->vcpu_info->arch.rrs[0]);