ia64/xen-unstable

changeset 16112:52d9f5028397

[IA64] Fix TLB insertion for subpaging

Without this patch, Longhorn is sure to hang up. .NET application
might hit this bug. itc.i instruction is repeated forever, because
TLB entry with smaller page size is volatile.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Alex Williamson <alex.williamson@hp.com>
date Fri Oct 12 14:49:37 2007 -0600 (2007-10-12)
parents 4e45ba84a1fa
children 2e13bfcf4abb
files xen/arch/ia64/vmx/vtlb.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/vtlb.c	Fri Oct 12 14:36:37 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vtlb.c	Fri Oct 12 14:49:37 2007 -0600
     1.3 @@ -572,13 +572,16 @@ int thash_purge_and_insert(VCPU *v, u64 
     1.4          }
     1.5          else {
     1.6              u64 psr;
     1.7 -            phy_pte  &= ~PAGE_FLAGS_RV_MASK;
     1.8 -            psr = ia64_clear_ic();
     1.9 -            ia64_itc(type + 1, ifa, phy_pte, IA64_ITIR_PS_KEY(ps, 0));
    1.10 -            ia64_set_psr(psr);
    1.11 -            ia64_srlz_i();
    1.12 -            // ps < mrr.ps, this is not supported
    1.13 -            // panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
    1.14 +
    1.15 +            vtlb_insert(v, pte, itir, ifa);
    1.16 +            vcpu_quick_region_set(PSCBX(v, tc_regions), ifa);
    1.17 +            if (!(pte & VTLB_PTE_IO)) {
    1.18 +                phy_pte  &= ~PAGE_FLAGS_RV_MASK;
    1.19 +                psr = ia64_clear_ic();
    1.20 +                ia64_itc(type + 1, ifa, phy_pte, IA64_ITIR_PS_KEY(ps, 0));
    1.21 +                ia64_set_psr(psr);
    1.22 +                ia64_srlz_i();
    1.23 +            }
    1.24          }
    1.25      }
    1.26      else{