ia64/xen-unstable

changeset 16764:50ac3b26b252

[IA64] Cleanup white space of vmx_switch_rr7. use tab.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents 234a7033e949
children 70db89a4beab
files xen/arch/ia64/vmx/vmx_entry.S
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_entry.S	Thu Jan 17 12:05:43 2008 -0700
     1.2 +++ b/xen/arch/ia64/vmx/vmx_entry.S	Thu Jan 17 12:05:43 2008 -0700
     1.3 @@ -620,140 +620,136 @@ END(ia64_leave_hypercall)
     1.4   * r8: will contain old rid value
     1.5   */
     1.6  
     1.7 -
     1.8 -#define PSR_BITS_TO_CLEAR                      \
     1.9 -   (IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_DB |IA64_PSR_RT |     \
    1.10 -    IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |    \
    1.11 -    IA64_PSR_DFL | IA64_PSR_DFH)
    1.12 +#define PSR_BITS_TO_CLEAR                                           \
    1.13 +	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_DB |     \
    1.14 +	 IA64_PSR_RT | IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI |    \
    1.15 +	 IA64_PSR_ED | IA64_PSR_DFL | IA64_PSR_DFH)
    1.16  #define PSR_BITS_TO_SET    IA64_PSR_BN
    1.17  
    1.18 -//extern void vmx_switch_rr7(unsigned long rid,void *shared_info, void *shared_arch_info, void *guest_vhpt, void * pal_vaddr );
    1.19 +//extern void vmx_switch_rr7(unsigned long rid, void *guest_vhpt, void * pal_vaddr );
    1.20  
    1.21  GLOBAL_ENTRY(vmx_switch_rr7)
    1.22 -   // not sure this unwind statement is correct...
    1.23 -   .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(1)
    1.24 -   alloc loc1 = ar.pfs, 3, 7, 0, 0
    1.25 -1: {
    1.26 -     mov r28  = in0        // copy procedure index
    1.27 -     mov r8   = ip         // save ip to compute branch
    1.28 -     mov loc0 = rp         // save rp
    1.29 -    };;
    1.30 -    .body
    1.31 -    movl loc2=PERCPU_ADDR
    1.32 -    ;;
    1.33 -    tpa loc2 = loc2         // get physical address of per cpu date
    1.34 -    tpa r3 = r8             // get physical address of ip
    1.35 -    dep loc5 = 0,in1,60,4          // get physical address of guest_vhpt
    1.36 -    dep loc6 = 0,in2,60,4          // get physical address of pal code
    1.37 -    ;;
    1.38 -    mov loc4 = psr          // save psr
    1.39 -    ;;
    1.40 -    mov loc3 = ar.rsc           // save RSE configuration
    1.41 -    ;;
    1.42 -    mov ar.rsc = 0          // put RSE in enforced lazy, LE mode
    1.43 -    movl r16=PSR_BITS_TO_CLEAR
    1.44 -    movl r17=PSR_BITS_TO_SET
    1.45 -    ;;
    1.46 -    or loc4 = loc4,r17      // add in psr the bits to set
    1.47 -    ;;
    1.48 -    andcm r16=loc4,r16      // removes bits to clear from psr
    1.49 -    br.call.sptk.many rp=ia64_switch_mode_phys
    1.50 +       // not sure this unwind statement is correct...
    1.51 +       .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(1)
    1.52 +       alloc loc1 = ar.pfs, 3, 7, 0, 0
    1.53 +1:{
    1.54 +	mov r28  = in0                  // copy procedure index
    1.55 +	mov r8   = ip                   // save ip to compute branch
    1.56 +	mov loc0 = rp                   // save rp
    1.57 +};;
    1.58 +	.body
    1.59 +	movl loc2=PERCPU_ADDR
    1.60 +	;;
    1.61 +	tpa loc2 = loc2                 // get physical address of per cpu date
    1.62 +	tpa r3 = r8                     // get physical address of ip
    1.63 +	dep loc5 = 0,in1,60,4           // get physical address of guest_vhpt
    1.64 +	dep loc6 = 0,in2,60,4           // get physical address of pal code
    1.65 +	;;
    1.66 +	mov loc4 = psr                  // save psr
    1.67 +	;;
    1.68 +	mov loc3 = ar.rsc               // save RSE configuration
    1.69 +	;;
    1.70 +	mov ar.rsc = 0                  // put RSE in enforced lazy, LE mode
    1.71 +	movl r16=PSR_BITS_TO_CLEAR
    1.72 +	movl r17=PSR_BITS_TO_SET
    1.73 +	;;
    1.74 +	or loc4 = loc4,r17              // add in psr the bits to set
    1.75 +	;;
    1.76 +	andcm r16=loc4,r16              // removes bits to clear from psr
    1.77 +	br.call.sptk.many rp=ia64_switch_mode_phys
    1.78  1:
    1.79 -   // now in physical mode with psr.i/ic off so do rr7 switch
    1.80 -    dep r16=-1,r0,61,3
    1.81 -    ;;
    1.82 -    mov rr[r16]=in0
    1.83 -    srlz.d
    1.84 -    ;;
    1.85 -    rsm 0x6000
    1.86 -    ;;
    1.87 -    srlz.d
    1.88 +	// now in physical mode with psr.i/ic off so do rr7 switch
    1.89 +	dep r16=-1,r0,61,3
    1.90 +	;;
    1.91 +	mov rr[r16]=in0
    1.92 +	srlz.d
    1.93 +	;;
    1.94 +	rsm 0x6000
    1.95 +	;;
    1.96 +	srlz.d
    1.97  
    1.98 -    // re-pin mappings for kernel text and data
    1.99 -    mov r18=KERNEL_TR_PAGE_SHIFT<<2
   1.100 -    movl r17=KERNEL_START
   1.101 -    ;;
   1.102 -    ptr.i   r17,r18
   1.103 -    ptr.d   r17,r18
   1.104 -    ;;
   1.105 -    mov cr.itir=r18
   1.106 -    mov cr.ifa=r17
   1.107 -    mov r16=IA64_TR_KERNEL
   1.108 -    movl r25 = PAGE_KERNEL
   1.109 -    dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
   1.110 -    ;;
   1.111 -    or r24=r2,r25
   1.112 -    ;;
   1.113 -   srlz.i
   1.114 -   ;;
   1.115 -   itr.i itr[r16]=r24
   1.116 -   ;;
   1.117 -   itr.d dtr[r16]=r24
   1.118 -   ;;
   1.119 -   /* xen heap is also identity mapped */
   1.120 -   mov r16 = IA64_TR_XEN_HEAP_REGS
   1.121 -   dep r17=-1,r3,60,4
   1.122 -   ;;
   1.123 -   ptr.d r17, r18
   1.124 -   ;;
   1.125 -   mov cr.ifa=r17
   1.126 -   ;;
   1.127 -   itr.d dtr[r16]=r24
   1.128 -   ;;
   1.129 -
   1.130 -   // re-pin mappings for per-cpu data
   1.131 +	// re-pin mappings for kernel text and data
   1.132 +	mov r18=KERNEL_TR_PAGE_SHIFT<<2
   1.133 +	movl r17=KERNEL_START
   1.134 +	;;
   1.135 +	ptr.i   r17,r18
   1.136 +	ptr.d   r17,r18
   1.137 +	;;
   1.138 +	mov cr.itir=r18
   1.139 +	mov cr.ifa=r17
   1.140 +	mov r16=IA64_TR_KERNEL
   1.141 +	movl r25 = PAGE_KERNEL
   1.142 +	dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
   1.143 +	;;
   1.144 +	or r24=r2,r25
   1.145 +	;;
   1.146 +	srlz.i
   1.147 +	;;
   1.148 +	itr.i itr[r16]=r24
   1.149 +	;;
   1.150 +	itr.d dtr[r16]=r24
   1.151 +	;;
   1.152 +	/* xen heap is also identity mapped */
   1.153 +	mov r16 = IA64_TR_XEN_HEAP_REGS
   1.154 +	dep r17=-1,r3,60,4
   1.155 +	;;
   1.156 +	ptr.d r17, r18
   1.157 +	;;
   1.158 +	mov cr.ifa=r17
   1.159 +	;;
   1.160 +	itr.d dtr[r16]=r24
   1.161 +	;;
   1.162  
   1.163 -   movl r22 = PERCPU_ADDR
   1.164 -   ;;
   1.165 -   mov r24=IA64_TR_PERCPU_DATA
   1.166 -   or loc2 = r25,loc2          // construct PA | page properties
   1.167 -   mov r23=PERCPU_PAGE_SHIFT<<2
   1.168 -   ;;
   1.169 -   ptr.d   r22,r23
   1.170 -   ;;
   1.171 -   mov cr.itir=r23
   1.172 -   mov cr.ifa=r22
   1.173 -   ;;
   1.174 -   itr.d dtr[r24]=loc2     // wire in new mapping...
   1.175 -   ;;
   1.176 -
   1.177 -   // re-pin mappings for guest_vhpt
   1.178 +	// re-pin mappings for per-cpu data
   1.179 +	movl r22 = PERCPU_ADDR
   1.180 +	;;
   1.181 +	mov r24=IA64_TR_PERCPU_DATA
   1.182 +	or loc2 = r25,loc2              // construct PA | page properties
   1.183 +	mov r23=PERCPU_PAGE_SHIFT<<2
   1.184 +	;;
   1.185 +	ptr.d   r22,r23
   1.186 +	;;
   1.187 +	mov cr.itir=r23
   1.188 +	mov cr.ifa=r22
   1.189 +	;;
   1.190 +	itr.d dtr[r24]=loc2             // wire in new mapping...
   1.191 +	;;
   1.192  
   1.193 -   mov r24=IA64_TR_VHPT
   1.194 -   movl r25=PAGE_KERNEL
   1.195 -   ;;
   1.196 -   or loc5 = r25,loc5          // construct PA | page properties
   1.197 -   mov r23 = IA64_GRANULE_SHIFT <<2
   1.198 -   ;;
   1.199 -   ptr.d   in1,r23
   1.200 -   ;;
   1.201 -   mov cr.itir=r23
   1.202 -   mov cr.ifa=in1
   1.203 -   ;;
   1.204 -   itr.d dtr[r24]=loc5     // wire in new mapping...
   1.205 -   ;;
   1.206 -
   1.207 -   // re-pin mappings for PAL code section
   1.208 +	// re-pin mappings for guest_vhpt
   1.209 +	mov r24=IA64_TR_VHPT
   1.210 +	movl r25=PAGE_KERNEL
   1.211 +	;;
   1.212 +	or loc5 = r25,loc5              // construct PA | page properties
   1.213 +	mov r23 = IA64_GRANULE_SHIFT <<2
   1.214 +	;;
   1.215 +	ptr.d   in1,r23
   1.216 +	;;
   1.217 +	mov cr.itir=r23
   1.218 +	mov cr.ifa=in1
   1.219 +	;;
   1.220 +	itr.d dtr[r24]=loc5             // wire in new mapping...
   1.221 +	;;
   1.222  
   1.223 -   mov r24=IA64_TR_PALCODE
   1.224 -   or loc6 = r25,loc6          // construct PA | page properties
   1.225 -   mov r23 = IA64_GRANULE_SHIFT<<2
   1.226 -   ;;
   1.227 -   ptr.i   in2,r23
   1.228 -   ;;
   1.229 -   mov cr.itir=r23
   1.230 -   mov cr.ifa=in2
   1.231 -   ;;
   1.232 -   itr.i itr[r24]=loc6     // wire in new mapping...
   1.233 -   ;;
   1.234 +	// re-pin mappings for PAL code section
   1.235 +	mov r24=IA64_TR_PALCODE
   1.236 +	or loc6 = r25,loc6              // construct PA | page properties
   1.237 +	mov r23 = IA64_GRANULE_SHIFT<<2
   1.238 +	;;
   1.239 +	ptr.i   in2,r23
   1.240 +	;;
   1.241 +	mov cr.itir=r23
   1.242 +	mov cr.ifa=in2
   1.243 +	;;
   1.244 +	itr.i itr[r24]=loc6             // wire in new mapping...
   1.245 +	;;
   1.246  
   1.247 -   // done, switch back to virtual and return
   1.248 -   mov r16=loc4            // r16= original psr
   1.249 -   br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   1.250 -   mov ar.pfs = loc1
   1.251 -   mov rp = loc0
   1.252 -   ;;
   1.253 -   mov ar.rsc=loc3         // restore RSE configuration
   1.254 -   srlz.d              // seralize restoration of psr.l
   1.255 -   br.ret.sptk.many rp
   1.256 +	// done, switch back to virtual and return
   1.257 +	mov r16=loc4                    // r16= original psr
   1.258 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   1.259 +	mov ar.pfs = loc1
   1.260 +	mov rp = loc0
   1.261 +	;;
   1.262 +	mov ar.rsc=loc3                 // restore RSE configuration
   1.263 +	srlz.d                          // seralize restoration of psr.l
   1.264 +	br.ret.sptk.many rp
   1.265  END(vmx_switch_rr7)