ia64/xen-unstable
changeset 5348:507ef62e9bec
bitkeeper revision 1.1668.1.2 (42a4904fwO30IinqLPqfFaI7md-pLA)
Merge corrections
Merge corrections
author | djm@kirby.fc.hp.com |
---|---|
date | Mon Jun 06 18:05:03 2005 +0000 (2005-06-06) |
parents | c061e9a30cdf |
children | f6850d7aec27 |
files | xen/arch/ia64/domain.c xen/arch/ia64/hyperprivop.S xen/arch/ia64/privop.c xen/arch/ia64/regionreg.c |
line diff
1.1 --- a/xen/arch/ia64/domain.c Mon Jun 06 17:13:19 2005 +0000 1.2 +++ b/xen/arch/ia64/domain.c Mon Jun 06 18:05:03 2005 +0000 1.3 @@ -257,7 +257,7 @@ void arch_do_createdomain(struct vcpu *v 1.4 d->xen_vaend = 0xf300000000000000; 1.5 d->shared_info_va = 0xf100000000000000; 1.6 d->arch.breakimm = 0x1000; 1.7 - ed->arch.breakimm = d->arch.breakimm; 1.8 + v->arch.breakimm = d->arch.breakimm; 1.9 // stay on kernel stack because may get interrupts! 1.10 // ia64_ret_from_clone (which b0 gets in new_thread) switches 1.11 // to user stack
2.1 --- a/xen/arch/ia64/hyperprivop.S Mon Jun 06 17:13:19 2005 +0000 2.2 +++ b/xen/arch/ia64/hyperprivop.S Mon Jun 06 18:05:03 2005 +0000 2.3 @@ -90,7 +90,7 @@ GLOBAL_ENTRY(fast_break_reflect) 2.4 mov cr.ipsr=r20;; 2.5 // save ipsr in shared_info, vipsr.cpl==(ipsr.cpl==3)?3:0 2.6 cmp.ne p7,p0=3,r21;; 2.7 -(p7) mov r21=r0 2.8 +(p7) mov r21=r0 ;; 2.9 dep r20=r21,r20,IA64_PSR_CPL0_BIT,2 ;; 2.10 dep r20=r23,r20,IA64_PSR_RI_BIT,2 ;; 2.11 // vipsr.i=vpsr.i 2.12 @@ -110,7 +110,7 @@ GLOBAL_ENTRY(fast_break_reflect) 2.13 // save ifs in shared_info 2.14 adds r21=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;; 2.15 st4 [r21]=r0 ;; 2.16 - adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 2.17 + adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;; 2.18 st8 [r21]=r0 ;; 2.19 cover ;; 2.20 mov r20=cr.ifs;;
3.1 --- a/xen/arch/ia64/privop.c Mon Jun 06 17:13:19 2005 +0000 3.2 +++ b/xen/arch/ia64/privop.c Mon Jun 06 18:05:03 2005 +0000 3.3 @@ -795,7 +795,7 @@ ia64_hyperprivop(unsigned long iim, REGS 3.4 (void)priv_itc_i(v,inst); 3.5 return 1; 3.6 case HYPERPRIVOP_SSM_I: 3.7 - (void)vcpu_set_psr_i(ed); 3.8 + (void)vcpu_set_psr_i(v); 3.9 return 1; 3.10 } 3.11 return 0;
4.1 --- a/xen/arch/ia64/regionreg.c Mon Jun 06 17:13:19 2005 +0000 4.2 +++ b/xen/arch/ia64/regionreg.c Mon Jun 06 18:05:03 2005 +0000 4.3 @@ -287,7 +287,7 @@ int set_one_rr(unsigned long rr, unsigne 4.4 if (rreg == 6) newrrv.ve = VHPT_ENABLED_REGION_7; 4.5 else newrrv.ve = VHPT_ENABLED_REGION_0_TO_6; 4.6 newrrv.ps = PAGE_SHIFT; 4.7 - if (rreg == 0) ed->arch.metaphysical_saved_rr0 = newrrv.rrval; 4.8 + if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval; 4.9 set_rr(rr,newrrv.rrval); 4.10 } 4.11 return 1; 4.12 @@ -296,11 +296,11 @@ int set_one_rr(unsigned long rr, unsigne 4.13 // set rr0 to the passed rid (for metaphysical mode so don't use domain offset 4.14 int set_metaphysical_rr0(void) 4.15 { 4.16 - struct exec_domain *ed = current; 4.17 + struct vcpu *v = current; 4.18 ia64_rr rrv; 4.19 4.20 // rrv.ve = 1; FIXME: TURN ME BACK ON WHEN VHPT IS WORKING 4.21 - set_rr(0,ed->arch.metaphysical_rr0); 4.22 + set_rr(0,v->arch.metaphysical_rr0); 4.23 } 4.24 4.25 // validates/changes region registers 0-6 in the currently executing domain 4.26 @@ -325,8 +325,7 @@ void init_all_rr(struct vcpu *v) 4.27 ia64_rr rrv; 4.28 4.29 rrv.rrval = 0; 4.30 - rrv.rid = v->domain->metaphysical_rid; 4.31 - rrv.rrval = ed->domain->arch.metaphysical_rr0; 4.32 + rrv.rrval = v->domain->arch.metaphysical_rr0; 4.33 rrv.ps = PAGE_SHIFT; 4.34 rrv.ve = 1; 4.35 if (!v->vcpu_info) { printf("Stopping in init_all_rr\n"); dummy(); } 4.36 @@ -380,9 +379,8 @@ unsigned long load_region_regs(struct vc 4.37 ia64_rr rrv; 4.38 4.39 rrv.rrval = 0; 4.40 - rrv.rid = v->domain->metaphysical_rid; 4.41 + rrv.rid = v->domain->arch.metaphysical_rr0; 4.42 rrv.ps = PAGE_SHIFT; 4.43 - rrv.rrval = v->domain->arch.metaphysical_rr0; 4.44 rrv.ve = 1; 4.45 rr0 = rrv.rrval; 4.46 set_rr_no_srlz(0x0000000000000000L, rr0);