ia64/xen-unstable

changeset 8386:50640456147b

LAPIC model is different on x86 and ia64, so make irq-pending
notification arch specific.

Signed-off-by Kevin Tian <Kevin.tian@intel.com>
Signed-off-by Yunhong Jiang <Yunhong.jiang@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Dec 14 19:44:42 2005 +0100 (2005-12-14)
parents 7ef59d40c26a
children dc8122d90670
files xen/arch/ia64/vmx/vlsapic.c xen/arch/x86/dm/vmx_vioapic.c xen/include/asm-ia64/vmx_platform.h xen/include/asm-ia64/vmx_vcpu.h xen/include/asm-x86/vmx_vlapic.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vlsapic.c	Wed Dec 14 19:41:06 2005 +0100
     1.2 +++ b/xen/arch/ia64/vmx/vlsapic.c	Wed Dec 14 19:44:42 2005 +0100
     1.3 @@ -476,19 +476,20 @@ static int irq_masked(VCPU *vcpu, int h_
     1.4   * May come from virtualization fault or
     1.5   * nested host interrupt.
     1.6   */
     1.7 -void vmx_vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector)
     1.8 +int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector)
     1.9  {
    1.10      uint64_t    spsr;
    1.11 +    int ret;
    1.12  
    1.13      if (vector & ~0xff) {
    1.14          DPRINTK("vmx_vcpu_pend_interrupt: bad vector\n");
    1.15          return;
    1.16      }
    1.17      local_irq_save(spsr);
    1.18 -    VCPU(vcpu,irr[vector>>6]) |= 1UL<<(vector&63);
    1.19 -    //vlapic_update_shared_irr(vcpu);
    1.20 +    ret = test_and_set_bit(vector, &VCPU(vcpu, irr[0]));
    1.21      local_irq_restore(spsr);
    1.22      vcpu->arch.irq_new_pending = 1;
    1.23 +    return ret;
    1.24  }
    1.25  
    1.26  /*
    1.27 @@ -505,7 +506,6 @@ void vmx_vcpu_pend_batch_interrupt(VCPU 
    1.28      for (i=0 ; i<4; i++ ) {
    1.29          VCPU(vcpu,irr[i]) |= pend_irr[i];
    1.30      }
    1.31 -    //vlapic_update_shared_irr(vcpu);
    1.32      local_irq_restore(spsr);
    1.33      vcpu->arch.irq_new_pending = 1;
    1.34  }
    1.35 @@ -592,7 +592,6 @@ uint64_t guest_read_vivr(VCPU *vcpu)
    1.36      VLSAPIC_INSVC(vcpu,vec>>6) |= (1UL <<(vec&63));
    1.37      VCPU(vcpu, irr[vec>>6]) &= ~(1UL <<(vec&63));
    1.38      update_vhpi(vcpu, NULL_VECTOR);     // clear VHPI till EOI or IRR write
    1.39 -    //vlapic_update_shared_irr(vcpu);
    1.40      local_irq_restore(spsr);
    1.41      return (uint64_t)vec;
    1.42  }
     2.1 --- a/xen/arch/x86/dm/vmx_vioapic.c	Wed Dec 14 19:41:06 2005 +0100
     2.2 +++ b/xen/arch/x86/dm/vmx_vioapic.c	Wed Dec 14 19:44:42 2005 +0100
     2.3 @@ -306,14 +306,8 @@ static int ioapic_inj_irq(vmx_vioapic_t 
     2.4      switch (delivery_mode) {
     2.5      case VLAPIC_DELIV_MODE_FIXED:
     2.6      case VLAPIC_DELIV_MODE_LPRI:
     2.7 -        if (test_and_set_bit(vector, &VLAPIC_IRR(target)) && trig_mode == 1) {
     2.8 -            /* the level interrupt should not happen before it is cleard */
     2.9 +        if (vlapic_set_irq(target, vector, trig_mode) && (trig_mode == 1))
    2.10              printk("<ioapic_inj_irq> level interrupt happen before cleard\n");
    2.11 -        }
    2.12 -#ifndef __ia64__
    2.13 -        if (trig_mode)
    2.14 -            test_and_set_bit(vector, &target->tmr[0]);
    2.15 -#endif
    2.16          result = 1;
    2.17          break;
    2.18      default:
     3.1 --- a/xen/include/asm-ia64/vmx_platform.h	Wed Dec 14 19:41:06 2005 +0100
     3.2 +++ b/xen/include/asm-ia64/vmx_platform.h	Wed Dec 14 19:44:42 2005 +0100
     3.3 @@ -55,6 +55,12 @@ extern uint64_t dummy_tmr[];
     3.4  #define VLAPIC_ID(l) (uint16_t)(VCPU((l)->vcpu, lid) >> 16)
     3.5  #define VLAPIC_IRR(l) VCPU((l)->vcpu, irr[0])
     3.6  
     3.7 +extern int vmx_vcpu_pend_interrupt(struct vcpu *vcpu, uint8_t vector);
     3.8 +static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
     3.9 +{
    3.10 +    return vmx_vcpu_pend_interrupt(t->vcpu, vec);
    3.11 +}
    3.12 +
    3.13  /* As long as we register vlsapic to ioapic controller, it's said enabled */
    3.14  #define vlapic_enabled(l) 1
    3.15  #define vmx_apic_support(d) 1
     4.1 --- a/xen/include/asm-ia64/vmx_vcpu.h	Wed Dec 14 19:41:06 2005 +0100
     4.2 +++ b/xen/include/asm-ia64/vmx_vcpu.h	Wed Dec 14 19:44:42 2005 +0100
     4.3 @@ -112,7 +112,7 @@ extern int vmx_check_pending_irq(VCPU *v
     4.4  extern void guest_write_eoi(VCPU *vcpu);
     4.5  extern uint64_t guest_read_vivr(VCPU *vcpu);
     4.6  extern void vmx_inject_vhpi(VCPU *vcpu, u8 vec);
     4.7 -extern void vmx_vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector);
     4.8 +extern int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector);
     4.9  extern struct virutal_platform_def *vmx_vcpu_get_plat(VCPU *vcpu);
    4.10  extern void memread_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s);
    4.11  extern void memread_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest, size_t s);
    4.12 @@ -474,4 +474,7 @@ vmx_vrrtomrr(VCPU *v, unsigned long val)
    4.13  #endif 
    4.14  
    4.15  }
    4.16 +
    4.17 +#define check_work_pending(v)	\
    4.18 +    (event_pending((v)) || ((v)->arch.irq_new_pending))
    4.19  #endif
     5.1 --- a/xen/include/asm-x86/vmx_vlapic.h	Wed Dec 14 19:41:06 2005 +0100
     5.2 +++ b/xen/include/asm-x86/vmx_vlapic.h	Wed Dec 14 19:44:42 2005 +0100
     5.3 @@ -202,6 +202,18 @@ struct vlapic
     5.4      struct domain      *domain;
     5.5  };
     5.6  
     5.7 +static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
     5.8 +{
     5.9 +    int ret;
    5.10 +
    5.11 +    ret = test_and_set_bit(vec, &t->irr[0]);
    5.12 +    if (trig)
    5.13 +	test_and_set_bit(vec, &t->tmr[0]);
    5.14 +
    5.15 +    /* We may need to wake up target vcpu, besides set pending bit here */
    5.16 +    return ret;
    5.17 +}
    5.18 +
    5.19  static inline int  vlapic_timer_active(struct vlapic *vlapic)
    5.20  {
    5.21      return  active_ac_timer(&(vlapic->vlapic_timer));