ia64/xen-unstable

changeset 13933:4f0353778233

[XEN][POWERPC] big lock to protect some TLB operations

970 requires locking around TLB operations, see code comment.

Signed-off-by: Jimi Xenidis <jimix@watson.ibm.com>
author Jimi Xenidis <jimix@watson.ibm.com>
date Sat Jan 20 18:57:15 2007 -0500 (2007-01-20)
parents 741adb202b82
children b8fac1c5e6ae
files xen/arch/powerpc/papr/xlate.c
line diff
     1.1 --- a/xen/arch/powerpc/papr/xlate.c	Fri Jan 19 15:36:17 2007 -0600
     1.2 +++ b/xen/arch/powerpc/papr/xlate.c	Sat Jan 20 18:57:15 2007 -0500
     1.3 @@ -72,6 +72,20 @@ static inline void pte_insert(union pte 
     1.4  }
     1.5  #endif
     1.6  
     1.7 +/*
     1.8 + * POWER Arch 2.03 Sec 4.12.1 (Yes 970 is one)
     1.9 + *
    1.10 + *   when a tlbsync instruction has been executed by a processor in a
    1.11 + *   given partition, a ptesync instruction must be executed by that
    1.12 + *   processor before a tlbie or tlbsync instruction is executed by
    1.13 + *   another processor in that partition.
    1.14 + *
    1.15 + * So for now, here is a BFLock to deal with it, the lock should be per-domain.
    1.16 + *
    1.17 + * XXX Will need to audit all tlb usege soon enough.
    1.18 + */
    1.19 +
    1.20 +static DEFINE_SPINLOCK(native_tlbie_lock);
    1.21  static void pte_tlbie(union pte volatile *pte, ulong ptex)
    1.22  {
    1.23      ulong va;
    1.24 @@ -91,6 +105,7 @@ static void pte_tlbie(union pte volatile
    1.25      va = (pi << 12) | (vsid << 28);
    1.26      va &= ~(0xffffULL << 48);
    1.27  
    1.28 +    spin_lock(&native_tlbie_lock);
    1.29  #ifndef FLUSH_THE_WHOLE_THING
    1.30      if (pte->bits.l) {
    1.31          va |= (pte->bits.rpn & 1);
    1.32 @@ -114,7 +129,7 @@ static void pte_tlbie(union pte volatile
    1.33          }
    1.34      }
    1.35  #endif
    1.36 -
    1.37 +    spin_unlock(&native_tlbie_lock);
    1.38  }
    1.39  
    1.40  long pte_enter(ulong flags, ulong ptex, ulong vsid, ulong rpn)