ia64/xen-unstable

changeset 4779:49599761f3ce

bitkeeper revision 1.1389.5.21 (427a5ee3rBlRFupS4xBvv_nWVHQlsA)

Clean up IO-APIC handling in domain0, and the hypercall interface
exported by Xen (inc. removal of PCI-related calls). This hopefully
fixes acpi=off.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu May 05 17:58:59 2005 +0000 (2005-05-05)
parents f6bcd68a03f6
children b2186544c8d4
files .rootkeys linux-2.6.11-xen-sparse/arch/xen/i386/kernel/apic.c linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h tools/libxc/xc_physdev.c xen/arch/ia64/domain.c xen/arch/ia64/xenmisc.c xen/arch/ia64/xensetup.c xen/arch/x86/domain.c xen/arch/x86/io_apic.c xen/arch/x86/physdev.c xen/common/Makefile xen/common/dom0_ops.c xen/common/domain.c xen/common/physdev.c xen/drivers/char/serial.c xen/include/asm-x86/config.h xen/include/asm-x86/physdev.h xen/include/public/dom0_ops.h xen/include/public/physdev.h xen/include/xen/physdev.h xen/include/xen/sched.h
line diff
     1.1 --- a/.rootkeys	Thu May 05 16:46:07 2005 +0000
     1.2 +++ b/.rootkeys	Thu May 05 17:58:59 2005 +0000
     1.3 @@ -352,7 +352,6 @@ 41979925z1MsKU1SfuuheM1IFDQ_bA linux-2.6
     1.4  4118b6a418gnL6AZsTdglC92YGqYTg linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/highmem.h
     1.5  42539fb5A9hsS3NFQ-2VY4y1TONZZQ linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/hypercall.h
     1.6  40f5623aJVXQwpJMOLE99XgvGsfQ8Q linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io.h
     1.7 -42778a69MXZVxch4pQqYsMPS0WnNSg linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h
     1.8  40f5623aKXkBBxgpLx2NcvkncQ1Yyw linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/mach-xen/irq_vectors.h
     1.9  40f5623aDMCsWOFO0jktZ4e8sjwvEg linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_post.h
    1.10  40f5623arsFXkGdPvIqvFi3yFXGR0Q linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_pre.h
    1.11 @@ -1216,6 +1215,7 @@ 41aaf567tqrKGSTDK8OVeAbpeoccPw xen/arch/
    1.12  41aaf567a36esU-rUK7twPiv-yTFyw xen/arch/x86/mtrr/mtrr.h
    1.13  41aaf567DcTL6pqVtLZJI5cSryyA1A xen/arch/x86/mtrr/state.c
    1.14  3f12cff65EV3qOG2j37Qm0ShgvXGRw xen/arch/x86/nmi.c
    1.15 +4051bcecFeq4DE70p4zGO5setf47CA xen/arch/x86/physdev.c
    1.16  3ddb79bc7KxGCEJsgBnkDX7XjD_ZEQ xen/arch/x86/rwlock.c
    1.17  3ddb79bcrD6Z_rUvSDgrvjyb4846Eg xen/arch/x86/setup.c
    1.18  405b8599xI_PoEr3zZoJ2on-jdn7iw xen/arch/x86/shadow.c
    1.19 @@ -1259,7 +1259,6 @@ 3ddb79bduhSEZI8xa7IbGQCpap5y2A xen/commo
    1.20  41a61536SZbR6cj1ukWTb0DYU-vz9w xen/common/multicall.c
    1.21  3ddb79bdD4SLmmdMD7yLW5HcUWucXw xen/common/page_alloc.c
    1.22  3e54c38dkHAev597bPr71-hGzTdocg xen/common/perfc.c
    1.23 -4051bcecFeq4DE70p4zGO5setf47CA xen/common/physdev.c
    1.24  3ddb79bdHqdQpATqC0rmUZNbsb6L6A xen/common/resource.c
    1.25  40589968dD2D1aejwSOvrROg7fOvGQ xen/common/sched_bvt.c
    1.26  3e397e6619PgAfBbw2XFbXkewvUWgw xen/common/schedule.c
    1.27 @@ -1354,6 +1353,7 @@ 41aaf567Mi3OishhvrCtET1y-mxQBg xen/inclu
    1.28  41a61536MFhNalgbVmYGXAhQsPTZNw xen/include/asm-x86/multicall.h
    1.29  3ddb79c3xjYnrv5t3VqYlR4tNEOl4Q xen/include/asm-x86/page.h
    1.30  3ddb79c3ysKUbxZuwKBRK3WXU2TlEg xen/include/asm-x86/pci.h
    1.31 +42422fb0FVX-TJkSvAXnbfwMf19XFA xen/include/asm-x86/physdev.h
    1.32  3ddb79c2QF5-pZGzuX4QukPCDAl59A xen/include/asm-x86/processor.h
    1.33  40cf1596bim9F9DNdV75klgRSZ6Y2A xen/include/asm-x86/regs.h
    1.34  3ddb79c2plf7ciNgoNjU-RsbUzawsw xen/include/asm-x86/rwlock.h
    1.35 @@ -1436,7 +1436,6 @@ 3ddb79c2Fg44_PBPVxHSC0gTOMq4Ow xen/inclu
    1.36  3ddb79c0MOVXq8qZDQRGb6z64_xAwg xen/include/xen/pci_ids.h
    1.37  3e54c38dlSCVdyVM4PKcrSfzLLxWUQ xen/include/xen/perfc.h
    1.38  3e54c38de9SUSYSAwxDf_DwkpAnQFA xen/include/xen/perfc_defn.h
    1.39 -42422fb0FVX-TJkSvAXnbfwMf19XFA xen/include/xen/physdev.h
    1.40  3ddb79c04nQVR3EYM5L4zxDV_MCo1g xen/include/xen/prefetch.h
    1.41  3e4540ccU1sgCx8seIMGlahmMfv7yQ xen/include/xen/reboot.h
    1.42  40589969nPq3DMzv24RDb5LXE9brHw xen/include/xen/sched-if.h
     2.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/apic.c	Thu May 05 16:46:07 2005 +0000
     2.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/apic.c	Thu May 05 17:58:59 2005 +0000
     2.3 @@ -16,8 +16,32 @@
     2.4  
     2.5  #include <linux/config.h>
     2.6  #include <linux/init.h>
     2.7 -#include <asm/apic.h>
     2.8 +
     2.9 +#include <linux/mm.h>
    2.10 +#include <linux/irq.h>
    2.11 +#include <linux/delay.h>
    2.12 +#include <linux/bootmem.h>
    2.13 +#include <linux/smp_lock.h>
    2.14 +#include <linux/interrupt.h>
    2.15 +#include <linux/mc146818rtc.h>
    2.16 +#include <linux/kernel_stat.h>
    2.17 +#include <linux/sysdev.h>
    2.18  
    2.19 +#include <asm/atomic.h>
    2.20 +#include <asm/smp.h>
    2.21 +#include <asm/mtrr.h>
    2.22 +#include <asm/mpspec.h>
    2.23 +#include <asm/desc.h>
    2.24 +#include <asm/arch_hooks.h>
    2.25 +#include <asm/hpet.h>
    2.26 +
    2.27 +#include <mach_apic.h>
    2.28 +
    2.29 +#include "io_ports.h"
    2.30 +
    2.31 +/*
    2.32 + * Debug level
    2.33 + */
    2.34  int apic_verbosity;
    2.35  
    2.36  int get_physical_broadcast(void)
    2.37 @@ -49,5 +73,11 @@ void ack_bad_irq(unsigned int irq)
    2.38   */
    2.39  int __init APIC_init_uniprocessor (void)
    2.40  {
    2.41 +#ifdef CONFIG_X86_IO_APIC
    2.42 +	if (smp_found_config)
    2.43 +		if (!skip_ioapic_setup && nr_ioapics)
    2.44 +			setup_IO_APIC();
    2.45 +#endif
    2.46 +
    2.47  	return 0;
    2.48  }
     3.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c	Thu May 05 16:46:07 2005 +0000
     3.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c	Thu May 05 17:58:59 2005 +0000
     3.3 @@ -37,18 +37,56 @@
     3.4  #include <asm/smp.h>
     3.5  #include <asm/desc.h>
     3.6  #include <asm/timer.h>
     3.7 -#include <asm/io_apic.h>
     3.8 -#include <asm/apic.h>
     3.9  
    3.10  #include <mach_apic.h>
    3.11  
    3.12  #include "io_ports.h"
    3.13  
    3.14 +#ifdef CONFIG_XEN
    3.15 +
    3.16 +#include <asm-xen/xen-public/xen.h>
    3.17 +#include <asm-xen/xen-public/physdev.h>
    3.18 +
    3.19 +/* Fake i8259 */
    3.20 +#define make_8259A_irq(_irq)     (io_apic_irqs &= ~(1UL<<(_irq)))
    3.21 +#define disable_8259A_irq(_irq)  ((void)0)
    3.22 +#define i8259A_irq_pending(_irq) (0)
    3.23 +
    3.24 +unsigned long io_apic_irqs;
    3.25 +
    3.26 +static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
    3.27 +{
    3.28 +	physdev_op_t op;
    3.29 +	int ret;
    3.30 +
    3.31 +	op.cmd = PHYSDEVOP_APIC_READ;
    3.32 +	op.u.apic_op.apic = mp_ioapics[apic].mpc_apicid;
    3.33 +	op.u.apic_op.offset = reg;
    3.34 +	ret = HYPERVISOR_physdev_op(&op);
    3.35 +	if (ret)
    3.36 +		return ret;
    3.37 +	return op.u.apic_op.value;
    3.38 +}
    3.39 +
    3.40 +static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
    3.41 +{
    3.42 +	physdev_op_t op;
    3.43 +
    3.44 +	op.cmd = PHYSDEVOP_APIC_WRITE;
    3.45 +	op.u.apic_op.apic = mp_ioapics[apic].mpc_apicid;
    3.46 +	op.u.apic_op.offset = reg;
    3.47 +	op.u.apic_op.value = value;
    3.48 +	HYPERVISOR_physdev_op(&op);
    3.49 +}
    3.50 +
    3.51 +#define io_apic_read(a,r)    xen_io_apic_read(a,r)
    3.52 +#define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
    3.53 +
    3.54 +#endif /* CONFIG_XEN */
    3.55 +
    3.56  int (*ioapic_renumber_irq)(int ioapic, int irq);
    3.57  atomic_t irq_mis_count;
    3.58  
    3.59 -unsigned long io_apic_irqs;
    3.60 -
    3.61  static DEFINE_SPINLOCK(ioapic_lock);
    3.62  
    3.63  /*
    3.64 @@ -111,6 +149,7 @@ static void add_pin_to_irq(unsigned int 
    3.65  	entry->pin = pin;
    3.66  }
    3.67  
    3.68 +#ifndef CONFIG_XEN
    3.69  /*
    3.70   * Reroute an IRQ to a different pin.
    3.71   */
    3.72 @@ -247,6 +286,9 @@ static void set_ioapic_affinity_irq(unsi
    3.73  	}
    3.74  	spin_unlock_irqrestore(&ioapic_lock, flags);
    3.75  }
    3.76 +#else
    3.77 +#define clear_IO_APIC() ((void)0)
    3.78 +#endif
    3.79  
    3.80  #if defined(CONFIG_IRQBALANCE)
    3.81  # include <asm/processor.h>	/* kernel_thread() */
    3.82 @@ -668,9 +710,7 @@ static inline void move_irq(int irq) { }
    3.83  #ifndef CONFIG_SMP
    3.84  void fastcall send_IPI_self(int vector)
    3.85  {
    3.86 -#if 1
    3.87 -	return;
    3.88 -#else
    3.89 +#ifndef CONFIG_XEN
    3.90  	unsigned int cfg;
    3.91  
    3.92  	/*
    3.93 @@ -686,7 +726,6 @@ void fastcall send_IPI_self(int vector)
    3.94  }
    3.95  #endif /* !CONFIG_SMP */
    3.96  
    3.97 -
    3.98  /*
    3.99   * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
   3.100   * specific CPU-side IRQs.
   3.101 @@ -752,6 +791,7 @@ static int find_irq_entry(int apic, int 
   3.102  	return -1;
   3.103  }
   3.104  
   3.105 +#ifndef CONFIG_XEN
   3.106  /*
   3.107   * Find the pin to which IRQ[irq] (ISA) is connected
   3.108   */
   3.109 @@ -774,6 +814,7 @@ static int find_isa_irq_pin(int irq, int
   3.110  	}
   3.111  	return -1;
   3.112  }
   3.113 +#endif
   3.114  
   3.115  /*
   3.116   * Find a specific PCI IRQ entry.
   3.117 @@ -821,6 +862,7 @@ int IO_APIC_get_PCI_irq_vector(int bus, 
   3.118  	return best_guess;
   3.119  }
   3.120  
   3.121 +#ifndef CONFIG_XEN
   3.122  /*
   3.123   * This function currently is only a helper for the i386 smp boot process where 
   3.124   * we need to reprogram the ioredtbls to cater for the cpus which have come online
   3.125 @@ -844,6 +886,7 @@ void __init setup_ioapic_dest(void)
   3.126  
   3.127  	}
   3.128  }
   3.129 +#endif /* !CONFIG_XEN */
   3.130  
   3.131  /*
   3.132   * EISA Edge/Level control register, ELCR
   3.133 @@ -1133,7 +1176,7 @@ static inline int IO_APIC_irq_trigger(in
   3.134  }
   3.135  
   3.136  /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
   3.137 -u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
   3.138 +u8 irq_vector[NR_IRQ_VECTORS]; /* = { FIRST_DEVICE_VECTOR , 0 }; */
   3.139  
   3.140  int assign_irq_vector(int irq)
   3.141  {
   3.142 @@ -1157,6 +1200,7 @@ int assign_irq_vector(int irq)
   3.143  	return current_vector;
   3.144  }
   3.145  
   3.146 +#ifndef CONFIG_XEN
   3.147  static struct hw_interrupt_type ioapic_level_type;
   3.148  static struct hw_interrupt_type ioapic_edge_type;
   3.149  
   3.150 @@ -1172,20 +1216,19 @@ static inline void ioapic_register_intr(
   3.151  			irq_desc[vector].handler = &ioapic_level_type;
   3.152  		else
   3.153  			irq_desc[vector].handler = &ioapic_edge_type;
   3.154 -#if 0
   3.155  		set_intr_gate(vector, interrupt[vector]);
   3.156 -#endif
   3.157  	} else	{
   3.158  		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
   3.159  				trigger == IOAPIC_LEVEL)
   3.160  			irq_desc[irq].handler = &ioapic_level_type;
   3.161  		else
   3.162  			irq_desc[irq].handler = &ioapic_edge_type;
   3.163 -#if 0
   3.164  		set_intr_gate(vector, interrupt[irq]);
   3.165 -#endif
   3.166  	}
   3.167  }
   3.168 +#else
   3.169 +#define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
   3.170 +#endif
   3.171  
   3.172  void __init setup_IO_APIC_irqs(void)
   3.173  {
   3.174 @@ -1241,7 +1284,7 @@ void __init setup_IO_APIC_irqs(void)
   3.175  		else
   3.176  			add_pin_to_irq(irq, apic, pin);
   3.177  
   3.178 -		if (!apic && !IO_APIC_IRQ(irq))
   3.179 +		if (/*!apic &&*/ !IO_APIC_IRQ(irq))
   3.180  			continue;
   3.181  
   3.182  		if (IO_APIC_IRQ(irq)) {
   3.183 @@ -1249,10 +1292,8 @@ void __init setup_IO_APIC_irqs(void)
   3.184  			entry.vector = vector;
   3.185  			ioapic_register_intr(irq, vector, IOAPIC_AUTO);
   3.186  		
   3.187 -#if 0
   3.188  			if (!apic && (irq < 16))
   3.189  				disable_8259A_irq(irq);
   3.190 -#endif
   3.191  		}
   3.192  		spin_lock_irqsave(&ioapic_lock, flags);
   3.193  		io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
   3.194 @@ -1268,6 +1309,7 @@ void __init setup_IO_APIC_irqs(void)
   3.195  /*
   3.196   * Set up the 8259A-master output pin:
   3.197   */
   3.198 +#ifndef CONFIG_XEN
   3.199  void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
   3.200  {
   3.201  	struct IO_APIC_route_entry entry;
   3.202 @@ -1275,9 +1317,7 @@ void __init setup_ExtINT_IRQ0_pin(unsign
   3.203  
   3.204  	memset(&entry,0,sizeof(entry));
   3.205  
   3.206 -#if 0
   3.207  	disable_8259A_irq(0);
   3.208 -#endif
   3.209  
   3.210  	/* mask LVT0 */
   3.211  	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
   3.212 @@ -1308,9 +1348,7 @@ void __init setup_ExtINT_IRQ0_pin(unsign
   3.213  	io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
   3.214  	spin_unlock_irqrestore(&ioapic_lock, flags);
   3.215  
   3.216 -#if 0
   3.217  	enable_8259A_irq(0);
   3.218 -#endif
   3.219  }
   3.220  
   3.221  static inline void UNEXPECTED_IO_APIC(void)
   3.222 @@ -1489,7 +1527,6 @@ static void print_APIC_bitfield (int bas
   3.223  
   3.224  void /*__init*/ print_local_APIC(void * dummy)
   3.225  {
   3.226 -#if 0
   3.227  	unsigned int v, ver, maxlvt;
   3.228  
   3.229  	if (apic_verbosity == APIC_QUIET)
   3.230 @@ -1569,7 +1606,6 @@ void /*__init*/ print_local_APIC(void * 
   3.231  	v = apic_read(APIC_TDCR);
   3.232  	printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
   3.233  	printk("\n");
   3.234 -#endif
   3.235  }
   3.236  
   3.237  void print_all_local_APICs (void)
   3.238 @@ -1609,6 +1645,9 @@ void /*__init*/ print_PIC(void)
   3.239  	v = inb(0x4d1) << 8 | inb(0x4d0);
   3.240  	printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
   3.241  }
   3.242 +#else
   3.243 +void __init print_IO_APIC(void) { }
   3.244 +#endif /* !CONFIG_XEN */
   3.245  
   3.246  static void __init enable_IO_APIC(void)
   3.247  {
   3.248 @@ -1650,7 +1689,7 @@ void disable_IO_APIC(void)
   3.249  	 */
   3.250  	clear_IO_APIC();
   3.251  
   3.252 -#if 0
   3.253 +#ifndef CONFIG_XEN
   3.254  	disconnect_bsp_APIC();
   3.255  #endif
   3.256  }
   3.257 @@ -1662,7 +1701,7 @@ void disable_IO_APIC(void)
   3.258   * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
   3.259   */
   3.260  
   3.261 -#ifndef CONFIG_X86_NUMAQ
   3.262 +#if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
   3.263  static void __init setup_ioapic_ids_from_mpc(void)
   3.264  {
   3.265  	union IO_APIC_reg_00 reg_00;
   3.266 @@ -1769,6 +1808,7 @@ static void __init setup_ioapic_ids_from
   3.267  static void __init setup_ioapic_ids_from_mpc(void) { }
   3.268  #endif
   3.269  
   3.270 +#ifndef CONFIG_XEN
   3.271  /*
   3.272   * There is a nasty bug in some older SMP boards, their mptable lies
   3.273   * about the timer IRQ. We do the following to work around the situation:
   3.274 @@ -1826,13 +1866,11 @@ static unsigned int startup_edge_ioapic_
   3.275  	unsigned long flags;
   3.276  
   3.277  	spin_lock_irqsave(&ioapic_lock, flags);
   3.278 -#if 0
   3.279  	if (irq < 16) {
   3.280  		disable_8259A_irq(irq);
   3.281  		if (i8259A_irq_pending(irq))
   3.282  			was_pending = 1;
   3.283  	}
   3.284 -#endif
   3.285  	__unmask_IO_APIC_irq(irq);
   3.286  	spin_unlock_irqrestore(&ioapic_lock, flags);
   3.287  
   3.288 @@ -1995,6 +2033,7 @@ static struct hw_interrupt_type ioapic_l
   3.289  	.end 		= end_level_ioapic,
   3.290  	.set_affinity 	= set_ioapic_affinity,
   3.291  };
   3.292 +#endif /* !CONFIG_XEN */
   3.293  
   3.294  static inline void init_IO_APIC_traps(void)
   3.295  {
   3.296 @@ -2024,17 +2063,18 @@ static inline void init_IO_APIC_traps(vo
   3.297  			 * so default to an old-fashioned 8259
   3.298  			 * interrupt if we can..
   3.299  			 */
   3.300 -#if 0
   3.301  			if (irq < 16)
   3.302  				make_8259A_irq(irq);
   3.303 +#ifndef CONFIG_XEN
   3.304  			else
   3.305 -#endif
   3.306  				/* Strange. Oh, well.. */
   3.307  				irq_desc[irq].handler = &no_irq_type;
   3.308 +#endif
   3.309  		}
   3.310  	}
   3.311  }
   3.312  
   3.313 +#ifndef CONFIG_XEN
   3.314  static void enable_lapic_irq (unsigned int irq)
   3.315  {
   3.316  	unsigned long v;
   3.317 @@ -2081,9 +2121,7 @@ static void setup_nmi (void)
   3.318  	 */ 
   3.319  	apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
   3.320  
   3.321 -#if 0
   3.322  	on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
   3.323 -#endif
   3.324  
   3.325  	apic_printk(APIC_VERBOSE, " done.\n");
   3.326  }
   3.327 @@ -2158,7 +2196,6 @@ static inline void unlock_ExtINT_logic(v
   3.328   */
   3.329  static inline void check_timer(void)
   3.330  {
   3.331 -#if 0
   3.332  	int pin1, pin2;
   3.333  	int vector;
   3.334  
   3.335 @@ -2265,8 +2302,10 @@ static inline void check_timer(void)
   3.336  	printk(" failed :(.\n");
   3.337  	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
   3.338  		"report.  Then try booting with the 'noapic' option");
   3.339 +}
   3.340 +#else
   3.341 +#define check_timer() ((void)0)
   3.342  #endif
   3.343 -}
   3.344  
   3.345  /*
   3.346   *
   3.347 @@ -2293,7 +2332,7 @@ void __init setup_IO_APIC(void)
   3.348  	 */
   3.349  	if (!acpi_ioapic)
   3.350  		setup_ioapic_ids_from_mpc();
   3.351 -#if 0
   3.352 +#ifndef CONFIG_XEN
   3.353  	sync_Arb_IDs();
   3.354  #endif
   3.355  	setup_IO_APIC_irqs();
   3.356 @@ -2417,6 +2456,7 @@ device_initcall(ioapic_init_sysfs);
   3.357  
   3.358  int __init io_apic_get_unique_id (int ioapic, int apic_id)
   3.359  {
   3.360 +#ifndef CONFIG_XEN
   3.361  	union IO_APIC_reg_00 reg_00;
   3.362  	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
   3.363  	physid_mask_t tmp;
   3.364 @@ -2445,7 +2485,6 @@ int __init io_apic_get_unique_id (int io
   3.365  		apic_id = reg_00.bits.ID;
   3.366  	}
   3.367  
   3.368 -#if 0
   3.369  	/*
   3.370  	 * Every APIC in a system must have a unique ID or we get lots of nice 
   3.371  	 * 'stuck on smp_invalidate_needed IPI wait' messages.
   3.372 @@ -2481,10 +2520,10 @@ int __init io_apic_get_unique_id (int io
   3.373  		if (reg_00.bits.ID != apic_id)
   3.374  			panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
   3.375  	}
   3.376 -#endif
   3.377  
   3.378  	apic_printk(APIC_VERBOSE, KERN_INFO
   3.379  			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
   3.380 +#endif /* !CONFIG_XEN */
   3.381  
   3.382  	return apic_id;
   3.383  }
   3.384 @@ -2555,12 +2594,10 @@ int io_apic_set_pci_routing (int ioapic,
   3.385  		mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
   3.386  		edge_level, active_high_low);
   3.387  
   3.388 -#ifndef CONFIG_XEN
   3.389  	ioapic_register_intr(irq, entry.vector, edge_level);
   3.390  
   3.391  	if (!ioapic && (irq < 16))
   3.392  		disable_8259A_irq(irq);
   3.393 -#endif
   3.394  
   3.395  	spin_lock_irqsave(&ioapic_lock, flags);
   3.396  	io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
     4.1 --- a/linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h	Thu May 05 16:46:07 2005 +0000
     4.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.3 @@ -1,229 +0,0 @@
     4.4 -#ifndef __ASM_IO_APIC_H
     4.5 -#define __ASM_IO_APIC_H
     4.6 -
     4.7 -#include <linux/config.h>
     4.8 -#include <asm/types.h>
     4.9 -#include <asm/mpspec.h>
    4.10 -
    4.11 -#include <asm-xen/xen-public/xen.h>
    4.12 -#include <asm-xen/xen-public/physdev.h>
    4.13 -
    4.14 -/*
    4.15 - * Intel IO-APIC support for SMP and UP systems.
    4.16 - *
    4.17 - * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
    4.18 - */
    4.19 -
    4.20 -#ifdef CONFIG_X86_IO_APIC
    4.21 -
    4.22 -#ifdef CONFIG_PCI_MSI
    4.23 -static inline int use_pci_vector(void)	{return 1;}
    4.24 -static inline void disable_edge_ioapic_vector(unsigned int vector) { }
    4.25 -static inline void mask_and_ack_level_ioapic_vector(unsigned int vector) { }
    4.26 -static inline void end_edge_ioapic_vector (unsigned int vector) { }
    4.27 -#define startup_level_ioapic	startup_level_ioapic_vector
    4.28 -#define shutdown_level_ioapic	mask_IO_APIC_vector
    4.29 -#define enable_level_ioapic	unmask_IO_APIC_vector
    4.30 -#define disable_level_ioapic	mask_IO_APIC_vector
    4.31 -#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_vector
    4.32 -#define end_level_ioapic	end_level_ioapic_vector
    4.33 -#define set_ioapic_affinity	set_ioapic_affinity_vector
    4.34 -
    4.35 -#define startup_edge_ioapic 	startup_edge_ioapic_vector
    4.36 -#define shutdown_edge_ioapic 	disable_edge_ioapic_vector
    4.37 -#define enable_edge_ioapic 	unmask_IO_APIC_vector
    4.38 -#define disable_edge_ioapic 	disable_edge_ioapic_vector
    4.39 -#define ack_edge_ioapic 	ack_edge_ioapic_vector
    4.40 -#define end_edge_ioapic 	end_edge_ioapic_vector
    4.41 -#else
    4.42 -static inline int use_pci_vector(void)	{return 0;}
    4.43 -static inline void disable_edge_ioapic_irq(unsigned int irq) { }
    4.44 -static inline void mask_and_ack_level_ioapic_irq(unsigned int irq) { }
    4.45 -static inline void end_edge_ioapic_irq (unsigned int irq) { }
    4.46 -#define startup_level_ioapic	startup_level_ioapic_irq
    4.47 -#define shutdown_level_ioapic	mask_IO_APIC_irq
    4.48 -#define enable_level_ioapic	unmask_IO_APIC_irq
    4.49 -#define disable_level_ioapic	mask_IO_APIC_irq
    4.50 -#define mask_and_ack_level_ioapic mask_and_ack_level_ioapic_irq
    4.51 -#define end_level_ioapic	end_level_ioapic_irq
    4.52 -#define set_ioapic_affinity	set_ioapic_affinity_irq
    4.53 -
    4.54 -#define startup_edge_ioapic 	startup_edge_ioapic_irq
    4.55 -#define shutdown_edge_ioapic 	disable_edge_ioapic_irq
    4.56 -#define enable_edge_ioapic 	unmask_IO_APIC_irq
    4.57 -#define disable_edge_ioapic 	disable_edge_ioapic_irq
    4.58 -#define ack_edge_ioapic 	ack_edge_ioapic_irq
    4.59 -#define end_edge_ioapic 	end_edge_ioapic_irq
    4.60 -#endif
    4.61 -
    4.62 -#define IO_APIC_BASE(idx) \
    4.63 -		((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
    4.64 -		+ (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
    4.65 -
    4.66 -/*
    4.67 - * The structure of the IO-APIC:
    4.68 - */
    4.69 -union IO_APIC_reg_00 {
    4.70 -	u32	raw;
    4.71 -	struct {
    4.72 -		u32	__reserved_2	: 14,
    4.73 -			LTS		:  1,
    4.74 -			delivery_type	:  1,
    4.75 -			__reserved_1	:  8,
    4.76 -			ID		:  8;
    4.77 -	} __attribute__ ((packed)) bits;
    4.78 -};
    4.79 -
    4.80 -union IO_APIC_reg_01 {
    4.81 -	u32	raw;
    4.82 -	struct {
    4.83 -		u32	version		:  8,
    4.84 -			__reserved_2	:  7,
    4.85 -			PRQ		:  1,
    4.86 -			entries		:  8,
    4.87 -			__reserved_1	:  8;
    4.88 -	} __attribute__ ((packed)) bits;
    4.89 -};
    4.90 -
    4.91 -union IO_APIC_reg_02 {
    4.92 -	u32	raw;
    4.93 -	struct {
    4.94 -		u32	__reserved_2	: 24,
    4.95 -			arbitration	:  4,
    4.96 -			__reserved_1	:  4;
    4.97 -	} __attribute__ ((packed)) bits;
    4.98 -};
    4.99 -
   4.100 -union IO_APIC_reg_03 {
   4.101 -	u32	raw;
   4.102 -	struct {
   4.103 -		u32	boot_DT		:  1,
   4.104 -			__reserved_1	: 31;
   4.105 -	} __attribute__ ((packed)) bits;
   4.106 -};
   4.107 -
   4.108 -/*
   4.109 - * # of IO-APICs and # of IRQ routing registers
   4.110 - */
   4.111 -extern int nr_ioapics;
   4.112 -extern int nr_ioapic_registers[MAX_IO_APICS];
   4.113 -
   4.114 -enum ioapic_irq_destination_types {
   4.115 -	dest_Fixed = 0,
   4.116 -	dest_LowestPrio = 1,
   4.117 -	dest_SMI = 2,
   4.118 -	dest__reserved_1 = 3,
   4.119 -	dest_NMI = 4,
   4.120 -	dest_INIT = 5,
   4.121 -	dest__reserved_2 = 6,
   4.122 -	dest_ExtINT = 7
   4.123 -};
   4.124 -
   4.125 -struct IO_APIC_route_entry {
   4.126 -	__u32	vector		:  8,
   4.127 -		delivery_mode	:  3,	/* 000: FIXED
   4.128 -					 * 001: lowest prio
   4.129 -					 * 111: ExtINT
   4.130 -					 */
   4.131 -		dest_mode	:  1,	/* 0: physical, 1: logical */
   4.132 -		delivery_status	:  1,
   4.133 -		polarity	:  1,
   4.134 -		irr		:  1,
   4.135 -		trigger		:  1,	/* 0: edge, 1: level */
   4.136 -		mask		:  1,	/* 0: enabled, 1: disabled */
   4.137 -		__reserved_2	: 15;
   4.138 -
   4.139 -	union {		struct { __u32
   4.140 -					__reserved_1	: 24,
   4.141 -					physical_dest	:  4,
   4.142 -					__reserved_2	:  4;
   4.143 -			} physical;
   4.144 -
   4.145 -			struct { __u32
   4.146 -					__reserved_1	: 24,
   4.147 -					logical_dest	:  8;
   4.148 -			} logical;
   4.149 -	} dest;
   4.150 -
   4.151 -} __attribute__ ((packed));
   4.152 -
   4.153 -/*
   4.154 - * MP-BIOS irq configuration table structures:
   4.155 - */
   4.156 -
   4.157 -/* I/O APIC entries */
   4.158 -extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
   4.159 -
   4.160 -/* # of MP IRQ source entries */
   4.161 -extern int mp_irq_entries;
   4.162 -
   4.163 -/* MP IRQ source entries */
   4.164 -extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
   4.165 -
   4.166 -/* non-0 if default (table-less) MP configuration */
   4.167 -extern int mpc_default_type;
   4.168 -
   4.169 -static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
   4.170 -{
   4.171 -	physdev_op_t op;
   4.172 -	int ret;
   4.173 -
   4.174 -	op.cmd = PHYSDEVOP_APIC_READ;
   4.175 -	op.u.apic_op.apic = apic;
   4.176 -	op.u.apic_op.offset = reg;
   4.177 -	ret = HYPERVISOR_physdev_op(&op);
   4.178 -	if (ret)
   4.179 -		return ret;
   4.180 -	return op.u.apic_op.value;
   4.181 -}
   4.182 -
   4.183 -static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
   4.184 -{
   4.185 -	physdev_op_t op;
   4.186 -
   4.187 -	op.cmd = PHYSDEVOP_APIC_WRITE;
   4.188 -	op.u.apic_op.apic = apic;
   4.189 -	op.u.apic_op.offset = reg;
   4.190 -	op.u.apic_op.value = value;
   4.191 -	HYPERVISOR_physdev_op(&op);
   4.192 -}
   4.193 -
   4.194 -/*
   4.195 - * Re-write a value: to be used for read-modify-write
   4.196 - * cycles where the read already set up the index register.
   4.197 - *
   4.198 - * Older SiS APIC requires we rewrite the index regiser
   4.199 - */
   4.200 -extern int sis_apic_bug;
   4.201 -static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
   4.202 -{
   4.203 -	if (sis_apic_bug)
   4.204 -		*IO_APIC_BASE(apic) = reg;
   4.205 -	*(IO_APIC_BASE(apic)+4) = value;
   4.206 -}
   4.207 -
   4.208 -/* 1 if "noapic" boot option passed */
   4.209 -extern int skip_ioapic_setup;
   4.210 -
   4.211 -/*
   4.212 - * If we use the IO-APIC for IRQ routing, disable automatic
   4.213 - * assignment of PCI IRQ's.
   4.214 - */
   4.215 -#define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
   4.216 -
   4.217 -#ifdef CONFIG_ACPI_BOOT
   4.218 -extern int io_apic_get_unique_id (int ioapic, int apic_id);
   4.219 -extern int io_apic_get_version (int ioapic);
   4.220 -extern int io_apic_get_redir_entries (int ioapic);
   4.221 -extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
   4.222 -#endif /*CONFIG_ACPI_BOOT*/
   4.223 -
   4.224 -extern int (*ioapic_renumber_irq)(int ioapic, int irq);
   4.225 -
   4.226 -#else  /* !CONFIG_X86_IO_APIC */
   4.227 -#define io_apic_assign_pci_irqs 0
   4.228 -#endif
   4.229 -
   4.230 -extern int assign_irq_vector(int irq);
   4.231 -
   4.232 -#endif
     5.1 --- a/tools/libxc/xc_physdev.c	Thu May 05 16:46:07 2005 +0000
     5.2 +++ b/tools/libxc/xc_physdev.c	Thu May 05 17:58:59 2005 +0000
     5.3 @@ -16,14 +16,6 @@ int xc_physdev_pci_access_modify(int xc_
     5.4                                   int func,
     5.5                                   int enable)
     5.6  {
     5.7 -    dom0_op_t op;
     5.8 -
     5.9 -    op.cmd = DOM0_PCIDEV_ACCESS;
    5.10 -    op.u.pcidev_access.domain = (domid_t)domid;
    5.11 -    op.u.pcidev_access.bus    = bus;
    5.12 -    op.u.pcidev_access.dev    = dev;
    5.13 -    op.u.pcidev_access.func   = func;
    5.14 -    op.u.pcidev_access.enable = enable;
    5.15 -
    5.16 -    return do_dom0_op(xc_handle, &op);
    5.17 +    errno = ENOSYS;
    5.18 +    return -1;
    5.19  }
     6.1 --- a/xen/arch/ia64/domain.c	Thu May 05 16:46:07 2005 +0000
     6.2 +++ b/xen/arch/ia64/domain.c	Thu May 05 17:58:59 2005 +0000
     6.3 @@ -621,8 +621,6 @@ int construct_dom0(struct domain *d,
     6.4  	unsigned long pkern_entry;
     6.5  	unsigned long pkern_end;
     6.6  
     6.7 -	extern void physdev_init_dom0(struct domain *);
     6.8 -
     6.9  //printf("construct_dom0: starting\n");
    6.10  	/* Sanity! */
    6.11  #ifndef CLONE_DOMAIN0
    6.12 @@ -755,12 +753,6 @@ int construct_dom0(struct domain *d,
    6.13  #endif
    6.14  	console_endboot(strstr(cmdline, "tty0") != NULL);
    6.15  
    6.16 -	/* DOM0 gets access to everything. */
    6.17 -#ifdef CLONE_DOMAIN0
    6.18 -if (d == dom0)
    6.19 -#endif
    6.20 -	physdev_init_dom0(d);
    6.21 -
    6.22  	set_bit(DF_CONSTRUCTED, &d->d_flags);
    6.23  
    6.24  	new_thread(ed, pkern_entry, 0, 0);
     7.1 --- a/xen/arch/ia64/xenmisc.c	Thu May 05 16:46:07 2005 +0000
     7.2 +++ b/xen/arch/ia64/xenmisc.c	Thu May 05 17:58:59 2005 +0000
     7.3 @@ -150,33 +150,6 @@ void dump_pageframe_info(struct domain *
     7.4  }
     7.5  
     7.6  ///////////////////////////////
     7.7 -// from common/physdev.c
     7.8 -///////////////////////////////
     7.9 -void
    7.10 -physdev_init_dom0(struct domain *d)
    7.11 -{
    7.12 -}
    7.13 -
    7.14 -int
    7.15 -physdev_pci_access_modify(domid_t id, int bus, int dev, int func, int enable)
    7.16 -{
    7.17 -	return -EINVAL;
    7.18 -}
    7.19 -
    7.20 -void physdev_modify_ioport_access_range(struct domain *d, int enable,
    7.21 -	int port, int num)
    7.22 -{
    7.23 -	printk("physdev_modify_ioport_access_range not implemented\n");
    7.24 -	dummy();
    7.25 -}
    7.26 -
    7.27 -void physdev_destroy_state(struct domain *d)
    7.28 -{
    7.29 -	printk("physdev_destroy_state not implemented\n");
    7.30 -	dummy();
    7.31 -}
    7.32 -
    7.33 -///////////////////////////////
    7.34  // called from arch/ia64/head.S
    7.35  ///////////////////////////////
    7.36  
     8.1 --- a/xen/arch/ia64/xensetup.c	Thu May 05 16:46:07 2005 +0000
     8.2 +++ b/xen/arch/ia64/xensetup.c	Thu May 05 17:58:59 2005 +0000
     8.3 @@ -69,9 +69,6 @@ unsigned char opt_pdb[10] = "none";
     8.4  unsigned int opt_tbuf_size = 10;
     8.5  /* opt_sched: scheduler - default to Borrowed Virtual Time */
     8.6  char opt_sched[10] = "bvt";
     8.7 -/* opt_physdev_dom0_hide: list of PCI slots to hide from domain 0. */
     8.8 -/* Format is '(%02x:%02x.%1x)(%02x:%02x.%1x)' and so on. */
     8.9 -char opt_physdev_dom0_hide[200] = "";
    8.10  /* opt_leveltrigger, opt_edgetrigger: Force an IO-APIC-routed IRQ to be */
    8.11  /*                                    level- or edge-triggered.         */
    8.12  /* Example: 'leveltrigger=4,5,6,20 edgetrigger=21'. */
     9.1 --- a/xen/arch/x86/domain.c	Thu May 05 16:46:07 2005 +0000
     9.2 +++ b/xen/arch/x86/domain.c	Thu May 05 17:58:59 2005 +0000
     9.3 @@ -37,6 +37,7 @@
     9.4  #include <asm/vmx.h>
     9.5  #include <asm/vmx_vmcs.h>
     9.6  #include <asm/msr.h>
     9.7 +#include <asm/physdev.h>
     9.8  #include <xen/kernel.h>
     9.9  #include <public/io/ioreq.h>
    9.10  #include <xen/multicall.h>
    9.11 @@ -968,6 +969,8 @@ void domain_relinquish_resources(struct 
    9.12  
    9.13      BUG_ON(d->cpuset != 0);
    9.14  
    9.15 +    physdev_destroy_state(d);
    9.16 +
    9.17      ptwr_destroy(d);
    9.18  
    9.19      /* Release device mappings of other domains */
    10.1 --- a/xen/arch/x86/io_apic.c	Thu May 05 16:46:07 2005 +0000
    10.2 +++ b/xen/arch/x86/io_apic.c	Thu May 05 17:58:59 2005 +0000
    10.3 @@ -615,9 +615,7 @@ static inline int IO_APIC_irq_trigger(in
    10.4  
    10.5  int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 };
    10.6  
    10.7 -#ifdef CONFIG_VMX
    10.8  int vector_irq[256];
    10.9 -#endif
   10.10  
   10.11  int assign_irq_vector(int irq)
   10.12  {
   10.13 @@ -641,10 +639,10 @@ next:
   10.14  		panic("ran out of interrupt sources!");
   10.15  
   10.16  	IO_APIC_VECTOR(irq) = current_vector;
   10.17 -#ifdef CONFIG_VMX
   10.18 +
   10.19          vector_irq[current_vector] = irq;
   10.20 -        printk("vector_irq[%x] = %d\n", current_vector, irq);
   10.21 -#endif
   10.22 +        DPRINTK("vector_irq[%x] = %d\n", current_vector, irq);
   10.23 +
   10.24  	return current_vector;
   10.25  }
   10.26  
   10.27 @@ -1627,6 +1625,16 @@ static inline void check_timer(void)
   10.28  	panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
   10.29  }
   10.30  
   10.31 +#define NR_IOAPIC_BIOSIDS 256
   10.32 +static u8 ioapic_biosid_to_apic_enum[NR_IOAPIC_BIOSIDS];
   10.33 +static void store_ioapic_biosid_mapping(void)
   10.34 +{
   10.35 +    u8 apic;
   10.36 +    memset(ioapic_biosid_to_apic_enum, ~0, NR_IOAPIC_BIOSIDS);
   10.37 +    for ( apic = 0; apic < nr_ioapics; apic++ )
   10.38 +        ioapic_biosid_to_apic_enum[mp_ioapics[apic].mpc_apicid] = apic;
   10.39 +}
   10.40 +
   10.41  /*
   10.42   *
   10.43   * IRQ's that are handled by the old PIC in all cases:
   10.44 @@ -1646,6 +1654,8 @@ static inline void check_timer(void)
   10.45  
   10.46  void __init setup_IO_APIC(void)
   10.47  {
   10.48 +	store_ioapic_biosid_mapping();
   10.49 +
   10.50  	enable_IO_APIC();
   10.51  
   10.52  	io_apic_irqs = ~PIC_IRQS;
   10.53 @@ -1949,3 +1959,67 @@ static int __init ioapic_trigger_setup(v
   10.54  }
   10.55  
   10.56  __initcall(ioapic_trigger_setup);
   10.57 +
   10.58 +int ioapic_guest_read(int apicid, int address, u32 *pval)
   10.59 +{
   10.60 +    u32 val;
   10.61 +    int apicenum;
   10.62 +    struct IO_APIC_reg_00 reg_00;
   10.63 +    unsigned long flags;
   10.64 +
   10.65 +    if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
   10.66 +         ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
   10.67 +            return -EINVAL;
   10.68 +
   10.69 +    spin_lock_irqsave(&ioapic_lock, flags);
   10.70 +    val = io_apic_read(apicenum, address);
   10.71 +    spin_unlock_irqrestore(&ioapic_lock, flags);
   10.72 +
   10.73 +    /* Rewrite APIC ID to what the BIOS originally specified. */
   10.74 +    if ( address == 0 )
   10.75 +    {
   10.76 +        *(int *)&reg_00 = val;
   10.77 +        reg_00.ID = apicid;
   10.78 +        val = *(u32 *)&reg_00;
   10.79 +    }
   10.80 +
   10.81 +    *pval = val;
   10.82 +    return 0;
   10.83 +}
   10.84 +
   10.85 +int ioapic_guest_write(int apicid, int address, u32 val)
   10.86 +{
   10.87 +    int apicenum, pin, irq;
   10.88 +    struct IO_APIC_route_entry rte = { 0 };
   10.89 +    unsigned long flags;
   10.90 +
   10.91 +    if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
   10.92 +         ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
   10.93 +            return -EINVAL;
   10.94 +
   10.95 +    /* Only write to the first half of a route entry. */
   10.96 +    if ( (address < 0x10) || (address & 1) )
   10.97 +        return 0;
   10.98 +    
   10.99 +    pin = (address - 0x10) >> 1;
  10.100 +
  10.101 +    rte.dest.logical.logical_dest = target_cpus();
  10.102 +    *(int *)&rte = val;
  10.103 +
  10.104 +    /* Make sure we handle edge/level triggering correctly. */
  10.105 +    if ( !rte.mask )
  10.106 +    {
  10.107 +        irq = vector_irq[rte.vector];
  10.108 +        if ( !IO_APIC_IRQ(irq) )
  10.109 +            return 0;
  10.110 +        irq_desc[irq].handler = rte.trigger ? 
  10.111 +            &ioapic_level_irq_type: &ioapic_edge_irq_type;
  10.112 +    }
  10.113 +    
  10.114 +    spin_lock_irqsave(&ioapic_lock, flags);
  10.115 +    io_apic_write(apicenum, 0x10 + 2 * pin, *(((int *)&rte) + 0));
  10.116 +    io_apic_write(apicenum, 0x11 + 2 * pin, *(((int *)&rte) + 1));
  10.117 +    spin_unlock_irqrestore(&ioapic_lock, flags);
  10.118 +
  10.119 +    return 0;
  10.120 +}
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/arch/x86/physdev.c	Thu May 05 17:58:59 2005 +0000
    11.3 @@ -0,0 +1,145 @@
    11.4 +
    11.5 +#include <xen/config.h>
    11.6 +#include <xen/init.h>
    11.7 +#include <xen/lib.h>
    11.8 +#include <xen/types.h>
    11.9 +#include <xen/sched.h>
   11.10 +#include <xen/irq.h>
   11.11 +#include <xen/event.h>
   11.12 +#include <asm/smpboot.h>
   11.13 +#include <public/xen.h>
   11.14 +#include <public/physdev.h>
   11.15 +
   11.16 +extern void (*interrupt[])(void);
   11.17 +
   11.18 +extern int ioapic_guest_read(int apicid, int address, u32 *pval);
   11.19 +extern int ioapic_guest_write(int apicid, int address, u32 pval);
   11.20 +
   11.21 +void physdev_modify_ioport_access_range(
   11.22 +    struct domain *d, int enable, int port, int num)
   11.23 +{
   11.24 +    int i;
   11.25 +    for ( i = port; i < (port + num); i++ )
   11.26 +        (enable ? clear_bit : set_bit)(i, d->arch.iobmp_mask);
   11.27 +}
   11.28 +
   11.29 +void physdev_destroy_state(struct domain *d)
   11.30 +{
   11.31 +    xfree(d->arch.iobmp_mask);
   11.32 +    d->arch.iobmp_mask = NULL;
   11.33 +}
   11.34 +
   11.35 +/* Check if a domain controls a device with IO memory within frame @pfn.
   11.36 + * Returns: 1 if the domain should be allowed to map @pfn, 0 otherwise.  */
   11.37 +int domain_iomem_in_pfn(struct domain *p, unsigned long pfn)
   11.38 +{
   11.39 +    return 0;
   11.40 +}
   11.41 +
   11.42 +/*
   11.43 + * Demuxing hypercall.
   11.44 + */
   11.45 +long do_physdev_op(physdev_op_t *uop)
   11.46 +{
   11.47 +    physdev_op_t op;
   11.48 +    long         ret;
   11.49 +    int          irq;
   11.50 +
   11.51 +    if ( unlikely(copy_from_user(&op, uop, sizeof(op)) != 0) )
   11.52 +        return -EFAULT;
   11.53 +
   11.54 +    switch ( op.cmd )
   11.55 +    {
   11.56 +    case PHYSDEVOP_IRQ_UNMASK_NOTIFY:
   11.57 +        ret = pirq_guest_unmask(current->domain);
   11.58 +        break;
   11.59 +
   11.60 +    case PHYSDEVOP_IRQ_STATUS_QUERY:
   11.61 +        irq = op.u.irq_status_query.irq;
   11.62 +        ret = -EINVAL;
   11.63 +        if ( (irq < 0) || (irq >= NR_IRQS) )
   11.64 +            break;
   11.65 +        op.u.irq_status_query.flags = 0;
   11.66 +        /* Edge-triggered interrupts don't need an explicit unmask downcall. */
   11.67 +        if ( strstr(irq_desc[irq].handler->typename, "edge") == NULL )
   11.68 +            op.u.irq_status_query.flags |= PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY;
   11.69 +        ret = 0;
   11.70 +        break;
   11.71 +
   11.72 +    case PHYSDEVOP_APIC_READ:
   11.73 +        ret = -EPERM;
   11.74 +        if ( !IS_PRIV(current->domain) )
   11.75 +            break;
   11.76 +        ret = ioapic_guest_read(
   11.77 +            op.u.apic_op.apic, op.u.apic_op.offset, &op.u.apic_op.value);
   11.78 +        break;
   11.79 +
   11.80 +    case PHYSDEVOP_APIC_WRITE:
   11.81 +        ret = -EPERM;
   11.82 +        if ( !IS_PRIV(current->domain) )
   11.83 +            break;
   11.84 +        ret = ioapic_guest_write(
   11.85 +            op.u.apic_op.apic, op.u.apic_op.offset, op.u.apic_op.value);
   11.86 +        break;
   11.87 +
   11.88 +    case PHYSDEVOP_ASSIGN_VECTOR:
   11.89 +        if ( !IS_PRIV(current->domain) )
   11.90 +            return -EPERM;
   11.91 +
   11.92 +        if ( (irq = op.u.irq_op.irq) >= NR_IRQS )
   11.93 +            return -EINVAL;
   11.94 +        
   11.95 +        op.u.irq_op.vector = assign_irq_vector(irq);
   11.96 +        set_intr_gate(op.u.irq_op.vector, interrupt[irq]);
   11.97 +        ret = 0;
   11.98 +        break;
   11.99 +
  11.100 +    case PHYSDEVOP_SET_IOPL:
  11.101 +        ret = -EINVAL;
  11.102 +        if ( op.u.set_iopl.iopl > 3 )
  11.103 +            break;
  11.104 +        ret = 0;
  11.105 +        current->arch.iopl = op.u.set_iopl.iopl;
  11.106 +        break;
  11.107 +
  11.108 +    case PHYSDEVOP_SET_IOBITMAP:
  11.109 +        ret = -EINVAL;
  11.110 +        if ( !access_ok(op.u.set_iobitmap.bitmap, IOBMP_BYTES) ||
  11.111 +             (op.u.set_iobitmap.nr_ports > 65536) )
  11.112 +            break;
  11.113 +        ret = 0;
  11.114 +        current->arch.iobmp       = (u8 *)op.u.set_iobitmap.bitmap;
  11.115 +        current->arch.iobmp_limit = op.u.set_iobitmap.nr_ports;
  11.116 +        break;
  11.117 +    default:
  11.118 +        ret = -EINVAL;
  11.119 +        break;
  11.120 +    }
  11.121 +
  11.122 +    if ( copy_to_user(uop, &op, sizeof(op)) )
  11.123 +        ret = -EFAULT;
  11.124 +
  11.125 +    return ret;
  11.126 +}
  11.127 +
  11.128 +/* Domain 0 has read access to all devices. */
  11.129 +void physdev_init_dom0(struct domain *d)
  11.130 +{
  11.131 +    /* Access to all I/O ports. */
  11.132 +    d->arch.iobmp_mask = xmalloc_array(u8, IOBMP_BYTES);
  11.133 +    BUG_ON(d->arch.iobmp_mask == NULL);
  11.134 +    memset(d->arch.iobmp_mask, 0, IOBMP_BYTES);
  11.135 +
  11.136 +    set_bit(DF_PHYSDEV, &d->d_flags);
  11.137 +}
  11.138 +
  11.139 +
  11.140 +/*
  11.141 + * Local variables:
  11.142 + * mode: C
  11.143 + * c-set-style: "BSD"
  11.144 + * c-basic-offset: 4
  11.145 + * tab-width: 4
  11.146 + * indent-tabs-mode: nil
  11.147 + * End:
  11.148 + */
    12.1 --- a/xen/common/Makefile	Thu May 05 16:46:07 2005 +0000
    12.2 +++ b/xen/common/Makefile	Thu May 05 17:58:59 2005 +0000
    12.3 @@ -4,7 +4,6 @@ include $(BASEDIR)/Rules.mk
    12.4  ifeq ($(TARGET_ARCH),ia64) 
    12.5  OBJS := $(subst dom_mem_ops.o,,$(OBJS))
    12.6  OBJS := $(subst grant_table.o,,$(OBJS))
    12.7 -OBJS := $(subst physdev.o,,$(OBJS))
    12.8  endif
    12.9  
   12.10  ifneq ($(perfc),y)
    13.1 --- a/xen/common/dom0_ops.c	Thu May 05 16:46:07 2005 +0000
    13.2 +++ b/xen/common/dom0_ops.c	Thu May 05 17:58:59 2005 +0000
    13.3 @@ -16,7 +16,6 @@
    13.4  #include <asm/domain_page.h>
    13.5  #include <xen/trace.h>
    13.6  #include <xen/console.h>
    13.7 -#include <xen/physdev.h>
    13.8  #include <public/sched_ctl.h>
    13.9  
   13.10  extern long arch_do_dom0_op(dom0_op_t *op, dom0_op_t *u_dom0_op);
   13.11 @@ -385,16 +384,6 @@ long do_dom0_op(dom0_op_t *u_dom0_op)
   13.12      }
   13.13      break;
   13.14  
   13.15 -    case DOM0_PCIDEV_ACCESS:
   13.16 -    {
   13.17 -        ret = physdev_pci_access_modify(op->u.pcidev_access.domain, 
   13.18 -                                        op->u.pcidev_access.bus,
   13.19 -                                        op->u.pcidev_access.dev,
   13.20 -                                        op->u.pcidev_access.func,
   13.21 -                                        op->u.pcidev_access.enable);
   13.22 -    }
   13.23 -    break;
   13.24 -
   13.25      case DOM0_SCHED_ID:
   13.26      {
   13.27          op->u.sched_id.sched_id = sched_id();
    14.1 --- a/xen/common/domain.c	Thu May 05 16:46:07 2005 +0000
    14.2 +++ b/xen/common/domain.c	Thu May 05 17:58:59 2005 +0000
    14.3 @@ -50,10 +50,6 @@ struct domain *do_createdomain(domid_t d
    14.4      INIT_LIST_HEAD(&d->page_list);
    14.5      INIT_LIST_HEAD(&d->xenpage_list);
    14.6  
    14.7 -    /* Per-domain PCI-device list. */
    14.8 -    spin_lock_init(&d->pcidev_lock);
    14.9 -    INIT_LIST_HEAD(&d->pcidev_list);
   14.10 -    
   14.11      if ( (d->id != IDLE_DOMAIN_ID) &&
   14.12           ((init_event_channels(d) != 0) || (grant_table_create(d) != 0)) )
   14.13      {
   14.14 @@ -106,12 +102,6 @@ struct domain *find_domain_by_id(domid_t
   14.15  }
   14.16  
   14.17  
   14.18 -#ifndef CONFIG_IA64
   14.19 -extern void physdev_destroy_state(struct domain *d);
   14.20 -#else
   14.21 -#define physdev_destroy_state(_d) ((void)0)
   14.22 -#endif
   14.23 -
   14.24  void domain_kill(struct domain *d)
   14.25  {
   14.26      struct exec_domain *ed;
   14.27 @@ -122,7 +112,6 @@ void domain_kill(struct domain *d)
   14.28          for_each_exec_domain(d, ed)
   14.29              sched_rem_domain(ed);
   14.30          domain_relinquish_resources(d);
   14.31 -        physdev_destroy_state(d);
   14.32          put_domain(d);
   14.33      }
   14.34  }
    15.1 --- a/xen/common/physdev.c	Thu May 05 16:46:07 2005 +0000
    15.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.3 @@ -1,832 +0,0 @@
    15.4 -/****************************************************************************
    15.5 - * (c) 2004 - Rolf Neugebauer - Intel Research Cambridge
    15.6 - * (c) 2004 - Keir Fraser - University of Cambridge
    15.7 - ****************************************************************************
    15.8 - * 
    15.9 - * Description: allows a domain to access devices on the PCI bus
   15.10 - *
   15.11 - * A guest OS may be given access to particular devices on the PCI bus.
   15.12 - * For each domain a list of PCI devices is maintained, describing the
   15.13 - * access mode for the domain. 
   15.14 - *
   15.15 - * Guests can figure out the virtualised PCI space through normal PCI config
   15.16 - * register access. Some of the accesses, in particular write accesses, are
   15.17 - * faked. For example the sequence for detecting the IO regions, which requires
   15.18 - * writes to determine the size of the region, is faked out by a very simple
   15.19 - * state machine, preventing direct writes to the PCI config registers by a
   15.20 - * guest.
   15.21 - */
   15.22 -
   15.23 -#include <xen/config.h>
   15.24 -#include <xen/init.h>
   15.25 -#include <xen/lib.h>
   15.26 -#include <xen/types.h>
   15.27 -#include <xen/sched.h>
   15.28 -#include <xen/pci.h>
   15.29 -#include <xen/irq.h>
   15.30 -#include <xen/event.h>
   15.31 -#include <asm/pci.h>
   15.32 -#include <public/xen.h>
   15.33 -#include <public/physdev.h>
   15.34 -
   15.35 -/* Called by PHYSDEV_PCI_INITIALISE_DEVICE to finalise IRQ routing. */
   15.36 -extern void pcibios_enable_irq(struct pci_dev *dev);
   15.37 -
   15.38 -#if 0
   15.39 -#define VERBOSE_INFO(_f, _a...) printk( _f , ## _a )
   15.40 -#else
   15.41 -#define VERBOSE_INFO(_f, _a...) ((void)0)
   15.42 -#endif
   15.43 -
   15.44 -#ifdef VERBOSE
   15.45 -#define INFO(_f, _a...) printk( _f, ## _a )
   15.46 -#else
   15.47 -#define INFO(_f, _a...) ((void)0)
   15.48 -#endif
   15.49 -
   15.50 -#define SLOPPY_CHECKING
   15.51 -
   15.52 -#define ACC_READ  1
   15.53 -#define ACC_WRITE 2
   15.54 -
   15.55 -/* Upper bounds for PCI-device addressing. */
   15.56 -#define PCI_BUSMAX  255
   15.57 -#define PCI_DEVMAX   31
   15.58 -#define PCI_FUNCMAX   7
   15.59 -#define PCI_REGMAX  255
   15.60 -
   15.61 -/* Bit offsets into state. */
   15.62 -#define ST_BASE_ADDRESS  0   /* bits 0-5: are for base address access */
   15.63 -#define ST_ROM_ADDRESS   6   /* bit 6: is for rom address access */    
   15.64 -
   15.65 -typedef struct _phys_dev_st {
   15.66 -    int flags;                       /* flags for access etc */
   15.67 -    struct pci_dev *dev;             /* the device */
   15.68 -    struct list_head node;           /* link to the list */
   15.69 -    struct domain *owner;       /* 'owner of this device' */
   15.70 -    int state;                       /* state for various checks */
   15.71 -} phys_dev_t;
   15.72 -
   15.73 -
   15.74 -/* Find a device on a per-domain device list. */
   15.75 -static phys_dev_t *find_pdev(struct domain *d, struct pci_dev *dev)
   15.76 -{
   15.77 -    phys_dev_t *t;
   15.78 -    list_for_each_entry ( t, &d->pcidev_list, node )
   15.79 -        if ( dev == t->dev )
   15.80 -            return t;
   15.81 -    return NULL;
   15.82 -}
   15.83 -
   15.84 -static int setup_ioport_memory_access(struct domain *d, struct pci_dev *pdev)
   15.85 -{
   15.86 -    struct resource *r;
   15.87 -    int i, j;
   15.88 -
   15.89 -    if ( d->arch.iobmp_mask == NULL )
   15.90 -    {
   15.91 -        if ( (d->arch.iobmp_mask = xmalloc_array(u8, IOBMP_BYTES)) == NULL )
   15.92 -            return -ENOMEM;
   15.93 -        memset(d->arch.iobmp_mask, 0xFF, IOBMP_BYTES);
   15.94 -    }
   15.95 -
   15.96 -    for ( i = 0; i < DEVICE_COUNT_RESOURCE; i++ )
   15.97 -    {
   15.98 -        r = &pdev->resource[i];         
   15.99 -        if ( r->flags & IORESOURCE_IO )
  15.100 -        {
  15.101 -            INFO("Giving domain %u IO resources (%lx - %lx) "
  15.102 -                 "for device %s\n", d->id, r->start, r->end, pdev->slot_name);
  15.103 -            for ( j = r->start; j < r->end + 1; j++ )
  15.104 -                clear_bit(j, d->arch.iobmp_mask);
  15.105 -        }
  15.106 -    }
  15.107 -
  15.108 -    return 0;
  15.109 -}
  15.110 -
  15.111 -void physdev_modify_ioport_access_range(
  15.112 -    struct domain *d, int enable, int port, int num)
  15.113 -{
  15.114 -    int i;
  15.115 -    for ( i = port; i < (port + num); i++ )
  15.116 -        (enable ? clear_bit : set_bit)(i, d->arch.iobmp_mask);
  15.117 -}
  15.118 -
  15.119 -/* Add a device to a per-domain device-access list. */
  15.120 -static int add_dev_to_task(struct domain *d, struct pci_dev *dev, int acc)
  15.121 -{
  15.122 -    phys_dev_t *physdev;
  15.123 -    int         rc;
  15.124 -    
  15.125 -    if ( (physdev = xmalloc(phys_dev_t)) == NULL )
  15.126 -    {
  15.127 -        INFO("Error allocating pdev structure.\n");
  15.128 -        return -ENOMEM;
  15.129 -    }
  15.130 -    
  15.131 -    if ( (rc = setup_ioport_memory_access(d, dev)) < 0 )
  15.132 -    {
  15.133 -        xfree(physdev);
  15.134 -        return rc;
  15.135 -    }
  15.136 -
  15.137 -    physdev->dev = dev;
  15.138 -    physdev->flags = acc;
  15.139 -    physdev->state = 0;
  15.140 -    list_add(&physdev->node, &d->pcidev_list);
  15.141 -
  15.142 -    if ( acc == ACC_WRITE )
  15.143 -        physdev->owner = d;
  15.144 -
  15.145 -    return 0;
  15.146 -}
  15.147 -
  15.148 -void physdev_destroy_state(struct domain *d)
  15.149 -{
  15.150 -    struct list_head *ent;
  15.151 -
  15.152 -    xfree(d->arch.iobmp_mask);
  15.153 -    d->arch.iobmp_mask = NULL;
  15.154 -
  15.155 -    while ( (ent = d->pcidev_list.next) != &d->pcidev_list )
  15.156 -    {
  15.157 -        list_del(ent);
  15.158 -        xfree(list_entry(ent, phys_dev_t, node));
  15.159 -    }
  15.160 -}
  15.161 -
  15.162 -/*
  15.163 - * physdev_pci_access_modify:
  15.164 - * Allow/disallow access to a specific PCI device.  Guests should not be
  15.165 - * allowed to see bridge devices as it needlessly complicates things (one
  15.166 - * possible exception to this is the AGP bridge).
  15.167 - */
  15.168 -int physdev_pci_access_modify(domid_t dom, int bus, int dev, int func, 
  15.169 -                              int enable)
  15.170 -{
  15.171 -    struct domain *p;
  15.172 -    struct pci_dev *pdev;
  15.173 -    phys_dev_t *physdev;
  15.174 -    int rc = 0;
  15.175 -    int oldacc = -1;
  15.176 -
  15.177 -    BUG_ON(!IS_PRIV(current->domain));
  15.178 -
  15.179 -    if ( (bus > PCI_BUSMAX) || (dev > PCI_DEVMAX) || (func > PCI_FUNCMAX) )
  15.180 -        return -EINVAL;
  15.181 -
  15.182 -    if ( !enable )
  15.183 -    {
  15.184 -        INFO("Disallowing access is not yet supported.\n");
  15.185 -        return -EINVAL;
  15.186 -    }
  15.187 -
  15.188 -    INFO("physdev_pci_access_modify: %02x:%02x:%02x\n", bus, dev, func);
  15.189 -
  15.190 -    if ( (p = find_domain_by_id(dom)) == NULL ) 
  15.191 -        return -ESRCH;
  15.192 -
  15.193 -    /* Make the domain privileged. */
  15.194 -    set_bit(DF_PHYSDEV, &p->d_flags);
  15.195 -    /* FIXME: MAW for now make the domain REALLY privileged so that it
  15.196 -     * can run a backend driver (hw access should work OK otherwise) */
  15.197 -    set_bit(DF_PRIVILEGED, &p->d_flags);
  15.198 -
  15.199 -    /* Grant write access to the specified device. */
  15.200 -    if ( (pdev = pci_find_slot(bus, PCI_DEVFN(dev, func))) == NULL )
  15.201 -    {
  15.202 -        INFO("  dev does not exist\n");
  15.203 -        rc = -ENODEV;
  15.204 -        goto out;
  15.205 -    }
  15.206 -    
  15.207 -    INFO("  add RW %02x:%02x:%02x\n", pdev->bus->number,
  15.208 -         PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
  15.209 -
  15.210 -    if ( (physdev = find_pdev(p, pdev)) != NULL )
  15.211 -    {
  15.212 -        oldacc = physdev->flags;
  15.213 -        physdev->flags = ACC_WRITE;
  15.214 -    }
  15.215 -    else
  15.216 -    {
  15.217 -        rc = add_dev_to_task(p, pdev, ACC_WRITE);
  15.218 -    }
  15.219 -
  15.220 - out:
  15.221 -    put_domain(p);
  15.222 -    return rc;
  15.223 -}
  15.224 -
  15.225 -/* Check if a domain controls a device with IO memory within frame @pfn.
  15.226 - * Returns: 1 if the domain should be allowed to map @pfn, 0 otherwise.  */
  15.227 -int domain_iomem_in_pfn(struct domain *p, unsigned long pfn)
  15.228 -{
  15.229 -    int ret = 0;
  15.230 -    phys_dev_t *phys_dev;
  15.231 -
  15.232 -    VERBOSE_INFO("Checking if physdev-capable domain %u needs access to "
  15.233 -                 "pfn %p\n", p->id, pfn);
  15.234 -    
  15.235 -    spin_lock(&p->pcidev_lock);
  15.236 -
  15.237 -    list_for_each_entry ( phys_dev, &p->pcidev_list, node )
  15.238 -    {
  15.239 -        int i;
  15.240 -        struct pci_dev *pci_dev = phys_dev->dev;
  15.241 -
  15.242 -        for ( i = 0; (i < DEVICE_COUNT_RESOURCE) && (ret == 0); i++ )
  15.243 -        {
  15.244 -            struct resource *r = &pci_dev->resource[i];
  15.245 -            
  15.246 -            if ( r->flags & IORESOURCE_MEM )
  15.247 -                if ( (r->start >> PAGE_SHIFT) == pfn
  15.248 -                     || (r->end >> PAGE_SHIFT) == pfn
  15.249 -                     || ((r->start >> PAGE_SHIFT < pfn)
  15.250 -                         && (r->end >> PAGE_SHIFT > pfn)) )
  15.251 -                    ret = 1;
  15.252 -        }
  15.253 -
  15.254 -        if ( ret != 0 ) break;
  15.255 -    }
  15.256 -    
  15.257 -    spin_unlock(&p->pcidev_lock);
  15.258 -
  15.259 -    VERBOSE_INFO("Domain %u %s mapping of pfn %p\n",
  15.260 -                 p->id, ret ? "allowed" : "disallowed", pfn);
  15.261 -
  15.262 -    return ret;
  15.263 -}
  15.264 -
  15.265 -/* check if a domain has general access to a device */
  15.266 -static inline int check_dev_acc(
  15.267 -    struct domain *d, int bus, int dev, int func, phys_dev_t **pdev)
  15.268 -{
  15.269 -    struct pci_dev *target_dev;
  15.270 -    phys_dev_t     *target_pdev;
  15.271 -    unsigned int    target_devfn;
  15.272 -
  15.273 -    *pdev = NULL;
  15.274 -
  15.275 -     if ( !IS_CAPABLE_PHYSDEV(d) )
  15.276 -         return -EPERM;
  15.277 -
  15.278 -    if ( (bus > PCI_BUSMAX) || (dev > PCI_DEVMAX) || (func > PCI_FUNCMAX) )
  15.279 -        return -EINVAL;
  15.280 -
  15.281 -    VERBOSE_INFO("b=%x d=%x f=%x ", bus, dev, func);
  15.282 -
  15.283 -    /* check target device */
  15.284 -    target_devfn = PCI_DEVFN(dev, func);
  15.285 -    target_dev   = pci_find_slot(bus, target_devfn);
  15.286 -    if ( !target_dev )
  15.287 -    {
  15.288 -        VERBOSE_INFO("target does not exist\n");
  15.289 -        return -ENODEV;
  15.290 -    }
  15.291 -
  15.292 -    /* check access */
  15.293 -    target_pdev = find_pdev(d, target_dev);
  15.294 -    if ( !target_pdev )
  15.295 -    {
  15.296 -        VERBOSE_INFO("dom has no access to target\n");
  15.297 -        return -EPERM;
  15.298 -    }
  15.299 -
  15.300 -    *pdev = target_pdev;
  15.301 -    return 0;
  15.302 -}
  15.303 -
  15.304 -#ifndef SLOPPY_CHECKING
  15.305 -/*
  15.306 - * Base address registers contain the base address for IO regions.
  15.307 - * The length can be determined by writing all 1s to the register and
  15.308 - * reading the value again. The device will zero the lower unused bits.
  15.309 - * 
  15.310 - * to work out the length of the io region a device probe typically does:
  15.311 - * 1) a = read_base_addr_reg()
  15.312 - * 2) write_base_addr_reg(0xffffffff)
  15.313 - * 3) b = read_base_addr_reg()  [device zeros lower bits]
  15.314 - * 4) write_base_addr_reg(a)    [restore original value]
  15.315 - * this function fakes out step 2-4. *no* writes are made to the device.
  15.316 - * 
  15.317 - * phys_dev_t contains a bit field (a bit for each base address register).
  15.318 - * if the bit for a register is set the guest had writen all 1s to the 
  15.319 - * register and subsequent read request need to fake out the b.
  15.320 - * if the guest restores the original value (step 4 above) the bit is
  15.321 - * cleared again. If the guest attempts to "restores" a wrong value an
  15.322 - * error is flagged.
  15.323 - */
  15.324 -static int do_base_address_access(phys_dev_t *pdev, int acc, int idx, 
  15.325 -                                  int len, u32 *val)
  15.326 -{
  15.327 -    int st_bit, reg = PCI_BASE_ADDRESS_0 + (idx*4), ret = -EINVAL;
  15.328 -    struct pci_dev *dev = pdev->dev;
  15.329 -    u32 orig_val, sz;
  15.330 -    struct resource *res;
  15.331 -
  15.332 -    if ( len != sizeof(u32) )
  15.333 -    {
  15.334 -        /* This isn't illegal, but there doesn't seem to be a very good reason
  15.335 -         * to do it for normal devices (bridges are another matter).  Since it
  15.336 -         * would complicate the code below, we don't support this for now. */
  15.337 -
  15.338 -        /* We could set *val to some value but the guest may well be in trouble
  15.339 -         * anyway if this write fails.  Hopefully the printk will give us a
  15.340 -         * clue what went wrong. */
  15.341 -        INFO("Guest %u attempting sub-dword %s to BASE_ADDRESS %d\n",
  15.342 -             pdev->owner->id, (acc == ACC_READ) ? "read" : "write", idx);
  15.343 -        
  15.344 -        return -EPERM;
  15.345 -    }
  15.346 -
  15.347 -    st_bit = idx + ST_BASE_ADDRESS;
  15.348 -    res    = &(pdev->dev->resource[idx]);
  15.349 -
  15.350 -    if ( acc == ACC_WRITE )
  15.351 -    {
  15.352 -        if ( (*val == 0xffffffff) || 
  15.353 -             ((res->flags & IORESOURCE_IO) && (*val == 0xffff)) )
  15.354 -        {
  15.355 -            /* Set bit and return. */
  15.356 -            set_bit(st_bit, &pdev->state);
  15.357 -            ret = 0;
  15.358 -        }
  15.359 -        else
  15.360 -        {
  15.361 -            /* Assume guest wants to set the base address. */
  15.362 -            clear_bit(st_bit, &pdev->state);
  15.363 -
  15.364 -            /* check if guest tries to restore orig value */
  15.365 -            ret = pci_read_config_dword(dev, reg, &orig_val);
  15.366 -            if ( (ret == 0) && (*val != orig_val) ) 
  15.367 -            {
  15.368 -                INFO("Guest attempting update to BASE_ADDRESS %d\n", idx);
  15.369 -                ret = -EPERM;
  15.370 -            }
  15.371 -        }
  15.372 -        VERBOSE_INFO("fixed pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x"
  15.373 -                     " val=0x%08x %x\n", 
  15.374 -                     dev->bus->number, PCI_SLOT(dev->devfn), 
  15.375 -                     PCI_FUNC(dev->devfn), reg, len, *val, pdev->state);
  15.376 -    }
  15.377 -    else if ( acc == ACC_READ )
  15.378 -    {
  15.379 -        ret = pci_read_config_dword(dev, reg, val);
  15.380 -        if ( (ret == 0) && test_bit(st_bit, &pdev->state) )
  15.381 -        {
  15.382 -            /* Cook the value. */
  15.383 -            sz  = res->end - res->start;
  15.384 -            if ( res->flags & IORESOURCE_MEM )
  15.385 -            {
  15.386 -                /* this is written out explicitly for clarity */
  15.387 -                *val = 0xffffffff;
  15.388 -                /* bit    0 = 0 */
  15.389 -                /* bit  21  = memory type */
  15.390 -                /* bit 3    = prefetchable */
  15.391 -                /* bit 4-31 width */
  15.392 -                sz   = sz >> 4; /* size in blocks of 16 byte */
  15.393 -                sz   = ~sz;     /* invert */
  15.394 -                *val = *val & (sz << 4); /* and in the size */
  15.395 -                /* use read values for low 4 bits */
  15.396 -                *val = *val | (orig_val & 0xf);
  15.397 -            }
  15.398 -            else if ( res->flags & IORESOURCE_IO )
  15.399 -            {
  15.400 -                *val = 0x0000ffff;
  15.401 -                /* bit 10 = 01 */
  15.402 -                /* bit 2-31 width */
  15.403 -                sz   = sz >> 2; /* size in dwords */
  15.404 -                sz   = ~sz & 0x0000ffff;
  15.405 -                *val = *val & (sz << 2);
  15.406 -                *val = *val | 0x1;
  15.407 -            }
  15.408 -        }
  15.409 -        VERBOSE_INFO("fixed pci read: %02x:%02x:%02x reg=0x%02x len=0x%02x"
  15.410 -                     " val=0x%08x %x\n", 
  15.411 -                     dev->bus->number, PCI_SLOT(dev->devfn), 
  15.412 -                     PCI_FUNC(dev->devfn), reg, len, *val, pdev->state);
  15.413 -    }
  15.414 -
  15.415 -    return ret;
  15.416 -}
  15.417 -
  15.418 -
  15.419 -static int do_rom_address_access(phys_dev_t *pdev, int acc, int len, u32 *val)
  15.420 -{
  15.421 -    int st_bit, ret = -EINVAL;
  15.422 -    struct pci_dev *dev = pdev->dev;
  15.423 -    u32 orig_val, sz;
  15.424 -    struct resource *res;
  15.425 -
  15.426 -    if ( len != sizeof(u32) )
  15.427 -    {
  15.428 -        INFO("Guest attempting sub-dword %s to ROM_ADDRESS\n", 
  15.429 -             (acc == ACC_READ) ? "read" : "write");
  15.430 -        return -EPERM;
  15.431 -    }
  15.432 -
  15.433 -    st_bit = ST_ROM_ADDRESS;
  15.434 -    res = &(pdev->dev->resource[PCI_ROM_RESOURCE]);
  15.435 -
  15.436 -    if ( acc == ACC_WRITE )
  15.437 -    {
  15.438 -        if ( (*val == 0xffffffff) || (*val == 0xfffffffe) )
  15.439 -        {
  15.440 -            /* NB. 0xffffffff would be unusual, but we trap it anyway. */
  15.441 -            set_bit(st_bit, &pdev->state);
  15.442 -            ret = 0;
  15.443 -        }
  15.444 -        else
  15.445 -        {
  15.446 -            /* Assume guest wants simply to set the base address. */
  15.447 -            clear_bit(st_bit, &pdev->state);
  15.448 -            
  15.449 -            /* Check if guest tries to restore the original value. */
  15.450 -            ret = pci_read_config_dword(dev, PCI_ROM_ADDRESS, &orig_val);
  15.451 -            if ( (ret == 0) && (*val != orig_val) ) 
  15.452 -            {
  15.453 -                if ( (*val != 0x00000000) )
  15.454 -                {
  15.455 -                    INFO("caution: guest tried to change rom address.\n");
  15.456 -                    ret = -EPERM;
  15.457 -                }
  15.458 -                else
  15.459 -                {
  15.460 -                    INFO("guest disabled rom access for %02x:%02x:%02x\n",
  15.461 -                         dev->bus->number, PCI_SLOT(dev->devfn), 
  15.462 -                         PCI_FUNC(dev->devfn));
  15.463 -                }
  15.464 -            }
  15.465 -        }
  15.466 -        VERBOSE_INFO("fixed pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x"
  15.467 -                     " val=0x%08x %x\n", 
  15.468 -                     dev->bus->number, PCI_SLOT(dev->devfn), 
  15.469 -                     PCI_FUNC(dev->devfn), PCI_ROM_ADDRESS, len, *val, pdev->state);
  15.470 -    }
  15.471 -    else if ( acc == ACC_READ )
  15.472 -    {
  15.473 -        ret = pci_read_config_dword(dev, PCI_ROM_ADDRESS, val);
  15.474 -        if ( (ret == 0) && test_bit(st_bit, &pdev->state) )
  15.475 -        {
  15.476 -            /* Cook the value. */
  15.477 -            sz  = res->end - res->start;
  15.478 -            *val = 0xffffffff;
  15.479 -            /* leave bit 0 untouched */
  15.480 -            /* bit 1-10 reserved, harwired to 0 */
  15.481 -            sz = sz >> 11; /* size is in 2KB blocks */
  15.482 -            sz = ~sz;
  15.483 -            *val = *val & (sz << 11);
  15.484 -            *val = *val | (orig_val & 0x1);
  15.485 -        }
  15.486 -        VERBOSE_INFO("fixed pci read: %02x:%02x:%02x reg=0x%02x len=0x%02x"
  15.487 -                     " val=0x%08x %x\n", 
  15.488 -                     dev->bus->number, PCI_SLOT(dev->devfn), 
  15.489 -                     PCI_FUNC(dev->devfn), PCI_ROM_ADDRESS, len, *val, pdev->state);
  15.490 -    }
  15.491 -
  15.492 -    return ret;
  15.493 -
  15.494 -}
  15.495 -#endif /* SLOPPY_CHECKING */
  15.496 -
  15.497 -#ifdef CONFIG_PCI
  15.498 -/*
  15.499 - * Handle a PCI config space read access if the domain has access privileges.
  15.500 - */
  15.501 -static long pci_cfgreg_read(int bus, int dev, int func, int reg,
  15.502 -                            int len, u32 *val)
  15.503 -{
  15.504 -    int ret;
  15.505 -    phys_dev_t *pdev;
  15.506 -
  15.507 -    if ( (ret = check_dev_acc(current->domain, bus, dev, func, &pdev)) != 0 )
  15.508 -    {
  15.509 -        /* PCI spec states that reads from non-existent devices should return
  15.510 -         * all 1s.  In this case the domain has no read access, which should
  15.511 -         * also look like the device is non-existent. */
  15.512 -        *val = 0xFFFFFFFF;
  15.513 -        return ret;
  15.514 -    }
  15.515 -
  15.516 -    /* Fake out read requests for some registers. */
  15.517 -    switch ( reg )
  15.518 -    {
  15.519 -#ifndef SLOPPY_CHECKING
  15.520 -    case PCI_BASE_ADDRESS_0:
  15.521 -        ret = do_base_address_access(pdev, ACC_READ, 0, len, val);
  15.522 -        break;
  15.523 -
  15.524 -    case PCI_BASE_ADDRESS_1:
  15.525 -        ret = do_base_address_access(pdev, ACC_READ, 1, len, val);
  15.526 -        break;
  15.527 -
  15.528 -    case PCI_BASE_ADDRESS_2:
  15.529 -        ret = do_base_address_access(pdev, ACC_READ, 2, len, val);
  15.530 -        break;
  15.531 -
  15.532 -    case PCI_BASE_ADDRESS_3:
  15.533 -        ret = do_base_address_access(pdev, ACC_READ, 3, len, val);
  15.534 -        break;
  15.535 -
  15.536 -    case PCI_BASE_ADDRESS_4:
  15.537 -        ret = do_base_address_access(pdev, ACC_READ, 4, len, val);
  15.538 -        break;
  15.539 -
  15.540 -    case PCI_BASE_ADDRESS_5:
  15.541 -        ret = do_base_address_access(pdev, ACC_READ, 5, len, val);
  15.542 -        break;
  15.543 -
  15.544 -    case PCI_ROM_ADDRESS:
  15.545 -        ret = do_rom_address_access(pdev, ACC_READ, len, val);
  15.546 -        break;        
  15.547 -#endif
  15.548 -
  15.549 -    case PCI_INTERRUPT_LINE:
  15.550 -        *val = pdev->dev->irq;
  15.551 -        ret = 0;
  15.552 -        break;
  15.553 -
  15.554 -    default:
  15.555 -        ret = pci_config_read(0, bus, dev, func, reg, len, val);        
  15.556 -        VERBOSE_INFO("pci read : %02x:%02x:%02x reg=0x%02x len=0x%02x "
  15.557 -                     "val=0x%08x\n", bus, dev, func, reg, len, *val);
  15.558 -        break;
  15.559 -    }
  15.560 -
  15.561 -    return ret;
  15.562 -}
  15.563 -
  15.564 -
  15.565 -/*
  15.566 - * Handle a PCI config space write access if the domain has access privileges.
  15.567 - */
  15.568 -static long pci_cfgreg_write(int bus, int dev, int func, int reg,
  15.569 -                             int len, u32 val)
  15.570 -{
  15.571 -    int ret;
  15.572 -    phys_dev_t *pdev;
  15.573 -
  15.574 -    if ( (ret = check_dev_acc(current->domain, bus, dev, func, &pdev)) != 0 )
  15.575 -        return ret;
  15.576 -
  15.577 -    /* special treatment for some registers */
  15.578 -    switch (reg)
  15.579 -    {
  15.580 -#ifndef SLOPPY_CHECKING
  15.581 -    case PCI_BASE_ADDRESS_0:
  15.582 -        ret = do_base_address_access(pdev, ACC_WRITE, 0, len, &val);
  15.583 -        break;
  15.584 -
  15.585 -    case PCI_BASE_ADDRESS_1:
  15.586 -        ret = do_base_address_access(pdev, ACC_WRITE, 1, len, &val);
  15.587 -        break;
  15.588 -
  15.589 -    case PCI_BASE_ADDRESS_2:
  15.590 -        ret = do_base_address_access(pdev, ACC_WRITE, 2, len, &val);
  15.591 -        break;
  15.592 -
  15.593 -    case PCI_BASE_ADDRESS_3:
  15.594 -        ret = do_base_address_access(pdev, ACC_WRITE, 3, len, &val);
  15.595 -        break;
  15.596 -
  15.597 -    case PCI_BASE_ADDRESS_4:
  15.598 -        ret = do_base_address_access(pdev, ACC_WRITE, 4, len, &val);
  15.599 -        break;
  15.600 -
  15.601 -    case PCI_BASE_ADDRESS_5:
  15.602 -        ret = do_base_address_access(pdev, ACC_WRITE, 5, len, &val);
  15.603 -        break;
  15.604 -
  15.605 -    case PCI_ROM_ADDRESS:
  15.606 -        ret = do_rom_address_access(pdev, ACC_WRITE, len, &val);
  15.607 -        break;        
  15.608 -#endif
  15.609 -
  15.610 -    default:
  15.611 -        if ( pdev->flags != ACC_WRITE ) 
  15.612 -        {
  15.613 -            INFO("pci write not allowed %02x:%02x:%02x: "
  15.614 -                 "reg=0x%02x len=0x%02x val=0x%08x\n",
  15.615 -                 bus, dev, func, reg, len, val);
  15.616 -            ret = -EPERM;
  15.617 -        }
  15.618 -        else
  15.619 -        {
  15.620 -            ret = pci_config_write(0, bus, dev, func, reg, len, val);
  15.621 -            VERBOSE_INFO("pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x "
  15.622 -                         "val=0x%08x\n", bus, dev, func, reg, len, val);
  15.623 -        }
  15.624 -        break;
  15.625 -    }
  15.626 -
  15.627 -    return ret;
  15.628 -}
  15.629 -
  15.630 -
  15.631 -static long pci_probe_root_buses(u32 *busmask)
  15.632 -{
  15.633 -    phys_dev_t *pdev;
  15.634 -
  15.635 -    memset(busmask, 0, 256/8);
  15.636 -
  15.637 -    list_for_each_entry ( pdev, &current->domain->pcidev_list, node )
  15.638 -        set_bit(pdev->dev->bus->number, busmask);
  15.639 -
  15.640 -    return 0;
  15.641 -}
  15.642 -#endif
  15.643 -
  15.644 -/*
  15.645 - * Demuxing hypercall.
  15.646 - */
  15.647 -long do_physdev_op(physdev_op_t *uop)
  15.648 -{
  15.649 -    physdev_op_t op;
  15.650 -    long         ret;
  15.651 -    u32          apic, irq;
  15.652 -    u32          address, val;
  15.653 -
  15.654 -    if ( unlikely(copy_from_user(&op, uop, sizeof(op)) != 0) )
  15.655 -        return -EFAULT;
  15.656 -
  15.657 -    switch ( op.cmd )
  15.658 -    {
  15.659 -#ifdef CONFIG_PCI
  15.660 -    case PHYSDEVOP_PCI_CFGREG_READ:
  15.661 -        ret = pci_cfgreg_read(op.u.pci_cfgreg_read.bus,
  15.662 -                              op.u.pci_cfgreg_read.dev, 
  15.663 -                              op.u.pci_cfgreg_read.func,
  15.664 -                              op.u.pci_cfgreg_read.reg, 
  15.665 -                              op.u.pci_cfgreg_read.len,
  15.666 -                              &op.u.pci_cfgreg_read.value);
  15.667 -        break;
  15.668 -
  15.669 -    case PHYSDEVOP_PCI_CFGREG_WRITE:
  15.670 -        ret = pci_cfgreg_write(op.u.pci_cfgreg_write.bus,
  15.671 -                               op.u.pci_cfgreg_write.dev, 
  15.672 -                               op.u.pci_cfgreg_write.func,
  15.673 -                               op.u.pci_cfgreg_write.reg, 
  15.674 -                               op.u.pci_cfgreg_write.len,
  15.675 -                               op.u.pci_cfgreg_write.value);
  15.676 -        break;
  15.677 -
  15.678 -    case PHYSDEVOP_PCI_INITIALISE_DEVICE:
  15.679 -        if ( (ret = check_dev_acc(current->domain, 
  15.680 -                                  op.u.pci_initialise_device.bus, 
  15.681 -                                  op.u.pci_initialise_device.dev, 
  15.682 -                                  op.u.pci_initialise_device.func, 
  15.683 -                                  &pdev)) == 0 )
  15.684 -            pcibios_enable_irq(pdev->dev);
  15.685 -        break;
  15.686 -
  15.687 -    case PHYSDEVOP_PCI_PROBE_ROOT_BUSES:
  15.688 -        ret = pci_probe_root_buses(op.u.pci_probe_root_buses.busmask);
  15.689 -        break;
  15.690 -#endif
  15.691 -    case PHYSDEVOP_IRQ_UNMASK_NOTIFY:
  15.692 -        ret = pirq_guest_unmask(current->domain);
  15.693 -        break;
  15.694 -
  15.695 -    case PHYSDEVOP_IRQ_STATUS_QUERY:
  15.696 -        irq = op.u.irq_status_query.irq;
  15.697 -        ret = -EINVAL;
  15.698 -        if ( (irq < 0) || (irq >= NR_IRQS) )
  15.699 -            break;
  15.700 -        op.u.irq_status_query.flags = 0;
  15.701 -        /* Edge-triggered interrupts don't need an explicit unmask downcall. */
  15.702 -        if ( strstr(irq_desc[irq].handler->typename, "edge") == NULL )
  15.703 -            op.u.irq_status_query.flags |= PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY;
  15.704 -        ret = 0;
  15.705 -        break;
  15.706 -#ifdef __ARCH_HAS_IOAPIC
  15.707 -    case PHYSDEVOP_APIC_READ:
  15.708 -        if ( !IS_PRIV(current->domain) )
  15.709 -                return -EPERM;
  15.710 -
  15.711 -        apic = op.u.apic_op.apic;
  15.712 -        address = op.u.apic_op.offset;
  15.713 -        ret = -EINVAL;
  15.714 -        if (apic >= nr_ioapics)
  15.715 -            break;
  15.716 -        val = io_apic_read(apic, address);
  15.717 -        DPRINTK("ioapic read: %x = %x\n", address, val);
  15.718 -        op.u.apic_op.value = val;
  15.719 -        ret = 0;
  15.720 -        break;
  15.721 -    case PHYSDEVOP_APIC_WRITE:
  15.722 -        if ( !IS_PRIV(current->domain) )
  15.723 -                return -EPERM;
  15.724 -
  15.725 -        apic = op.u.apic_op.apic;
  15.726 -        address = op.u.apic_op.offset;
  15.727 -        val = op.u.apic_op.value;
  15.728 -        ret = -EINVAL;
  15.729 -        if (apic >= nr_ioapics)
  15.730 -            break;
  15.731 -
  15.732 -        DPRINTK("ioapic write: %x = %x\n", address, val);
  15.733 -        io_apic_write(apic, address, val);
  15.734 -        ret = 0;
  15.735 -        break;
  15.736 -    case PHYSDEVOP_ASSIGN_VECTOR:
  15.737 -        if ( !IS_PRIV(current->domain) )
  15.738 -                return -EPERM;
  15.739 -        
  15.740 -        irq = op.u.irq_op.irq;
  15.741 -        op.u.irq_op.vector = assign_irq_vector(irq);
  15.742 -        ret = 0;
  15.743 -        break;
  15.744 -#endif
  15.745 -    case PHYSDEVOP_SET_IOPL:
  15.746 -        ret = -EINVAL;
  15.747 -        if ( op.u.set_iopl.iopl > 3 )
  15.748 -            break;
  15.749 -        ret = 0;
  15.750 -        current->arch.iopl = op.u.set_iopl.iopl;
  15.751 -        break;
  15.752 -
  15.753 -    case PHYSDEVOP_SET_IOBITMAP:
  15.754 -        ret = -EINVAL;
  15.755 -        if ( !access_ok(op.u.set_iobitmap.bitmap, IOBMP_BYTES) ||
  15.756 -             (op.u.set_iobitmap.nr_ports > 65536) )
  15.757 -            break;
  15.758 -        ret = 0;
  15.759 -        current->arch.iobmp       = (u8 *)op.u.set_iobitmap.bitmap;
  15.760 -        current->arch.iobmp_limit = op.u.set_iobitmap.nr_ports;
  15.761 -        break;
  15.762 -    default:
  15.763 -        ret = -EINVAL;
  15.764 -        break;
  15.765 -    }
  15.766 -
  15.767 -    if (copy_to_user(uop, &op, sizeof(op)))
  15.768 -        ret = -EFAULT;
  15.769 -
  15.770 -    return ret;
  15.771 -}
  15.772 -
  15.773 -/* opt_physdev_dom0_hide: list of PCI slots to hide from domain 0. */
  15.774 -/* Format is '(%02x:%02x.%1x)(%02x:%02x.%1x)' and so on. */
  15.775 -static char opt_physdev_dom0_hide[200] = "";
  15.776 -string_param("physdev_dom0_hide", opt_physdev_dom0_hide);
  15.777 -
  15.778 -/* Test if boot params specify this device should NOT be visible to DOM0
  15.779 - * (e.g. so that another domain can control it instead) */
  15.780 -static int pcidev_dom0_hidden(struct pci_dev *dev)
  15.781 -{
  15.782 -    char cmp[10] = "(.......)";
  15.783 -    
  15.784 -    strncpy(&cmp[1], dev->slot_name, 7);
  15.785 -
  15.786 -    if ( strstr(opt_physdev_dom0_hide, dev->slot_name) == NULL )
  15.787 -        return 0;
  15.788 -    
  15.789 -    return 1;
  15.790 -}
  15.791 -
  15.792 -
  15.793 -/* Domain 0 has read access to all devices. */
  15.794 -void physdev_init_dom0(struct domain *d)
  15.795 -{
  15.796 -    struct pci_dev *dev;
  15.797 -    phys_dev_t *pdev;
  15.798 -
  15.799 -    /* Access to all I/O ports. */
  15.800 -    d->arch.iobmp_mask = xmalloc_array(u8, IOBMP_BYTES);
  15.801 -    BUG_ON(d->arch.iobmp_mask == NULL);
  15.802 -    memset(d->arch.iobmp_mask, 0, IOBMP_BYTES);
  15.803 -
  15.804 -    /* Access to all PCI devices. */
  15.805 -    pci_for_each_dev(dev)
  15.806 -    {
  15.807 -        if ( pcidev_dom0_hidden(dev) )
  15.808 -        {            
  15.809 -            printk("Hiding PCI device %s from DOM0\n", dev->slot_name);
  15.810 -            continue;
  15.811 -        }
  15.812 -
  15.813 -        pdev = xmalloc(phys_dev_t);
  15.814 -        BUG_ON(pdev == NULL);
  15.815 -
  15.816 -        pdev->dev = dev;
  15.817 -        pdev->flags = ACC_WRITE;
  15.818 -        pdev->state = 0;
  15.819 -        pdev->owner = d;
  15.820 -        list_add(&pdev->node, &d->pcidev_list);
  15.821 -    }
  15.822 -
  15.823 -    set_bit(DF_PHYSDEV, &d->d_flags);
  15.824 -}
  15.825 -
  15.826 -
  15.827 -/*
  15.828 - * Local variables:
  15.829 - * mode: C
  15.830 - * c-set-style: "BSD"
  15.831 - * c-basic-offset: 4
  15.832 - * tab-width: 4
  15.833 - * indent-tabs-mode: nil
  15.834 - * End:
  15.835 - */
    16.1 --- a/xen/drivers/char/serial.c	Thu May 05 16:46:07 2005 +0000
    16.2 +++ b/xen/drivers/char/serial.c	Thu May 05 17:58:59 2005 +0000
    16.3 @@ -15,9 +15,12 @@
    16.4  #include <xen/reboot.h>
    16.5  #include <xen/sched.h>
    16.6  #include <xen/serial.h>
    16.7 -#include <xen/physdev.h>
    16.8  #include <asm/io.h>
    16.9  
   16.10 +#ifdef CONFIG_X86
   16.11 +#include <asm/physdev.h>
   16.12 +#endif
   16.13 +
   16.14  /* Config serial port with a string <baud>,DPS,<io-base>,<irq>. */
   16.15  static char opt_com1[30] = OPT_COM1_STR, opt_com2[30] = OPT_COM2_STR;
   16.16  string_param("com1", opt_com1);
   16.17 @@ -482,10 +485,12 @@ void serial_force_unlock(int handle)
   16.18  
   16.19  void serial_endboot(void)
   16.20  {
   16.21 +#ifdef CONFIG_X86
   16.22      int i;
   16.23      for ( i = 0; i < ARRAY_SIZE(com); i++ )
   16.24          if ( UART_ENABLED(&com[i]) )
   16.25              physdev_modify_ioport_access_range(dom0, 0, com[i].io_base, 8);
   16.26 +#endif
   16.27  }
   16.28  
   16.29  /*
    17.1 --- a/xen/include/asm-x86/config.h	Thu May 05 16:46:07 2005 +0000
    17.2 +++ b/xen/include/asm-x86/config.h	Thu May 05 17:58:59 2005 +0000
    17.3 @@ -315,6 +315,4 @@ extern unsigned long xenheap_phys_end; /
    17.4  #define ELFSIZE 32
    17.5  #endif
    17.6  
    17.7 -#define __ARCH_HAS_IOAPIC
    17.8 -
    17.9  #endif /* __X86_CONFIG_H__ */
    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/xen/include/asm-x86/physdev.h	Thu May 05 17:58:59 2005 +0000
    18.3 @@ -0,0 +1,17 @@
    18.4 +/******************************************************************************
    18.5 + * physdev.h
    18.6 + */
    18.7 +
    18.8 +#ifndef __XEN_PHYSDEV_H__
    18.9 +#define __XEN_PHYSDEV_H__
   18.10 +
   18.11 +#include <public/physdev.h>
   18.12 +
   18.13 +void physdev_modify_ioport_access_range(
   18.14 +    struct domain *d, int enable, int port, int num );
   18.15 +void physdev_destroy_state(struct domain *d);
   18.16 +int domain_iomem_in_pfn(struct domain *p, unsigned long pfn);
   18.17 +long do_physdev_op(physdev_op_t *uop);
   18.18 +void physdev_init_dom0(struct domain *d);
   18.19 +
   18.20 +#endif /* __XEN_PHYSDEV_H__ */
    19.1 --- a/xen/include/public/dom0_ops.h	Thu May 05 16:46:07 2005 +0000
    19.2 +++ b/xen/include/public/dom0_ops.h	Thu May 05 17:58:59 2005 +0000
    19.3 @@ -208,19 +208,6 @@ typedef struct {
    19.4      memory_t free_pages;
    19.5  } dom0_physinfo_t;
    19.6  
    19.7 -/* 
    19.8 - * Allow a domain access to a physical PCI device
    19.9 - */
   19.10 -#define DOM0_PCIDEV_ACCESS    23
   19.11 -typedef struct {
   19.12 -    /* IN variables. */
   19.13 -    domid_t      domain;
   19.14 -    u32          bus;
   19.15 -    u32          dev;
   19.16 -    u32          func;
   19.17 -    u32          enable;
   19.18 -} dom0_pcidev_access_t;
   19.19 -
   19.20  /*
   19.21   * Get the ID of the current scheduler.
   19.22   */
   19.23 @@ -376,7 +363,6 @@ typedef struct {
   19.24          dom0_pincpudomain_t      pincpudomain;
   19.25          dom0_tbufcontrol_t       tbufcontrol;
   19.26          dom0_physinfo_t          physinfo;
   19.27 -        dom0_pcidev_access_t     pcidev_access;
   19.28          dom0_sched_id_t          sched_id;
   19.29          dom0_shadow_control_t    shadow_control;
   19.30          dom0_setdomainmaxmem_t   setdomainmaxmem;
    20.1 --- a/xen/include/public/physdev.h	Thu May 05 16:46:07 2005 +0000
    20.2 +++ b/xen/include/public/physdev.h	Thu May 05 17:58:59 2005 +0000
    20.3 @@ -1,18 +1,8 @@
    20.4 -/****************************************************************************
    20.5 - * (c) 2004 - Rolf Neugebauer - Intel Research Cambridge
    20.6 - * (c) 2004 - Keir Fraser - University of Cambridge
    20.7 - ****************************************************************************
    20.8 - * Description: Interface for domains to access physical devices on the PCI bus
    20.9 - */
   20.10  
   20.11  #ifndef __XEN_PUBLIC_PHYSDEV_H__
   20.12  #define __XEN_PUBLIC_PHYSDEV_H__
   20.13  
   20.14  /* Commands to HYPERVISOR_physdev_op() */
   20.15 -#define PHYSDEVOP_PCI_CFGREG_READ       0
   20.16 -#define PHYSDEVOP_PCI_CFGREG_WRITE      1
   20.17 -#define PHYSDEVOP_PCI_INITIALISE_DEVICE 2
   20.18 -#define PHYSDEVOP_PCI_PROBE_ROOT_BUSES  3
   20.19  #define PHYSDEVOP_IRQ_UNMASK_NOTIFY     4
   20.20  #define PHYSDEVOP_IRQ_STATUS_QUERY      5
   20.21  #define PHYSDEVOP_SET_IOPL              6
   20.22 @@ -21,43 +11,6 @@
   20.23  #define PHYSDEVOP_APIC_WRITE            9
   20.24  #define PHYSDEVOP_ASSIGN_VECTOR         10
   20.25  
   20.26 -/* Read from PCI configuration space. */
   20.27 -typedef struct {
   20.28 -    /* IN */
   20.29 -    u32 bus;                          /*  0 */
   20.30 -    u32 dev;                          /*  4 */
   20.31 -    u32 func;                         /*  8 */
   20.32 -    u32 reg;                          /* 12 */
   20.33 -    u32 len;                          /* 16 */
   20.34 -    /* OUT */
   20.35 -    u32 value;                        /* 20 */
   20.36 -} PACKED physdevop_pci_cfgreg_read_t; /* 24 bytes */
   20.37 -
   20.38 -/* Write to PCI configuration space. */
   20.39 -typedef struct {
   20.40 -    /* IN */
   20.41 -    u32 bus;                          /*  0 */
   20.42 -    u32 dev;                          /*  4 */
   20.43 -    u32 func;                         /*  8 */
   20.44 -    u32 reg;                          /* 12 */
   20.45 -    u32 len;                          /* 16 */
   20.46 -    u32 value;                        /* 20 */
   20.47 -} PACKED physdevop_pci_cfgreg_write_t; /* 24 bytes */
   20.48 -
   20.49 -/* Do final initialisation of a PCI device (e.g., last-moment IRQ routing). */
   20.50 -typedef struct {
   20.51 -    /* IN */
   20.52 -    u32 bus;                          /*  0 */
   20.53 -    u32 dev;                          /*  4 */
   20.54 -    u32 func;                         /*  8 */
   20.55 -} PACKED physdevop_pci_initialise_device_t; /* 12 bytes */
   20.56 -
   20.57 -/* Find the root buses for subsequent scanning. */
   20.58 -typedef struct {
   20.59 -    /* OUT */
   20.60 -    u32 busmask[256/32];              /*  0 */
   20.61 -} PACKED physdevop_pci_probe_root_buses_t; /* 32 bytes */
   20.62 -
   20.63  typedef struct {
   20.64      /* IN */
   20.65      u32 irq;                          /*  0 */
   20.66 @@ -85,7 +38,7 @@ typedef struct {
   20.67      u32 apic;                          /*  0 */
   20.68      u32 offset;
   20.69      /* IN or OUT */
   20.70 -    u64 value;
   20.71 +    u32 value;
   20.72  } PACKED physdevop_apic_t; 
   20.73  
   20.74  typedef struct {
   20.75 @@ -100,12 +53,6 @@ typedef struct _physdev_op_st
   20.76      u32 cmd;                          /*  0 */
   20.77      u32 __pad;                        /*  4 */
   20.78      union {                           /*  8 */
   20.79 -#ifdef CONFIG_PCI
   20.80 -        physdevop_pci_cfgreg_read_t       pci_cfgreg_read;
   20.81 -        physdevop_pci_cfgreg_write_t      pci_cfgreg_write;
   20.82 -        physdevop_pci_initialise_device_t pci_initialise_device;
   20.83 -        physdevop_pci_probe_root_buses_t  pci_probe_root_buses;
   20.84 -#endif
   20.85          physdevop_irq_status_query_t      irq_status_query;
   20.86          physdevop_set_iopl_t              set_iopl;
   20.87          physdevop_set_iobitmap_t          set_iobitmap;
    21.1 --- a/xen/include/xen/physdev.h	Thu May 05 16:46:07 2005 +0000
    21.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.3 @@ -1,19 +0,0 @@
    21.4 -/******************************************************************************
    21.5 - * physdev.h
    21.6 - */
    21.7 -
    21.8 -#ifndef __XEN_PHYSDEV_H__
    21.9 -#define __XEN_PHYSDEV_H__
   21.10 -
   21.11 -#include <public/physdev.h>
   21.12 -
   21.13 -void physdev_modify_ioport_access_range(
   21.14 -    struct domain *d, int enable, int port, int num );
   21.15 -void physdev_destroy_state(struct domain *d);
   21.16 -int physdev_pci_access_modify(
   21.17 -    domid_t dom, int bus, int dev, int func, int enable);
   21.18 -int domain_iomem_in_pfn(struct domain *p, unsigned long pfn);
   21.19 -long do_physdev_op(physdev_op_t *uop);
   21.20 -void physdev_init_dom0(struct domain *d);
   21.21 -
   21.22 -#endif /* __XEN_PHYSDEV_H__ */
    22.1 --- a/xen/include/xen/sched.h	Thu May 05 16:46:07 2005 +0000
    22.2 +++ b/xen/include/xen/sched.h	Thu May 05 17:58:59 2005 +0000
    22.3 @@ -129,10 +129,6 @@ struct domain
    22.4      u16 pirq_to_evtchn[NR_PIRQS];
    22.5      u32 pirq_mask[NR_PIRQS/32];
    22.6  
    22.7 -    /* Physical I/O */
    22.8 -    spinlock_t       pcidev_lock;
    22.9 -    struct list_head pcidev_list;
   22.10 -
   22.11      unsigned long d_flags;
   22.12      unsigned long vm_assist;
   22.13