ia64/xen-unstable

changeset 328:47f6cdee5a9b

bitkeeper revision 1.145 (3e76131eo2ToZ75trWvK5ELYWyDIXQ)

pci_ids.h, pci.ids, tg3.h, tg3.c:
Brand new exciting tg3 driver. IAP can test this :-)
author kaf24@scramble.cl.cam.ac.uk
date Mon Mar 17 18:25:34 2003 +0000 (2003-03-17)
parents cdaace96648d
children 79e370880245
files xen/drivers/net/tg3.c xen/drivers/net/tg3.h xen/drivers/pci/pci.ids xen/include/xeno/pci_ids.h
line diff
     1.1 --- a/xen/drivers/net/tg3.c	Sun Mar 16 19:38:44 2003 +0000
     1.2 +++ b/xen/drivers/net/tg3.c	Mon Mar 17 18:25:34 2003 +0000
     1.3 @@ -1,4 +1,4 @@
     1.4 -/* $Id: tg3.c,v 1.43.2.80 2002/03/14 00:10:04 davem Exp $
     1.5 +/*
     1.6   * tg3.c: Broadcom Tigon3 ethernet driver.
     1.7   *
     1.8   * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
     1.9 @@ -9,9 +9,9 @@
    1.10  
    1.11  #include <linux/module.h>
    1.12  
    1.13 -//#include <linux/kernel.h>
    1.14 +#include <linux/lib.h>
    1.15  #include <linux/types.h>
    1.16 -//#include <linux/compiler.h>
    1.17 +#include <linux/tqueue.h>
    1.18  #include <linux/slab.h>
    1.19  #include <linux/delay.h>
    1.20  #include <linux/init.h>
    1.21 @@ -50,8 +50,8 @@
    1.22  
    1.23  #define DRV_MODULE_NAME		"tg3"
    1.24  #define PFX DRV_MODULE_NAME	": "
    1.25 -#define DRV_MODULE_VERSION	"1.2a"
    1.26 -#define DRV_MODULE_RELDATE	"Dec 9, 2002"
    1.27 +#define DRV_MODULE_VERSION	"1.4c"
    1.28 +#define DRV_MODULE_RELDATE	"Feb 18, 2003"
    1.29  
    1.30  #define TG3_DEF_MAC_MODE	0
    1.31  #define TG3_DEF_RX_MODE		0
    1.32 @@ -137,6 +137,12 @@ static struct pci_device_id tg3_pci_tbl[
    1.33  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
    1.34  	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
    1.35  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
    1.36 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
    1.37 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
    1.38 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
    1.39 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
    1.40 +	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
    1.41 +	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
    1.42  	{ PCI_VENDOR_ID_SYSKONNECT, 0x4400,
    1.43  	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
    1.44  	{ PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
    1.45 @@ -159,6 +165,8 @@ static void tg3_write_indirect_reg32(str
    1.46  		spin_unlock_irqrestore(&tp->indirect_lock, flags);
    1.47  	} else {
    1.48  		writel(val, tp->regs + off);
    1.49 +		if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
    1.50 +			readl(tp->regs + off);
    1.51  	}
    1.52  }
    1.53  
    1.54 @@ -204,6 +212,12 @@ static void tg3_disable_ints(struct tg3 
    1.55  	tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
    1.56  }
    1.57  
    1.58 +static inline void tg3_cond_int(struct tg3 *tp)
    1.59 +{
    1.60 +	if (tp->hw_status->status & SD_STATUS_UPDATED)
    1.61 +		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
    1.62 +}
    1.63 +
    1.64  static void tg3_enable_ints(struct tg3 *tp)
    1.65  {
    1.66  	tw32(TG3PCI_MISC_HOST_CTRL,
    1.67 @@ -211,9 +225,61 @@ static void tg3_enable_ints(struct tg3 *
    1.68  	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000);
    1.69  	tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
    1.70  
    1.71 -	if (tp->hw_status->status & SD_STATUS_UPDATED)
    1.72 -		tw32(GRC_LOCAL_CTRL,
    1.73 -		     tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
    1.74 +	tg3_cond_int(tp);
    1.75 +}
    1.76 +
    1.77 +#ifdef NAPI
    1.78 +/* these netif_xxx funcs should be moved into generic net layer */
    1.79 +static void netif_poll_disable(struct net_device *dev)
    1.80 +{
    1.81 +	while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) {
    1.82 +		current->state = TASK_INTERRUPTIBLE;
    1.83 +		schedule_timeout(1);
    1.84 +	}
    1.85 +}
    1.86 +
    1.87 +static inline void netif_poll_enable(struct net_device *dev)
    1.88 +{
    1.89 +	clear_bit(__LINK_STATE_RX_SCHED, &dev->state);
    1.90 +}
    1.91 +
    1.92 +/* same as netif_rx_complete, except that local_irq_save(flags)
    1.93 + * has already been issued
    1.94 + */
    1.95 +static inline void __netif_rx_complete(struct net_device *dev)
    1.96 +{
    1.97 +	if (!test_bit(__LINK_STATE_RX_SCHED, &dev->state)) BUG();
    1.98 +	list_del(&dev->poll_list);
    1.99 +	clear_bit(__LINK_STATE_RX_SCHED, &dev->state);
   1.100 +}
   1.101 +#endif
   1.102 +
   1.103 +static inline void netif_tx_disable(struct net_device *dev)
   1.104 +{
   1.105 +	spin_lock_bh(&dev->xmit_lock);
   1.106 +	netif_stop_queue(dev);
   1.107 +	spin_unlock_bh(&dev->xmit_lock);
   1.108 +}
   1.109 +
   1.110 +static inline void tg3_netif_stop(struct tg3 *tp)
   1.111 +{
   1.112 +#ifdef NAPI
   1.113 +	netif_poll_disable(tp->dev);
   1.114 +#endif
   1.115 +	netif_tx_disable(tp->dev);
   1.116 +}
   1.117 +
   1.118 +static inline void tg3_netif_start(struct tg3 *tp)
   1.119 +{
   1.120 +	netif_wake_queue(tp->dev);
   1.121 +	/* NOTE: unconditional netif_wake_queue is only appropriate
   1.122 +	 * so long as all callers are assured to have free tx slots
   1.123 +	 * (such as after tg3_init_hw)
   1.124 +	 */
   1.125 +#ifdef NAPI
   1.126 +	netif_poll_enable(tp->dev);
   1.127 +#endif
   1.128 +	tg3_cond_int(tp);
   1.129  }
   1.130  
   1.131  static void tg3_switch_clocks(struct tg3 *tp)
   1.132 @@ -375,7 +441,6 @@ static int tg3_phy_reset(struct tg3 *tp,
   1.133  }
   1.134  
   1.135  static int tg3_setup_phy(struct tg3 *);
   1.136 -static int tg3_halt(struct tg3 *);
   1.137  
   1.138  static int tg3_set_power_state(struct tg3 *tp, int state)
   1.139  {
   1.140 @@ -446,8 +511,6 @@ static int tg3_set_power_state(struct tg
   1.141  		tg3_setup_phy(tp);
   1.142  	}
   1.143  
   1.144 -	tg3_halt(tp);
   1.145 -
   1.146  	pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
   1.147  
   1.148  	if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
   1.149 @@ -879,6 +942,20 @@ static int tg3_setup_copper_phy(struct t
   1.150  
   1.151  	tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
   1.152  
   1.153 +	/* Some third-party PHYs need to be reset on link going
   1.154 +	 * down.
   1.155 +	 *
   1.156 +	 * XXX 5705 note: This workaround also applies to 5705_a0
   1.157 +	 */
   1.158 +	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
   1.159 +	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
   1.160 +	    netif_carrier_ok(tp->dev)) {
   1.161 +		tg3_readphy(tp, MII_BMSR, &bmsr);
   1.162 +		tg3_readphy(tp, MII_BMSR, &bmsr);
   1.163 +		if (!(bmsr & BMSR_LSTATUS))
   1.164 +			tg3_phy_reset(tp, 1);
   1.165 +	}
   1.166 +
   1.167  	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
   1.168  		tg3_readphy(tp, MII_BMSR, &bmsr);
   1.169  		tg3_readphy(tp, MII_BMSR, &bmsr);
   1.170 @@ -1937,13 +2014,12 @@ static int tg3_rx(struct tg3 *tp, int bu
   1.171  		}
   1.172  
   1.173  		if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
   1.174 -		    (desc->type_flags & RXD_FLAG_TCPUDP_CSUM)) {
   1.175 -			skb->csum = htons((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
   1.176 -					  >> RXD_TCPCSUM_SHIFT);
   1.177 -			skb->ip_summed = CHECKSUM_HW;
   1.178 -		} else {
   1.179 +		    (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
   1.180 +		    (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
   1.181 +		      >> RXD_TCPCSUM_SHIFT) == 0xffff))
   1.182 +			skb->ip_summed = CHECKSUM_UNNECESSARY;
   1.183 +		else
   1.184  			skb->ip_summed = CHECKSUM_NONE;
   1.185 -		}
   1.186  
   1.187  		skb->protocol = eth_type_trans(skb, tp->dev);
   1.188  #if TG3_VLAN_TAG_USED
   1.189 @@ -1953,11 +2029,10 @@ static int tg3_rx(struct tg3 *tp, int bu
   1.190  				    desc->err_vlan & RXD_VLAN_MASK);
   1.191  		} else
   1.192  #endif
   1.193 -
   1.194  #ifdef NAPI
   1.195  			netif_receive_skb(skb);
   1.196  #else
   1.197 -		        netif_rx(skb);
   1.198 +			netif_rx(skb);
   1.199  #endif
   1.200  		tp->dev->last_rx = jiffies;
   1.201  		received++;
   1.202 @@ -2000,11 +2075,12 @@ static int tg3_poll(struct net_device *n
   1.203  {
   1.204  	struct tg3 *tp = netdev->priv;
   1.205  	struct tg3_hw_status *sblk = tp->hw_status;
   1.206 +	unsigned long flags;
   1.207  	int done;
   1.208 -#ifdef NAPI
   1.209 -	unsigned long flags;
   1.210 +
   1.211  	spin_lock_irqsave(&tp->lock, flags);
   1.212 -#endif
   1.213 +
   1.214 +	/* handle link change and other phy events */
   1.215  	if (!(tp->tg3_flags &
   1.216  	      (TG3_FLAG_USE_LINKCHG_REG |
   1.217  	       TG3_FLAG_POLL_SERDES))) {
   1.218 @@ -2015,26 +2091,33 @@ static int tg3_poll(struct net_device *n
   1.219  		}
   1.220  	}
   1.221  
   1.222 +	/* run TX completion thread */
   1.223  	if (sblk->idx[0].tx_consumer != tp->tx_cons) {
   1.224  		spin_lock(&tp->tx_lock);
   1.225  		tg3_tx(tp);
   1.226  		spin_unlock(&tp->tx_lock);
   1.227  	}
   1.228  
   1.229 +	spin_unlock_irqrestore(&tp->lock, flags);
   1.230 +
   1.231 +	/* run RX thread, within the bounds set by NAPI.
   1.232 +	 * All RX "locking" is done by ensuring outside
   1.233 +	 * code synchronizes with dev->poll()
   1.234 +	 */
   1.235  	done = 1;
   1.236  	if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
   1.237  		int work_done;
   1.238  #ifdef NAPI
   1.239  		int orig_budget = *budget;
   1.240 +
   1.241  		if (orig_budget > netdev->quota)
   1.242  			orig_budget = netdev->quota;
   1.243  
   1.244  		work_done = tg3_rx(tp, orig_budget);
   1.245 -		
   1.246 +
   1.247  		*budget -= work_done;
   1.248  		netdev->quota -= work_done;
   1.249  
   1.250 -
   1.251  		if (work_done >= orig_budget)
   1.252  			done = 0;
   1.253  #else
   1.254 @@ -2042,12 +2125,13 @@ static int tg3_poll(struct net_device *n
   1.255  #endif
   1.256  	}
   1.257  #ifdef NAPI
   1.258 +	/* if no more work, tell net stack and NIC we're done */
   1.259  	if (done) {
   1.260 -		netif_rx_complete(netdev);
   1.261 +		spin_lock_irqsave(&tp->lock, flags);
   1.262 +		__netif_rx_complete(netdev);
   1.263  		tg3_enable_ints(tp);
   1.264 -	}
   1.265 -
   1.266 -	spin_unlock_irqrestore(&tp->lock, flags);
   1.267 +		spin_unlock_irqrestore(&tp->lock, flags);
   1.268 +	}
   1.269  #endif
   1.270  	return (done ? 0 : 1);
   1.271  }
   1.272 @@ -2057,12 +2141,14 @@ static inline unsigned int tg3_has_work(
   1.273  	struct tg3_hw_status *sblk = tp->hw_status;
   1.274  	unsigned int work_exists = 0;
   1.275  
   1.276 +	/* check for phy events */
   1.277  	if (!(tp->tg3_flags &
   1.278  	      (TG3_FLAG_USE_LINKCHG_REG |
   1.279  	       TG3_FLAG_POLL_SERDES))) {
   1.280  		if (sblk->status & SD_STATUS_LINK_CHG)
   1.281  			work_exists = 1;
   1.282  	}
   1.283 +	/* check for RX/TX work to do */
   1.284  	if (sblk->idx[0].tx_consumer != tp->tx_cons ||
   1.285  	    sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
   1.286  		work_exists = 1;
   1.287 @@ -2080,16 +2166,30 @@ static void tg3_interrupt(int irq, void 
   1.288  	unsigned long flags;
   1.289  
   1.290  	spin_lock_irqsave(&tp->lock, flags);
   1.291 -#if NAPI
   1.292 +#ifdef NAPI
   1.293  	if (sblk->status & SD_STATUS_UPDATED) {
   1.294 +		/*
   1.295 +		 * writing any value to intr-mbox-0 clears PCI INTA# and
   1.296 +		 * chip-internal interrupt pending events.
   1.297 +		 * writing non-zero to intr-mbox-0 additional tells the
   1.298 +		 * NIC to stop sending us irqs, engaging "in-intr-handler"
   1.299 +		 * event coalescing.
   1.300 +		 */
   1.301  		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
   1.302  			     0x00000001);
   1.303 +		/*
   1.304 +		 * Flush PCI write.  This also guarantees that our
   1.305 +		 * status block has been flushed to host memory.
   1.306 +		 */
   1.307  		tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   1.308  		sblk->status &= ~SD_STATUS_UPDATED;
   1.309  
   1.310  		if (likely(tg3_has_work(dev, tp)))
   1.311 -			netif_rx_schedule(dev);
   1.312 +			netif_rx_schedule(dev);		/* schedule NAPI poll */
   1.313  		else {
   1.314 +			/* no work, shared interrupt perhaps?  re-enable
   1.315 +			 * interrupts, and flush that PCI write
   1.316 +			 */
   1.317  			tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
   1.318  			     	0x00000000);
   1.319  			tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   1.320 @@ -2097,33 +2197,34 @@ static void tg3_interrupt(int irq, void 
   1.321  	}
   1.322  #else
   1.323  	{
   1.324 -	  int budget = 1000;
   1.325 -	  tg3_poll( dev, &budget );
   1.326 -
   1.327 -	  tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
   1.328 +		int budget = 1000;
   1.329 +		tg3_poll( dev, &budget );
   1.330 +
   1.331 +		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
   1.332  		       0x00000000);
   1.333 -	  tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   1.334 -
   1.335 -
   1.336 +		tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
   1.337  	}
   1.338  #endif
   1.339 -
   1.340  	spin_unlock_irqrestore(&tp->lock, flags);
   1.341  }
   1.342  
   1.343  static void tg3_init_rings(struct tg3 *);
   1.344  static int tg3_init_hw(struct tg3 *);
   1.345 -
   1.346 -static void tg3_tx_timeout(struct net_device *dev)
   1.347 +static int tg3_halt(struct tg3 *);
   1.348 +
   1.349 +static void tg3_reset_task(void *_data)
   1.350  {
   1.351 -	struct tg3 *tp = dev->priv;
   1.352 -
   1.353 -	printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
   1.354 -	       dev->name);
   1.355 +	struct tg3 *tp = _data;
   1.356 +	unsigned int restart_timer;
   1.357 +
   1.358 +	tg3_netif_stop(tp);
   1.359  
   1.360  	spin_lock_irq(&tp->lock);
   1.361  	spin_lock(&tp->tx_lock);
   1.362  
   1.363 +	restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
   1.364 +	tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
   1.365 +
   1.366  	tg3_halt(tp);
   1.367  	tg3_init_rings(tp);
   1.368  	tg3_init_hw(tp);
   1.369 @@ -2131,7 +2232,30 @@ static void tg3_tx_timeout(struct net_de
   1.370  	spin_unlock(&tp->tx_lock);
   1.371  	spin_unlock_irq(&tp->lock);
   1.372  
   1.373 -	netif_wake_queue(dev);
   1.374 +	tg3_netif_start(tp);
   1.375 +
   1.376 +	if (restart_timer)
   1.377 +		mod_timer(&tp->timer, jiffies + 1);
   1.378 +}
   1.379 +
   1.380 +static void tg3_tx_timeout(struct net_device *dev)
   1.381 +{
   1.382 +        struct tg3 *tp = dev->priv;
   1.383 +
   1.384 +        printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
   1.385 +               dev->name);
   1.386 +
   1.387 +        spin_lock_irq(&tp->lock);
   1.388 +        spin_lock(&tp->tx_lock);
   1.389 +
   1.390 +        tg3_halt(tp);
   1.391 +        tg3_init_rings(tp);
   1.392 +        tg3_init_hw(tp);
   1.393 +
   1.394 +        spin_unlock(&tp->tx_lock);
   1.395 +        spin_unlock_irq(&tp->lock);
   1.396 +
   1.397 +        netif_wake_queue(dev);
   1.398  }
   1.399  
   1.400  #if !PCI_DMA_BUS_IS_PHYS
   1.401 @@ -2206,11 +2330,6 @@ static int tigon3_4gb_hwbug_workaround(s
   1.402  		return -1;
   1.403  	}
   1.404  
   1.405 -	/* NOTE: Broadcom's driver botches this case up really bad.
   1.406 -	 *       This is especially true if any of the frag pages
   1.407 -	 *       are in highmem.  It will instantly oops in that case.
   1.408 -	 */
   1.409 -
   1.410  	/* New SKB is guarenteed to be linear. */
   1.411  	entry = *start;
   1.412  	new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
   1.413 @@ -2642,6 +2761,7 @@ static int tg3_change_mtu(struct net_dev
   1.414  		return 0;
   1.415  	}
   1.416  
   1.417 +	tg3_netif_stop(tp);
   1.418  	spin_lock_irq(&tp->lock);
   1.419  	spin_lock(&tp->tx_lock);
   1.420  
   1.421 @@ -2654,6 +2774,7 @@ static int tg3_change_mtu(struct net_dev
   1.422  
   1.423  	spin_unlock(&tp->tx_lock);
   1.424  	spin_unlock_irq(&tp->lock);
   1.425 +	tg3_netif_start(tp);
   1.426  
   1.427  	return 0;
   1.428  }
   1.429 @@ -3029,6 +3150,7 @@ out:
   1.430  static void tg3_chip_reset(struct tg3 *tp)
   1.431  {
   1.432  	u32 val;
   1.433 +	u32 flags_save;
   1.434  
   1.435  	/* Force NVRAM to settle.
   1.436  	 * This deals with a chip bug which can result in EEPROM
   1.437 @@ -3045,8 +3167,21 @@ static void tg3_chip_reset(struct tg3 *t
   1.438  		}
   1.439  	}
   1.440  
   1.441 +	/*
   1.442 +	 * We must avoid the readl() that normally takes place.
   1.443 +	 * It locks machines, causes machine checks, and other
   1.444 +	 * fun things.  So, temporarily disable the 5701
   1.445 +	 * hardware workaround, while we do the reset.
   1.446 +	 */
   1.447 +	flags_save = tp->tg3_flags;
   1.448 +	tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
   1.449 +
   1.450 +	/* do the reset */
   1.451  	tw32(GRC_MISC_CFG, GRC_MISC_CFG_CORECLK_RESET);
   1.452  
   1.453 +	/* restore 5701 hardware bug workaround flag */
   1.454 +	tp->tg3_flags = flags_save;
   1.455 +
   1.456  	/* Flush PCI posted writes.  The normal MMIO registers
   1.457  	 * are inaccessible at this time so this is the only
   1.458  	 * way to make this reliably.  I tried to use indirect
   1.459 @@ -4120,18 +4255,29 @@ static int tg3_reset_hw(struct tg3 *tp)
   1.460  		udelay(10);
   1.461  	}
   1.462  
   1.463 -        // akw: I have set these all back to default coalescing values.
   1.464 -        
   1.465 -	tw32(HOSTCC_RXCOL_TICKS, DEFAULT_RXCOL_TICKS); //0);
   1.466 -	tw32(HOSTCC_RXMAX_FRAMES, DEFAULT_RXMAX_FRAMES); //1);
   1.467 -	tw32(HOSTCC_RXCOAL_TICK_INT, DEFAULT_RXCOAL_TICK_INT); //, 0);
   1.468 -	tw32(HOSTCC_RXCOAL_MAXF_INT, DEFAULT_RXCOAL_MAXF_INT); //, 1);
   1.469 -	tw32(HOSTCC_TXCOL_TICKS, DEFAULT_TXCOL_TICKS); //, LOW_TXCOL_TICKS);
   1.470 -	tw32(HOSTCC_TXMAX_FRAMES, DEFAULT_TXMAX_FRAMES); //, LOW_RXMAX_FRAMES);
   1.471 -	tw32(HOSTCC_TXCOAL_TICK_INT, DEFAULT_TXCOAL_TICK_INT); //, 0);
   1.472 -	tw32(HOSTCC_TXCOAL_MAXF_INT, DEFAULT_TXCOAL_MAXF_INT); //, 0);
   1.473 +#ifdef NAPI
   1.474 +	tw32(HOSTCC_RXCOL_TICKS, 0);
   1.475 +	tw32(HOSTCC_RXMAX_FRAMES, 1);
   1.476 +	tw32(HOSTCC_RXCOAL_TICK_INT, 0);
   1.477 +	tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
   1.478 +	tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
   1.479 +	tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
   1.480 +	tw32(HOSTCC_TXCOAL_TICK_INT, 0);
   1.481 +	tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
   1.482  	tw32(HOSTCC_STAT_COAL_TICKS,
   1.483  	     DEFAULT_STAT_COAL_TICKS);
   1.484 +#else
   1.485 +	tw32(HOSTCC_RXCOL_TICKS, DEFAULT_RXCOL_TICKS);
   1.486 +	tw32(HOSTCC_RXMAX_FRAMES, DEFAULT_RXMAX_FRAMES);
   1.487 +	tw32(HOSTCC_RXCOAL_TICK_INT, DEFAULT_RXCOAL_TICK_INT);
   1.488 +	tw32(HOSTCC_RXCOAL_MAXF_INT, DEFAULT_RXCOAL_MAXF_INT);
   1.489 +	tw32(HOSTCC_TXCOL_TICKS, DEFAULT_TXCOL_TICKS);
   1.490 +	tw32(HOSTCC_TXMAX_FRAMES, DEFAULT_TXMAX_FRAMES);
   1.491 +	tw32(HOSTCC_TXCOAL_TICK_INT, DEFAULT_TXCOAL_TICK_INT);
   1.492 +	tw32(HOSTCC_TXCOAL_MAXF_INT, DEFAULT_TXCOAL_MAXF_INT);
   1.493 +	tw32(HOSTCC_STAT_COAL_TICKS,
   1.494 +	     DEFAULT_STAT_COAL_TICKS);
   1.495 +#endif
   1.496  
   1.497  	/* Status/statistics block address. */
   1.498  	tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
   1.499 @@ -4258,6 +4404,12 @@ static int tg3_reset_hw(struct tg3 *tp)
   1.500  	if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
   1.501  		tw32(MAC_SERDES_CFG, 0x616000);
   1.502  
   1.503 +	/* Prevent chip from dropping frames when flow control
   1.504 +	 * is enabled.
   1.505 +	 */
   1.506 +	tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
   1.507 +	tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
   1.508 +
   1.509  	err = tg3_setup_phy(tp);
   1.510  	if (err)
   1.511  		return err;
   1.512 @@ -4344,9 +4496,17 @@ static void tg3_timer(unsigned long __op
   1.513  	}
   1.514  
   1.515  	if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
   1.516 -		tg3_halt(tp);
   1.517 -		tg3_init_rings(tp);
   1.518 -		tg3_init_hw(tp);
   1.519 +		tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
   1.520 +		spin_unlock(&tp->tx_lock);
   1.521 +		spin_unlock_irqrestore(&tp->lock, flags);
   1.522 +#if 0
   1.523 +		schedule_task(&tp->reset_task);
   1.524 +#else
   1.525 +                tg3_halt(tp);
   1.526 +                tg3_init_rings(tp);
   1.527 +                tg3_init_hw(tp);
   1.528 +#endif
   1.529 +		return;
   1.530  	}
   1.531  
   1.532  	/* This part only runs once per second. */
   1.533 @@ -4477,8 +4637,6 @@ static int tg3_open(struct net_device *d
   1.534  		return err;
   1.535  	}
   1.536  
   1.537 -	netif_start_queue(dev);
   1.538 -
   1.539  	spin_lock_irq(&tp->lock);
   1.540  	spin_lock(&tp->tx_lock);
   1.541  
   1.542 @@ -4487,6 +4645,8 @@ static int tg3_open(struct net_device *d
   1.543  	spin_unlock(&tp->tx_lock);
   1.544  	spin_unlock_irq(&tp->lock);
   1.545  
   1.546 +	netif_start_queue(dev);
   1.547 +
   1.548  	return 0;
   1.549  }
   1.550  
   1.551 @@ -5252,6 +5412,7 @@ static int tg3_ethtool_ioctl (struct net
   1.552  		    (ering.tx_pending > TG3_TX_RING_SIZE - 1))
   1.553  			return -EINVAL;
   1.554  
   1.555 +		tg3_netif_stop(tp);
   1.556  		spin_lock_irq(&tp->lock);
   1.557  		spin_lock(&tp->tx_lock);
   1.558  
   1.559 @@ -5265,6 +5426,7 @@ static int tg3_ethtool_ioctl (struct net
   1.560  		netif_wake_queue(tp->dev);
   1.561  		spin_unlock(&tp->tx_lock);
   1.562  		spin_unlock_irq(&tp->lock);
   1.563 +		tg3_netif_start(tp);
   1.564  
   1.565  		return 0;
   1.566  	}
   1.567 @@ -5287,6 +5449,7 @@ static int tg3_ethtool_ioctl (struct net
   1.568  		if (copy_from_user(&epause, useraddr, sizeof(epause)))
   1.569  			return -EFAULT;
   1.570  
   1.571 +		tg3_netif_stop(tp);
   1.572  		spin_lock_irq(&tp->lock);
   1.573  		spin_lock(&tp->tx_lock);
   1.574  		if (epause.autoneg)
   1.575 @@ -5306,6 +5469,7 @@ static int tg3_ethtool_ioctl (struct net
   1.576  		tg3_init_hw(tp);
   1.577  		spin_unlock(&tp->tx_lock);
   1.578  		spin_unlock_irq(&tp->lock);
   1.579 +		tg3_netif_start(tp);
   1.580  
   1.581  		return 0;
   1.582  	}
   1.583 @@ -5974,6 +6138,14 @@ static int __devinit tg3_get_invariants(
   1.584  			pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
   1.585  		}
   1.586  	}
   1.587 +
   1.588 +	/* Back to back register writes can cause problems on this chip,
   1.589 +	 * the workaround is to read back all reg writes except those to
   1.590 +	 * mailbox regs.  See tg3_write_indirect_reg32().
   1.591 +	 */
   1.592 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
   1.593 +		tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
   1.594 +
   1.595  	if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
   1.596  		tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
   1.597  	if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
   1.598 @@ -6000,18 +6172,14 @@ static int __devinit tg3_get_invariants(
   1.599  	if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
   1.600  		tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
   1.601  
   1.602 -	/* Regardless of whether checksums work or not, we configure
   1.603 -	 * the StrongARM chips to not compute the pseudo header checksums
   1.604 -	 * in either direction.  Because of the way Linux checksum support
   1.605 -	 * works we do not need the chips to do this, and taking the load
   1.606 -	 * off of the TX/RX onboard StrongARM cpus means that they will not be
   1.607 -	 * the bottleneck.  Whoever wrote Broadcom's driver did not
   1.608 -	 * understand the situation at all.  He could have bothered
   1.609 -	 * to read Jes's Acenic driver because the logic (and this part of
   1.610 -	 * the Tigon2 hardware/firmware) is pretty much identical.
   1.611 +	/* Pseudo-header checksum is done by hardware logic and not
   1.612 +	 * the offload processers, so make the chip do the pseudo-
   1.613 +	 * header checksums on receive.  For transmit it is more
   1.614 +	 * convenient to do the pseudo-header checksum in software
   1.615 +	 * as Linux does that on transmit for us in all cases.
   1.616  	 */
   1.617  	tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
   1.618 -	tp->tg3_flags |= TG3_FLAG_NO_RX_PSEUDO_CSUM;
   1.619 +	tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
   1.620  
   1.621  	/* Derive initial jumbo mode from MTU assigned in
   1.622  	 * ether_setup() via the alloc_etherdev() call
   1.623 @@ -6089,24 +6257,8 @@ static int __devinit tg3_get_invariants(
   1.624  	if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
   1.625  		tp->tg3_flags |= TG3_FLAG_HOST_TXDS;
   1.626  
   1.627 -	/* Quick sanity check.  Make sure we see an expected
   1.628 -	 * value here.
   1.629 -	 */
   1.630  	grc_misc_cfg = tr32(GRC_MISC_CFG);
   1.631  	grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
   1.632 -	if (grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5700 &&
   1.633 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5701 &&
   1.634 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5702FE &&
   1.635 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5703 &&
   1.636 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5703S &&
   1.637 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5704 &&
   1.638 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5704_A2 &&
   1.639 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_5704_X &&
   1.640 -	    grc_misc_cfg != GRC_MISC_CFG_BOARD_ID_AC91002A1) {
   1.641 -		printk(KERN_ERR PFX "(%s) unknown board id 0x%08X\n",
   1.642 -		       tp->pdev->slot_name, grc_misc_cfg);
   1.643 -		return -ENODEV;
   1.644 -	}
   1.645  
   1.646  	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
   1.647  	    grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
   1.648 @@ -6114,10 +6266,7 @@ static int __devinit tg3_get_invariants(
   1.649  		tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
   1.650  	}
   1.651  
   1.652 -	/* ROFL, you should see Broadcom's driver code implementing
   1.653 -	 * this, stuff like "if (a || b)" where a and b are always
   1.654 -	 * mutually exclusive.  DaveM finds like 6 bugs today, hello!
   1.655 -	 */
   1.656 +	/* this one is limited to 10/100 only */
   1.657  	if (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5702FE)
   1.658  		tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
   1.659  
   1.660 @@ -6180,24 +6329,18 @@ static int __devinit tg3_get_invariants(
   1.661  	/* 5700 chips can get confused if TX buffers straddle the
   1.662  	 * 4GB address boundary in some cases.
   1.663  	 */
   1.664 -	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
   1.665 -		/* ROFL!  Latest Broadcom driver disables NETIF_F_HIGHDMA
   1.666 -		 * in this case instead of fixing their workaround code.
   1.667 -		 *
   1.668 -		 * Like, hey, there is this skb_copy() thing guys,
   1.669 -		 * use it.  Oh I can't stop laughing...
   1.670 -		 */
   1.671 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
   1.672  		tp->dev->hard_start_xmit = tg3_start_xmit_4gbug;
   1.673 -	} else {
   1.674 +	else
   1.675  		tp->dev->hard_start_xmit = tg3_start_xmit;
   1.676 -	}
   1.677  
   1.678  	tp->rx_offset = 2;
   1.679 -
   1.680 +/* XXX Xen: we trust our ASICs, for better or worse ;-) */
   1.681 +#if 0
   1.682  	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
   1.683  	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
   1.684 -                printk("WARNING: This card may not support unaligned receive pointers.\n");
   1.685 -		//tp->rx_offset = 0;
   1.686 +		tp->rx_offset = 0;
   1.687 +#endif
   1.688  
   1.689  	/* By default, disable wake-on-lan.  User can change this
   1.690  	 * using ETHTOOL_SWOL.
   1.691 @@ -6358,6 +6501,7 @@ static int __devinit tg3_test_dma(struct
   1.692  			(0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
   1.693  			(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
   1.694  			(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
   1.695 +		/* XXX 5705 note: set MIN_DMA to zero here */
   1.696  	} else {
   1.697  		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
   1.698  			tp->dma_rwctrl =
   1.699 @@ -6375,12 +6519,19 @@ static int __devinit tg3_test_dma(struct
   1.700  				(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
   1.701  
   1.702  		/* Wheee, some more chip bugs... */
   1.703 -		if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1 ||
   1.704 -		    tp->pci_chip_rev_id == CHIPREV_ID_5703_A2 ||
   1.705 -		    tp->pci_chip_rev_id == CHIPREV_ID_5703_A3 ||
   1.706 -		    tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
   1.707 -			tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
   1.708 -	}
   1.709 +		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
   1.710 +		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
   1.711 +			u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
   1.712 +
   1.713 +			if (ccval == 0x6 || ccval == 0x7)
   1.714 +				tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
   1.715 +		}
   1.716 +	}
   1.717 +
   1.718 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
   1.719 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
   1.720 +		tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA
   1.721 +				    << DMA_RWCTRL_MIN_DMA_SHIFT);
   1.722  
   1.723  	/* We don't do this on x86 because it seems to hurt performace.
   1.724  	 * It does help things on other platforms though.
   1.725 @@ -6445,8 +6596,11 @@ static int __devinit tg3_test_dma(struct
   1.726  	}
   1.727  #endif
   1.728  
   1.729 -	/* Remove this if it causes problems for some boards. */
   1.730 -	tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
   1.731 +	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
   1.732 +	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
   1.733 +		/* Remove this if it causes problems for some boards. */
   1.734 +		tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
   1.735 +	}
   1.736  
   1.737  	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
   1.738  
   1.739 @@ -6676,6 +6830,7 @@ static int __devinit tg3_init_one(struct
   1.740  	spin_lock_init(&tp->lock);
   1.741  	spin_lock_init(&tp->tx_lock);
   1.742  	spin_lock_init(&tp->indirect_lock);
   1.743 +	PREPARE_TQUEUE(&tp->reset_task, tg3_reset_task, tp);
   1.744  
   1.745  	tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
   1.746  	if (tp->regs == 0UL) {
   1.747 @@ -6808,6 +6963,8 @@ static int tg3_suspend(struct pci_dev *p
   1.748  	if (!netif_running(dev))
   1.749  		return 0;
   1.750  
   1.751 +	tg3_netif_stop(tp);
   1.752 +
   1.753  	spin_lock_irq(&tp->lock);
   1.754  	spin_lock(&tp->tx_lock);
   1.755  	tg3_disable_ints(tp);
   1.756 @@ -6834,6 +6991,7 @@ static int tg3_suspend(struct pci_dev *p
   1.757  		spin_unlock_irq(&tp->lock);
   1.758  
   1.759  		netif_device_attach(dev);
   1.760 +		tg3_netif_start(tp);
   1.761  	}
   1.762  
   1.763  	return err;
   1.764 @@ -6864,6 +7022,8 @@ static int tg3_resume(struct pci_dev *pd
   1.765  	spin_unlock(&tp->tx_lock);
   1.766  	spin_unlock_irq(&tp->lock);
   1.767  
   1.768 +	tg3_netif_start(tp);
   1.769 +
   1.770  	return 0;
   1.771  }
   1.772  
     2.1 --- a/xen/drivers/net/tg3.h	Sun Mar 16 19:38:44 2003 +0000
     2.2 +++ b/xen/drivers/net/tg3.h	Mon Mar 17 18:25:34 2003 +0000
     2.3 @@ -21,7 +21,8 @@
     2.4  #define TG3_BDINFO_NIC_ADDR		0xcUL /* 32-bit */
     2.5  #define TG3_BDINFO_SIZE			0x10UL
     2.6  
     2.7 -#define RX_COPY_THRESHOLD  		0 //256
     2.8 +/* XXX Xen: No copy break. */
     2.9 +#define RX_COPY_THRESHOLD  		0 /*256*/
    2.10  
    2.11  #define RX_STD_MAX_SIZE			1536
    2.12  #define RX_JUMBO_MAX_SIZE		0xdeadbeef /* XXX */
    2.13 @@ -456,6 +457,7 @@
    2.14  #define  RCV_RULE_DISABLE_MASK		 0x7fffffff
    2.15  #define MAC_RCV_RULE_CFG		0x00000500
    2.16  #define  RCV_RULE_CFG_DEFAULT_CLASS	0x00000008
    2.17 +#define MAC_LOW_WMARK_MAX_RX_FRAME	0x00000504
    2.18  /* 0x504 --> 0x590 unused */
    2.19  #define MAC_SERDES_CFG			0x00000590
    2.20  #define MAC_SERDES_STAT			0x00000594
    2.21 @@ -1139,7 +1141,6 @@
    2.22  #define  GRC_MISC_CFG_BOARD_ID_5704	0x00000000
    2.23  #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
    2.24  #define  GRC_MISC_CFG_BOARD_ID_5704_A2	0x00008000
    2.25 -#define  GRC_MISC_CFG_BOARD_ID_5704_X	0x0000C000
    2.26  #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
    2.27  #define GRC_LOCAL_CTRL			0x00006808
    2.28  #define  GRC_LCLCTRL_INT_ACTIVE		0x00000001
    2.29 @@ -1795,6 +1796,7 @@ struct tg3 {
    2.30  #define TG3_FLAG_USE_LINKCHG_REG	0x00000008
    2.31  #define TG3_FLAG_USE_MI_INTERRUPT	0x00000010
    2.32  #define TG3_FLAG_ENABLE_ASF		0x00000020
    2.33 +#define TG3_FLAG_5701_REG_WRITE_BUG	0x00000040
    2.34  #define TG3_FLAG_POLL_SERDES		0x00000080
    2.35  #define TG3_FLAG_MBOX_WRITE_REORDER	0x00000100
    2.36  #define TG3_FLAG_PCIX_TARGET_HWBUG	0x00000200
    2.37 @@ -1820,6 +1822,8 @@ struct tg3 {
    2.38  #define TG3_FLAG_GOT_SERDES_FLOWCTL	0x20000000
    2.39  #define TG3_FLAG_SPLIT_MODE		0x40000000
    2.40  #define TG3_FLAG_INIT_COMPLETE		0x80000000
    2.41 +	u32				tg3_flags2;
    2.42 +#define TG3_FLG2_RESTART_TIMER		0x00000001
    2.43  
    2.44  	u32				split_mode_max_reqs;
    2.45  #define SPLIT_MODE_5704_MAX_REQ		3
    2.46 @@ -1888,6 +1892,7 @@ struct tg3 {
    2.47  
    2.48  	struct tg3_hw_stats		*hw_stats;
    2.49  	dma_addr_t			stats_mapping;
    2.50 +	struct tq_struct		reset_task;
    2.51  };
    2.52  
    2.53  #endif /* !(_T3_H) */
     3.1 --- a/xen/drivers/pci/pci.ids	Sun Mar 16 19:38:44 2003 +0000
     3.2 +++ b/xen/drivers/pci/pci.ids	Mon Mar 17 18:25:34 2003 +0000
     3.3 @@ -3062,15 +3062,25 @@ 1148  Syskonnect (Schneider & Koch)
     3.4  		1148 5843  FDDI SK-5843 (SK-NET FDDI-LP64)
     3.5  		1148 5844  FDDI SK-5844 (SK-NET FDDI-LP64 DAS)
     3.6  	4200  Token Ring adapter
     3.7 -	4300  Gigabit Ethernet
     3.8 -		1148 9821  SK-9821 (1000Base-T single link)
     3.9 -		1148 9822  SK-9822 (1000Base-T dual link)
    3.10 -		1148 9841  SK-9841 (1000Base-LX single link)
    3.11 -		1148 9842  SK-9842 (1000Base-LX dual link)
    3.12 -		1148 9843  SK-9843 (1000Base-SX single link)
    3.13 -		1148 9844  SK-9844 (1000Base-SX dual link)
    3.14 -		1148 9861  SK-9861 (1000Base-SX VF45 single link)
    3.15 -		1148 9862  SK-9862 (1000Base-SX VF45 dual link)
    3.16 +	4300  SK-98xx Gigabit Ethernet Server Adapter
    3.17 +		1148 9821  SK-9821 Gigabit Ethernet 1000Base-T Server Adapter
    3.18 +		1148 9822  SK-9822 Gigabit Ethernet 1000Base-T Dual Port Server Adapter
    3.19 +		1148 9841  SK-9841 Gigabit Ethernet 1000Base-LX Server Adapter
    3.20 +		1148 9842  SK-9842 Gigabit Ethernet 1000Base-LX Dual Port Server Adapter
    3.21 +		1148 9843  SK-9843 Gigabit Ethernet 1000Base-SX Server Adapter
    3.22 +		1148 9844  SK-9844 Gigabit Ethernet 1000Base-SX Dual Port Server Adapter
    3.23 +		1148 9861  SK-9861 Gigabit Ethernet 1000Base-SX Server Adapter
    3.24 +		1148 9862  SK-9862 Gigabit Ethernet 1000Base-SX Dual Port Server Adapter
    3.25 +		1148 9871  SK-9871 Gigabit Ethernet 1000Base-ZX Server Adapter
    3.26 +		1148 9872  SK-9872 Gigabit Ethernet 1000Base-ZX Dual Port Server Adapter
    3.27 +	4320  SK-98xx Gigabit Ethernet Server Adapter
    3.28 +		1148 9521  SK-9521 10/100/1000Base-T Adapter
    3.29 +		1148 5021  SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter
    3.30 +		1148 5041  SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter
    3.31 +		1148 5043  SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter
    3.32 +		1148 5051  SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter
    3.33 +		1148 5061  SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter
    3.34 +		1148 5071  SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter
    3.35  	4400  Gigabit Ethernet
    3.36  1149  Win System Corporation
    3.37  114a  VMIC
    3.38 @@ -5078,6 +5088,9 @@ 14e4  Broadcom Corporation
    3.39  	164d  NetXtreme BCM5702FE Gigabit Ethernet
    3.40  	16a6  NetXtreme BCM5702X Gigabit Ethernet
    3.41  	16a7  NetXtreme BCM5703X Gigabit Ethernet
    3.42 +	16a8  NetXtreme BCM5704S Gigabit Ethernet
    3.43 +	16c6  NetXtreme BCM5702A3 Gigabit Ethernet
    3.44 +	16c7  NetXtreme BCM5703A3 Gigabit Ethernet
    3.45  	4212  BCM v.90 56k modem
    3.46  	5820  BCM5820 Crypto Accelerator
    3.47  	5821  BCM5821 Crypto Accelerator
     4.1 --- a/xen/include/xeno/pci_ids.h	Sun Mar 16 19:38:44 2003 +0000
     4.2 +++ b/xen/include/xeno/pci_ids.h	Mon Mar 17 18:25:34 2003 +0000
     4.3 @@ -412,6 +412,7 @@
     4.4  #define PCI_DEVICE_ID_AMD_8111_LAN	0x7462
     4.5  #define PCI_DEVICE_ID_AMD_8111_IDE     0x7469
     4.6  #define PCI_DEVICE_ID_AMD_8111_AC97    0x746d
     4.7 +#define PCI_DEVICE_ID_AMD_8131_APIC     0x7450
     4.8  
     4.9  #define PCI_VENDOR_ID_TRIDENT		0x1023
    4.10  #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
    4.11 @@ -830,6 +831,14 @@
    4.12  #define PCI_DEVICE_ID_3COM_3C905TX	0x9050
    4.13  #define PCI_DEVICE_ID_3COM_3C905T4	0x9051
    4.14  #define PCI_DEVICE_ID_3COM_3C905B_TX	0x9055
    4.15 +#define PCI_DEVICE_ID_3COM_3CR990	0x9900
    4.16 +#define PCI_DEVICE_ID_3COM_3CR990_TX_95	0x9902
    4.17 +#define PCI_DEVICE_ID_3COM_3CR990_TX_97	0x9903
    4.18 +#define PCI_DEVICE_ID_3COM_3CR990B	0x9904
    4.19 +#define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
    4.20 +#define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
    4.21 +#define PCI_DEVICE_ID_3COM_3CR990SVR97	0x9909
    4.22 +#define PCI_DEVICE_ID_3COM_3CR990SVR	0x990a
    4.23  
    4.24  #define PCI_VENDOR_ID_SMC		0x10b8
    4.25  #define PCI_DEVICE_ID_SMC_EPIC100	0x0005
    4.26 @@ -1118,6 +1127,7 @@
    4.27  #define PCI_DEVICE_ID_SYSKONNECT_FP	0x4000
    4.28  #define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
    4.29  #define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
    4.30 +#define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
    4.31  
    4.32  #define PCI_VENDOR_ID_VMIC		0x114a
    4.33  #define PCI_DEVICE_ID_VMIC_VME		0x7587
    4.34 @@ -1580,6 +1590,9 @@
    4.35  #define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
    4.36  #define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
    4.37  #define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
    4.38 +#define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
    4.39 +#define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
    4.40 +#define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
    4.41  
    4.42  #define PCI_VENDOR_ID_SYBA		0x1592
    4.43  #define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
    4.44 @@ -1771,6 +1784,7 @@
    4.45  #define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
    4.46  #define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
    4.47  #define PCI_DEVICE_ID_INTEL_82451NX	0x84ca
    4.48 +#define PCI_DEVICE_ID_INTEL_82454NX	0x84cb
    4.49  
    4.50  #define PCI_VENDOR_ID_COMPUTONE		0x8e0e
    4.51  #define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291