ia64/xen-unstable

changeset 11894:47718a3d011e

[HVM] XenTrace enhancement for HVM SMP guests.

Signed-off-by: Yunfeng Zhao <yunfeng.zhao@intel.com>
Signed-off-by: Xin Li <xin.b.li@intel.com>
author kfraser@localhost.localdomain
date Wed Oct 18 19:20:36 2006 +0100 (2006-10-18)
parents b2e71d574045
children 20522afb2615
files tools/xentrace/formats xen/arch/x86/hvm/svm/intr.c xen/arch/x86/hvm/svm/svm.c xen/arch/x86/hvm/vmx/io.c xen/arch/x86/hvm/vmx/vmx.c xen/include/public/trace.h
line diff
     1.1 --- a/tools/xentrace/formats	Wed Oct 18 19:14:34 2006 +0100
     1.2 +++ b/tools/xentrace/formats	Wed Oct 18 19:20:36 2006 +0100
     1.3 @@ -12,10 +12,29 @@ 0x0002f00B	CPU%(cpu)d	%(tsc)d		s_timer_f
     1.4  0x0002f00c	CPU%(cpu)d	%(tsc)d		t_timer_fn
     1.5  0x0002f00d	CPU%(cpu)d	%(tsc)d		dom_timer_fn
     1.6  
     1.7 -0x00080001	CPU%(cpu)d      %(tsc)d		VMX_VMEXIT		[ domid = 0x%(1)08x, eip = 0x%(2)08x, reason = 0x%(3)08x ]
     1.8 -0x00080002	CPU%(cpu)d      %(tsc)d		VMX_VECTOR		[ domid = 0x%(1)08x, eip = 0x%(2)08x, vector = 0x%(3)08x ]
     1.9 -0x00080003	CPU%(cpu)d      %(tsc)d		VMX_INT			[ domid = 0x%(1)08x, trap = 0x%(2)08x, va = 0x%(3)08x ]
    1.10 +0x00080001	CPU%(cpu)d	%(tsc)d		VMX_VMEXIT		[ domid = 0x%(1)08x, eip = 0x%(2)08x, reason = 0x%(3)08x ]
    1.11 +0x00084001	CPU%(cpu)d	%(tsc)d		VMX_INTR		[ domid = 0x%(1)08x, trap = 0x%(2)08x, va = 0x%(3)08x ]
    1.12 +
    1.13 +0x00081001	CPU%(cpu)d	%(tsc)d		VMEXIT_0		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.14 +0x00082001	CPU%(cpu)d	%(tsc)d		VMENTRY_0		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.15 +
    1.16 +0x00081002	CPU%(cpu)d	%(tsc)d		VMEXIT_1		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.17 +0x00082002	CPU%(cpu)d	%(tsc)d		VMENTRY_1		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.18 +
    1.19 +0x00081003	CPU%(cpu)d	%(tsc)d		VMEXIT_2		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.20 +0x00082003	CPU%(cpu)d	%(tsc)d		VMENTRY_2		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.21  
    1.22 -0x00081001      CPU%(cpu)d      %(tsc)d         VMEXIT                  0x%(1)08x 0x%(2)08x 0x%(3)08x 
    1.23 -0x00081002      CPU%(cpu)d      %(tsc)d         VMENTRY                 0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.24 +0x00081004	CPU%(cpu)d	%(tsc)d		VMEXIT_3		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.25 +0x00082004	CPU%(cpu)d	%(tsc)d		VMENTRY_3		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.26 +
    1.27 +0x00081005	CPU%(cpu)d	%(tsc)d		VMEXIT_4		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.28 +0x00082005	CPU%(cpu)d	%(tsc)d		VMENTRY_4		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.29  
    1.30 +0x00081006	CPU%(cpu)d	%(tsc)d		VMEXIT_5		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.31 +0x00082006	CPU%(cpu)d	%(tsc)d		VMENTRY_5		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.32 +
    1.33 +0x00081007	CPU%(cpu)d	%(tsc)d		VMEXIT_6		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.34 +0x00082007	CPU%(cpu)d	%(tsc)d		VMENTRY_6		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.35 +
    1.36 +0x00081008	CPU%(cpu)d	%(tsc)d		VMEXIT_7		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.37 +0x00082008	CPU%(cpu)d	%(tsc)d		VMENTRY_7		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
     2.1 --- a/xen/arch/x86/hvm/svm/intr.c	Wed Oct 18 19:14:34 2006 +0100
     2.2 +++ b/xen/arch/x86/hvm/svm/intr.c	Wed Oct 18 19:20:36 2006 +0100
     2.3 @@ -145,7 +145,7 @@ asmlinkage void svm_intr_assist(void)
     2.4                      ++pt->pending_intr_nr;
     2.5              }
     2.6              /* let's inject this interrupt */
     2.7 -            TRACE_3D(TRC_VMX_INT, v->domain->domain_id, intr_vector, 0);
     2.8 +            TRACE_3D(TRC_VMX_INTR, v->domain->domain_id, intr_vector, 0);
     2.9              svm_inject_extint(v, intr_vector, VMX_DELIVER_NO_ERROR_CODE);
    2.10              hvm_interrupt_post(v, intr_vector, intr_type);
    2.11              break;
     3.1 --- a/xen/arch/x86/hvm/svm/svm.c	Wed Oct 18 19:14:34 2006 +0100
     3.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Wed Oct 18 19:20:36 2006 +0100
     3.3 @@ -2797,7 +2797,7 @@ asmlinkage void svm_vmexit_handler(struc
     3.4  
     3.5              v->arch.hvm_svm.cpu_cr2 = va;
     3.6              vmcb->cr2 = va;
     3.7 -            TRACE_3D(TRC_VMX_INT, v->domain->domain_id, 
     3.8 +            TRACE_3D(TRC_VMX_INTR, v->domain->domain_id,
     3.9                       VMEXIT_EXCEPTION_PF, va);
    3.10          }
    3.11          break;
     4.1 --- a/xen/arch/x86/hvm/vmx/io.c	Wed Oct 18 19:14:34 2006 +0100
     4.2 +++ b/xen/arch/x86/hvm/vmx/io.c	Wed Oct 18 19:20:36 2006 +0100
     4.3 @@ -153,7 +153,7 @@ asmlinkage void vmx_intr_assist(void)
     4.4      case APIC_DM_FIXED:
     4.5      case APIC_DM_LOWEST:
     4.6          vmx_inject_extint(v, highest_vector, VMX_DELIVER_NO_ERROR_CODE);
     4.7 -        TRACE_3D(TRC_VMX_INT, v->domain->domain_id, highest_vector, 0);
     4.8 +        TRACE_3D(TRC_VMX_INTR, v->domain->domain_id, highest_vector, 0);
     4.9          break;
    4.10  
    4.11      case APIC_DM_SMI:
     5.1 --- a/xen/arch/x86/hvm/vmx/vmx.c	Wed Oct 18 19:14:34 2006 +0100
     5.2 +++ b/xen/arch/x86/hvm/vmx/vmx.c	Wed Oct 18 19:20:36 2006 +0100
     5.3 @@ -871,7 +871,7 @@ static int vmx_do_page_fault(unsigned lo
     5.4  
     5.5      result = shadow_fault(va, regs);
     5.6  
     5.7 -    TRACE_VMEXIT (2,result);
     5.8 +    TRACE_VMEXIT(2, result);
     5.9  #if 0
    5.10      if ( !result )
    5.11      {
    5.12 @@ -902,7 +902,7 @@ static void vmx_do_no_device_fault(void)
    5.13  }
    5.14  
    5.15  #define bitmaskof(idx) (1U << ((idx)&31))
    5.16 -static void vmx_vmexit_do_cpuid(struct cpu_user_regs *regs)
    5.17 +static void vmx_do_cpuid(struct cpu_user_regs *regs)
    5.18  {
    5.19      unsigned int input = (unsigned int)regs->eax;
    5.20      unsigned int count = (unsigned int)regs->ecx;
    5.21 @@ -1027,14 +1027,14 @@ static void vmx_dr_access(unsigned long 
    5.22   * Invalidate the TLB for va. Invalidate the shadow page corresponding
    5.23   * the address va.
    5.24   */
    5.25 -static void vmx_vmexit_do_invlpg(unsigned long va)
    5.26 +static void vmx_do_invlpg(unsigned long va)
    5.27  {
    5.28      unsigned long eip;
    5.29      struct vcpu *v = current;
    5.30  
    5.31      __vmread(GUEST_RIP, &eip);
    5.32  
    5.33 -    HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
    5.34 +    HVM_DBG_LOG(DBG_LEVEL_VMMU, "eip=%lx, va=%lx",
    5.35                  eip, va);
    5.36  
    5.37      /*
    5.38 @@ -1647,6 +1647,10 @@ static int mov_to_cr(int gp, int cr, str
    5.39          __hvm_bug(regs);
    5.40      }
    5.41  
    5.42 +    TRACE_VMEXIT(1, TYPE_MOV_TO_CR);
    5.43 +    TRACE_VMEXIT(2, cr);
    5.44 +    TRACE_VMEXIT(3, value);
    5.45 +
    5.46      HVM_DBG_LOG(DBG_LEVEL_1, "CR%d, value = %lx", cr, value);
    5.47  
    5.48      switch ( cr ) {
    5.49 @@ -1828,6 +1832,10 @@ static void mov_from_cr(int cr, int gp, 
    5.50          __hvm_bug(regs);
    5.51      }
    5.52  
    5.53 +    TRACE_VMEXIT(1, TYPE_MOV_FROM_CR);
    5.54 +    TRACE_VMEXIT(2, cr);
    5.55 +    TRACE_VMEXIT(3, value);
    5.56 +
    5.57      HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR%d, value = %lx", cr, value);
    5.58  }
    5.59  
    5.60 @@ -1842,20 +1850,14 @@ static int vmx_cr_access(unsigned long e
    5.61      case TYPE_MOV_TO_CR:
    5.62          gp = exit_qualification & CONTROL_REG_ACCESS_REG;
    5.63          cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
    5.64 -        TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
    5.65 -        TRACE_VMEXIT(2,cr);
    5.66 -        TRACE_VMEXIT(3,gp);
    5.67          return mov_to_cr(gp, cr, regs);
    5.68      case TYPE_MOV_FROM_CR:
    5.69          gp = exit_qualification & CONTROL_REG_ACCESS_REG;
    5.70          cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
    5.71 -        TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
    5.72 -        TRACE_VMEXIT(2,cr);
    5.73 -        TRACE_VMEXIT(3,gp);
    5.74          mov_from_cr(cr, gp, regs);
    5.75          break;
    5.76      case TYPE_CLTS:
    5.77 -        TRACE_VMEXIT(1,TYPE_CLTS);
    5.78 +        TRACE_VMEXIT(1, TYPE_CLTS);
    5.79  
    5.80          /* We initialise the FPU now, to avoid needing another vmexit. */
    5.81          setup_fpu(v);
    5.82 @@ -1870,10 +1872,11 @@ static int vmx_cr_access(unsigned long e
    5.83          __vmwrite(CR0_READ_SHADOW, value);
    5.84          break;
    5.85      case TYPE_LMSW:
    5.86 -        TRACE_VMEXIT(1,TYPE_LMSW);
    5.87          __vmread_vcpu(v, CR0_READ_SHADOW, &value);
    5.88          value = (value & ~0xF) |
    5.89              (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
    5.90 +        TRACE_VMEXIT(1, TYPE_LMSW);
    5.91 +        TRACE_VMEXIT(2, value);
    5.92          return vmx_set_cr0(value);
    5.93          break;
    5.94      default:
    5.95 @@ -1889,7 +1892,7 @@ static inline void vmx_do_msr_read(struc
    5.96      u32 eax, edx;
    5.97      struct vcpu *v = current;
    5.98  
    5.99 -    HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
   5.100 +    HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%lx, eax=%lx, edx=%lx",
   5.101                  (unsigned long)regs->ecx, (unsigned long)regs->eax,
   5.102                  (unsigned long)regs->edx);
   5.103      switch (regs->ecx) {
   5.104 @@ -1926,8 +1929,7 @@ static inline void vmx_do_msr_read(struc
   5.105      regs->eax = msr_content & 0xFFFFFFFF;
   5.106      regs->edx = msr_content >> 32;
   5.107  
   5.108 -    HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
   5.109 -                "ecx=%lx, eax=%lx, edx=%lx",
   5.110 +    HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%lx, eax=%lx, edx=%lx",
   5.111                  (unsigned long)regs->ecx, (unsigned long)regs->eax,
   5.112                  (unsigned long)regs->edx);
   5.113  }
   5.114 @@ -1937,7 +1939,7 @@ static inline void vmx_do_msr_write(stru
   5.115      u64 msr_content;
   5.116      struct vcpu *v = current;
   5.117  
   5.118 -    HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
   5.119 +    HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%lx, eax=%lx, edx=%lx",
   5.120                  (unsigned long)regs->ecx, (unsigned long)regs->eax,
   5.121                  (unsigned long)regs->edx);
   5.122  
   5.123 @@ -1965,20 +1967,19 @@ static inline void vmx_do_msr_write(stru
   5.124          break;
   5.125      }
   5.126  
   5.127 -    HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
   5.128 -                "ecx=%lx, eax=%lx, edx=%lx",
   5.129 +    HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%lx, eax=%lx, edx=%lx",
   5.130                  (unsigned long)regs->ecx, (unsigned long)regs->eax,
   5.131                  (unsigned long)regs->edx);
   5.132  }
   5.133  
   5.134 -void vmx_vmexit_do_hlt(void)
   5.135 +static void vmx_do_hlt(void)
   5.136  {
   5.137      unsigned long rflags;
   5.138      __vmread(GUEST_RFLAGS, &rflags);
   5.139      hvm_hlt(rflags);
   5.140  }
   5.141  
   5.142 -static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
   5.143 +static inline void vmx_do_extint(struct cpu_user_regs *regs)
   5.144  {
   5.145      unsigned int vector;
   5.146      int error;
   5.147 @@ -1999,7 +2000,7 @@ static inline void vmx_vmexit_do_extint(
   5.148          __hvm_bug(regs);
   5.149  
   5.150      vector &= INTR_INFO_VECTOR_MASK;
   5.151 -    TRACE_VMEXIT(1,vector);
   5.152 +    TRACE_VMEXIT(1, vector);
   5.153  
   5.154      switch(vector) {
   5.155      case LOCAL_TIMER_VECTOR:
   5.156 @@ -2130,7 +2131,7 @@ static void vmx_reflect_exception(struct
   5.157  asmlinkage void vmx_vmexit_handler(struct cpu_user_regs *regs)
   5.158  {
   5.159      unsigned int exit_reason;
   5.160 -    unsigned long exit_qualification, rip, inst_len = 0;
   5.161 +    unsigned long exit_qualification, inst_len = 0;
   5.162      struct vcpu *v = current;
   5.163  
   5.164      __vmread(VM_EXIT_REASON, &exit_reason);
   5.165 @@ -2172,7 +2173,7 @@ asmlinkage void vmx_vmexit_handler(struc
   5.166          domain_crash_synchronous();
   5.167      }
   5.168  
   5.169 -    TRACE_VMEXIT(0,exit_reason);
   5.170 +    TRACE_VMEXIT(0, exit_reason);
   5.171  
   5.172      switch ( exit_reason )
   5.173      {
   5.174 @@ -2184,14 +2185,13 @@ asmlinkage void vmx_vmexit_handler(struc
   5.175           * (2) NMI
   5.176           */
   5.177          unsigned int vector;
   5.178 -        unsigned long va;
   5.179  
   5.180          if ( __vmread(VM_EXIT_INTR_INFO, &vector) ||
   5.181               !(vector & INTR_INFO_VALID_MASK) )
   5.182              domain_crash_synchronous();
   5.183          vector &= INTR_INFO_VECTOR_MASK;
   5.184  
   5.185 -        TRACE_VMEXIT(1,vector);
   5.186 +        TRACE_VMEXIT(1, vector);
   5.187          perfc_incra(cause_vector, vector);
   5.188  
   5.189          switch ( vector ) {
   5.190 @@ -2247,11 +2247,11 @@ asmlinkage void vmx_vmexit_handler(struc
   5.191          }
   5.192          case TRAP_page_fault:
   5.193          {
   5.194 -            __vmread(EXIT_QUALIFICATION, &va);
   5.195 +            __vmread(EXIT_QUALIFICATION, &exit_qualification);
   5.196              __vmread(VM_EXIT_INTR_ERROR_CODE, &regs->error_code);
   5.197  
   5.198              TRACE_VMEXIT(3, regs->error_code);
   5.199 -            TRACE_VMEXIT(4, va);
   5.200 +            TRACE_VMEXIT(4, exit_qualification);
   5.201  
   5.202              HVM_DBG_LOG(DBG_LEVEL_VMMU,
   5.203                          "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
   5.204 @@ -2259,13 +2259,13 @@ asmlinkage void vmx_vmexit_handler(struc
   5.205                          (unsigned long)regs->ecx, (unsigned long)regs->edx,
   5.206                          (unsigned long)regs->esi, (unsigned long)regs->edi);
   5.207  
   5.208 -            if ( !vmx_do_page_fault(va, regs) )
   5.209 +            if ( !vmx_do_page_fault(exit_qualification, regs) )
   5.210              {
   5.211                  /* Inject #PG using Interruption-Information Fields. */
   5.212                  vmx_inject_hw_exception(v, TRAP_page_fault, regs->error_code);
   5.213 -                v->arch.hvm_vmx.cpu_cr2 = va;
   5.214 -                TRACE_3D(TRC_VMX_INT, v->domain->domain_id,
   5.215 -                         TRAP_page_fault, va);
   5.216 +                v->arch.hvm_vmx.cpu_cr2 = exit_qualification;
   5.217 +                TRACE_3D(TRC_VMX_INTR, v->domain->domain_id,
   5.218 +                         TRAP_page_fault, exit_qualification);
   5.219              }
   5.220              break;
   5.221          }
   5.222 @@ -2279,7 +2279,7 @@ asmlinkage void vmx_vmexit_handler(struc
   5.223          break;
   5.224      }
   5.225      case EXIT_REASON_EXTERNAL_INTERRUPT:
   5.226 -        vmx_vmexit_do_extint(regs);
   5.227 +        vmx_do_extint(regs);
   5.228          break;
   5.229      case EXIT_REASON_TRIPLE_FAULT:
   5.230          domain_crash_synchronous();
   5.231 @@ -2296,39 +2296,35 @@ asmlinkage void vmx_vmexit_handler(struc
   5.232      case EXIT_REASON_CPUID:
   5.233          inst_len = __get_instruction_length(); /* Safe: CPUID */
   5.234          __update_guest_eip(inst_len);
   5.235 -        vmx_vmexit_do_cpuid(regs);
   5.236 +        vmx_do_cpuid(regs);
   5.237          break;
   5.238      case EXIT_REASON_HLT:
   5.239          inst_len = __get_instruction_length(); /* Safe: HLT */
   5.240          __update_guest_eip(inst_len);
   5.241 -        vmx_vmexit_do_hlt();
   5.242 +        vmx_do_hlt();
   5.243          break;
   5.244      case EXIT_REASON_INVLPG:
   5.245      {
   5.246 -        unsigned long va;
   5.247          inst_len = __get_instruction_length(); /* Safe: INVLPG */
   5.248          __update_guest_eip(inst_len);
   5.249 -        __vmread(EXIT_QUALIFICATION, &va);
   5.250 -        vmx_vmexit_do_invlpg(va);
   5.251 +        __vmread(EXIT_QUALIFICATION, &exit_qualification);
   5.252 +        vmx_do_invlpg(exit_qualification);
   5.253 +        TRACE_VMEXIT(4, exit_qualification);
   5.254          break;
   5.255      }
   5.256      case EXIT_REASON_VMCALL:
   5.257      {
   5.258          inst_len = __get_instruction_length(); /* Safe: VMCALL */
   5.259          __update_guest_eip(inst_len);
   5.260 -        __vmread(GUEST_RIP, &rip);
   5.261 -        __vmread(EXIT_QUALIFICATION, &exit_qualification);
   5.262          hvm_do_hypercall(regs);
   5.263          break;
   5.264      }
   5.265      case EXIT_REASON_CR_ACCESS:
   5.266      {
   5.267 -        __vmread(GUEST_RIP, &rip);
   5.268          __vmread(EXIT_QUALIFICATION, &exit_qualification);
   5.269          inst_len = __get_instruction_length(); /* Safe: MOV Cn, LMSW, CLTS */
   5.270          if ( vmx_cr_access(exit_qualification, regs) )
   5.271              __update_guest_eip(inst_len);
   5.272 -        TRACE_VMEXIT(3, regs->error_code);
   5.273          TRACE_VMEXIT(4, exit_qualification);
   5.274          break;
   5.275      }
   5.276 @@ -2340,17 +2336,23 @@ asmlinkage void vmx_vmexit_handler(struc
   5.277          __vmread(EXIT_QUALIFICATION, &exit_qualification);
   5.278          inst_len = __get_instruction_length(); /* Safe: IN, INS, OUT, OUTS */
   5.279          vmx_io_instruction(exit_qualification, inst_len);
   5.280 -        TRACE_VMEXIT(4,exit_qualification);
   5.281 +        TRACE_VMEXIT(4, exit_qualification);
   5.282          break;
   5.283      case EXIT_REASON_MSR_READ:
   5.284          inst_len = __get_instruction_length(); /* Safe: RDMSR */
   5.285          __update_guest_eip(inst_len);
   5.286          vmx_do_msr_read(regs);
   5.287 +        TRACE_VMEXIT(1, regs->ecx);
   5.288 +        TRACE_VMEXIT(2, regs->eax);
   5.289 +        TRACE_VMEXIT(3, regs->edx);
   5.290          break;
   5.291      case EXIT_REASON_MSR_WRITE:
   5.292          inst_len = __get_instruction_length(); /* Safe: WRMSR */
   5.293          __update_guest_eip(inst_len);
   5.294          vmx_do_msr_write(regs);
   5.295 +        TRACE_VMEXIT(1, regs->ecx);
   5.296 +        TRACE_VMEXIT(2, regs->eax);
   5.297 +        TRACE_VMEXIT(3, regs->edx);
   5.298          break;
   5.299      case EXIT_REASON_MWAIT_INSTRUCTION:
   5.300      case EXIT_REASON_MONITOR_INSTRUCTION:
   5.301 @@ -2384,26 +2386,25 @@ asmlinkage void vmx_load_cr2(void)
   5.302      asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
   5.303  }
   5.304  
   5.305 -asmlinkage void vmx_trace_vmentry (void)
   5.306 +asmlinkage void vmx_trace_vmentry(void)
   5.307  {
   5.308 -    TRACE_5D(TRC_VMX_VMENTRY,
   5.309 +    TRACE_5D(TRC_VMX_VMENTRY + current->vcpu_id,
   5.310               this_cpu(trace_values)[0],
   5.311               this_cpu(trace_values)[1],
   5.312               this_cpu(trace_values)[2],
   5.313               this_cpu(trace_values)[3],
   5.314               this_cpu(trace_values)[4]);
   5.315 -    TRACE_VMEXIT(0,9);
   5.316 -    TRACE_VMEXIT(1,9);
   5.317 -    TRACE_VMEXIT(2,9);
   5.318 -    TRACE_VMEXIT(3,9);
   5.319 -    TRACE_VMEXIT(4,9);
   5.320 -    return;
   5.321 +
   5.322 +    TRACE_VMEXIT(0, 0);
   5.323 +    TRACE_VMEXIT(1, 0);
   5.324 +    TRACE_VMEXIT(2, 0);
   5.325 +    TRACE_VMEXIT(3, 0);
   5.326 +    TRACE_VMEXIT(4, 0);
   5.327  }
   5.328  
   5.329  asmlinkage void vmx_trace_vmexit (void)
   5.330  {
   5.331 -    TRACE_3D(TRC_VMX_VMEXIT,0,0,0);
   5.332 -    return;
   5.333 +    TRACE_3D(TRC_VMX_VMEXIT + current->vcpu_id, 0, 0, 0);
   5.334  }
   5.335  
   5.336  /*
     6.1 --- a/xen/include/public/trace.h	Wed Oct 18 19:14:34 2006 +0100
     6.2 +++ b/xen/include/public/trace.h	Wed Oct 18 19:20:36 2006 +0100
     6.3 @@ -19,11 +19,11 @@
     6.4  
     6.5  /* Trace subclasses */
     6.6  #define TRC_SUBCLS_SHIFT 12
     6.7 +
     6.8  /* trace subclasses for VMX */
     6.9  #define TRC_VMXEXIT  0x00081000   /* VMX exit trace            */
    6.10 -#define TRC_VMXTIMER 0x00082000   /* VMX timer trace           */
    6.11 -#define TRC_VMXINT   0x00084000   /* VMX interrupt trace       */
    6.12 -#define TRC_VMXIO    0x00088000   /* VMX io emulation trace  */
    6.13 +#define TRC_VMXENTRY 0x00082000   /* VMX exit trace            */
    6.14 +#define TRC_VMXINTR  0x00084000   /* VMX interrupt trace       */
    6.15  
    6.16  /* Trace events per class */
    6.17  #define TRC_LOST_RECORDS        (TRC_GEN + 1)
    6.18 @@ -50,11 +50,8 @@
    6.19  
    6.20  /* trace events per subclass */
    6.21  #define TRC_VMX_VMEXIT          (TRC_VMXEXIT + 1)
    6.22 -#define TRC_VMX_VMENTRY         (TRC_VMXEXIT + 2)
    6.23 -
    6.24 -#define TRC_VMX_TIMER_INTR      (TRC_VMXTIMER + 1)
    6.25 -
    6.26 -#define TRC_VMX_INT             (TRC_VMXINT + 1)
    6.27 +#define TRC_VMX_VMENTRY         (TRC_VMXENTRY + 1)
    6.28 +#define TRC_VMX_INTR            (TRC_VMXINTR + 1)
    6.29  
    6.30  
    6.31  /* This structure represents a single trace buffer record. */