ia64/xen-unstable

changeset 9279:463c67da6f0a

[IA64] fixed a vcpu_translate bug

There are some below code segments in guest OS
1. Rsm psr.dt
...
2. itc.d r18
...
3. rfi

After executing instruction 1, domain is in metaphysical mode.
When executing instruction 2, VMM gets control to emulate this
instruction. Firstly VMM will try to get opcode, which may
trigger a tlb miss. At this time domain is in metaphysical mode
and the fault address is in region 5. vcpu_translate handles this
as normal guest metaphysical mode.

It's not correct; sometimes this will make dom0 hang.

cpu_translate should handle this situation as if
guest is not in metaphysical mode.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Fri Mar 17 14:06:20 2006 -0700 (2006-03-17)
parents edc63b5dd71d
children ccde0eab2545
files xen/arch/ia64/xen/vcpu.c
line diff
     1.1 --- a/xen/arch/ia64/xen/vcpu.c	Fri Mar 17 13:44:48 2006 -0700
     1.2 +++ b/xen/arch/ia64/xen/vcpu.c	Fri Mar 17 14:06:20 2006 -0700
     1.3 @@ -1283,13 +1283,23 @@ IA64FAULT vcpu_translate(VCPU *vcpu, UIN
     1.4  // FIXME: This seems to happen even though it shouldn't.  Need to track
     1.5  // this down, but since it has been apparently harmless, just flag it for now
     1.6  //			panic_domain(vcpu_regs(vcpu),
     1.7 -			printk(
     1.8 -			 "vcpu_translate: bad physical address: 0x%lx\n",address);
     1.9 +
    1.10 +			/*
    1.11 +			 * Guest may execute itc.d and rfi with psr.dt=0
    1.12 +			 * When VMM try to fetch opcode, tlb miss may happen,
    1.13 +			 * At this time PSCB(vcpu,metaphysical_mode)=1,
    1.14 +			 * region=5,VMM need to handle this tlb miss as if
    1.15 +			 * PSCB(vcpu,metaphysical_mode)=0
    1.16 +			 */           
    1.17 +			printk("vcpu_translate: bad physical address: 0x%lx\n",
    1.18 +			       address);
    1.19 +		} else {
    1.20 +			*pteval = (address & _PAGE_PPN_MASK) | __DIRTY_BITS |
    1.21 +			          _PAGE_PL_2 | _PAGE_AR_RWX;
    1.22 +			*itir = PAGE_SHIFT << 2;
    1.23 +			phys_translate_count++;
    1.24 +			return IA64_NO_FAULT;
    1.25  		}
    1.26 -		*pteval = (address & _PAGE_PPN_MASK) | __DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX;
    1.27 -		*itir = PAGE_SHIFT << 2;
    1.28 -		phys_translate_count++;
    1.29 -		return IA64_NO_FAULT;
    1.30  	}
    1.31  	else if (!region && warn_region0_address) {
    1.32  		REGS *regs = vcpu_regs(vcpu);