1.1 --- a/.rootkeys	Wed Jul 09 10:27:24 2003 +0000
     1.2 +++ b/.rootkeys	Wed Jul 09 16:27:59 2003 +0000
     1.3 @@ -204,8 +204,21 @@ 3ddb79bdkDY1bSOYkToP1Cc49VdBxg xen/drive
     1.4  3ddb79bdPyAvT_WZTAFhaX0jp-yXSw xen/drivers/ide/ide_modes.h
     1.5  3e4a8d401aSwOzCScQXR3lsmNlAwUQ xen/drivers/ide/piix.c
     1.6  3ddb79bfMlOcWUwjtg6oMYhGySHDDw xen/drivers/net/3c59x.c
     1.7 +3f0c423bjmEpn1Nbk1Q8fv8ElccwAA xen/drivers/net/8139too.c
     1.8  3ddb79c0tWiE8xIFHszxipeVCGKTSA xen/drivers/net/Makefile
     1.9 +3f0c4247730LYUgz3p5ziYqy-s_glw xen/drivers/net/SUPPORTED_CARDS
    1.10  3ddb79bfU-H1Hms4BuJEPPydjXUEaQ xen/drivers/net/Space.c
    1.11 +3f0c428e41JP96bh-J0jnX59vJyUeQ xen/drivers/net/e100/LICENSE
    1.12 +3f0c428es_xrZnnZQXXHhjzuqj9CTg xen/drivers/net/e100/Makefile
    1.13 +3f0c428eCEnifr-r6XCZKUkzIEHdYw xen/drivers/net/e100/e100.h
    1.14 +3f0c428eyYDJIqvO7W_QbgnGnbgPqA xen/drivers/net/e100/e100_config.c
    1.15 +3f0c428e-NvNXlOyIw8H3YllFL6lfA xen/drivers/net/e100/e100_config.h
    1.16 +3f0c428ecPXSlA_4rp_-6O09uQqHbg xen/drivers/net/e100/e100_eeprom.c
    1.17 +3f0c428eWlXUzaulDjS1UpUP7Ckejg xen/drivers/net/e100/e100_main.c
    1.18 +3f0c428eKW1sEaCen-HIMUwMtQXnVQ xen/drivers/net/e100/e100_phy.c
    1.19 +3f0c428eR00XnyLIZKb5H5QF_I9QDg xen/drivers/net/e100/e100_phy.h
    1.20 +3f0c428eII-G2i_Qv_aCQjLzHcDKEQ xen/drivers/net/e100/e100_test.c
    1.21 +3f0c428eJ_gqbOFzS3bWSI7geA--Eg xen/drivers/net/e100/e100_ucode.h
    1.22  3e4540ccS4bfbx9rLiLElP0F1OVwZA xen/drivers/net/e1000/LICENSE
    1.23  3e4540ccXG6af_6-u0IiKKvtdGHJyA xen/drivers/net/e1000/Makefile
    1.24  3e4540ccoY2eo4VIkbR4sCOj0bVzSA xen/drivers/net/e1000/e1000.h
    1.25 @@ -215,14 +228,23 @@ 3e4540cczrrQVyyj-s1-viyX1kMUlA xen/drive
    1.26  3e4540ccvQ9Dtoh9tV-L3ULUwN9X7g xen/drivers/net/e1000/e1000_main.c
    1.27  3e4540cc3t7_y-YLeyMG2pX9xtdXPA xen/drivers/net/e1000/e1000_osdep.h
    1.28  3e4540cct_8Ig-Y1W_vM2gS_u7mC0A xen/drivers/net/e1000/e1000_param.c
    1.29 -3e465c00t2nochqR27eEY_FBjxsUCw xen/drivers/net/ne/8390.c
    1.30 -3e465c00AIRmk20x1vYETtnL71eGvA xen/drivers/net/ne/8390.h
    1.31 -3e465c00UIvPTAtAcgcQWCVFa2bwww xen/drivers/net/ne/Makefile
    1.32 -3e465c00rWSHiXmHuOWLRf7r2n8S3g xen/drivers/net/ne/ne.c
    1.33  3ddb79bfKvn9mt0kofpkw0QaWjxO6A xen/drivers/net/net_init.c
    1.34 +3f0c428exbF4as5zi8GyGyDSUITmxg xen/drivers/net/pcnet32.c
    1.35  3ddb79bf_CBcu3QWYwq4bNAOnM2RqQ xen/drivers/net/setup.c
    1.36  3e45a0c6u66EL2AI36eLOmf_abXs7g xen/drivers/net/tg3.c
    1.37  3e45a0c6yrXj5pmQT0PvVSJ01YLABQ xen/drivers/net/tg3.h
    1.38 +3f0c428e0tn3ZknveWidRNtHYcyHzw xen/drivers/net/tulip/21142.c
    1.39 +3f0c428esCXQWoJHSJ5zUZ7iQc_rlQ xen/drivers/net/tulip/ChangeLog
    1.40 +3f0c428eB8pVjwDolFZDa0YZMQW1rw xen/drivers/net/tulip/Makefile
    1.41 +3f0c428el4rtJgjSoK_K04g5Udg2Tw xen/drivers/net/tulip/eeprom.c
    1.42 +3f0c428eYyDHq5AnrB60p3g0uXWYwA xen/drivers/net/tulip/interrupt.c
    1.43 +3f0c428eI99GG-HH2aQCIQ4tyISe8w xen/drivers/net/tulip/media.c
    1.44 +3f0c428eErjUSQiTzPJJlSrR0ORJog xen/drivers/net/tulip/pnic.c
    1.45 +3f0c428eyyo0-aI_fj4gDBiNYe-Idw xen/drivers/net/tulip/pnic2.c
    1.46 +3f0c428eZQhoTueBPxOO5YbuzoTofw xen/drivers/net/tulip/timer.c
    1.47 +3f0c428eoDFGJZJrBRnA7918Yovt0A xen/drivers/net/tulip/tulip.h
    1.48 +3f0c428e46klSV-upTm6D8tCdzQs8Q xen/drivers/net/tulip/tulip_core.c
    1.49 +3f0c428eu_CTRPhmTgGIjoiGI_PmrA xen/drivers/net/via-rhine.c
    1.50  3ddb79beUWngyIhMHgyPtuTem4o4JA xen/drivers/pci/Makefile
    1.51  3ddb79beU9td0Mnm0VUMklerBa37qQ xen/drivers/pci/compat.c
    1.52  3ddb79beHkGQE58z5t5gyUCYiwOxvw xen/drivers/pci/gen-devlist.c
    1.53 @@ -387,6 +409,7 @@ 3ddb79c0c0cX_DZE209-Bb-Rx1v-Aw xen/inclu
    1.54  3e9c248aEG_nCngztiFmv5CfayNkcA xen/include/xeno/cdrom.h
    1.55  3ddb79c259jh8hE7vre_8NuE7nwNSA xen/include/xeno/config.h
    1.56  3eb165e0eawr3R-p2ZQtSdLWtLRN_A xen/include/xeno/console.h
    1.57 +3f0c428eIwGr7n9fj4FkBdX2YvA_Rw xen/include/xeno/crc32.h
    1.58  3ddb79c1V44RD26YqCUm-kqIupM37A xen/include/xeno/ctype.h
    1.59  3ddb79c05DdHQ0UxX_jKsXdR4QlMCA xen/include/xeno/delay.h
    1.60  3e6377eaioRoNm0m_HSDEAd4Vqrq_w xen/include/xeno/dom_mem_ops.h

     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen/drivers/net/8139too.c	Wed Jul 09 16:27:59 2003 +0000
     2.3 @@ -0,0 +1,2671 @@
     2.4 +/*
     2.5 +
     2.6 +	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
     2.7 +
     2.8 +	Maintained by Jeff Garzik <jgarzik@pobox.com>
     2.9 +	Copyright 2000-2002 Jeff Garzik
    2.10 +
    2.11 +	Much code comes from Donald Becker's rtl8139.c driver,
    2.12 +	versions 1.13 and older.  This driver was originally based
    2.13 +	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:
    2.14 +
    2.15 +	-----<snip>-----
    2.16 +
    2.17 +        	Written 1997-2001 by Donald Becker.
    2.18 +		This software may be used and distributed according to the
    2.19 +		terms of the GNU General Public License (GPL), incorporated
    2.20 +		herein by reference.  Drivers based on or derived from this
    2.21 +		code fall under the GPL and must retain the authorship,
    2.22 +		copyright and license notice.  This file is not a complete
    2.23 +		program and may only be used when the entire operating
    2.24 +		system is licensed under the GPL.
    2.25 +
    2.26 +		This driver is for boards based on the RTL8129 and RTL8139
    2.27 +		PCI ethernet chips.
    2.28 +
    2.29 +		The author may be reached as becker@scyld.com, or C/O Scyld
    2.30 +		Computing Corporation 410 Severn Ave., Suite 210 Annapolis
    2.31 +		MD 21403
    2.32 +
    2.33 +		Support and updates available at
    2.34 +		http://www.scyld.com/network/rtl8139.html
    2.35 +
    2.36 +		Twister-tuning table provided by Kinston
    2.37 +		<shangh@realtek.com.tw>.
    2.38 +
    2.39 +	-----<snip>-----
    2.40 +
    2.41 +	This software may be used and distributed according to the terms
    2.42 +	of the GNU General Public License, incorporated herein by reference.
    2.43 +
    2.44 +	Contributors:
    2.45 +
    2.46 +		Donald Becker - he wrote the original driver, kudos to him!
    2.47 +		(but please don't e-mail him for support, this isn't his driver)
    2.48 +
    2.49 +		Tigran Aivazian - bug fixes, skbuff free cleanup
    2.50 +
    2.51 +		Martin Mares - suggestions for PCI cleanup
    2.52 +
    2.53 +		David S. Miller - PCI DMA and softnet updates
    2.54 +
    2.55 +		Ernst Gill - fixes ported from BSD driver
    2.56 +
    2.57 +		Daniel Kobras - identified specific locations of
    2.58 +			posted MMIO write bugginess
    2.59 +
    2.60 +		Gerard Sharp - bug fix, testing and feedback
    2.61 +
    2.62 +		David Ford - Rx ring wrap fix
    2.63 +
    2.64 +		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
    2.65 +		to find and fix a crucial bug on older chipsets.
    2.66 +
    2.67 +		Donald Becker/Chris Butterworth/Marcus Westergren -
    2.68 +		Noticed various Rx packet size-related buglets.
    2.69 +
    2.70 +		Santiago Garcia Mantinan - testing and feedback
    2.71 +
    2.72 +		Jens David - 2.2.x kernel backports
    2.73 +
    2.74 +		Martin Dennett - incredibly helpful insight on undocumented
    2.75 +		features of the 8139 chips
    2.76 +
    2.77 +		Jean-Jacques Michel - bug fix
    2.78 +
    2.79 +		Tobias Ringström - Rx interrupt status checking suggestion
    2.80 +
    2.81 +		Andrew Morton - Clear blocked signals, avoid
    2.82 +		buffer overrun setting current->comm.
    2.83 +
    2.84 +		Kalle Olavi Niemitalo - Wake-on-LAN ioctls
    2.85 +
    2.86 +		Robert Kuebel - Save kernel thread from dying on any signal.
    2.87 +
    2.88 +	Submitting bug reports:
    2.89 +
    2.90 +		"rtl8139-diag -mmmaaavvveefN" output
    2.91 +		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
    2.92 +
    2.93 +		See 8139too.txt for more details.
    2.94 +
    2.95 +*/
    2.96 +
    2.97 +#define DRV_NAME	"8139too"
    2.98 +#define DRV_VERSION	"0.9.26"
    2.99 +
   2.100 +#include <linux/config.h>
   2.101 +#include <linux/module.h>
   2.102 +#include <linux/kernel.h>
   2.103 +#include <linux/lib.h>
   2.104 +#include <linux/timer.h>
   2.105 +#include <linux/pci.h>
   2.106 +#include <linux/init.h>
   2.107 +#include <linux/ioport.h>
   2.108 +#include <linux/netdevice.h>
   2.109 +#include <linux/etherdevice.h>
   2.110 +#include <linux/delay.h>
   2.111 +#include <linux/ethtool.h>
   2.112 +#include <linux/mii.h>
   2.113 +#include <linux/crc32.h>
   2.114 +#include <asm/io.h>
   2.115 +#include <asm/uaccess.h>
   2.116 +
   2.117 +/* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
   2.118 +static int next_tick = 3 * HZ;
   2.119 +
   2.120 +#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION
   2.121 +#define PFX DRV_NAME ": "
   2.122 +
   2.123 +
   2.124 +/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
   2.125 +#ifdef CONFIG_8139TOO_PIO
   2.126 +#define USE_IO_OPS 1
   2.127 +#endif
   2.128 +
   2.129 +/* define to 1 to enable copious debugging info */
   2.130 +#undef RTL8139_DEBUG
   2.131 +
   2.132 +/* define to 1 to disable lightweight runtime debugging checks */
   2.133 +#undef RTL8139_NDEBUG
   2.134 +
   2.135 +
   2.136 +#ifdef RTL8139_DEBUG
   2.137 +/* note: prints function name for you */
   2.138 +#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
   2.139 +#else
   2.140 +#  define DPRINTK(fmt, args...)
   2.141 +#endif
   2.142 +
   2.143 +#ifdef RTL8139_NDEBUG
   2.144 +#  define assert(expr) do {} while (0)
   2.145 +#else
   2.146 +#  define assert(expr) \
   2.147 +        if(!(expr)) {					\
   2.148 +        printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
   2.149 +        #expr,__FILE__,__FUNCTION__,__LINE__);		\
   2.150 +        }
   2.151 +#endif
   2.152 +
   2.153 +
   2.154 +/* A few user-configurable values. */
   2.155 +/* media options */
   2.156 +#define MAX_UNITS 8
   2.157 +static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
   2.158 +static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
   2.159 +
   2.160 +/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
   2.161 +static int max_interrupt_work = 20;
   2.162 +
   2.163 +/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   2.164 +   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
   2.165 +static int multicast_filter_limit = 32;
   2.166 +
   2.167 +#if 0
   2.168 +/* bitmapped message enable number */
   2.169 +static int debug = -1;
   2.170 +#endif
   2.171 +
   2.172 +/* Size of the in-memory receive ring. */
   2.173 +#define RX_BUF_LEN_IDX	2	/* 0==8K, 1==16K, 2==32K, 3==64K */
   2.174 +#define RX_BUF_LEN	(8192 << RX_BUF_LEN_IDX)
   2.175 +#define RX_BUF_PAD	16
   2.176 +#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
   2.177 +#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
   2.178 +
   2.179 +/* Number of Tx descriptor registers. */
   2.180 +#define NUM_TX_DESC	4
   2.181 +
   2.182 +/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
   2.183 +#define MAX_ETH_FRAME_SIZE	1536
   2.184 +
   2.185 +/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
   2.186 +#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE
   2.187 +#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)
   2.188 +
   2.189 +/* PCI Tuning Parameters
   2.190 +   Threshold is bytes transferred to chip before transmission starts. */
   2.191 +#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
   2.192 +
   2.193 +/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
   2.194 +#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */
   2.195 +#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */
   2.196 +#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
   2.197 +#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */
   2.198 +
   2.199 +/* Operational parameters that usually are not changed. */
   2.200 +/* Time in jiffies before concluding the transmitter is hung. */
   2.201 +#define TX_TIMEOUT  (6*HZ)
   2.202 +
   2.203 +
   2.204 +enum {
   2.205 +	HAS_MII_XCVR = 0x010000,
   2.206 +	HAS_CHIP_XCVR = 0x020000,
   2.207 +	HAS_LNK_CHNG = 0x040000,
   2.208 +};
   2.209 +
   2.210 +#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */
   2.211 +#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */
   2.212 +#define RTL_MIN_IO_SIZE 0x80
   2.213 +#define RTL8139B_IO_SIZE 256
   2.214 +
   2.215 +#define RTL8129_CAPS	HAS_MII_XCVR
   2.216 +#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG
   2.217 +
   2.218 +typedef enum {
   2.219 +	RTL8139 = 0,
   2.220 +	RTL8139_CB,
   2.221 +	SMC1211TX,
   2.222 +	/*MPX5030,*/
   2.223 +	DELTA8139,
   2.224 +	ADDTRON8139,
   2.225 +	DFE538TX,
   2.226 +	DFE690TXD,
   2.227 +	FE2000VX,
   2.228 +	ALLIED8139,
   2.229 +	RTL8129,
   2.230 +	FNW3603TX,
   2.231 +	FNW3800TX,
   2.232 +} board_t;
   2.233 +
   2.234 +
   2.235 +/* indexed by board_t, above */
   2.236 +static struct {
   2.237 +	const char *name;
   2.238 +	u32 hw_flags;
   2.239 +} board_info[] __devinitdata = {
   2.240 +	{ "RealTek RTL8139 Fast Ethernet", RTL8139_CAPS },
   2.241 +	{ "RealTek RTL8139B PCI/CardBus", RTL8139_CAPS },
   2.242 +	{ "SMC1211TX EZCard 10/100 (RealTek RTL8139)", RTL8139_CAPS },
   2.243 +/*	{ MPX5030, "Accton MPX5030 (RealTek RTL8139)", RTL8139_CAPS },*/
   2.244 +	{ "Delta Electronics 8139 10/100BaseTX", RTL8139_CAPS },
   2.245 +	{ "Addtron Technolgy 8139 10/100BaseTX", RTL8139_CAPS },
   2.246 +	{ "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },
   2.247 +	{ "D-Link DFE-690TXD (RealTek RTL8139)", RTL8139_CAPS },
   2.248 +	{ "AboCom FE2000VX (RealTek RTL8139)", RTL8139_CAPS },
   2.249 +	{ "Allied Telesyn 8139 CardBus", RTL8139_CAPS },
   2.250 +	{ "RealTek RTL8129", RTL8129_CAPS },
   2.251 +	{ "Planex FNW-3603-TX 10/100 CardBus", RTL8139_CAPS },
   2.252 +	{ "Planex FNW-3800-TX 10/100 CardBus", RTL8139_CAPS },
   2.253 +};
   2.254 +
   2.255 +
   2.256 +static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = {
   2.257 +	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
   2.258 +	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139_CB },
   2.259 +	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
   2.260 +/*	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
   2.261 +	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
   2.262 +	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
   2.263 +	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX },
   2.264 +	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE690TXD },
   2.265 +	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FE2000VX },
   2.266 +	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ALLIED8139 },
   2.267 +	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3603TX },
   2.268 +	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3800TX },
   2.269 +
   2.270 +#ifdef CONFIG_8139TOO_8129
   2.271 +	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
   2.272 +#endif
   2.273 +
   2.274 +	/* some crazy cards report invalid vendor ids like
   2.275 +	 * 0x0001 here.  The other ids are valid and constant,
   2.276 +	 * so we simply don't match on the main vendor id.
   2.277 +	 */
   2.278 +	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
   2.279 +	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, DFE538TX },
   2.280 +	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, FE2000VX },
   2.281 +
   2.282 +	{0,}
   2.283 +};
   2.284 +MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
   2.285 +
   2.286 +#if 0
   2.287 +static struct {
   2.288 +	const char str[ETH_GSTRING_LEN];
   2.289 +} ethtool_stats_keys[] = {
   2.290 +	{ "early_rx" },
   2.291 +	{ "tx_buf_mapped" },
   2.292 +	{ "tx_timeouts" },
   2.293 +	{ "rx_lost_in_ring" },
   2.294 +};
   2.295 +#endif
   2.296 +
   2.297 +/* The rest of these values should never change. */
   2.298 +
   2.299 +/* Symbolic offsets to registers. */
   2.300 +enum RTL8139_registers {
   2.301 +	MAC0 = 0,		/* Ethernet hardware address. */
   2.302 +	MAR0 = 8,		/* Multicast filter. */
   2.303 +	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */
   2.304 +	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */
   2.305 +	RxBuf = 0x30,
   2.306 +	ChipCmd = 0x37,
   2.307 +	RxBufPtr = 0x38,
   2.308 +	RxBufAddr = 0x3A,
   2.309 +	IntrMask = 0x3C,
   2.310 +	IntrStatus = 0x3E,
   2.311 +	TxConfig = 0x40,
   2.312 +	ChipVersion = 0x43,
   2.313 +	RxConfig = 0x44,
   2.314 +	Timer = 0x48,		/* A general-purpose counter. */
   2.315 +	RxMissed = 0x4C,	/* 24 bits valid, write clears. */
   2.316 +	Cfg9346 = 0x50,
   2.317 +	Config0 = 0x51,
   2.318 +	Config1 = 0x52,
   2.319 +	FlashReg = 0x54,
   2.320 +	MediaStatus = 0x58,
   2.321 +	Config3 = 0x59,
   2.322 +	Config4 = 0x5A,		/* absent on RTL-8139A */
   2.323 +	HltClk = 0x5B,
   2.324 +	MultiIntr = 0x5C,
   2.325 +	TxSummary = 0x60,
   2.326 +	BasicModeCtrl = 0x62,
   2.327 +	BasicModeStatus = 0x64,
   2.328 +	NWayAdvert = 0x66,
   2.329 +	NWayLPAR = 0x68,
   2.330 +	NWayExpansion = 0x6A,
   2.331 +	/* Undocumented registers, but required for proper operation. */
   2.332 +	FIFOTMS = 0x70,		/* FIFO Control and test. */
   2.333 +	CSCR = 0x74,		/* Chip Status and Configuration Register. */
   2.334 +	PARA78 = 0x78,
   2.335 +	PARA7c = 0x7c,		/* Magic transceiver parameter register. */
   2.336 +	Config5 = 0xD8,		/* absent on RTL-8139A */
   2.337 +};
   2.338 +
   2.339 +enum ClearBitMasks {
   2.340 +	MultiIntrClear = 0xF000,
   2.341 +	ChipCmdClear = 0xE2,
   2.342 +	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
   2.343 +};
   2.344 +
   2.345 +enum ChipCmdBits {
   2.346 +	CmdReset = 0x10,
   2.347 +	CmdRxEnb = 0x08,
   2.348 +	CmdTxEnb = 0x04,
   2.349 +	RxBufEmpty = 0x01,
   2.350 +};
   2.351 +
   2.352 +/* Interrupt register bits, using my own meaningful names. */
   2.353 +enum IntrStatusBits {
   2.354 +	PCIErr = 0x8000,
   2.355 +	PCSTimeout = 0x4000,
   2.356 +	RxFIFOOver = 0x40,
   2.357 +	RxUnderrun = 0x20,
   2.358 +	RxOverflow = 0x10,
   2.359 +	TxErr = 0x08,
   2.360 +	TxOK = 0x04,
   2.361 +	RxErr = 0x02,
   2.362 +	RxOK = 0x01,
   2.363 +
   2.364 +	RxAckBits = RxFIFOOver | RxOverflow | RxOK,
   2.365 +};
   2.366 +
   2.367 +enum TxStatusBits {
   2.368 +	TxHostOwns = 0x2000,
   2.369 +	TxUnderrun = 0x4000,
   2.370 +	TxStatOK = 0x8000,
   2.371 +	TxOutOfWindow = 0x20000000,
   2.372 +	TxAborted = 0x40000000,
   2.373 +	TxCarrierLost = 0x80000000,
   2.374 +};
   2.375 +enum RxStatusBits {
   2.376 +	RxMulticast = 0x8000,
   2.377 +	RxPhysical = 0x4000,
   2.378 +	RxBroadcast = 0x2000,
   2.379 +	RxBadSymbol = 0x0020,
   2.380 +	RxRunt = 0x0010,
   2.381 +	RxTooLong = 0x0008,
   2.382 +	RxCRCErr = 0x0004,
   2.383 +	RxBadAlign = 0x0002,
   2.384 +	RxStatusOK = 0x0001,
   2.385 +};
   2.386 +
   2.387 +/* Bits in RxConfig. */
   2.388 +enum rx_mode_bits {
   2.389 +	AcceptErr = 0x20,
   2.390 +	AcceptRunt = 0x10,
   2.391 +	AcceptBroadcast = 0x08,
   2.392 +	AcceptMulticast = 0x04,
   2.393 +	AcceptMyPhys = 0x02,
   2.394 +	AcceptAllPhys = 0x01,
   2.395 +};
   2.396 +
   2.397 +/* Bits in TxConfig. */
   2.398 +enum tx_config_bits {
   2.399 +	TxIFG1 = (1 << 25),	/* Interframe Gap Time */
   2.400 +	TxIFG0 = (1 << 24),	/* Enabling these bits violates IEEE 802.3 */
   2.401 +	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
   2.402 +	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */
   2.403 +	TxClearAbt = (1 << 0),	/* Clear abort (WO) */
   2.404 +	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */
   2.405 +	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */
   2.406 +
   2.407 +	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
   2.408 +};
   2.409 +
   2.410 +/* Bits in Config1 */
   2.411 +enum Config1Bits {
   2.412 +	Cfg1_PM_Enable = 0x01,
   2.413 +	Cfg1_VPD_Enable = 0x02,
   2.414 +	Cfg1_PIO = 0x04,
   2.415 +	Cfg1_MMIO = 0x08,
   2.416 +	LWAKE = 0x10,		/* not on 8139, 8139A */
   2.417 +	Cfg1_Driver_Load = 0x20,
   2.418 +	Cfg1_LED0 = 0x40,
   2.419 +	Cfg1_LED1 = 0x80,
   2.420 +	SLEEP = (1 << 1),	/* only on 8139, 8139A */
   2.421 +	PWRDN = (1 << 0),	/* only on 8139, 8139A */
   2.422 +};
   2.423 +
   2.424 +/* Bits in Config3 */
   2.425 +enum Config3Bits {
   2.426 +	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */
   2.427 +	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
   2.428 +	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
   2.429 +	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */
   2.430 +	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */
   2.431 +	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
   2.432 +	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */
   2.433 +	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
   2.434 +};
   2.435 +
   2.436 +/* Bits in Config4 */
   2.437 +enum Config4Bits {
   2.438 +	LWPTN = (1 << 2),	/* not on 8139, 8139A */
   2.439 +};
   2.440 +
   2.441 +/* Bits in Config5 */
   2.442 +enum Config5Bits {
   2.443 +	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */
   2.444 +	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */
   2.445 +	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */
   2.446 +	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
   2.447 +	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */
   2.448 +	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */
   2.449 +	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */
   2.450 +};
   2.451 +
   2.452 +enum RxConfigBits {
   2.453 +	/* rx fifo threshold */
   2.454 +	RxCfgFIFOShift = 13,
   2.455 +	RxCfgFIFONone = (7 << RxCfgFIFOShift),
   2.456 +
   2.457 +	/* Max DMA burst */
   2.458 +	RxCfgDMAShift = 8,
   2.459 +	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
   2.460 +
   2.461 +	/* rx ring buffer length */
   2.462 +	RxCfgRcv8K = 0,
   2.463 +	RxCfgRcv16K = (1 << 11),
   2.464 +	RxCfgRcv32K = (1 << 12),
   2.465 +	RxCfgRcv64K = (1 << 11) | (1 << 12),
   2.466 +
   2.467 +	/* Disable packet wrap at end of Rx buffer */
   2.468 +	RxNoWrap = (1 << 7),
   2.469 +};
   2.470 +
   2.471 +
   2.472 +/* Twister tuning parameters from RealTek.
   2.473 +   Completely undocumented, but required to tune bad links on some boards. */
   2.474 +enum CSCRBits {
   2.475 +	CSCR_LinkOKBit = 0x0400,
   2.476 +	CSCR_LinkChangeBit = 0x0800,
   2.477 +	CSCR_LinkStatusBits = 0x0f000,
   2.478 +	CSCR_LinkDownOffCmd = 0x003c0,
   2.479 +	CSCR_LinkDownCmd = 0x0f3c0,
   2.480 +};
   2.481 +
   2.482 +
   2.483 +enum Cfg9346Bits {
   2.484 +	Cfg9346_Lock = 0x00,
   2.485 +	Cfg9346_Unlock = 0xC0,
   2.486 +};
   2.487 +
   2.488 +#ifdef CONFIG_8139TOO_TUNE_TWISTER
   2.489 +
   2.490 +enum TwisterParamVals {
   2.491 +	PARA78_default	= 0x78fa8388,
   2.492 +	PARA7c_default	= 0xcb38de43,	/* param[0][3] */
   2.493 +	PARA7c_xxx	= 0xcb38de43,
   2.494 +};
   2.495 +
   2.496 +static const unsigned long param[4][4] = {
   2.497 +	{0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
   2.498 +	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
   2.499 +	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
   2.500 +	{0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
   2.501 +};
   2.502 +
   2.503 +#endif /* CONFIG_8139TOO_TUNE_TWISTER */
   2.504 +
   2.505 +typedef enum {
   2.506 +	CH_8139 = 0,
   2.507 +	CH_8139_K,
   2.508 +	CH_8139A,
   2.509 +	CH_8139B,
   2.510 +	CH_8130,
   2.511 +	CH_8139C,
   2.512 +} chip_t;
   2.513 +
   2.514 +enum chip_flags {
   2.515 +	HasHltClk = (1 << 0),
   2.516 +	HasLWake = (1 << 1),
   2.517 +};
   2.518 +
   2.519 +
   2.520 +/* directly indexed by chip_t, above */
   2.521 +const static struct {
   2.522 +	const char *name;
   2.523 +	u8 version; /* from RTL8139C docs */
   2.524 +	u32 RxConfigMask; /* should clear the bits supported by this chip */
   2.525 +	u32 flags;
   2.526 +} rtl_chip_info[] = {
   2.527 +	{ "RTL-8139",
   2.528 +	  0x40,
   2.529 +	  0xf0fe0040, /* XXX copied from RTL8139A, verify */
   2.530 +	  HasHltClk,
   2.531 +	},
   2.532 +
   2.533 +	{ "RTL-8139 rev K",
   2.534 +	  0x60,
   2.535 +	  0xf0fe0040,
   2.536 +	  HasHltClk,
   2.537 +	},
   2.538 +
   2.539 +	{ "RTL-8139A",
   2.540 +	  0x70,
   2.541 +	  0xf0fe0040,
   2.542 +	  HasHltClk, /* XXX undocumented? */
   2.543 +	},
   2.544 +
   2.545 +	{ "RTL-8139B",
   2.546 +	  0x78,
   2.547 +	  0xf0fc0040,
   2.548 +	  HasLWake,
   2.549 +	},
   2.550 +
   2.551 +	{ "RTL-8130",
   2.552 +	  0x7C,
   2.553 +	  0xf0fe0040, /* XXX copied from RTL8139A, verify */
   2.554 +	  HasLWake,
   2.555 +	},
   2.556 +
   2.557 +	{ "RTL-8139C",
   2.558 +	  0x74,
   2.559 +	  0xf0fc0040, /* XXX copied from RTL8139B, verify */
   2.560 +	  HasLWake,
   2.561 +	},
   2.562 +
   2.563 +};
   2.564 +
   2.565 +struct rtl_extra_stats {
   2.566 +	unsigned long early_rx;
   2.567 +	unsigned long tx_buf_mapped;
   2.568 +	unsigned long tx_timeouts;
   2.569 +	unsigned long rx_lost_in_ring;
   2.570 +};
   2.571 +
   2.572 +struct rtl8139_private {
   2.573 +	void *mmio_addr;
   2.574 +	int drv_flags;
   2.575 +	struct pci_dev *pci_dev;
   2.576 +	struct net_device_stats stats;
   2.577 +	unsigned char *rx_ring;
   2.578 +	unsigned int cur_rx;	/* Index into the Rx buffer of next Rx pkt. */
   2.579 +	unsigned int tx_flag;
   2.580 +	unsigned long cur_tx;
   2.581 +	unsigned long dirty_tx;
   2.582 +	unsigned char *tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */
   2.583 +	unsigned char *tx_bufs;	/* Tx bounce buffer region. */
   2.584 +	dma_addr_t rx_ring_dma;
   2.585 +	dma_addr_t tx_bufs_dma;
   2.586 +	signed char phys[4];		/* MII device addresses. */
   2.587 +	char twistie, twist_row, twist_col;	/* Twister tune state. */
   2.588 +	unsigned int default_port:4;	/* Last dev->if_port value. */
   2.589 +	spinlock_t lock;
   2.590 +	chip_t chipset;
   2.591 +#if 0
   2.592 +	pid_t thr_pid;
   2.593 +	wait_queue_head_t thr_wait;
   2.594 +	struct completion thr_exited;
   2.595 +#else
   2.596 +	struct timer_list timer;
   2.597 +#endif
   2.598 +	u32 rx_config;
   2.599 +	struct rtl_extra_stats xstats;
   2.600 +	int time_to_die;
   2.601 +	struct mii_if_info mii;
   2.602 +	unsigned int regs_len;
   2.603 +};
   2.604 +
   2.605 +MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
   2.606 +MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
   2.607 +MODULE_LICENSE("GPL");
   2.608 +
   2.609 +MODULE_PARM (multicast_filter_limit, "i");
   2.610 +MODULE_PARM (max_interrupt_work, "i");
   2.611 +MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
   2.612 +MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
   2.613 +MODULE_PARM (debug, "i");
   2.614 +MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
   2.615 +MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
   2.616 +MODULE_PARM_DESC (max_interrupt_work, "8139too maximum events handled per interrupt");
   2.617 +MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
   2.618 +MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
   2.619 +
   2.620 +static int read_eeprom (void *ioaddr, int location, int addr_len);
   2.621 +static int rtl8139_open (struct net_device *dev);
   2.622 +static int mdio_read (struct net_device *dev, int phy_id, int location);
   2.623 +static void mdio_write (struct net_device *dev, int phy_id, int location,
   2.624 +			int val);
   2.625 +#if 0
   2.626 +static int rtl8139_thread (void *data);
   2.627 +#else
   2.628 +static void rtl8139_timer (unsigned long arg);
   2.629 +#endif
   2.630 +static void rtl8139_tx_timeout (struct net_device *dev);
   2.631 +static void rtl8139_init_ring (struct net_device *dev);
   2.632 +static int rtl8139_start_xmit (struct sk_buff *skb,
   2.633 +			       struct net_device *dev);
   2.634 +static void rtl8139_interrupt (int irq, void *dev_instance,
   2.635 +			       struct pt_regs *regs);
   2.636 +static int rtl8139_close (struct net_device *dev);
   2.637 +#if 0
   2.638 +static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
   2.639 +#endif
   2.640 +static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
   2.641 +static void rtl8139_set_rx_mode (struct net_device *dev);
   2.642 +static void __set_rx_mode (struct net_device *dev);
   2.643 +static void rtl8139_hw_start (struct net_device *dev);
   2.644 +
   2.645 +#ifdef USE_IO_OPS
   2.646 +
   2.647 +#define RTL_R8(reg)		inb (((unsigned long)ioaddr) + (reg))
   2.648 +#define RTL_R16(reg)		inw (((unsigned long)ioaddr) + (reg))
   2.649 +#define RTL_R32(reg)		((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
   2.650 +#define RTL_W8(reg, val8)	outb ((val8), ((unsigned long)ioaddr) + (reg))
   2.651 +#define RTL_W16(reg, val16)	outw ((val16), ((unsigned long)ioaddr) + (reg))
   2.652 +#define RTL_W32(reg, val32)	outl ((val32), ((unsigned long)ioaddr) + (reg))
   2.653 +#define RTL_W8_F		RTL_W8
   2.654 +#define RTL_W16_F		RTL_W16
   2.655 +#define RTL_W32_F		RTL_W32
   2.656 +#undef readb
   2.657 +#undef readw
   2.658 +#undef readl
   2.659 +#undef writeb
   2.660 +#undef writew
   2.661 +#undef writel
   2.662 +#define readb(addr) inb((unsigned long)(addr))
   2.663 +#define readw(addr) inw((unsigned long)(addr))
   2.664 +#define readl(addr) inl((unsigned long)(addr))
   2.665 +#define writeb(val,addr) outb((val),(unsigned long)(addr))
   2.666 +#define writew(val,addr) outw((val),(unsigned long)(addr))
   2.667 +#define writel(val,addr) outl((val),(unsigned long)(addr))
   2.668 +
   2.669 +#else
   2.670 +
   2.671 +/* write MMIO register, with flush */
   2.672 +/* Flush avoids rtl8139 bug w/ posted MMIO writes */
   2.673 +#define RTL_W8_F(reg, val8)	do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
   2.674 +#define RTL_W16_F(reg, val16)	do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
   2.675 +#define RTL_W32_F(reg, val32)	do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
   2.676 +
   2.677 +
   2.678 +#define MMIO_FLUSH_AUDIT_COMPLETE 1
   2.679 +#if MMIO_FLUSH_AUDIT_COMPLETE
   2.680 +
   2.681 +/* write MMIO register */
   2.682 +#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
   2.683 +#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
   2.684 +#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
   2.685 +
   2.686 +#else
   2.687 +
   2.688 +/* write MMIO register, then flush */
   2.689 +#define RTL_W8		RTL_W8_F
   2.690 +#define RTL_W16		RTL_W16_F
   2.691 +#define RTL_W32		RTL_W32_F
   2.692 +
   2.693 +#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
   2.694 +
   2.695 +/* read MMIO register */
   2.696 +#define RTL_R8(reg)		readb (ioaddr + (reg))
   2.697 +#define RTL_R16(reg)		readw (ioaddr + (reg))
   2.698 +#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
   2.699 +
   2.700 +#endif /* USE_IO_OPS */
   2.701 +
   2.702 +
   2.703 +static const u16 rtl8139_intr_mask =
   2.704 +	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
   2.705 +	TxErr | TxOK | RxErr | RxOK;
   2.706 +
   2.707 +static const unsigned int rtl8139_rx_config =
   2.708 +	RxCfgRcv32K | RxNoWrap |
   2.709 +	(RX_FIFO_THRESH << RxCfgFIFOShift) |
   2.710 +	(RX_DMA_BURST << RxCfgDMAShift);
   2.711 +
   2.712 +static const unsigned int rtl8139_tx_config =
   2.713 +	(TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
   2.714 +
   2.715 +static void __rtl8139_cleanup_dev (struct net_device *dev)
   2.716 +{
   2.717 +	struct rtl8139_private *tp;
   2.718 +	struct pci_dev *pdev;
   2.719 +
   2.720 +	assert (dev != NULL);
   2.721 +	assert (dev->priv != NULL);
   2.722 +
   2.723 +	tp = dev->priv;
   2.724 +	assert (tp->pci_dev != NULL);
   2.725 +	pdev = tp->pci_dev;
   2.726 +
   2.727 +#ifndef USE_IO_OPS
   2.728 +	if (tp->mmio_addr)
   2.729 +		iounmap (tp->mmio_addr);
   2.730 +#endif /* !USE_IO_OPS */
   2.731 +
   2.732 +	/* it's ok to call this even if we have no regions to free */
   2.733 +	pci_release_regions (pdev);
   2.734 +
   2.735 +#ifndef RTL8139_NDEBUG
   2.736 +	/* poison memory before freeing */
   2.737 +	memset (dev, 0xBC,
   2.738 +		sizeof (struct net_device) +
   2.739 +		sizeof (struct rtl8139_private));
   2.740 +#endif /* RTL8139_NDEBUG */
   2.741 +
   2.742 +	kfree (dev);
   2.743 +
   2.744 +	pci_set_drvdata (pdev, NULL);
   2.745 +}
   2.746 +
   2.747 +
   2.748 +static void rtl8139_chip_reset (void *ioaddr)
   2.749 +{
   2.750 +	int i;
   2.751 +
   2.752 +	/* Soft reset the chip. */
   2.753 +	RTL_W8 (ChipCmd, CmdReset);
   2.754 +
   2.755 +	/* Check that the chip has finished the reset. */
   2.756 +	for (i = 1000; i > 0; i--) {
   2.757 +		barrier();
   2.758 +		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
   2.759 +			break;
   2.760 +		udelay (10);
   2.761 +	}
   2.762 +}
   2.763 +
   2.764 +
   2.765 +static int __devinit rtl8139_init_board (struct pci_dev *pdev,
   2.766 +					 struct net_device **dev_out)
   2.767 +{
   2.768 +	void *ioaddr;
   2.769 +	struct net_device *dev;
   2.770 +	struct rtl8139_private *tp;
   2.771 +	u8 tmp8;
   2.772 +	int rc;
   2.773 +	unsigned int i;
   2.774 +	u32 pio_start, pio_end, pio_flags, pio_len;
   2.775 +	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
   2.776 +	u32 tmp;
   2.777 +
   2.778 +	assert (pdev != NULL);
   2.779 +
   2.780 +	*dev_out = NULL;
   2.781 +
   2.782 +	/* dev and dev->priv zeroed in alloc_etherdev */
   2.783 +	dev = alloc_etherdev (sizeof (*tp));
   2.784 +	if (dev == NULL) {
   2.785 +		printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pdev->slot_name);
   2.786 +		return -ENOMEM;
   2.787 +	}
   2.788 +	SET_MODULE_OWNER(dev);
   2.789 +	tp = dev->priv;
   2.790 +	tp->pci_dev = pdev;
   2.791 +
   2.792 +	/* enable device (incl. PCI PM wakeup and hotplug setup) */
   2.793 +	rc = pci_enable_device (pdev);
   2.794 +	if (rc)
   2.795 +		goto err_out;
   2.796 +
   2.797 +	pio_start = pci_resource_start (pdev, 0);
   2.798 +	pio_end = pci_resource_end (pdev, 0);
   2.799 +	pio_flags = pci_resource_flags (pdev, 0);
   2.800 +	pio_len = pci_resource_len (pdev, 0);
   2.801 +
   2.802 +	mmio_start = pci_resource_start (pdev, 1);
   2.803 +	mmio_end = pci_resource_end (pdev, 1);
   2.804 +	mmio_flags = pci_resource_flags (pdev, 1);
   2.805 +	mmio_len = pci_resource_len (pdev, 1);
   2.806 +
   2.807 +	/* set this immediately, we need to know before
   2.808 +	 * we talk to the chip directly */
   2.809 +	DPRINTK("PIO region size == 0x%02X\n", pio_len);
   2.810 +	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
   2.811 +
   2.812 +#ifdef USE_IO_OPS
   2.813 +	/* make sure PCI base addr 0 is PIO */
   2.814 +	if (!(pio_flags & IORESOURCE_IO)) {
   2.815 +		printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pdev->slot_name);
   2.816 +		rc = -ENODEV;
   2.817 +		goto err_out;
   2.818 +	}
   2.819 +	/* check for weird/broken PCI region reporting */
   2.820 +	if (pio_len < RTL_MIN_IO_SIZE) {
   2.821 +		printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pdev->slot_name);
   2.822 +		rc = -ENODEV;
   2.823 +		goto err_out;
   2.824 +	}
   2.825 +#else
   2.826 +	/* make sure PCI base addr 1 is MMIO */
   2.827 +	if (!(mmio_flags & IORESOURCE_MEM)) {
   2.828 +		printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pdev->slot_name);
   2.829 +		rc = -ENODEV;
   2.830 +		goto err_out;
   2.831 +	}
   2.832 +	if (mmio_len < RTL_MIN_IO_SIZE) {
   2.833 +		printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pdev->slot_name);
   2.834 +		rc = -ENODEV;
   2.835 +		goto err_out;
   2.836 +	}
   2.837 +#endif
   2.838 +
   2.839 +	rc = pci_request_regions (pdev, "8139too");
   2.840 +	if (rc)
   2.841 +		goto err_out;
   2.842 +
   2.843 +	/* enable PCI bus-mastering */
   2.844 +	pci_set_master (pdev);
   2.845 +
   2.846 +#ifdef USE_IO_OPS
   2.847 +	ioaddr = (void *) pio_start;
   2.848 +	dev->base_addr = pio_start;
   2.849 +	tp->mmio_addr = ioaddr;
   2.850 +	tp->regs_len = pio_len;
   2.851 +#else
   2.852 +	/* ioremap MMIO region */
   2.853 +	ioaddr = ioremap (mmio_start, mmio_len);
   2.854 +	if (ioaddr == NULL) {
   2.855 +		printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pdev->slot_name);
   2.856 +		rc = -EIO;
   2.857 +		goto err_out;
   2.858 +	}
   2.859 +	dev->base_addr = (long) ioaddr;
   2.860 +	tp->mmio_addr = ioaddr;
   2.861 +	tp->regs_len = mmio_len;
   2.862 +#endif /* USE_IO_OPS */
   2.863 +
   2.864 +	/* Bring old chips out of low-power mode. */
   2.865 +	RTL_W8 (HltClk, 'R');
   2.866 +
   2.867 +	/* check for missing/broken hardware */
   2.868 +	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
   2.869 +		printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
   2.870 +			pdev->slot_name);
   2.871 +		rc = -EIO;
   2.872 +		goto err_out;
   2.873 +	}
   2.874 +
   2.875 +	/* identify chip attached to board */
   2.876 +	tmp = RTL_R8 (ChipVersion);
   2.877 +	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
   2.878 +		if (tmp == rtl_chip_info[i].version) {
   2.879 +			tp->chipset = i;
   2.880 +			goto match;
   2.881 +		}
   2.882 +
   2.883 +	/* if unknown chip, assume array element #0, original RTL-8139 in this case */
   2.884 +	printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
   2.885 +		pdev->slot_name);
   2.886 +	printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pdev->slot_name, RTL_R32 (TxConfig));
   2.887 +	tp->chipset = 0;
   2.888 +
   2.889 +match:
   2.890 +	DPRINTK ("chipset id (%d) == index %d, '%s'\n",
   2.891 +		tmp,
   2.892 +		tp->chipset,
   2.893 +		rtl_chip_info[tp->chipset].name);
   2.894 +
   2.895 +	if (tp->chipset >= CH_8139B) {
   2.896 +		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
   2.897 +		DPRINTK("PCI PM wakeup\n");
   2.898 +		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
   2.899 +		    (tmp8 & LWAKE))
   2.900 +			new_tmp8 &= ~LWAKE;
   2.901 +		new_tmp8 |= Cfg1_PM_Enable;
   2.902 +		if (new_tmp8 != tmp8) {
   2.903 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
   2.904 +			RTL_W8 (Config1, tmp8);
   2.905 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
   2.906 +		}
   2.907 +		if (rtl_chip_info[tp->chipset].flags & HasLWake) {
   2.908 +			tmp8 = RTL_R8 (Config4);
   2.909 +			if (tmp8 & LWPTN)
   2.910 +				RTL_W8 (Config4, tmp8 & ~LWPTN);
   2.911 +		}
   2.912 +	} else {
   2.913 +		DPRINTK("Old chip wakeup\n");
   2.914 +		tmp8 = RTL_R8 (Config1);
   2.915 +		tmp8 &= ~(SLEEP | PWRDN);
   2.916 +		RTL_W8 (Config1, tmp8);
   2.917 +	}
   2.918 +
   2.919 +	rtl8139_chip_reset (ioaddr);
   2.920 +
   2.921 +	*dev_out = dev;
   2.922 +	return 0;
   2.923 +
   2.924 +err_out:
   2.925 +	__rtl8139_cleanup_dev (dev);
   2.926 +	return rc;
   2.927 +}
   2.928 +
   2.929 +
   2.930 +static int __devinit rtl8139_init_one (struct pci_dev *pdev,
   2.931 +				       const struct pci_device_id *ent)
   2.932 +{
   2.933 +	struct net_device *dev = NULL;
   2.934 +	struct rtl8139_private *tp;
   2.935 +	int i, addr_len, option;
   2.936 +	void *ioaddr;
   2.937 +	static int board_idx = -1;
   2.938 +	u8 pci_rev;
   2.939 +
   2.940 +	assert (pdev != NULL);
   2.941 +	assert (ent != NULL);
   2.942 +
   2.943 +	board_idx++;
   2.944 +
   2.945 +	/* when we're built into the kernel, the driver version message
   2.946 +	 * is only printed if at least one 8139 board has been found
   2.947 +	 */
   2.948 +#ifndef MODULE
   2.949 +	{
   2.950 +		static int printed_version;
   2.951 +		if (!printed_version++)
   2.952 +			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
   2.953 +	}
   2.954 +#endif
   2.955 +
   2.956 +	pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
   2.957 +
   2.958 +	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
   2.959 +	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
   2.960 +		printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
   2.961 +		       pdev->slot_name, pdev->vendor, pdev->device, pci_rev);
   2.962 +		printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
   2.963 +	}
   2.964 +
   2.965 +	i = rtl8139_init_board (pdev, &dev);
   2.966 +	if (i < 0)
   2.967 +		return i;
   2.968 +
   2.969 +	tp = dev->priv;
   2.970 +	ioaddr = tp->mmio_addr;
   2.971 +
   2.972 +	assert (ioaddr != NULL);
   2.973 +	assert (dev != NULL);
   2.974 +	assert (tp != NULL);
   2.975 +
   2.976 +	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
   2.977 +	for (i = 0; i < 3; i++)
   2.978 +		((u16 *) (dev->dev_addr))[i] =
   2.979 +		    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
   2.980 +
   2.981 +	/* The Rtl8139-specific entries in the device structure. */
   2.982 +	dev->open = rtl8139_open;
   2.983 +	dev->hard_start_xmit = rtl8139_start_xmit;
   2.984 +	dev->stop = rtl8139_close;
   2.985 +	dev->get_stats = rtl8139_get_stats;
   2.986 +	dev->set_multicast_list = rtl8139_set_rx_mode;
   2.987 +#if 0
   2.988 +	dev->do_ioctl = netdev_ioctl;
   2.989 +#endif
   2.990 +	dev->tx_timeout = rtl8139_tx_timeout;
   2.991 +	dev->watchdog_timeo = TX_TIMEOUT;
   2.992 +
   2.993 +	/* note: the hardware is not capable of sg/csum/highdma, however
   2.994 +	 * through the use of skb_copy_and_csum_dev we enable these
   2.995 +	 * features
   2.996 +	 */
   2.997 +	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
   2.998 +
   2.999 +	dev->irq = pdev->irq;
  2.1000 +
  2.1001 +	/* dev->priv/tp zeroed and aligned in init_etherdev */
  2.1002 +	tp = dev->priv;
  2.1003 +
  2.1004 +	/* note: tp->chipset set in rtl8139_init_board */
  2.1005 +	tp->drv_flags = board_info[ent->driver_data].hw_flags;
  2.1006 +	tp->mmio_addr = ioaddr;
  2.1007 +	spin_lock_init (&tp->lock);
  2.1008 +#if 0
  2.1009 +	init_waitqueue_head (&tp->thr_wait);
  2.1010 +	init_completion (&tp->thr_exited);
  2.1011 +#endif
  2.1012 +	tp->mii.dev = dev;
  2.1013 +	tp->mii.mdio_read = mdio_read;
  2.1014 +	tp->mii.mdio_write = mdio_write;
  2.1015 +	tp->mii.phy_id_mask = 0x3f;
  2.1016 +	tp->mii.reg_num_mask = 0x1f;
  2.1017 +
  2.1018 +	/* dev is fully set up and ready to use now */
  2.1019 +	DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
  2.1020 +	i = register_netdev (dev);
  2.1021 +	if (i) goto err_out;
  2.1022 +
  2.1023 +	pci_set_drvdata (pdev, dev);
  2.1024 +
  2.1025 +	printk (KERN_INFO "%s: %s at 0x%lx, "
  2.1026 +		"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
  2.1027 +		"IRQ %d\n",
  2.1028 +		dev->name,
  2.1029 +		board_info[ent->driver_data].name,
  2.1030 +		dev->base_addr,
  2.1031 +		dev->dev_addr[0], dev->dev_addr[1],
  2.1032 +		dev->dev_addr[2], dev->dev_addr[3],
  2.1033 +		dev->dev_addr[4], dev->dev_addr[5],
  2.1034 +		dev->irq);
  2.1035 +
  2.1036 +	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",
  2.1037 +		dev->name, rtl_chip_info[tp->chipset].name);
  2.1038 +
  2.1039 +	/* Find the connected MII xcvrs.
  2.1040 +	   Doing this in open() would allow detecting external xcvrs later, but
  2.1041 +	   takes too much time. */
  2.1042 +#ifdef CONFIG_8139TOO_8129
  2.1043 +	if (tp->drv_flags & HAS_MII_XCVR) {
  2.1044 +		int phy, phy_idx = 0;
  2.1045 +		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
  2.1046 +			int mii_status = mdio_read(dev, phy, 1);
  2.1047 +			if (mii_status != 0xffff  &&  mii_status != 0x0000) {
  2.1048 +				u16 advertising = mdio_read(dev, phy, 4);
  2.1049 +				tp->phys[phy_idx++] = phy;
  2.1050 +				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
  2.1051 +					   "advertising %4.4x.\n",
  2.1052 +					   dev->name, phy, mii_status, advertising);
  2.1053 +			}
  2.1054 +		}
  2.1055 +		if (phy_idx == 0) {
  2.1056 +			printk(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "
  2.1057 +				   "transceiver.\n",
  2.1058 +				   dev->name);
  2.1059 +			tp->phys[0] = 32;
  2.1060 +		}
  2.1061 +	} else
  2.1062 +#endif
  2.1063 +		tp->phys[0] = 32;
  2.1064 +	tp->mii.phy_id = tp->phys[0];
  2.1065 +
  2.1066 +	/* The lower four bits are the media type. */
  2.1067 +	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
  2.1068 +	if (option > 0) {
  2.1069 +		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
  2.1070 +		tp->default_port = option & 0xFF;
  2.1071 +		if (tp->default_port)
  2.1072 +			tp->mii.force_media = 1;
  2.1073 +	}
  2.1074 +	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)
  2.1075 +		tp->mii.full_duplex = full_duplex[board_idx];
  2.1076 +	if (tp->mii.full_duplex) {
  2.1077 +		printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
  2.1078 +		/* Changing the MII-advertised media because might prevent
  2.1079 +		   re-connection. */
  2.1080 +		tp->mii.force_media = 1;
  2.1081 +	}
  2.1082 +	if (tp->default_port) {
  2.1083 +		printk(KERN_INFO "  Forcing %dMbps %s-duplex operation.\n",
  2.1084 +			   (option & 0x20 ? 100 : 10),
  2.1085 +			   (option & 0x10 ? "full" : "half"));
  2.1086 +		mdio_write(dev, tp->phys[0], 0,
  2.1087 +				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */
  2.1088 +				   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
  2.1089 +	}
  2.1090 +
  2.1091 +	/* Put the chip into low-power mode. */
  2.1092 +	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  2.1093 +		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
  2.1094 +
  2.1095 +        alert_slow_netdevice(dev, (char *)board_info[ent->driver_data].name);
  2.1096 +
  2.1097 +	return 0;
  2.1098 +
  2.1099 +err_out:
  2.1100 +	__rtl8139_cleanup_dev (dev);
  2.1101 +	return i;
  2.1102 +}
  2.1103 +
  2.1104 +
  2.1105 +static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
  2.1106 +{
  2.1107 +	struct net_device *dev = pci_get_drvdata (pdev);
  2.1108 +	struct rtl8139_private *np;
  2.1109 +
  2.1110 +	assert (dev != NULL);
  2.1111 +	np = dev->priv;
  2.1112 +	assert (np != NULL);
  2.1113 +
  2.1114 +	unregister_netdev (dev);
  2.1115 +
  2.1116 +	__rtl8139_cleanup_dev (dev);
  2.1117 +}
  2.1118 +
  2.1119 +
  2.1120 +/* Serial EEPROM section. */
  2.1121 +
  2.1122 +/*  EEPROM_Ctrl bits. */
  2.1123 +#define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
  2.1124 +#define EE_CS			0x08	/* EEPROM chip select. */
  2.1125 +#define EE_DATA_WRITE	0x02	/* EEPROM chip data in. */
  2.1126 +#define EE_WRITE_0		0x00
  2.1127 +#define EE_WRITE_1		0x02
  2.1128 +#define EE_DATA_READ	0x01	/* EEPROM chip data out. */
  2.1129 +#define EE_ENB			(0x80 | EE_CS)
  2.1130 +
  2.1131 +/* Delay between EEPROM clock transitions.
  2.1132 +   No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
  2.1133 + */
  2.1134 +
  2.1135 +#define eeprom_delay()	readl(ee_addr)
  2.1136 +
  2.1137 +/* The EEPROM commands include the alway-set leading bit. */
  2.1138 +#define EE_WRITE_CMD	(5)
  2.1139 +#define EE_READ_CMD		(6)
  2.1140 +#define EE_ERASE_CMD	(7)
  2.1141 +
  2.1142 +static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
  2.1143 +{
  2.1144 +	int i;
  2.1145 +	unsigned retval = 0;
  2.1146 +	void *ee_addr = ioaddr + Cfg9346;
  2.1147 +	int read_cmd = location | (EE_READ_CMD << addr_len);
  2.1148 +
  2.1149 +	writeb (EE_ENB & ~EE_CS, ee_addr);
  2.1150 +	writeb (EE_ENB, ee_addr);
  2.1151 +	eeprom_delay ();
  2.1152 +
  2.1153 +	/* Shift the read command bits out. */
  2.1154 +	for (i = 4 + addr_len; i >= 0; i--) {
  2.1155 +		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  2.1156 +		writeb (EE_ENB | dataval, ee_addr);
  2.1157 +		eeprom_delay ();
  2.1158 +		writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
  2.1159 +		eeprom_delay ();
  2.1160 +	}
  2.1161 +	writeb (EE_ENB, ee_addr);
  2.1162 +	eeprom_delay ();
  2.1163 +
  2.1164 +	for (i = 16; i > 0; i--) {
  2.1165 +		writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
  2.1166 +		eeprom_delay ();
  2.1167 +		retval =
  2.1168 +		    (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
  2.1169 +				     0);
  2.1170 +		writeb (EE_ENB, ee_addr);
  2.1171 +		eeprom_delay ();
  2.1172 +	}
  2.1173 +
  2.1174 +	/* Terminate the EEPROM access. */
  2.1175 +	writeb (~EE_CS, ee_addr);
  2.1176 +	eeprom_delay ();
  2.1177 +
  2.1178 +	return retval;
  2.1179 +}
  2.1180 +
  2.1181 +/* MII serial management: mostly bogus for now. */
  2.1182 +/* Read and write the MII management registers using software-generated
  2.1183 +   serial MDIO protocol.
  2.1184 +   The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
  2.1185 +   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
  2.1186 +   "overclocking" issues. */
  2.1187 +#define MDIO_DIR		0x80
  2.1188 +#define MDIO_DATA_OUT	0x04
  2.1189 +#define MDIO_DATA_IN	0x02
  2.1190 +#define MDIO_CLK		0x01
  2.1191 +#define MDIO_WRITE0 (MDIO_DIR)
  2.1192 +#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
  2.1193 +
  2.1194 +#define mdio_delay(mdio_addr)	readb(mdio_addr)
  2.1195 +
  2.1196 +
  2.1197 +static char mii_2_8139_map[8] = {
  2.1198 +	BasicModeCtrl,
  2.1199 +	BasicModeStatus,
  2.1200 +	0,
  2.1201 +	0,
  2.1202 +	NWayAdvert,
  2.1203 +	NWayLPAR,
  2.1204 +	NWayExpansion,
  2.1205 +	0
  2.1206 +};
  2.1207 +
  2.1208 +
  2.1209 +#ifdef CONFIG_8139TOO_8129
  2.1210 +/* Syncronize the MII management interface by shifting 32 one bits out. */
  2.1211 +static void mdio_sync (void *mdio_addr)
  2.1212 +{
  2.1213 +	int i;
  2.1214 +
  2.1215 +	for (i = 32; i >= 0; i--) {
  2.1216 +		writeb (MDIO_WRITE1, mdio_addr);
  2.1217 +		mdio_delay (mdio_addr);
  2.1218 +		writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
  2.1219 +		mdio_delay (mdio_addr);
  2.1220 +	}
  2.1221 +}
  2.1222 +#endif
  2.1223 +
  2.1224 +static int mdio_read (struct net_device *dev, int phy_id, int location)
  2.1225 +{
  2.1226 +	struct rtl8139_private *tp = dev->priv;
  2.1227 +	int retval = 0;
  2.1228 +#ifdef CONFIG_8139TOO_8129
  2.1229 +	void *mdio_addr = tp->mmio_addr + Config4;
  2.1230 +	int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
  2.1231 +	int i;
  2.1232 +#endif
  2.1233 +
  2.1234 +	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
  2.1235 +		return location < 8 && mii_2_8139_map[location] ?
  2.1236 +		    readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
  2.1237 +	}
  2.1238 +
  2.1239 +#ifdef CONFIG_8139TOO_8129
  2.1240 +	mdio_sync (mdio_addr);
  2.1241 +	/* Shift the read command bits out. */
  2.1242 +	for (i = 15; i >= 0; i--) {
  2.1243 +		int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
  2.1244 +
  2.1245 +		writeb (MDIO_DIR | dataval, mdio_addr);
  2.1246 +		mdio_delay (mdio_addr);
  2.1247 +		writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
  2.1248 +		mdio_delay (mdio_addr);
  2.1249 +	}
  2.1250 +
  2.1251 +	/* Read the two transition, 16 data, and wire-idle bits. */
  2.1252 +	for (i = 19; i > 0; i--) {
  2.1253 +		writeb (0, mdio_addr);
  2.1254 +		mdio_delay (mdio_addr);
  2.1255 +		retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
  2.1256 +		writeb (MDIO_CLK, mdio_addr);
  2.1257 +		mdio_delay (mdio_addr);
  2.1258 +	}
  2.1259 +#endif
  2.1260 +
  2.1261 +	return (retval >> 1) & 0xffff;
  2.1262 +}
  2.1263 +
  2.1264 +
  2.1265 +static void mdio_write (struct net_device *dev, int phy_id, int location,
  2.1266 +			int value)
  2.1267 +{
  2.1268 +	struct rtl8139_private *tp = dev->priv;
  2.1269 +#ifdef CONFIG_8139TOO_8129
  2.1270 +	void *mdio_addr = tp->mmio_addr + Config4;
  2.1271 +	int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
  2.1272 +	int i;
  2.1273 +#endif
  2.1274 +
  2.1275 +	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
  2.1276 +		void *ioaddr = tp->mmio_addr;
  2.1277 +		if (location == 0) {
  2.1278 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.1279 +			RTL_W16 (BasicModeCtrl, value);
  2.1280 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1281 +		} else if (location < 8 && mii_2_8139_map[location])
  2.1282 +			RTL_W16 (mii_2_8139_map[location], value);
  2.1283 +		return;
  2.1284 +	}
  2.1285 +
  2.1286 +#ifdef CONFIG_8139TOO_8129
  2.1287 +	mdio_sync (mdio_addr);
  2.1288 +
  2.1289 +	/* Shift the command bits out. */
  2.1290 +	for (i = 31; i >= 0; i--) {
  2.1291 +		int dataval =
  2.1292 +		    (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
  2.1293 +		writeb (dataval, mdio_addr);
  2.1294 +		mdio_delay (mdio_addr);
  2.1295 +		writeb (dataval | MDIO_CLK, mdio_addr);
  2.1296 +		mdio_delay (mdio_addr);
  2.1297 +	}
  2.1298 +	/* Clear out extra bits. */
  2.1299 +	for (i = 2; i > 0; i--) {
  2.1300 +		writeb (0, mdio_addr);
  2.1301 +		mdio_delay (mdio_addr);
  2.1302 +		writeb (MDIO_CLK, mdio_addr);
  2.1303 +		mdio_delay (mdio_addr);
  2.1304 +	}
  2.1305 +#endif
  2.1306 +}
  2.1307 +
  2.1308 +
  2.1309 +static int rtl8139_open (struct net_device *dev)
  2.1310 +{
  2.1311 +	struct rtl8139_private *tp = dev->priv;
  2.1312 +	int retval;
  2.1313 +#ifdef RTL8139_DEBUG
  2.1314 +	void *ioaddr = tp->mmio_addr;
  2.1315 +#endif
  2.1316 +
  2.1317 +	retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
  2.1318 +	if (retval)
  2.1319 +		return retval;
  2.1320 +
  2.1321 +	tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  2.1322 +					   &tp->tx_bufs_dma);
  2.1323 +	tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  2.1324 +					   &tp->rx_ring_dma);
  2.1325 +	if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
  2.1326 +		free_irq(dev->irq, dev);
  2.1327 +
  2.1328 +		if (tp->tx_bufs)
  2.1329 +			pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  2.1330 +					    tp->tx_bufs, tp->tx_bufs_dma);
  2.1331 +		if (tp->rx_ring)
  2.1332 +			pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  2.1333 +					    tp->rx_ring, tp->rx_ring_dma);
  2.1334 +
  2.1335 +		return -ENOMEM;
  2.1336 +
  2.1337 +	}
  2.1338 +
  2.1339 +	tp->mii.full_duplex = tp->mii.force_media;
  2.1340 +	tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
  2.1341 +	tp->twistie = (tp->chipset == CH_8139_K) ? 1 : 0;
  2.1342 +	tp->time_to_die = 0;
  2.1343 +
  2.1344 +	rtl8139_init_ring (dev);
  2.1345 +	rtl8139_hw_start (dev);
  2.1346 +
  2.1347 +	DPRINTK ("%s: rtl8139_open() ioaddr %#lx IRQ %d"
  2.1348 +			" GP Pins %2.2x %s-duplex.\n",
  2.1349 +			dev->name, pci_resource_start (tp->pci_dev, 1),
  2.1350 +			dev->irq, RTL_R8 (MediaStatus),
  2.1351 +			tp->mii.full_duplex ? "full" : "half");
  2.1352 +
  2.1353 +#if 0
  2.1354 +	tp->thr_pid = kernel_thread (rtl8139_thread, dev, CLONE_FS | CLONE_FILES);
  2.1355 +	if (tp->thr_pid < 0)
  2.1356 +		printk (KERN_WARNING "%s: unable to start kernel thread\n",
  2.1357 +			dev->name);
  2.1358 +#else
  2.1359 +	init_timer(&tp->timer);
  2.1360 +	tp->timer.expires = jiffies + next_tick;
  2.1361 +	tp->timer.data = (unsigned long)dev;
  2.1362 +	tp->timer.function = rtl8139_timer;
  2.1363 +	add_timer(&tp->timer);
  2.1364 +#endif
  2.1365 +
  2.1366 +	return 0;
  2.1367 +}
  2.1368 +
  2.1369 +
  2.1370 +static void rtl_check_media (struct net_device *dev)
  2.1371 +{
  2.1372 +	struct rtl8139_private *tp = dev->priv;
  2.1373 +
  2.1374 +	if (tp->phys[0] >= 0) {
  2.1375 +		u16 mii_lpa = mdio_read(dev, tp->phys[0], MII_LPA);
  2.1376 +		if (mii_lpa == 0xffff)
  2.1377 +			;					/* Not there */
  2.1378 +		else if ((mii_lpa & LPA_100FULL) == LPA_100FULL
  2.1379 +				 || (mii_lpa & 0x00C0) == LPA_10FULL)
  2.1380 +			tp->mii.full_duplex = 1;
  2.1381 +
  2.1382 +		printk (KERN_INFO"%s: Setting %s%s-duplex based on"
  2.1383 +				" auto-negotiated partner ability %4.4x.\n",
  2.1384 +		        dev->name, mii_lpa == 0 ? "" :
  2.1385 +				(mii_lpa & 0x0180) ? "100mbps " : "10mbps ",
  2.1386 +			tp->mii.full_duplex ? "full" : "half", mii_lpa);
  2.1387 +	}
  2.1388 +}
  2.1389 +
  2.1390 +/* Start the hardware at open or resume. */
  2.1391 +static void rtl8139_hw_start (struct net_device *dev)
  2.1392 +{
  2.1393 +	struct rtl8139_private *tp = dev->priv;
  2.1394 +	void *ioaddr = tp->mmio_addr;
  2.1395 +	u32 i;
  2.1396 +	u8 tmp;
  2.1397 +
  2.1398 +	/* Bring old chips out of low-power mode. */
  2.1399 +	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  2.1400 +		RTL_W8 (HltClk, 'R');
  2.1401 +
  2.1402 +	rtl8139_chip_reset (ioaddr);
  2.1403 +
  2.1404 +	/* unlock Config[01234] and BMCR register writes */
  2.1405 +	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
  2.1406 +	/* Restore our idea of the MAC address. */
  2.1407 +	RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
  2.1408 +	RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
  2.1409 +
  2.1410 +	/* Must enable Tx/Rx before setting transfer thresholds! */
  2.1411 +	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1412 +
  2.1413 +	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
  2.1414 +	RTL_W32 (RxConfig, tp->rx_config);
  2.1415 +
  2.1416 +	/* Check this value: the documentation for IFG contradicts ifself. */
  2.1417 +	RTL_W32 (TxConfig, rtl8139_tx_config);
  2.1418 +
  2.1419 +	tp->cur_rx = 0;
  2.1420 +
  2.1421 +	rtl_check_media (dev);
  2.1422 +
  2.1423 +	if (tp->chipset >= CH_8139B) {
  2.1424 +		/* Disable magic packet scanning, which is enabled
  2.1425 +		 * when PM is enabled in Config1.  It can be reenabled
  2.1426 +		 * via ETHTOOL_SWOL if desired.  */
  2.1427 +		RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
  2.1428 +	}
  2.1429 +
  2.1430 +	DPRINTK("init buffer addresses\n");
  2.1431 +
  2.1432 +	/* Lock Config[01234] and BMCR register writes */
  2.1433 +	RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1434 +
  2.1435 +	/* init Rx ring buffer DMA address */
  2.1436 +	RTL_W32_F (RxBuf, tp->rx_ring_dma);
  2.1437 +
  2.1438 +	/* init Tx buffer DMA addresses */
  2.1439 +	for (i = 0; i < NUM_TX_DESC; i++)
  2.1440 +		RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
  2.1441 +
  2.1442 +	RTL_W32 (RxMissed, 0);
  2.1443 +
  2.1444 +	rtl8139_set_rx_mode (dev);
  2.1445 +
  2.1446 +	/* no early-rx interrupts */
  2.1447 +	RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
  2.1448 +
  2.1449 +	/* make sure RxTx has started */
  2.1450 +	tmp = RTL_R8 (ChipCmd);
  2.1451 +	if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
  2.1452 +		RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1453 +
  2.1454 +	/* Enable all known interrupts by setting the interrupt mask. */
  2.1455 +	RTL_W16 (IntrMask, rtl8139_intr_mask);
  2.1456 +
  2.1457 +	netif_start_queue (dev);
  2.1458 +}
  2.1459 +
  2.1460 +
  2.1461 +/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
  2.1462 +static void rtl8139_init_ring (struct net_device *dev)
  2.1463 +{
  2.1464 +	struct rtl8139_private *tp = dev->priv;
  2.1465 +	int i;
  2.1466 +
  2.1467 +	tp->cur_rx = 0;
  2.1468 +	tp->cur_tx = 0;
  2.1469 +	tp->dirty_tx = 0;
  2.1470 +
  2.1471 +	for (i = 0; i < NUM_TX_DESC; i++)
  2.1472 +		tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
  2.1473 +}
  2.1474 +
  2.1475 +
  2.1476 +#ifndef CONFIG_8139TOO_TUNE_TWISTER
  2.1477 +static inline void rtl8139_tune_twister (struct net_device *dev,
  2.1478 +				  struct rtl8139_private *tp) {}
  2.1479 +#else
  2.1480 +static void rtl8139_tune_twister (struct net_device *dev,
  2.1481 +				  struct rtl8139_private *tp)
  2.1482 +{
  2.1483 +	int linkcase;
  2.1484 +	void *ioaddr = tp->mmio_addr;
  2.1485 +
  2.1486 +	/* This is a complicated state machine to configure the "twister" for
  2.1487 +	   impedance/echos based on the cable length.
  2.1488 +	   All of this is magic and undocumented.
  2.1489 +	 */
  2.1490 +	switch (tp->twistie) {
  2.1491 +	case 1:
  2.1492 +		if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
  2.1493 +			/* We have link beat, let us tune the twister. */
  2.1494 +			RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
  2.1495 +			tp->twistie = 2;	/* Change to state 2. */
  2.1496 +			next_tick = HZ / 10;
  2.1497 +		} else {
  2.1498 +			/* Just put in some reasonable defaults for when beat returns. */
  2.1499 +			RTL_W16 (CSCR, CSCR_LinkDownCmd);
  2.1500 +			RTL_W32 (FIFOTMS, 0x20);	/* Turn on cable test mode. */
  2.1501 +			RTL_W32 (PARA78, PARA78_default);
  2.1502 +			RTL_W32 (PARA7c, PARA7c_default);
  2.1503 +			tp->twistie = 0;	/* Bail from future actions. */
  2.1504 +		}
  2.1505 +		break;
  2.1506 +	case 2:
  2.1507 +		/* Read how long it took to hear the echo. */
  2.1508 +		linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
  2.1509 +		if (linkcase == 0x7000)
  2.1510 +			tp->twist_row = 3;
  2.1511 +		else if (linkcase == 0x3000)
  2.1512 +			tp->twist_row = 2;
  2.1513 +		else if (linkcase == 0x1000)
  2.1514 +			tp->twist_row = 1;
  2.1515 +		else
  2.1516 +			tp->twist_row = 0;
  2.1517 +		tp->twist_col = 0;
  2.1518 +		tp->twistie = 3;	/* Change to state 2. */
  2.1519 +		next_tick = HZ / 10;
  2.1520 +		break;
  2.1521 +	case 3:
  2.1522 +		/* Put out four tuning parameters, one per 100msec. */
  2.1523 +		if (tp->twist_col == 0)
  2.1524 +			RTL_W16 (FIFOTMS, 0);
  2.1525 +		RTL_W32 (PARA7c, param[(int) tp->twist_row]
  2.1526 +			 [(int) tp->twist_col]);
  2.1527 +		next_tick = HZ / 10;
  2.1528 +		if (++tp->twist_col >= 4) {
  2.1529 +			/* For short cables we are done.
  2.1530 +			   For long cables (row == 3) check for mistune. */
  2.1531 +			tp->twistie =
  2.1532 +			    (tp->twist_row == 3) ? 4 : 0;
  2.1533 +		}
  2.1534 +		break;
  2.1535 +	case 4:
  2.1536 +		/* Special case for long cables: check for mistune. */
  2.1537 +		if ((RTL_R16 (CSCR) &
  2.1538 +		     CSCR_LinkStatusBits) == 0x7000) {
  2.1539 +			tp->twistie = 0;
  2.1540 +			break;
  2.1541 +		} else {
  2.1542 +			RTL_W32 (PARA7c, 0xfb38de03);
  2.1543 +			tp->twistie = 5;
  2.1544 +			next_tick = HZ / 10;
  2.1545 +		}
  2.1546 +		break;
  2.1547 +	case 5:
  2.1548 +		/* Retune for shorter cable (column 2). */
  2.1549 +		RTL_W32 (FIFOTMS, 0x20);
  2.1550 +		RTL_W32 (PARA78, PARA78_default);
  2.1551 +		RTL_W32 (PARA7c, PARA7c_default);
  2.1552 +		RTL_W32 (FIFOTMS, 0x00);
  2.1553 +		tp->twist_row = 2;
  2.1554 +		tp->twist_col = 0;
  2.1555 +		tp->twistie = 3;
  2.1556 +		next_tick = HZ / 10;
  2.1557 +		break;
  2.1558 +
  2.1559 +	default:
  2.1560 +		/* do nothing */
  2.1561 +		break;
  2.1562 +	}
  2.1563 +}
  2.1564 +#endif /* CONFIG_8139TOO_TUNE_TWISTER */
  2.1565 +
  2.1566 +
  2.1567 +static inline void rtl8139_thread_iter (struct net_device *dev,
  2.1568 +				 struct rtl8139_private *tp,
  2.1569 +				 void *ioaddr)
  2.1570 +{
  2.1571 +	int mii_lpa;
  2.1572 +
  2.1573 +	mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
  2.1574 +
  2.1575 +	if (!tp->mii.force_media && mii_lpa != 0xffff) {
  2.1576 +		int duplex = (mii_lpa & LPA_100FULL)
  2.1577 +		    || (mii_lpa & 0x01C0) == 0x0040;
  2.1578 +		if (tp->mii.full_duplex != duplex) {
  2.1579 +			tp->mii.full_duplex = duplex;
  2.1580 +
  2.1581 +			if (mii_lpa) {
  2.1582 +				printk (KERN_INFO
  2.1583 +					"%s: Setting %s-duplex based on MII #%d link"
  2.1584 +					" partner ability of %4.4x.\n",
  2.1585 +					dev->name,
  2.1586 +					tp->mii.full_duplex ? "full" : "half",
  2.1587 +					tp->phys[0], mii_lpa);
  2.1588 +			} else {
  2.1589 +				printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
  2.1590 +				       dev->name);
  2.1591 +			}
  2.1592 +#if 0
  2.1593 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.1594 +			RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
  2.1595 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1596 +#endif
  2.1597 +		}
  2.1598 +	}
  2.1599 +
  2.1600 +	next_tick = HZ * 60;
  2.1601 +
  2.1602 +	rtl8139_tune_twister (dev, tp);
  2.1603 +
  2.1604 +	DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
  2.1605 +		 dev->name, RTL_R16 (NWayLPAR));
  2.1606 +	DPRINTK ("%s:  Other registers are IntMask %4.4x IntStatus %4.4x\n",
  2.1607 +		 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
  2.1608 +	DPRINTK ("%s:  Chip config %2.2x %2.2x.\n",
  2.1609 +		 dev->name, RTL_R8 (Config0),
  2.1610 +		 RTL_R8 (Config1));
  2.1611 +}
  2.1612 +
  2.1613 +
  2.1614 +#if 0
  2.1615 +static int rtl8139_thread (void *data)
  2.1616 +{
  2.1617 +	struct net_device *dev = data;
  2.1618 +	struct rtl8139_private *tp = dev->priv;
  2.1619 +	unsigned long timeout;
  2.1620 +
  2.1621 +	daemonize ();
  2.1622 +	reparent_to_init();
  2.1623 +	spin_lock_irq(&current->sigmask_lock);
  2.1624 +	sigemptyset(&current->blocked);
  2.1625 +	recalc_sigpending(current);
  2.1626 +	spin_unlock_irq(&current->sigmask_lock);
  2.1627 +
  2.1628 +	strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
  2.1629 +	current->comm[sizeof(current->comm) - 1] = '\0';
  2.1630 +
  2.1631 +	while (1) {
  2.1632 +		timeout = next_tick;
  2.1633 +		do {
  2.1634 +			timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
  2.1635 +		} while (!signal_pending (current) && (timeout > 0));
  2.1636 +
  2.1637 +		if (signal_pending (current)) {
  2.1638 +			spin_lock_irq(&current->sigmask_lock);
  2.1639 +			flush_signals(current);
  2.1640 +			spin_unlock_irq(&current->sigmask_lock);
  2.1641 +		}
  2.1642 +
  2.1643 +		if (tp->time_to_die)
  2.1644 +			break;
  2.1645 +
  2.1646 +		rtnl_lock ();
  2.1647 +		rtl8139_thread_iter (dev, tp, tp->mmio_addr);
  2.1648 +		rtnl_unlock ();
  2.1649 +	}
  2.1650 +
  2.1651 +	complete_and_exit (&tp->thr_exited, 0);
  2.1652 +}
  2.1653 +#else
  2.1654 +static void rtl8139_timer(unsigned long arg)
  2.1655 +{
  2.1656 +	struct net_device *dev = (struct net_device *)arg;
  2.1657 +	struct rtl8139_private *tp = dev->priv;
  2.1658 +	rtl8139_thread_iter (dev, tp, tp->mmio_addr);
  2.1659 +	mod_timer(&tp->timer, jiffies + next_tick);
  2.1660 +}
  2.1661 +#endif
  2.1662 +
  2.1663 +
  2.1664 +static void rtl8139_tx_clear (struct rtl8139_private *tp)
  2.1665 +{
  2.1666 +	tp->cur_tx = 0;
  2.1667 +	tp->dirty_tx = 0;
  2.1668 +
  2.1669 +	/* XXX account for unsent Tx packets in tp->stats.tx_dropped */
  2.1670 +}
  2.1671 +
  2.1672 +
  2.1673 +static void rtl8139_tx_timeout (struct net_device *dev)
  2.1674 +{
  2.1675 +	struct rtl8139_private *tp = dev->priv;
  2.1676 +	void *ioaddr = tp->mmio_addr;
  2.1677 +	int i;
  2.1678 +	u8 tmp8;
  2.1679 +	unsigned long flags;
  2.1680 +
  2.1681 +	DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
  2.1682 +		 "media %2.2x.\n", dev->name,
  2.1683 +		 RTL_R8 (ChipCmd),
  2.1684 +		 RTL_R16 (IntrStatus),
  2.1685 +		 RTL_R8 (MediaStatus));
  2.1686 +
  2.1687 +	tp->xstats.tx_timeouts++;
  2.1688 +
  2.1689 +	/* disable Tx ASAP, if not already */
  2.1690 +	tmp8 = RTL_R8 (ChipCmd);
  2.1691 +	if (tmp8 & CmdTxEnb)
  2.1692 +		RTL_W8 (ChipCmd, CmdRxEnb);
  2.1693 +
  2.1694 +	/* Disable interrupts by clearing the interrupt mask. */
  2.1695 +	RTL_W16 (IntrMask, 0x0000);
  2.1696 +
  2.1697 +	/* Emit info to figure out what went wrong. */
  2.1698 +	printk (KERN_DEBUG "%s: Tx queue start entry %ld  dirty entry %ld.\n",
  2.1699 +		dev->name, tp->cur_tx, tp->dirty_tx);
  2.1700 +	for (i = 0; i < NUM_TX_DESC; i++)
  2.1701 +		printk (KERN_DEBUG "%s:  Tx descriptor %d is %8.8lx.%s\n",
  2.1702 +			dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
  2.1703 +			i == tp->dirty_tx % NUM_TX_DESC ?
  2.1704 +				" (queue head)" : "");
  2.1705 +
  2.1706 +	/* Stop a shared interrupt from scavenging while we are. */
  2.1707 +	spin_lock_irqsave (&tp->lock, flags);
  2.1708 +	rtl8139_tx_clear (tp);
  2.1709 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.1710 +
  2.1711 +	/* ...and finally, reset everything */
  2.1712 +	rtl8139_hw_start (dev);
  2.1713 +
  2.1714 +	netif_wake_queue (dev);
  2.1715 +}
  2.1716 +
  2.1717 +
  2.1718 +static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
  2.1719 +{
  2.1720 +	struct rtl8139_private *tp = dev->priv;
  2.1721 +	void *ioaddr = tp->mmio_addr;
  2.1722 +	unsigned int entry;
  2.1723 +	unsigned int len = skb->len;
  2.1724 +
  2.1725 +	/* Calculate the next Tx descriptor entry. */
  2.1726 +	entry = tp->cur_tx % NUM_TX_DESC;
  2.1727 +
  2.1728 +	if (likely(len < TX_BUF_SIZE)) {
  2.1729 +		if(len < ETH_ZLEN)
  2.1730 +			memset(tp->tx_buf[entry], 0, ETH_ZLEN);
  2.1731 +#if 0
  2.1732 +		skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
  2.1733 +#else
  2.1734 +		skb_copy_bits(skb, 0, tp->tx_buf[entry], skb->len);
  2.1735 +#endif
  2.1736 +		dev_kfree_skb(skb);
  2.1737 +	} else {
  2.1738 +		dev_kfree_skb(skb);
  2.1739 +		tp->stats.tx_dropped++;
  2.1740 +		return 0;
  2.1741 +	}
  2.1742 +
  2.1743 +	/* Note: the chip doesn't have auto-pad! */
  2.1744 +	spin_lock_irq(&tp->lock);
  2.1745 +	RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
  2.1746 +		   tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
  2.1747 +
  2.1748 +	dev->trans_start = jiffies;
  2.1749 +
  2.1750 +	tp->cur_tx++;
  2.1751 +	wmb();
  2.1752 +
  2.1753 +	if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
  2.1754 +		netif_stop_queue (dev);
  2.1755 +	spin_unlock_irq(&tp->lock);
  2.1756 +
  2.1757 +	DPRINTK ("%s: Queued Tx packet size %u to slot %d.\n",
  2.1758 +		 dev->name, len, entry);
  2.1759 +
  2.1760 +	return 0;
  2.1761 +}
  2.1762 +
  2.1763 +
  2.1764 +static void rtl8139_tx_interrupt (struct net_device *dev,
  2.1765 +				  struct rtl8139_private *tp,
  2.1766 +				  void *ioaddr)
  2.1767 +{
  2.1768 +	unsigned long dirty_tx, tx_left;
  2.1769 +
  2.1770 +	assert (dev != NULL);
  2.1771 +	assert (tp != NULL);
  2.1772 +	assert (ioaddr != NULL);
  2.1773 +
  2.1774 +	dirty_tx = tp->dirty_tx;
  2.1775 +	tx_left = tp->cur_tx - dirty_tx;
  2.1776 +	while (tx_left > 0) {
  2.1777 +		int entry = dirty_tx % NUM_TX_DESC;
  2.1778 +		int txstatus;
  2.1779 +
  2.1780 +		txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
  2.1781 +
  2.1782 +		if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
  2.1783 +			break;	/* It still hasn't been Txed */
  2.1784 +
  2.1785 +		/* Note: TxCarrierLost is always asserted at 100mbps. */
  2.1786 +		if (txstatus & (TxOutOfWindow | TxAborted)) {
  2.1787 +			/* There was an major error, log it. */
  2.1788 +			DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
  2.1789 +				 dev->name, txstatus);
  2.1790 +			tp->stats.tx_errors++;
  2.1791 +			if (txstatus & TxAborted) {
  2.1792 +				tp->stats.tx_aborted_errors++;
  2.1793 +				RTL_W32 (TxConfig, TxClearAbt);
  2.1794 +				RTL_W16 (IntrStatus, TxErr);
  2.1795 +				wmb();
  2.1796 +			}
  2.1797 +			if (txstatus & TxCarrierLost)
  2.1798 +				tp->stats.tx_carrier_errors++;
  2.1799 +			if (txstatus & TxOutOfWindow)
  2.1800 +				tp->stats.tx_window_errors++;
  2.1801 +		} else {
  2.1802 +			if (txstatus & TxUnderrun) {
  2.1803 +				/* Add 64 to the Tx FIFO threshold. */
  2.1804 +				if (tp->tx_flag < 0x00300000)
  2.1805 +					tp->tx_flag += 0x00020000;
  2.1806 +				tp->stats.tx_fifo_errors++;
  2.1807 +			}
  2.1808 +			tp->stats.collisions += (txstatus >> 24) & 15;
  2.1809 +			tp->stats.tx_bytes += txstatus & 0x7ff;
  2.1810 +			tp->stats.tx_packets++;
  2.1811 +		}
  2.1812 +
  2.1813 +		dirty_tx++;
  2.1814 +		tx_left--;
  2.1815 +	}
  2.1816 +
  2.1817 +#ifndef RTL8139_NDEBUG
  2.1818 +	if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
  2.1819 +		printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
  2.1820 +		        dev->name, dirty_tx, tp->cur_tx);
  2.1821 +		dirty_tx += NUM_TX_DESC;
  2.1822 +	}
  2.1823 +#endif /* RTL8139_NDEBUG */
  2.1824 +
  2.1825 +	/* only wake the queue if we did work, and the queue is stopped */
  2.1826 +	if (tp->dirty_tx != dirty_tx) {
  2.1827 +		tp->dirty_tx = dirty_tx;
  2.1828 +		mb();
  2.1829 +		if (netif_queue_stopped (dev))
  2.1830 +			netif_wake_queue (dev);
  2.1831 +	}
  2.1832 +}
  2.1833 +
  2.1834 +
  2.1835 +/* TODO: clean this up!  Rx reset need not be this intensive */
  2.1836 +static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
  2.1837 +			    struct rtl8139_private *tp, void *ioaddr)
  2.1838 +{
  2.1839 +	u8 tmp8;
  2.1840 +#ifdef CONFIG_8139_OLD_RX_RESET
  2.1841 +	int tmp_work;
  2.1842 +#endif
  2.1843 +
  2.1844 +	DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
  2.1845 +	         dev->name, rx_status);
  2.1846 +	tp->stats.rx_errors++;
  2.1847 +	if (!(rx_status & RxStatusOK)) {
  2.1848 +		if (rx_status & RxTooLong) {
  2.1849 +			DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
  2.1850 +			 	dev->name, rx_status);
  2.1851 +			/* A.C.: The chip hangs here. */
  2.1852 +		}
  2.1853 +		if (rx_status & (RxBadSymbol | RxBadAlign))
  2.1854 +			tp->stats.rx_frame_errors++;
  2.1855 +		if (rx_status & (RxRunt | RxTooLong))
  2.1856 +			tp->stats.rx_length_errors++;
  2.1857 +		if (rx_status & RxCRCErr)
  2.1858 +			tp->stats.rx_crc_errors++;
  2.1859 +	} else {
  2.1860 +		tp->xstats.rx_lost_in_ring++;
  2.1861 +	}
  2.1862 +
  2.1863 +#ifndef CONFIG_8139_OLD_RX_RESET
  2.1864 +	tmp8 = RTL_R8 (ChipCmd);
  2.1865 +	RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
  2.1866 +	RTL_W8 (ChipCmd, tmp8);
  2.1867 +	RTL_W32 (RxConfig, tp->rx_config);
  2.1868 +	tp->cur_rx = 0;
  2.1869 +#else
  2.1870 +	/* Reset the receiver, based on RealTek recommendation. (Bug?) */
  2.1871 +
  2.1872 +	/* disable receive */
  2.1873 +	RTL_W8_F (ChipCmd, CmdTxEnb);
  2.1874 +	tmp_work = 200;
  2.1875 +	while (--tmp_work > 0) {
  2.1876 +		udelay(1);
  2.1877 +		tmp8 = RTL_R8 (ChipCmd);
  2.1878 +		if (!(tmp8 & CmdRxEnb))
  2.1879 +			break;
  2.1880 +	}
  2.1881 +	if (tmp_work <= 0)
  2.1882 +		printk (KERN_WARNING PFX "rx stop wait too long\n");
  2.1883 +	/* restart receive */
  2.1884 +	tmp_work = 200;
  2.1885 +	while (--tmp_work > 0) {
  2.1886 +		RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1887 +		udelay(1);
  2.1888 +		tmp8 = RTL_R8 (ChipCmd);
  2.1889 +		if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
  2.1890 +			break;
  2.1891 +	}
  2.1892 +	if (tmp_work <= 0)
  2.1893 +		printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
  2.1894 +
  2.1895 +	/* and reinitialize all rx related registers */
  2.1896 +	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
  2.1897 +	/* Must enable Tx/Rx before setting transfer thresholds! */
  2.1898 +	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1899 +
  2.1900 +	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
  2.1901 +	RTL_W32 (RxConfig, tp->rx_config);
  2.1902 +	tp->cur_rx = 0;
  2.1903 +
  2.1904 +	DPRINTK("init buffer addresses\n");
  2.1905 +
  2.1906 +	/* Lock Config[01234] and BMCR register writes */
  2.1907 +	RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1908 +
  2.1909 +	/* init Rx ring buffer DMA address */
  2.1910 +	RTL_W32_F (RxBuf, tp->rx_ring_dma);
  2.1911 +
  2.1912 +	/* A.C.: Reset the multicast list. */
  2.1913 +	__set_rx_mode (dev);
  2.1914 +#endif
  2.1915 +}
  2.1916 +
  2.1917 +static void rtl8139_rx_interrupt (struct net_device *dev,
  2.1918 +				  struct rtl8139_private *tp, void *ioaddr)
  2.1919 +{
  2.1920 +	unsigned char *rx_ring;
  2.1921 +	u16 cur_rx;
  2.1922 +
  2.1923 +	assert (dev != NULL);
  2.1924 +	assert (tp != NULL);
  2.1925 +	assert (ioaddr != NULL);
  2.1926 +
  2.1927 +	rx_ring = tp->rx_ring;
  2.1928 +	cur_rx = tp->cur_rx;
  2.1929 +
  2.1930 +	DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
  2.1931 +		 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
  2.1932 +		 RTL_R16 (RxBufAddr),
  2.1933 +		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
  2.1934 +
  2.1935 +	while ((RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
  2.1936 +		int ring_offset = cur_rx % RX_BUF_LEN;
  2.1937 +		u32 rx_status;
  2.1938 +		unsigned int rx_size;
  2.1939 +		unsigned int pkt_size;
  2.1940 +		struct sk_buff *skb;
  2.1941 +
  2.1942 +		rmb();
  2.1943 +
  2.1944 +		/* read size+status of next frame from DMA ring buffer */
  2.1945 +		rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
  2.1946 +		rx_size = rx_status >> 16;
  2.1947 +		pkt_size = rx_size - 4;
  2.1948 +
  2.1949 +		DPRINTK ("%s:  rtl8139_rx() status %4.4x, size %4.4x,"
  2.1950 +			 " cur %4.4x.\n", dev->name, rx_status,
  2.1951 +			 rx_size, cur_rx);
  2.1952 +#if RTL8139_DEBUG > 2
  2.1953 +		{
  2.1954 +			int i;
  2.1955 +			DPRINTK ("%s: Frame contents ", dev->name);
  2.1956 +			for (i = 0; i < 70; i++)
  2.1957 +				printk (" %2.2x",
  2.1958 +					rx_ring[ring_offset + i]);
  2.1959 +			printk (".\n");
  2.1960 +		}
  2.1961 +#endif
  2.1962 +
  2.1963 +		/* Packet copy from FIFO still in progress.
  2.1964 +		 * Theoretically, this should never happen
  2.1965 +		 * since EarlyRx is disabled.
  2.1966 +		 */
  2.1967 +		if (rx_size == 0xfff0) {
  2.1968 +			tp->xstats.early_rx++;
  2.1969 +			break;
  2.1970 +		}
  2.1971 +
  2.1972 +		/* If Rx err or invalid rx_size/rx_status received
  2.1973 +		 * (which happens if we get lost in the ring),
  2.1974 +		 * Rx process gets reset, so we abort any further
  2.1975 +		 * Rx processing.
  2.1976 +		 */
  2.1977 +		if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
  2.1978 +		    (rx_size < 8) ||
  2.1979 +		    (!(rx_status & RxStatusOK))) {
  2.1980 +			rtl8139_rx_err (rx_status, dev, tp, ioaddr);
  2.1981 +			return;
  2.1982 +		}
  2.1983 +
  2.1984 +		/* Malloc up new buffer, compatible with net-2e. */
  2.1985 +		/* Omit the four octet CRC from the length. */
  2.1986 +
  2.1987 +		/* TODO: consider allocating skb's outside of
  2.1988 +		 * interrupt context, both to speed interrupt processing,
  2.1989 +		 * and also to reduce the chances of having to
  2.1990 +		 * drop packets here under memory pressure.
  2.1991 +		 */
  2.1992 +
  2.1993 +		skb = dev_alloc_skb (pkt_size + 2);
  2.1994 +		if (skb) {
  2.1995 +			skb->dev = dev;
  2.1996 +			skb_reserve (skb, 2);	/* 16 byte align the IP fields. */
  2.1997 +
  2.1998 +			eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
  2.1999 +			skb_put (skb, pkt_size);
  2.2000 +
  2.2001 +			skb->protocol = eth_type_trans (skb, dev);
  2.2002 +			netif_rx (skb);
  2.2003 +			dev->last_rx = jiffies;
  2.2004 +			tp->stats.rx_bytes += pkt_size;
  2.2005 +			tp->stats.rx_packets++;
  2.2006 +		} else {
  2.2007 +			printk (KERN_WARNING
  2.2008 +				"%s: Memory squeeze, dropping packet.\n",
  2.2009 +				dev->name);
  2.2010 +			tp->stats.rx_dropped++;
  2.2011 +		}
  2.2012 +
  2.2013 +		cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
  2.2014 +		RTL_W16 (RxBufPtr, cur_rx - 16);
  2.2015 +
  2.2016 +		if (RTL_R16 (IntrStatus) & RxAckBits)
  2.2017 +			RTL_W16_F (IntrStatus, RxAckBits);
  2.2018 +	}
  2.2019 +
  2.2020 +	DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
  2.2021 +		 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
  2.2022 +		 RTL_R16 (RxBufAddr),
  2.2023 +		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
  2.2024 +
  2.2025 +	tp->cur_rx = cur_rx;
  2.2026 +}
  2.2027 +
  2.2028 +
  2.2029 +static void rtl8139_weird_interrupt (struct net_device *dev,
  2.2030 +				     struct rtl8139_private *tp,
  2.2031 +				     void *ioaddr,
  2.2032 +				     int status, int link_changed)
  2.2033 +{
  2.2034 +	DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
  2.2035 +		 dev->name, status);
  2.2036 +
  2.2037 +	assert (dev != NULL);
  2.2038 +	assert (tp != NULL);
  2.2039 +	assert (ioaddr != NULL);
  2.2040 +
  2.2041 +	/* Update the error count. */
  2.2042 +	tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2043 +	RTL_W32 (RxMissed, 0);
  2.2044 +
  2.2045 +	if ((status & RxUnderrun) && link_changed &&
  2.2046 +	    (tp->drv_flags & HAS_LNK_CHNG)) {
  2.2047 +		/* Really link-change on new chips. */
  2.2048 +		int lpar = RTL_R16 (NWayLPAR);
  2.2049 +		int duplex = (lpar & LPA_100FULL) || (lpar & 0x01C0) == 0x0040
  2.2050 +				|| tp->mii.force_media;
  2.2051 +		if (tp->mii.full_duplex != duplex) {
  2.2052 +			tp->mii.full_duplex = duplex;
  2.2053 +#if 0
  2.2054 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.2055 +			RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
  2.2056 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.2057 +#endif
  2.2058 +		}
  2.2059 +		status &= ~RxUnderrun;
  2.2060 +	}
  2.2061 +
  2.2062 +	/* XXX along with rtl8139_rx_err, are we double-counting errors? */
  2.2063 +	if (status &
  2.2064 +	    (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
  2.2065 +		tp->stats.rx_errors++;
  2.2066 +
  2.2067 +	if (status & PCSTimeout)
  2.2068 +		tp->stats.rx_length_errors++;
  2.2069 +	if (status & (RxUnderrun | RxFIFOOver))
  2.2070 +		tp->stats.rx_fifo_errors++;
  2.2071 +	if (status & PCIErr) {
  2.2072 +		u16 pci_cmd_status;
  2.2073 +		pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
  2.2074 +		pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
  2.2075 +
  2.2076 +		printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
  2.2077 +			dev->name, pci_cmd_status);
  2.2078 +	}
  2.2079 +}
  2.2080 +
  2.2081 +
  2.2082 +/* The interrupt handler does all of the Rx thread work and cleans up
  2.2083 +   after the Tx thread. */
  2.2084 +static void rtl8139_interrupt (int irq, void *dev_instance,
  2.2085 +			       struct pt_regs *regs)
  2.2086 +{
  2.2087 +	struct net_device *dev = (struct net_device *) dev_instance;
  2.2088 +	struct rtl8139_private *tp = dev->priv;
  2.2089 +	int boguscnt = max_interrupt_work;
  2.2090 +	void *ioaddr = tp->mmio_addr;
  2.2091 +	int ackstat, status;
  2.2092 +	int link_changed = 0; /* avoid bogus "uninit" warning */
  2.2093 +
  2.2094 +	spin_lock (&tp->lock);
  2.2095 +
  2.2096 +	do {
  2.2097 +		status = RTL_R16 (IntrStatus);
  2.2098 +
  2.2099 +		/* h/w no longer present (hotplug?) or major error, bail */
  2.2100 +		if (status == 0xFFFF)
  2.2101 +			break;
  2.2102 +
  2.2103 +		if ((status &
  2.2104 +		     (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
  2.2105 +		      RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
  2.2106 +			break;
  2.2107 +
  2.2108 +		/* Acknowledge all of the current interrupt sources ASAP, but
  2.2109 +		   an first get an additional status bit from CSCR. */
  2.2110 +		if (status & RxUnderrun)
  2.2111 +			link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
  2.2112 +
  2.2113 +		/* The chip takes special action when we clear RxAckBits,
  2.2114 +		 * so we clear them later in rtl8139_rx_interrupt
  2.2115 +		 */
  2.2116 +		ackstat = status & ~(RxAckBits | TxErr);
  2.2117 +		RTL_W16 (IntrStatus, ackstat);
  2.2118 +
  2.2119 +		DPRINTK ("%s: interrupt  status=%#4.4x ackstat=%#4.4x new intstat=%#4.4x.\n",
  2.2120 +			 dev->name, ackstat, status, RTL_R16 (IntrStatus));
  2.2121 +
  2.2122 +		if (netif_running (dev) && (status & RxAckBits))
  2.2123 +			rtl8139_rx_interrupt (dev, tp, ioaddr);
  2.2124 +
  2.2125 +		/* Check uncommon events with one test. */
  2.2126 +		if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
  2.2127 +		  	      RxFIFOOver | RxErr))
  2.2128 +			rtl8139_weird_interrupt (dev, tp, ioaddr,
  2.2129 +						 status, link_changed);
  2.2130 +
  2.2131 +		if (netif_running (dev) && (status & (TxOK | TxErr))) {
  2.2132 +			rtl8139_tx_interrupt (dev, tp, ioaddr);
  2.2133 +			if (status & TxErr)
  2.2134 +				RTL_W16 (IntrStatus, TxErr);
  2.2135 +		}
  2.2136 +
  2.2137 +		boguscnt--;
  2.2138 +	} while (boguscnt > 0);
  2.2139 +
  2.2140 +	if (boguscnt <= 0) {
  2.2141 +		printk (KERN_WARNING "%s: Too much work at interrupt, "
  2.2142 +			"IntrStatus=0x%4.4x.\n", dev->name, status);
  2.2143 +
  2.2144 +		/* Clear all interrupt sources. */
  2.2145 +		RTL_W16 (IntrStatus, 0xffff);
  2.2146 +	}
  2.2147 +
  2.2148 +	spin_unlock (&tp->lock);
  2.2149 +
  2.2150 +	DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
  2.2151 +		 dev->name, RTL_R16 (IntrStatus));
  2.2152 +}
  2.2153 +
  2.2154 +
  2.2155 +static int rtl8139_close (struct net_device *dev)
  2.2156 +{
  2.2157 +	struct rtl8139_private *tp = dev->priv;
  2.2158 +	void *ioaddr = tp->mmio_addr;
  2.2159 +#if 0
  2.2160 +	int ret = 0;
  2.2161 +#endif
  2.2162 +	unsigned long flags;
  2.2163 +
  2.2164 +	netif_stop_queue (dev);
  2.2165 +
  2.2166 +#if 0
  2.2167 +	if (tp->thr_pid >= 0) {
  2.2168 +		tp->time_to_die = 1;
  2.2169 +		wmb();
  2.2170 +		ret = kill_proc (tp->thr_pid, SIGTERM, 1);
  2.2171 +		if (ret) {
  2.2172 +			printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
  2.2173 +			return ret;
  2.2174 +		}
  2.2175 +		wait_for_completion (&tp->thr_exited);
  2.2176 +	}
  2.2177 +#else
  2.2178 +	del_timer_sync(&tp->timer);
  2.2179 +#endif
  2.2180 +
  2.2181 +	DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
  2.2182 +			dev->name, RTL_R16 (IntrStatus));
  2.2183 +
  2.2184 +	spin_lock_irqsave (&tp->lock, flags);
  2.2185 +
  2.2186 +	/* Stop the chip's Tx and Rx DMA processes. */
  2.2187 +	RTL_W8 (ChipCmd, 0);
  2.2188 +
  2.2189 +	/* Disable interrupts by clearing the interrupt mask. */
  2.2190 +	RTL_W16 (IntrMask, 0);
  2.2191 +
  2.2192 +	/* Update the error counts. */
  2.2193 +	tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2194 +	RTL_W32 (RxMissed, 0);
  2.2195 +
  2.2196 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.2197 +
  2.2198 +	synchronize_irq ();
  2.2199 +	free_irq (dev->irq, dev);
  2.2200 +
  2.2201 +	rtl8139_tx_clear (tp);
  2.2202 +
  2.2203 +	pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  2.2204 +			    tp->rx_ring, tp->rx_ring_dma);
  2.2205 +	pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  2.2206 +			    tp->tx_bufs, tp->tx_bufs_dma);
  2.2207 +	tp->rx_ring = NULL;
  2.2208 +	tp->tx_bufs = NULL;
  2.2209 +
  2.2210 +	/* Green! Put the chip in low-power mode. */
  2.2211 +	RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.2212 +
  2.2213 +	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  2.2214 +		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
  2.2215 +
  2.2216 +	return 0;
  2.2217 +}
  2.2218 +
  2.2219 +
  2.2220 +/* Get the ethtool Wake-on-LAN settings.  Assumes that wol points to
  2.2221 +   kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
  2.2222 +   other threads or interrupts aren't messing with the 8139.  */
  2.2223 +static void netdev_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
  2.2224 +{
  2.2225 +	struct rtl8139_private *np = dev->priv;
  2.2226 +	void *ioaddr = np->mmio_addr;
  2.2227 +
  2.2228 +	if (rtl_chip_info[np->chipset].flags & HasLWake) {
  2.2229 +		u8 cfg3 = RTL_R8 (Config3);
  2.2230 +		u8 cfg5 = RTL_R8 (Config5);
  2.2231 +
  2.2232 +		wol->supported = WAKE_PHY | WAKE_MAGIC
  2.2233 +			| WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
  2.2234 +
  2.2235 +		wol->wolopts = 0;
  2.2236 +		if (cfg3 & Cfg3_LinkUp)
  2.2237 +			wol->wolopts |= WAKE_PHY;
  2.2238 +		if (cfg3 & Cfg3_Magic)
  2.2239 +			wol->wolopts |= WAKE_MAGIC;
  2.2240 +		/* (KON)FIXME: See how netdev_set_wol() handles the
  2.2241 +		   following constants.  */
  2.2242 +		if (cfg5 & Cfg5_UWF)
  2.2243 +			wol->wolopts |= WAKE_UCAST;
  2.2244 +		if (cfg5 & Cfg5_MWF)
  2.2245 +			wol->wolopts |= WAKE_MCAST;
  2.2246 +		if (cfg5 & Cfg5_BWF)
  2.2247 +			wol->wolopts |= WAKE_BCAST;
  2.2248 +	}
  2.2249 +}
  2.2250 +
  2.2251 +
  2.2252 +/* Set the ethtool Wake-on-LAN settings.  Return 0 or -errno.  Assumes
  2.2253 +   that wol points to kernel memory and other threads or interrupts
  2.2254 +   aren't messing with the 8139.  */
  2.2255 +static int netdev_set_wol (struct net_device *dev,
  2.2256 +			   const struct ethtool_wolinfo *wol)
  2.2257 +{
  2.2258 +	struct rtl8139_private *np = dev->priv;
  2.2259 +	void *ioaddr = np->mmio_addr;
  2.2260 +	u32 support;
  2.2261 +	u8 cfg3, cfg5;
  2.2262 +
  2.2263 +	support = ((rtl_chip_info[np->chipset].flags & HasLWake)
  2.2264 +		   ? (WAKE_PHY | WAKE_MAGIC
  2.2265 +		      | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
  2.2266 +		   : 0);
  2.2267 +	if (wol->wolopts & ~support)
  2.2268 +		return -EINVAL;
  2.2269 +
  2.2270 +	cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
  2.2271 +	if (wol->wolopts & WAKE_PHY)
  2.2272 +		cfg3 |= Cfg3_LinkUp;
  2.2273 +	if (wol->wolopts & WAKE_MAGIC)
  2.2274 +		cfg3 |= Cfg3_Magic;
  2.2275 +	RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.2276 +	RTL_W8 (Config3, cfg3);
  2.2277 +	RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.2278 +
  2.2279 +	cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
  2.2280 +	/* (KON)FIXME: These are untested.  We may have to set the
  2.2281 +	   CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
  2.2282 +	   documentation.  */
  2.2283 +	if (wol->wolopts & WAKE_UCAST)
  2.2284 +		cfg5 |= Cfg5_UWF;
  2.2285 +	if (wol->wolopts & WAKE_MCAST)
  2.2286 +		cfg5 |= Cfg5_MWF;
  2.2287 +	if (wol->wolopts & WAKE_BCAST)
  2.2288 +		cfg5 |= Cfg5_BWF;
  2.2289 +	RTL_W8 (Config5, cfg5);	/* need not unlock via Cfg9346 */
  2.2290 +
  2.2291 +	return 0;
  2.2292 +}
  2.2293 +
  2.2294 +#if 0
  2.2295 +static int netdev_ethtool_ioctl (struct net_device *dev, void *useraddr)
  2.2296 +{
  2.2297 +	struct rtl8139_private *np = dev->priv;
  2.2298 +	u32 ethcmd;
  2.2299 +
  2.2300 +	/* dev_ioctl() in ../../net/core/dev.c has already checked
  2.2301 +	   capable(CAP_NET_ADMIN), so don't bother with that here.  */
  2.2302 +
  2.2303 +	if (get_user(ethcmd, (u32 *)useraddr))
  2.2304 +		return -EFAULT;
  2.2305 +
  2.2306 +	switch (ethcmd) {
  2.2307 +
  2.2308 +	case ETHTOOL_GDRVINFO: {
  2.2309 +		struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
  2.2310 +		strcpy (info.driver, DRV_NAME);
  2.2311 +		strcpy (info.version, DRV_VERSION);
  2.2312 +		strcpy (info.bus_info, np->pci_dev->slot_name);
  2.2313 +		info.regdump_len = np->regs_len;
  2.2314 +		if (copy_to_user (useraddr, &info, sizeof (info)))
  2.2315 +			return -EFAULT;
  2.2316 +		return 0;
  2.2317 +	}
  2.2318 +
  2.2319 +	/* get settings */
  2.2320 +	case ETHTOOL_GSET: {
  2.2321 +		struct ethtool_cmd ecmd = { ETHTOOL_GSET };
  2.2322 +		spin_lock_irq(&np->lock);
  2.2323 +		mii_ethtool_gset(&np->mii, &ecmd);
  2.2324 +		spin_unlock_irq(&np->lock);
  2.2325 +		if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
  2.2326 +			return -EFAULT;
  2.2327 +		return 0;
  2.2328 +	}
  2.2329 +	/* set settings */
  2.2330 +	case ETHTOOL_SSET: {
  2.2331 +		int r;
  2.2332 +		struct ethtool_cmd ecmd;
  2.2333 +		if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
  2.2334 +			return -EFAULT;
  2.2335 +		spin_lock_irq(&np->lock);
  2.2336 +		r = mii_ethtool_sset(&np->mii, &ecmd);
  2.2337 +		spin_unlock_irq(&np->lock);
  2.2338 +		return r;
  2.2339 +	}
  2.2340 +	/* restart autonegotiation */
  2.2341 +	case ETHTOOL_NWAY_RST: {
  2.2342 +		return mii_nway_restart(&np->mii);
  2.2343 +	}
  2.2344 +	/* get link status */
  2.2345 +	case ETHTOOL_GLINK: {
  2.2346 +		struct ethtool_value edata = {ETHTOOL_GLINK};
  2.2347 +		edata.data = mii_link_ok(&np->mii);
  2.2348 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.2349 +			return -EFAULT;
  2.2350 +		return 0;
  2.2351 +	}
  2.2352 +
  2.2353 +	/* get message-level */
  2.2354 +	case ETHTOOL_GMSGLVL: {
  2.2355 +		struct ethtool_value edata = {ETHTOOL_GMSGLVL};
  2.2356 +		edata.data = debug;
  2.2357 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.2358 +			return -EFAULT;
  2.2359 +		return 0;
  2.2360 +	}
  2.2361 +	/* set message-level */
  2.2362 +	case ETHTOOL_SMSGLVL: {
  2.2363 +		struct ethtool_value edata;
  2.2364 +		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.2365 +			return -EFAULT;
  2.2366 +		debug = edata.data;
  2.2367 +		return 0;
  2.2368 +	}
  2.2369 +
  2.2370 +	case ETHTOOL_GWOL:
  2.2371 +		{
  2.2372 +			struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
  2.2373 +			spin_lock_irq (&np->lock);
  2.2374 +			netdev_get_wol (dev, &wol);
  2.2375 +			spin_unlock_irq (&np->lock);
  2.2376 +			if (copy_to_user (useraddr, &wol, sizeof (wol)))
  2.2377 +				return -EFAULT;
  2.2378 +			return 0;
  2.2379 +		}
  2.2380 +
  2.2381 +	case ETHTOOL_SWOL:
  2.2382 +		{
  2.2383 +			struct ethtool_wolinfo wol;
  2.2384 +			int rc;
  2.2385 +			if (copy_from_user (&wol, useraddr, sizeof (wol)))
  2.2386 +				return -EFAULT;
  2.2387 +			spin_lock_irq (&np->lock);
  2.2388 +			rc = netdev_set_wol (dev, &wol);
  2.2389 +			spin_unlock_irq (&np->lock);
  2.2390 +			return rc;
  2.2391 +		}
  2.2392 +
  2.2393 +/* TODO: we are too slack to do reg dumping for pio, for now */
  2.2394 +#ifndef CONFIG_8139TOO_PIO
  2.2395 +	/* NIC register dump */
  2.2396 +	case ETHTOOL_GREGS: {
  2.2397 +                struct ethtool_regs regs;
  2.2398 +		unsigned int regs_len = np->regs_len;
  2.2399 +                u8 *regbuf = kmalloc(regs_len, GFP_KERNEL);
  2.2400 +                int rc;
  2.2401 +
  2.2402 +		if (!regbuf)
  2.2403 +			return -ENOMEM;
  2.2404 +		memset(regbuf, 0, regs_len);
  2.2405 +
  2.2406 +                rc = copy_from_user(&regs, useraddr, sizeof(regs));
  2.2407 +		if (rc) {
  2.2408 +			rc = -EFAULT;
  2.2409 +			goto err_out_gregs;
  2.2410 +		}
  2.2411 +                
  2.2412 +                if (regs.len > regs_len)
  2.2413 +                        regs.len = regs_len;
  2.2414 +                if (regs.len < regs_len) {
  2.2415 +			rc = -EINVAL;
  2.2416 +			goto err_out_gregs;
  2.2417 +		}
  2.2418 +
  2.2419 +                regs.version = RTL_REGS_VER;
  2.2420 +                rc = copy_to_user(useraddr, &regs, sizeof(regs));
  2.2421 +		if (rc) {
  2.2422 +			rc = -EFAULT;
  2.2423 +			goto err_out_gregs;
  2.2424 +		}
  2.2425 +
  2.2426 +                useraddr += offsetof(struct ethtool_regs, data);
  2.2427 +
  2.2428 +                spin_lock_irq(&np->lock);
  2.2429 +                memcpy_fromio(regbuf, np->mmio_addr, regs_len);
  2.2430 +                spin_unlock_irq(&np->lock);
  2.2431 +
  2.2432 +                if (copy_to_user(useraddr, regbuf, regs_len))
  2.2433 +                        rc = -EFAULT;
  2.2434 +
  2.2435 +err_out_gregs:
  2.2436 +		kfree(regbuf);
  2.2437 +		return rc;
  2.2438 +	}
  2.2439 +#endif /* CONFIG_8139TOO_PIO */
  2.2440 +
  2.2441 +	/* get string list(s) */
  2.2442 +	case ETHTOOL_GSTRINGS: {
  2.2443 +		struct ethtool_gstrings estr = { ETHTOOL_GSTRINGS };
  2.2444 +
  2.2445 +		if (copy_from_user(&estr, useraddr, sizeof(estr)))
  2.2446 +			return -EFAULT;
  2.2447 +		if (estr.string_set != ETH_SS_STATS)
  2.2448 +			return -EINVAL;
  2.2449 +
  2.2450 +		estr.len = RTL_NUM_STATS;
  2.2451 +		if (copy_to_user(useraddr, &estr, sizeof(estr)))
  2.2452 +			return -EFAULT;
  2.2453 +		if (copy_to_user(useraddr + sizeof(estr),
  2.2454 +				 &ethtool_stats_keys,
  2.2455 +				 sizeof(ethtool_stats_keys)))
  2.2456 +			return -EFAULT;
  2.2457 +		return 0;
  2.2458 +	}
  2.2459 +
  2.2460 +	/* get NIC-specific statistics */
  2.2461 +	case ETHTOOL_GSTATS: {
  2.2462 +		struct ethtool_stats estats = { ETHTOOL_GSTATS };
  2.2463 +		u64 *tmp_stats;
  2.2464 +		const unsigned int sz = sizeof(u64) * RTL_NUM_STATS;
  2.2465 +		int i;
  2.2466 +
  2.2467 +		estats.n_stats = RTL_NUM_STATS;
  2.2468 +		if (copy_to_user(useraddr, &estats, sizeof(estats)))
  2.2469 +			return -EFAULT;
  2.2470 +
  2.2471 +		tmp_stats = kmalloc(sz, GFP_KERNEL);
  2.2472 +		if (!tmp_stats)
  2.2473 +			return -ENOMEM;
  2.2474 +		memset(tmp_stats, 0, sz);
  2.2475 +
  2.2476 +		i = 0;
  2.2477 +		tmp_stats[i++] = np->xstats.early_rx;
  2.2478 +		tmp_stats[i++] = np->xstats.tx_buf_mapped;
  2.2479 +		tmp_stats[i++] = np->xstats.tx_timeouts;
  2.2480 +		tmp_stats[i++] = np->xstats.rx_lost_in_ring;
  2.2481 +		if (i != RTL_NUM_STATS)
  2.2482 +			BUG();
  2.2483 +
  2.2484 +		i = copy_to_user(useraddr + sizeof(estats), tmp_stats, sz);
  2.2485 +		kfree(tmp_stats);
  2.2486 +
  2.2487 +		if (i)
  2.2488 +			return -EFAULT;
  2.2489 +		return 0;
  2.2490 +	}
  2.2491 +	default:
  2.2492 +		break;
  2.2493 +	}
  2.2494 +
  2.2495 +	return -EOPNOTSUPP;
  2.2496 +}
  2.2497 +
  2.2498 +
  2.2499 +static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2.2500 +{
  2.2501 +	struct rtl8139_private *np = dev->priv;
  2.2502 +	struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
  2.2503 +	int rc;
  2.2504 +
  2.2505 +	if (!netif_running(dev))
  2.2506 +		return -EINVAL;
  2.2507 +
  2.2508 +	if (cmd == SIOCETHTOOL)
  2.2509 +		rc = netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
  2.2510 +
  2.2511 +	else {
  2.2512 +		spin_lock_irq(&np->lock);
  2.2513 +		rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
  2.2514 +		spin_unlock_irq(&np->lock);
  2.2515 +	}
  2.2516 +
  2.2517 +	return rc;
  2.2518 +}
  2.2519 +#endif
  2.2520 +
  2.2521 +
  2.2522 +static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
  2.2523 +{
  2.2524 +	struct rtl8139_private *tp = dev->priv;
  2.2525 +	void *ioaddr = tp->mmio_addr;
  2.2526 +	unsigned long flags;
  2.2527 +
  2.2528 +	if (netif_running(dev)) {
  2.2529 +		spin_lock_irqsave (&tp->lock, flags);
  2.2530 +		tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2531 +		RTL_W32 (RxMissed, 0);
  2.2532 +		spin_unlock_irqrestore (&tp->lock, flags);
  2.2533 +	}
  2.2534 +
  2.2535 +	return &tp->stats;
  2.2536 +}
  2.2537 +
  2.2538 +/* Set or clear the multicast filter for this adaptor.
  2.2539 +   This routine is not state sensitive and need not be SMP locked. */
  2.2540 +
  2.2541 +static void __set_rx_mode (struct net_device *dev)
  2.2542 +{
  2.2543 +	struct rtl8139_private *tp = dev->priv;
  2.2544 +	void *ioaddr = tp->mmio_addr;
  2.2545 +	u32 mc_filter[2];	/* Multicast hash filter */
  2.2546 +	int i, rx_mode;
  2.2547 +	u32 tmp;
  2.2548 +
  2.2549 +	DPRINTK ("%s:   rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
  2.2550 +			dev->name, dev->flags, RTL_R32 (RxConfig));
  2.2551 +
  2.2552 +	/* Note: do not reorder, GCC is clever about common statements. */
  2.2553 +	if (dev->flags & IFF_PROMISC) {
  2.2554 +		/* Unconditionally log net taps. */
  2.2555 +		printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
  2.2556 +			dev->name);
  2.2557 +		rx_mode =
  2.2558 +		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  2.2559 +		    AcceptAllPhys;
  2.2560 +		mc_filter[1] = mc_filter[0] = 0xffffffff;
  2.2561 +	} else if ((dev->mc_count > multicast_filter_limit)
  2.2562 +		   || (dev->flags & IFF_ALLMULTI)) {
  2.2563 +		/* Too many to filter perfectly -- accept all multicasts. */
  2.2564 +		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  2.2565 +		mc_filter[1] = mc_filter[0] = 0xffffffff;
  2.2566 +	} else {
  2.2567 +		struct dev_mc_list *mclist;
  2.2568 +		rx_mode = AcceptBroadcast | AcceptMyPhys;
  2.2569 +		mc_filter[1] = mc_filter[0] = 0;
  2.2570 +		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2.2571 +		     i++, mclist = mclist->next) {
  2.2572 +			int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
  2.2573 +
  2.2574 +			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  2.2575 +			rx_mode |= AcceptMulticast;
  2.2576 +		}
  2.2577 +	}
  2.2578 +
  2.2579 +	/* We can safely update without stopping the chip. */
  2.2580 +	tmp = rtl8139_rx_config | rx_mode;
  2.2581 +	if (tp->rx_config != tmp) {
  2.2582 +		RTL_W32_F (RxConfig, tmp);
  2.2583 +		tp->rx_config = tmp;
  2.2584 +	}
  2.2585 +	RTL_W32_F (MAR0 + 0, mc_filter[0]);
  2.2586 +	RTL_W32_F (MAR0 + 4, mc_filter[1]);
  2.2587 +}
  2.2588 +
  2.2589 +static void rtl8139_set_rx_mode (struct net_device *dev)
  2.2590 +{
  2.2591 +	unsigned long flags;
  2.2592 +	struct rtl8139_private *tp = dev->priv;
  2.2593 +
  2.2594 +	spin_lock_irqsave (&tp->lock, flags);
  2.2595 +	__set_rx_mode(dev);
  2.2596 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.2597 +}
  2.2598 +
  2.2599 +#ifdef CONFIG_PM
  2.2600 +
  2.2601 +static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
  2.2602 +{
  2.2603 +	struct net_device *dev = pci_get_drvdata (pdev);
  2.2604 +	struct rtl8139_private *tp = dev->priv;
  2.2605 +	void *ioaddr = tp->mmio_addr;
  2.2606 +	unsigned long flags;
  2.2607 +
  2.2608 +	if (!netif_running (dev))
  2.2609 +		return 0;
  2.2610 +
  2.2611 +	netif_device_detach (dev);
  2.2612 +
  2.2613 +	spin_lock_irqsave (&tp->lock, flags);
  2.2614 +
  2.2615 +	/* Disable interrupts, stop Tx and Rx. */
  2.2616 +	RTL_W16 (IntrMask, 0);
  2.2617 +	RTL_W8 (ChipCmd, 0);
  2.2618 +
  2.2619 +	/* Update the error counts. */
  2.2620 +	tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2621 +	RTL_W32 (RxMissed, 0);
  2.2622 +
  2.2623 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.2624 +	return 0;
  2.2625 +}
  2.2626 +
  2.2627 +
  2.2628 +static int rtl8139_resume (struct pci_dev *pdev)
  2.2629 +{
  2.2630 +	struct net_device *dev = pci_get_drvdata (pdev);
  2.2631 +
  2.2632 +	if (!netif_running (dev))
  2.2633 +		return 0;
  2.2634 +	netif_device_attach (dev);
  2.2635 +	rtl8139_hw_start (dev);
  2.2636 +	return 0;
  2.2637 +}
  2.2638 +
  2.2639 +#endif /* CONFIG_PM */
  2.2640 +
  2.2641 +
  2.2642 +static struct pci_driver rtl8139_pci_driver = {
  2.2643 +	.name		= DRV_NAME,
  2.2644 +	.id_table	= rtl8139_pci_tbl,
  2.2645 +	.probe		= rtl8139_init_one,
  2.2646 +	.remove		= __devexit_p(rtl8139_remove_one),
  2.2647 +#ifdef CONFIG_PM
  2.2648 +	.suspend	= rtl8139_suspend,
  2.2649 +	.resume		= rtl8139_resume,
  2.2650 +#endif /* CONFIG_PM */
  2.2651 +};
  2.2652 +
  2.2653 +
  2.2654 +static int __init rtl8139_init_module (void)
  2.2655 +{
  2.2656 +	/* when we're a module, we always print a version message,
  2.2657 +	 * even if no 8139 board is found.
  2.2658 +	 */
  2.2659 +#ifdef MODULE
  2.2660 +	printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
  2.2661 +#endif
  2.2662 +
  2.2663 +	return pci_module_init (&rtl8139_pci_driver);
  2.2664 +}
  2.2665 +
  2.2666 +
  2.2667 +static void __exit rtl8139_cleanup_module (void)
  2.2668 +{
  2.2669 +	pci_unregister_driver (&rtl8139_pci_driver);
  2.2670 +}
  2.2671 +
  2.2672 +
  2.2673 +module_init(rtl8139_init_module);
  2.2674 +module_exit(rtl8139_cleanup_module);

     3.1 --- a/xen/drivers/net/Makefile	Wed Jul 09 10:27:24 2003 +0000
     3.2 +++ b/xen/drivers/net/Makefile	Wed Jul 09 16:27:59 2003 +0000
     3.3 @@ -2,12 +2,14 @@
     3.4  include $(BASEDIR)/Rules.mk
     3.5  
     3.6  default: $(OBJS)
     3.7 -	$(MAKE) -C ne
     3.8 +	$(MAKE) -C tulip
     3.9 +	$(MAKE) -C e100
    3.10  	$(MAKE) -C e1000
    3.11 -	$(LD) -r -o driver.o e1000/e1000.o $(OBJS) ne/ne_drv.o
    3.12 +	$(LD) -r -o driver.o e100/e100.o e1000/e1000.o $(OBJS) tulip/tulip.o
    3.13  
    3.14  clean:
    3.15 -	$(MAKE) -C ne clean
    3.16 +	$(MAKE) -C tulip clean
    3.17 +	$(MAKE) -C e100 clean
    3.18  	$(MAKE) -C e1000 clean
    3.19  	rm -f *.o *~ core
    3.20  

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/xen/drivers/net/SUPPORTED_CARDS	Wed Jul 09 16:27:59 2003 +0000
     4.3 @@ -0,0 +1,14 @@
     4.4 +
     4.5 +Recommended (cards tested and working at full efficiency):
     4.6 + 3com 3c905   (3c59x.c Linux driver)
     4.7 + Broadcom tg3 (tg3.c Linux driver)
     4.8 + Intel e1000  (e1000 Linux driver)
     4.9 + Intel e100   (e100 Linux driver) [*]
    4.10 +
    4.11 +Driver ported, but may not be tested, and won't work at full 
    4.12 +efficiency (extra copies are incurred within Xen):
    4.13 + ne2k, pcnet32/lance, rtl8139, tulip, via-rhine, 
    4.14 +
    4.15 +*: Note that certain revisions of e100 do not support
    4.16 +   scatter/gather DMA. These cards will incur an extra 
    4.17 +   copy within Xen for every transmitted packet.
    4.18 \ No newline at end of file

     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen/drivers/net/e100/LICENSE	Wed Jul 09 16:27:59 2003 +0000
     5.3 @@ -0,0 +1,339 @@
     5.4 +
     5.5 +"This software program is licensed subject to the GNU General Public License 
     5.6 +(GPL). Version 2, June 1991, available at 
     5.7 +<http://www.fsf.org/copyleft/gpl.html>"
     5.8 +
     5.9 +GNU General Public License 
    5.10 +
    5.11 +Version 2, June 1991
    5.12 +
    5.13 +Copyright (C) 1989, 1991 Free Software Foundation, Inc.  
    5.14 +59 Temple Place - Suite 330, Boston, MA  02111-1307, USA
    5.15 +
    5.16 +Everyone is permitted to copy and distribute verbatim copies of this license
    5.17 +document, but changing it is not allowed.
    5.18 +
    5.19 +Preamble
    5.20 +
    5.21 +The licenses for most software are designed to take away your freedom to 
    5.22 +share and change it. By contrast, the GNU General Public License is intended
    5.23 +to guarantee your freedom to share and change free software--to make sure 
    5.24 +the software is free for all its users. This General Public License applies 
    5.25 +to most of the Free Software Foundation's software and to any other program 
    5.26 +whose authors commit to using it. (Some other Free Software Foundation 
    5.27 +software is covered by the GNU Library General Public License instead.) You 
    5.28 +can apply it to your programs, too.
    5.29 +
    5.30 +When we speak of free software, we are referring to freedom, not price. Our
    5.31 +General Public Licenses are designed to make sure that you have the freedom 
    5.32 +to distribute copies of free software (and charge for this service if you 
    5.33 +wish), that you receive source code or can get it if you want it, that you 
    5.34 +can change the software or use pieces of it in new free programs; and that 
    5.35 +you know you can do these things.
    5.36 +
    5.37 +To protect your rights, we need to make restrictions that forbid anyone to 
    5.38 +deny you these rights or to ask you to surrender the rights. These 
    5.39 +restrictions translate to certain responsibilities for you if you distribute
    5.40 +copies of the software, or if you modify it.
    5.41 +
    5.42 +For example, if you distribute copies of such a program, whether gratis or 
    5.43 +for a fee, you must give the recipients all the rights that you have. You 
    5.44 +must make sure that they, too, receive or can get the source code. And you 
    5.45 +must show them these terms so they know their rights.
    5.46 + 
    5.47 +We protect your rights with two steps: (1) copyright the software, and (2) 
    5.48 +offer you this license which gives you legal permission to copy, distribute 
    5.49 +and/or modify the software. 
    5.50 +
    5.51 +Also, for each author's protection and ours, we want to make certain that 
    5.52 +everyone understands that there is no warranty for this free software. If 
    5.53 +the software is modified by someone else and passed on, we want its 
    5.54 +recipients to know that what they have is not the original, so that any 
    5.55 +problems introduced by others will not reflect on the original authors' 
    5.56 +reputations. 
    5.57 +
    5.58 +Finally, any free program is threatened constantly by software patents. We 
    5.59 +wish to avoid the danger that redistributors of a free program will 
    5.60 +individually obtain patent licenses, in effect making the program 
    5.61 +proprietary. To prevent this, we have made it clear that any patent must be 
    5.62 +licensed for everyone's free use or not licensed at all. 
    5.63 +
    5.64 +The precise terms and conditions for copying, distribution and modification 
    5.65 +follow. 
    5.66 +
    5.67 +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
    5.68 +
    5.69 +0. This License applies to any program or other work which contains a notice
    5.70 +   placed by the copyright holder saying it may be distributed under the 
    5.71 +   terms of this General Public License. The "Program", below, refers to any
    5.72 +   such program or work, and a "work based on the Program" means either the 
    5.73 +   Program or any derivative work under copyright law: that is to say, a 
    5.74 +   work containing the Program or a portion of it, either verbatim or with 
    5.75 +   modifications and/or translated into another language. (Hereinafter, 
    5.76 +   translation is included without limitation in the term "modification".) 
    5.77 +   Each licensee is addressed as "you". 
    5.78 +
    5.79 +   Activities other than copying, distribution and modification are not 
    5.80 +   covered by this License; they are outside its scope. The act of running 
    5.81 +   the Program is not restricted, and the output from the Program is covered 
    5.82 +   only if its contents constitute a work based on the Program (independent 
    5.83 +   of having been made by running the Program). Whether that is true depends
    5.84 +   on what the Program does. 
    5.85 +
    5.86 +1. You may copy and distribute verbatim copies of the Program's source code 
    5.87 +   as you receive it, in any medium, provided that you conspicuously and 
    5.88 +   appropriately publish on each copy an appropriate copyright notice and 
    5.89 +   disclaimer of warranty; keep intact all the notices that refer to this 
    5.90 +   License and to the absence of any warranty; and give any other recipients 
    5.91 +   of the Program a copy of this License along with the Program. 
    5.92 +
    5.93 +   You may charge a fee for the physical act of transferring a copy, and you 
    5.94 +   may at your option offer warranty protection in exchange for a fee. 
    5.95 +
    5.96 +2. You may modify your copy or copies of the Program or any portion of it, 
    5.97 +   thus forming a work based on the Program, and copy and distribute such 
    5.98 +   modifications or work under the terms of Section 1 above, provided that 
    5.99 +   you also meet all of these conditions: 
   5.100 +
   5.101 +   * a) You must cause the modified files to carry prominent notices stating 
   5.102 +        that you changed the files and the date of any change. 
   5.103 +
   5.104 +   * b) You must cause any work that you distribute or publish, that in 
   5.105 +        whole or in part contains or is derived from the Program or any part 
   5.106 +        thereof, to be licensed as a whole at no charge to all third parties
   5.107 +        under the terms of this License. 
   5.108 +
   5.109 +   * c) If the modified program normally reads commands interactively when 
   5.110 +        run, you must cause it, when started running for such interactive 
   5.111 +        use in the most ordinary way, to print or display an announcement 
   5.112 +        including an appropriate copyright notice and a notice that there is
   5.113 +        no warranty (or else, saying that you provide a warranty) and that 
   5.114 +        users may redistribute the program under these conditions, and 
   5.115 +        telling the user how to view a copy of this License. (Exception: if 
   5.116 +        the Program itself is interactive but does not normally print such 
   5.117 +        an announcement, your work based on the Program is not required to 
   5.118 +        print an announcement.) 
   5.119 +
   5.120 +   These requirements apply to the modified work as a whole. If identifiable 
   5.121 +   sections of that work are not derived from the Program, and can be 
   5.122 +   reasonably considered independent and separate works in themselves, then 
   5.123 +   this License, and its terms, do not apply to those sections when you 
   5.124 +   distribute them as separate works. But when you distribute the same 
   5.125 +   sections as part of a whole which is a work based on the Program, the 
   5.126 +   distribution of the whole must be on the terms of this License, whose 
   5.127 +   permissions for other licensees extend to the entire whole, and thus to 
   5.128 +   each and every part regardless of who wrote it. 
   5.129 +
   5.130 +   Thus, it is not the intent of this section to claim rights or contest 
   5.131 +   your rights to work written entirely by you; rather, the intent is to 
   5.132 +   exercise the right to control the distribution of derivative or 
   5.133 +   collective works based on the Program. 
   5.134 +
   5.135 +   In addition, mere aggregation of another work not based on the Program 
   5.136 +   with the Program (or with a work based on the Program) on a volume of a 
   5.137 +   storage or distribution medium does not bring the other work under the 
   5.138 +   scope of this License. 
   5.139 +
   5.140 +3. You may copy and distribute the Program (or a work based on it, under 
   5.141 +   Section 2) in object code or executable form under the terms of Sections 
   5.142 +   1 and 2 above provided that you also do one of the following: 
   5.143 +
   5.144 +   * a) Accompany it with the complete corresponding machine-readable source 
   5.145 +        code, which must be distributed under the terms of Sections 1 and 2 
   5.146 +        above on a medium customarily used for software interchange; or, 
   5.147 +
   5.148 +   * b) Accompany it with a written offer, valid for at least three years, 
   5.149 +        to give any third party, for a charge no more than your cost of 
   5.150 +        physically performing source distribution, a complete machine-
   5.151 +        readable copy of the corresponding source code, to be distributed 
   5.152 +        under the terms of Sections 1 and 2 above on a medium customarily 
   5.153 +        used for software interchange; or, 
   5.154 +
   5.155 +   * c) Accompany it with the information you received as to the offer to 
   5.156 +        distribute corresponding source code. (This alternative is allowed 
   5.157 +        only for noncommercial distribution and only if you received the 
   5.158 +        program in object code or executable form with such an offer, in 
   5.159 +        accord with Subsection b above.) 
   5.160 +
   5.161 +   The source code for a work means the preferred form of the work for 
   5.162 +   making modifications to it. For an executable work, complete source code 
   5.163 +   means all the source code for all modules it contains, plus any 
   5.164 +   associated interface definition files, plus the scripts used to control 
   5.165 +   compilation and installation of the executable. However, as a special 
   5.166 +   exception, the source code distributed need not include anything that is 
   5.167 +   normally distributed (in either source or binary form) with the major 
   5.168 +   components (compiler, kernel, and so on) of the operating system on which
   5.169 +   the executable runs, unless that component itself accompanies the 
   5.170 +   executable. 
   5.171 +
   5.172 +   If distribution of executable or object code is made by offering access 
   5.173 +   to copy from a designated place, then offering equivalent access to copy 
   5.174 +   the source code from the same place counts as distribution of the source 
   5.175 +   code, even though third parties are not compelled to copy the source 
   5.176 +   along with the object code. 
   5.177 +
   5.178 +4. You may not copy, modify, sublicense, or distribute the Program except as
   5.179 +   expressly provided under this License. Any attempt otherwise to copy, 
   5.180 +   modify, sublicense or distribute the Program is void, and will 
   5.181 +   automatically terminate your rights under this License. However, parties 
   5.182 +   who have received copies, or rights, from you under this License will not
   5.183 +   have their licenses terminated so long as such parties remain in full 
   5.184 +   compliance. 
   5.185 +
   5.186 +5. You are not required to accept this License, since you have not signed 
   5.187 +   it. However, nothing else grants you permission to modify or distribute 
   5.188 +   the Program or its derivative works. These actions are prohibited by law 
   5.189 +   if you do not accept this License. Therefore, by modifying or 
   5.190 +   distributing the Program (or any work based on the Program), you 
   5.191 +   indicate your acceptance of this License to do so, and all its terms and
   5.192 +   conditions for copying, distributing or modifying the Program or works 
   5.193 +   based on it. 
   5.194 +
   5.195 +6. Each time you redistribute the Program (or any work based on the 
   5.196 +   Program), the recipient automatically receives a license from the 
   5.197 +   original licensor to copy, distribute or modify the Program subject to 
   5.198 +   these terms and conditions. You may not impose any further restrictions 
   5.199 +   on the recipients' exercise of the rights granted herein. You are not 
   5.200 +   responsible for enforcing compliance by third parties to this License. 
   5.201 +
   5.202 +7. If, as a consequence of a court judgment or allegation of patent 
   5.203 +   infringement or for any other reason (not limited to patent issues), 
   5.204 +   conditions are imposed on you (whether by court order, agreement or 
   5.205 +   otherwise) that contradict the conditions of this License, they do not 
   5.206 +   excuse you from the conditions of this License. If you cannot distribute 
   5.207 +   so as to satisfy simultaneously your obligations under this License and 
   5.208 +   any other pertinent obligations, then as a consequence you may not 
   5.209 +   distribute the Program at all. For example, if a patent license would 
   5.210 +   not permit royalty-free redistribution of the Program by all those who 
   5.211 +   receive copies directly or indirectly through you, then the only way you 
   5.212 +   could satisfy both it and this License would be to refrain entirely from 
   5.213 +   distribution of the Program. 
   5.214 +
   5.215 +   If any portion of this section is held invalid or unenforceable under any
   5.216 +   particular circumstance, the balance of the section is intended to apply
   5.217 +   and the section as a whole is intended to apply in other circumstances. 
   5.218 +
   5.219 +   It is not the purpose of this section to induce you to infringe any 
   5.220 +   patents or other property right claims or to contest validity of any 
   5.221 +   such claims; this section has the sole purpose of protecting the 
   5.222 +   integrity of the free software distribution system, which is implemented 
   5.223 +   by public license practices. Many people have made generous contributions
   5.224 +   to the wide range of software distributed through that system in 
   5.225 +   reliance on consistent application of that system; it is up to the 
   5.226 +   author/donor to decide if he or she is willing to distribute software 
   5.227 +   through any other system and a licensee cannot impose that choice. 
   5.228 +
   5.229 +   This section is intended to make thoroughly clear what is believed to be 
   5.230 +   a consequence of the rest of this License. 
   5.231 +
   5.232 +8. If the distribution and/or use of the Program is restricted in certain 
   5.233 +   countries either by patents or by copyrighted interfaces, the original 
   5.234 +   copyright holder who places the Program under this License may add an 
   5.235 +   explicit geographical distribution limitation excluding those countries, 
   5.236 +   so that distribution is permitted only in or among countries not thus 
   5.237 +   excluded. In such case, this License incorporates the limitation as if 
   5.238 +   written in the body of this License. 
   5.239 +
   5.240 +9. The Free Software Foundation may publish revised and/or new versions of 
   5.241 +   the General Public License from time to time. Such new versions will be 
   5.242 +   similar in spirit to the present version, but may differ in detail to 
   5.243 +   address new problems or concerns. 
   5.244 +
   5.245 +   Each version is given a distinguishing version number. If the Program 
   5.246 +   specifies a version number of this License which applies to it and "any 
   5.247 +   later version", you have the option of following the terms and 
   5.248 +   conditions either of that version or of any later version published by 
   5.249 +   the Free Software Foundation. If the Program does not specify a version 
   5.250 +   number of this License, you may choose any version ever published by the 
   5.251 +   Free Software Foundation. 
   5.252 +
   5.253 +10. If you wish to incorporate parts of the Program into other free programs
   5.254 +    whose distribution conditions are different, write to the author to ask 
   5.255 +    for permission. For software which is copyrighted by the Free Software 
   5.256 +    Foundation, write to the Free Software Foundation; we sometimes make 
   5.257 +    exceptions for this. Our decision will be guided by the two goals of 
   5.258 +    preserving the free status of all derivatives of our free software and 
   5.259 +    of promoting the sharing and reuse of software generally. 
   5.260 +
   5.261 +   NO WARRANTY
   5.262 +
   5.263 +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY 
   5.264 +    FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN 
   5.265 +    OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES 
   5.266 +    PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 
   5.267 +    EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
   5.268 +    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE 
   5.269 +    ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH 
   5.270 +    YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 
   5.271 +    NECESSARY SERVICING, REPAIR OR CORRECTION. 
   5.272 +
   5.273 +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 
   5.274 +    WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 
   5.275 +    REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR 
   5.276 +    DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL 
   5.277 +    DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM 
   5.278 +    (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED 
   5.279 +    INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF 
   5.280 +    THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR 
   5.281 +    OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
   5.282 +
   5.283 +END OF TERMS AND CONDITIONS
   5.284 +
   5.285 +How to Apply These Terms to Your New Programs
   5.286 +
   5.287 +If you develop a new program, and you want it to be of the greatest 
   5.288 +possible use to the public, the best way to achieve this is to make it free 
   5.289 +software which everyone can redistribute and change under these terms. 
   5.290 +
   5.291 +To do so, attach the following notices to the program. It is safest to 
   5.292 +attach them to the start of each source file to most effectively convey the
   5.293 +exclusion of warranty; and each file should have at least the "copyright" 
   5.294 +line and a pointer to where the full notice is found. 
   5.295 +
   5.296 +one line to give the program's name and an idea of what it does.
   5.297 +Copyright (C) yyyy  name of author
   5.298 +
   5.299 +This program is free software; you can redistribute it and/or modify it 
   5.300 +under the terms of the GNU General Public License as published by the Free 
   5.301 +Software Foundation; either version 2 of the License, or (at your option) 
   5.302 +any later version.
   5.303 +
   5.304 +This program is distributed in the hope that it will be useful, but WITHOUT 
   5.305 +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   5.306 +FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   5.307 +more details.
   5.308 +
   5.309 +You should have received a copy of the GNU General Public License along with
   5.310 +this program; if not, write to the Free Software Foundation, Inc., 59 
   5.311 +Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   5.312 +
   5.313 +Also add information on how to contact you by electronic and paper mail. 
   5.314 +
   5.315 +If the program is interactive, make it output a short notice like this when 
   5.316 +it starts in an interactive mode: 
   5.317 +
   5.318 +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes 
   5.319 +with ABSOLUTELY NO WARRANTY; for details type 'show w'.  This is free 
   5.320 +software, and you are welcome to redistribute it under certain conditions; 
   5.321 +type 'show c' for details.
   5.322 +
   5.323 +The hypothetical commands 'show w' and 'show c' should show the appropriate 
   5.324 +parts of the General Public License. Of course, the commands you use may be 
   5.325 +called something other than 'show w' and 'show c'; they could even be 
   5.326 +mouse-clicks or menu items--whatever suits your program. 
   5.327 +
   5.328 +You should also get your employer (if you work as a programmer) or your 
   5.329 +school, if any, to sign a "copyright disclaimer" for the program, if 
   5.330 +necessary. Here is a sample; alter the names: 
   5.331 +
   5.332 +Yoyodyne, Inc., hereby disclaims all copyright interest in the program 
   5.333 +'Gnomovision' (which makes passes at compilers) written by James Hacker.
   5.334 +
   5.335 +signature of Ty Coon, 1 April 1989
   5.336 +Ty Coon, President of Vice
   5.337 +
   5.338 +This General Public License does not permit incorporating your program into 
   5.339 +proprietary programs. If your program is a subroutine library, you may 
   5.340 +consider it more useful to permit linking proprietary applications with the 
   5.341 +library. If this is what you want to do, use the GNU Library General Public 
   5.342 +License instead of this License.

     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/drivers/net/e100/Makefile	Wed Jul 09 16:27:59 2003 +0000
     6.3 @@ -0,0 +1,8 @@
     6.4 +
     6.5 +include $(BASEDIR)/Rules.mk
     6.6 +
     6.7 +default: $(OBJS)
     6.8 +	$(LD) -r -o e100.o $(OBJS)
     6.9 +
    6.10 +clean:
    6.11 +	rm -f *.o *~ core

     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/xen/drivers/net/e100/e100.h	Wed Jul 09 16:27:59 2003 +0000
     7.3 @@ -0,0 +1,996 @@
     7.4 +/*******************************************************************************
     7.5 +
     7.6 +  
     7.7 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
     7.8 +  
     7.9 +  This program is free software; you can redistribute it and/or modify it 
    7.10 +  under the terms of the GNU General Public License as published by the Free 
    7.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    7.12 +  any later version.
    7.13 +  
    7.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    7.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    7.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    7.17 +  more details.
    7.18 +  
    7.19 +  You should have received a copy of the GNU General Public License along with
    7.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    7.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    7.22 +  
    7.23 +  The full GNU General Public License is included in this distribution in the
    7.24 +  file called LICENSE.
    7.25 +  
    7.26 +  Contact Information:
    7.27 +  Linux NICS <linux.nics@intel.com>
    7.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    7.29 +*******************************************************************************/
    7.30 +
    7.31 +#ifndef _E100_INC_
    7.32 +#define _E100_INC_
    7.33 +
    7.34 +#include <linux/module.h>
    7.35 +#include <linux/types.h>
    7.36 +#include <linux/init.h>
    7.37 +#include <linux/mm.h>
    7.38 +#include <linux/errno.h>
    7.39 +#include <linux/ioport.h>
    7.40 +#include <linux/pci.h>
    7.41 +#include <linux/kernel.h>
    7.42 +#include <linux/netdevice.h>
    7.43 +#include <linux/etherdevice.h>
    7.44 +#include <linux/skbuff.h>
    7.45 +#include <linux/delay.h>
    7.46 +#include <linux/timer.h>
    7.47 +#include <linux/slab.h>
    7.48 +#include <linux/interrupt.h>
    7.49 +#include <linux/version.h>
    7.50 +#include <linux/string.h>
    7.51 +/*#include <linux/wait.h>*/
    7.52 +#include <linux/reboot.h>
    7.53 +#include <asm/io.h>
    7.54 +#include <asm/unaligned.h>
    7.55 +#include <asm/processor.h>
    7.56 +#include <linux/ethtool.h>
    7.57 +/*#include <linux/inetdevice.h>*/
    7.58 +#include <asm/bitops.h>
    7.59 +
    7.60 +#include <linux/if.h>
    7.61 +#include <asm/uaccess.h>
    7.62 +/*#include <linux/ip.h>*/
    7.63 +#include <linux/if_vlan.h>
    7.64 +#include <linux/mii.h>
    7.65 +
    7.66 +#define yield() ((void)0)
    7.67 +
    7.68 +#define E100_REGS_LEN 1
    7.69 +/*
    7.70 + *  Configure parameters for buffers per controller.
    7.71 + *  If the machine this is being used on is a faster machine (i.e. > 150MHz)
    7.72 + *  and running on a 10MBS network then more queueing of data occurs. This
    7.73 + *  may indicate the some of the numbers below should be adjusted.  Here are
    7.74 + *  some typical numbers:
    7.75 + *                             MAX_TCB 64
    7.76 + *                             MAX_RFD 64
    7.77 + *  The default numbers give work well on most systems tests so no real
    7.78 + *  adjustments really need to take place.  Also, if the machine is connected
    7.79 + *  to a 100MBS network the numbers described above can be lowered from the
    7.80 + *  defaults as considerably less data will be queued.
    7.81 + */
    7.82 +
    7.83 +#define TX_FRAME_CNT   8	/* consecutive transmit frames per interrupt */
    7.84 +/* TX_FRAME_CNT must be less than MAX_TCB    */
    7.85 +
    7.86 +#define E100_DEFAULT_TCB   64
    7.87 +#define E100_MIN_TCB       2*TX_FRAME_CNT + 3	/* make room for at least 2 interrupts */
    7.88 +#define E100_MAX_TCB       1024
    7.89 +
    7.90 +#define E100_DEFAULT_RFD   64
    7.91 +#define E100_MIN_RFD       8
    7.92 +#define E100_MAX_RFD       1024
    7.93 +
    7.94 +#define E100_DEFAULT_XSUM         true
    7.95 +#define E100_DEFAULT_BER          ZLOCK_MAX_ERRORS
    7.96 +#define E100_DEFAULT_SPEED_DUPLEX 0
    7.97 +#define E100_DEFAULT_FC           0
    7.98 +#define E100_DEFAULT_IFS          true
    7.99 +#define E100_DEFAULT_UCODE        true
   7.100 +
   7.101 +#define TX_THRSHLD     8
   7.102 +
   7.103 +/* IFS parameters */
   7.104 +#define MIN_NUMBER_OF_TRANSMITS_100 1000
   7.105 +#define MIN_NUMBER_OF_TRANSMITS_10  100
   7.106 +
   7.107 +#define E100_MAX_NIC 16
   7.108 +
   7.109 +#define E100_MAX_SCB_WAIT	100	/* Max udelays in wait_scb */
   7.110 +#define E100_MAX_CU_IDLE_WAIT	50	/* Max udelays in wait_cus_idle */
   7.111 +
   7.112 +/* HWI feature related constant */
   7.113 +#define HWI_MAX_LOOP                    100
   7.114 +#define MAX_SAME_RESULTS		3
   7.115 +#define HWI_REGISTER_GRANULARITY        80	/* register granularity = 80 Cm */
   7.116 +#define HWI_NEAR_END_BOUNDARY           1000	/* Near end is defined as < 10 meters */
   7.117 +
   7.118 +/* CPUSAVER_BUNDLE_MAX: Sets the maximum number of frames that will be bundled.
   7.119 + * In some situations, such as the TCP windowing algorithm, it may be
   7.120 + * better to limit the growth of the bundle size than let it go as
   7.121 + * high as it can, because that could cause too much added latency.
   7.122 + * The default is six, because this is the number of packets in the
   7.123 + * default TCP window size.  A value of 1 would make CPUSaver indicate
   7.124 + * an interrupt for every frame received.  If you do not want to put
   7.125 + * a limit on the bundle size, set this value to xFFFF.
   7.126 + */
   7.127 +#define E100_DEFAULT_CPUSAVER_BUNDLE_MAX	6
   7.128 +#define E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY	0x600
   7.129 +#define E100_DEFAULT_BUNDLE_SMALL_FR		false
   7.130 +
   7.131 +/* end of configurables */
   7.132 +
   7.133 +/* ====================================================================== */
   7.134 +/*                                hw                                      */
   7.135 +/* ====================================================================== */
   7.136 +
   7.137 +/* timeout for command completion */
   7.138 +#define E100_CMD_WAIT   100	/* iterations */
   7.139 +
   7.140 +struct driver_stats {
   7.141 +	struct net_device_stats net_stats;
   7.142 +
   7.143 +	unsigned long tx_late_col;
   7.144 +	unsigned long tx_ok_defrd;
   7.145 +	unsigned long tx_one_retry;
   7.146 +	unsigned long tx_mt_one_retry;
   7.147 +	unsigned long rcv_cdt_frames;
   7.148 +	unsigned long xmt_fc_pkts;
   7.149 +	unsigned long rcv_fc_pkts;
   7.150 +	unsigned long rcv_fc_unsupported;
   7.151 +	unsigned long xmt_tco_pkts;
   7.152 +	unsigned long rcv_tco_pkts;
   7.153 +	unsigned long rx_intr_pkts;
   7.154 +};
   7.155 +
   7.156 +/* TODO: kill me when we can do C99 */
   7.157 +#define false		(0)
   7.158 +#define true		(1)
   7.159 +
   7.160 +/* Changed for 82558 and 82559 enhancements */
   7.161 +/* defines for 82558/9 flow control CSR values */
   7.162 +#define DFLT_FC_THLD       0x00	/* Rx FIFO threshold of 0.5KB free  */
   7.163 +#define DFLT_FC_CMD        0x00	/* FC Command in CSR */
   7.164 +
   7.165 +/* ====================================================================== */
   7.166 +/*                              equates                                   */
   7.167 +/* ====================================================================== */
   7.168 +
   7.169 +/*
   7.170 + * These are general purpose defines 
   7.171 + */
   7.172 +
   7.173 +/* Bit Mask definitions */
   7.174 +#define BIT_0       0x0001
   7.175 +#define BIT_1       0x0002
   7.176 +#define BIT_2       0x0004
   7.177 +#define BIT_3       0x0008
   7.178 +#define BIT_4       0x0010
   7.179 +#define BIT_5       0x0020
   7.180 +#define BIT_6       0x0040
   7.181 +#define BIT_7       0x0080
   7.182 +#define BIT_8       0x0100
   7.183 +#define BIT_9       0x0200
   7.184 +#define BIT_10      0x0400
   7.185 +#define BIT_11      0x0800
   7.186 +#define BIT_12      0x1000
   7.187 +#define BIT_13      0x2000
   7.188 +#define BIT_14      0x4000
   7.189 +#define BIT_15      0x8000
   7.190 +#define BIT_28      0x10000000
   7.191 +
   7.192 +#define BIT_0_2     0x0007
   7.193 +#define BIT_0_3     0x000F
   7.194 +#define BIT_0_4     0x001F
   7.195 +#define BIT_0_5     0x003F
   7.196 +#define BIT_0_6     0x007F
   7.197 +#define BIT_0_7     0x00FF
   7.198 +#define BIT_0_8     0x01FF
   7.199 +#define BIT_0_13    0x3FFF
   7.200 +#define BIT_0_15    0xFFFF
   7.201 +#define BIT_1_2     0x0006
   7.202 +#define BIT_1_3     0x000E
   7.203 +#define BIT_2_5     0x003C
   7.204 +#define BIT_3_4     0x0018
   7.205 +#define BIT_4_5     0x0030
   7.206 +#define BIT_4_6     0x0070
   7.207 +#define BIT_4_7     0x00F0
   7.208 +#define BIT_5_7     0x00E0
   7.209 +#define BIT_5_12    0x1FE0
   7.210 +#define BIT_5_15    0xFFE0
   7.211 +#define BIT_6_7     0x00c0
   7.212 +#define BIT_7_11    0x0F80
   7.213 +#define BIT_8_10    0x0700
   7.214 +#define BIT_9_13    0x3E00
   7.215 +#define BIT_12_15   0xF000
   7.216 +#define BIT_8_15    0xFF00
   7.217 +
   7.218 +#define BIT_16_20   0x001F0000
   7.219 +#define BIT_21_25   0x03E00000
   7.220 +#define BIT_26_27   0x0C000000
   7.221 +
   7.222 +/* Transmit Threshold related constants */
   7.223 +#define DEFAULT_TX_PER_UNDERRUN         20000
   7.224 +
   7.225 +#define MAX_MULTICAST_ADDRS             64
   7.226 +#define MAX_FILTER                      16
   7.227 +
   7.228 +#define FULL_DUPLEX      2
   7.229 +#define HALF_DUPLEX      1
   7.230 +
   7.231 +/*
   7.232 + * These defines are specific to the 82557 
   7.233 + */
   7.234 +
   7.235 +/* E100 PORT functions -- lower 4 bits */
   7.236 +#define PORT_SOFTWARE_RESET         0
   7.237 +#define PORT_SELFTEST               1
   7.238 +#define PORT_SELECTIVE_RESET        2
   7.239 +#define PORT_DUMP                   3
   7.240 +
   7.241 +/* SCB Status Word bit definitions */
   7.242 +/* Interrupt status/ack fields */
   7.243 +/* ER and FCP interrupts for 82558 masks  */
   7.244 +#define SCB_STATUS_ACK_MASK        BIT_8_15	/* Status Mask */
   7.245 +#define SCB_STATUS_ACK_CX          BIT_15	/* CU Completed Action Cmd */
   7.246 +#define SCB_STATUS_ACK_FR          BIT_14	/* RU Received A Frame */
   7.247 +#define SCB_STATUS_ACK_CNA         BIT_13	/* CU Became Inactive (IDLE) */
   7.248 +#define SCB_STATUS_ACK_RNR         BIT_12	/* RU Became Not Ready */
   7.249 +#define SCB_STATUS_ACK_MDI         BIT_11	/* MDI read or write done */
   7.250 +#define SCB_STATUS_ACK_SWI         BIT_10	/* S/W generated interrupt */
   7.251 +#define SCB_STATUS_ACK_ER          BIT_9	/* Early Receive */
   7.252 +#define SCB_STATUS_ACK_FCP         BIT_8	/* Flow Control Pause */
   7.253 +
   7.254 +/*- CUS Fields */
   7.255 +#define SCB_CUS_MASK            (BIT_6 | BIT_7)	/* CUS 2-bit Mask */
   7.256 +#define SCB_CUS_IDLE            0	/* CU Idle */
   7.257 +#define SCB_CUS_SUSPEND         BIT_6	/* CU Suspended */
   7.258 +#define SCB_CUS_ACTIVE          BIT_7	/* CU Active */
   7.259 +
   7.260 +/*- RUS Fields */
   7.261 +#define SCB_RUS_IDLE            0	/* RU Idle */
   7.262 +#define SCB_RUS_MASK            BIT_2_5	/* RUS 3-bit Mask */
   7.263 +#define SCB_RUS_SUSPEND         BIT_2	/* RU Suspended */
   7.264 +#define SCB_RUS_NO_RESOURCES    BIT_3	/* RU Out Of Resources */
   7.265 +#define SCB_RUS_READY           BIT_4	/* RU Ready */
   7.266 +#define SCB_RUS_SUSP_NO_RBDS    (BIT_2 | BIT_5)	/* RU No More RBDs */
   7.267 +#define SCB_RUS_NO_RBDS         (BIT_3 | BIT_5)	/* RU No More RBDs */
   7.268 +#define SCB_RUS_READY_NO_RBDS   (BIT_4 | BIT_5)	/* RU Ready, No RBDs */
   7.269 +
   7.270 +/* SCB Command Word bit definitions */
   7.271 +/*- CUC fields */
   7.272 +/* Changing mask to 4 bits */
   7.273 +#define SCB_CUC_MASK            BIT_4_7	/* CUC 4-bit Mask */
   7.274 +#define SCB_CUC_NOOP            0
   7.275 +#define SCB_CUC_START           BIT_4	/* CU Start */
   7.276 +#define SCB_CUC_RESUME          BIT_5	/* CU Resume */
   7.277 +#define SCB_CUC_UNKNOWN         BIT_7	/* CU unknown command */
   7.278 +/* Changed for 82558 enhancements */
   7.279 +#define SCB_CUC_STATIC_RESUME   (BIT_5 | BIT_7)	/* 82558/9 Static Resume */
   7.280 +#define SCB_CUC_DUMP_ADDR       BIT_6	/* CU Dump Counters Address */
   7.281 +#define SCB_CUC_DUMP_STAT       (BIT_4 | BIT_6)	/* CU Dump stat. counters */
   7.282 +#define SCB_CUC_LOAD_BASE       (BIT_5 | BIT_6)	/* Load the CU base */
   7.283 +/* Below was defined as BIT_4_7 */
   7.284 +#define SCB_CUC_DUMP_RST_STAT   BIT_4_6	/* CU Dump & reset statistics cntrs */
   7.285 +
   7.286 +/*- RUC fields */
   7.287 +#define SCB_RUC_MASK            BIT_0_2	/* RUC 3-bit Mask */
   7.288 +#define SCB_RUC_START           BIT_0	/* RU Start */
   7.289 +#define SCB_RUC_RESUME          BIT_1	/* RU Resume */
   7.290 +#define SCB_RUC_ABORT           BIT_2	/* RU Abort */
   7.291 +#define SCB_RUC_LOAD_HDS        (BIT_0 | BIT_2)	/* Load RFD Header Data Size */
   7.292 +#define SCB_RUC_LOAD_BASE       (BIT_1 | BIT_2)	/* Load the RU base */
   7.293 +#define SCB_RUC_RBD_RESUME      BIT_0_2	/* RBD resume */
   7.294 +
   7.295 +/* Interrupt fields (assuming byte addressing) */
   7.296 +#define SCB_INT_MASK            BIT_0	/* Mask interrupts */
   7.297 +#define SCB_SOFT_INT            BIT_1	/* Generate a S/W interrupt */
   7.298 +/*  Specific Interrupt Mask Bits (upper byte of SCB Command word) */
   7.299 +#define SCB_FCP_INT_MASK        BIT_2	/* Flow Control Pause */
   7.300 +#define SCB_ER_INT_MASK         BIT_3	/* Early Receive */
   7.301 +#define SCB_RNR_INT_MASK        BIT_4	/* RU Not Ready */
   7.302 +#define SCB_CNA_INT_MASK        BIT_5	/* CU Not Active */
   7.303 +#define SCB_FR_INT_MASK         BIT_6	/* Frame Received */
   7.304 +#define SCB_CX_INT_MASK         BIT_7	/* CU eXecution w/ I-bit done */
   7.305 +#define SCB_BACHELOR_INT_MASK   BIT_2_7	/* 82558 interrupt mask bits */
   7.306 +
   7.307 +#define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7
   7.308 +
   7.309 +/* EEPROM bit definitions */
   7.310 +/*- EEPROM control register bits */
   7.311 +#define EEPROM_FLAG_ASF  0x8000
   7.312 +#define EEPROM_FLAG_GCL  0x4000
   7.313 +
   7.314 +#define EN_TRNF          0x10	/* Enable turnoff */
   7.315 +#define EEDO             0x08	/* EEPROM data out */
   7.316 +#define EEDI             0x04	/* EEPROM data in (set for writing data) */
   7.317 +#define EECS             0x02	/* EEPROM chip select (1=hi, 0=lo) */
   7.318 +#define EESK             0x01	/* EEPROM shift clock (1=hi, 0=lo) */
   7.319 +
   7.320 +/*- EEPROM opcodes */
   7.321 +#define EEPROM_READ_OPCODE          06
   7.322 +#define EEPROM_WRITE_OPCODE         05
   7.323 +#define EEPROM_ERASE_OPCODE         07
   7.324 +#define EEPROM_EWEN_OPCODE          19	/* Erase/write enable */
   7.325 +#define EEPROM_EWDS_OPCODE          16	/* Erase/write disable */
   7.326 +
   7.327 +/*- EEPROM data locations */
   7.328 +#define EEPROM_NODE_ADDRESS_BYTE_0      0
   7.329 +#define EEPROM_COMPATIBILITY_WORD       3
   7.330 +#define EEPROM_PWA_NO                   8
   7.331 +#define EEPROM_ID_WORD			0x0A
   7.332 +#define EEPROM_CONFIG_ASF		0x0D
   7.333 +#define EEPROM_SMBUS_ADDR		0x90
   7.334 +
   7.335 +#define EEPROM_SUM                      0xbaba
   7.336 +
   7.337 +// Zero Locking Algorithm definitions:
   7.338 +#define ZLOCK_ZERO_MASK		0x00F0
   7.339 +#define ZLOCK_MAX_READS		50	
   7.340 +#define ZLOCK_SET_ZERO		0x2010
   7.341 +#define ZLOCK_MAX_SLEEP		300 * HZ	
   7.342 +#define ZLOCK_MAX_ERRORS	300
   7.343 +
   7.344 +/* E100 Action Commands */
   7.345 +#define CB_IA_ADDRESS           1
   7.346 +#define CB_CONFIGURE            2
   7.347 +#define CB_MULTICAST            3
   7.348 +#define CB_TRANSMIT             4
   7.349 +#define CB_LOAD_MICROCODE       5
   7.350 +#define CB_LOAD_FILTER		8
   7.351 +#define CB_MAX_NONTX_CMD        9
   7.352 +#define CB_IPCB_TRANSMIT        9
   7.353 +
   7.354 +/* Pre-defined Filter Bits */
   7.355 +#define CB_FILTER_EL            0x80000000
   7.356 +#define CB_FILTER_FIX           0x40000000
   7.357 +#define CB_FILTER_ARP           0x08000000
   7.358 +#define CB_FILTER_IA_MATCH      0x02000000
   7.359 +
   7.360 +/* Command Block (CB) Field Definitions */
   7.361 +/*- CB Command Word */
   7.362 +#define CB_EL_BIT           BIT_15	/* CB EL Bit */
   7.363 +#define CB_S_BIT            BIT_14	/* CB Suspend Bit */
   7.364 +#define CB_I_BIT            BIT_13	/* CB Interrupt Bit */
   7.365 +#define CB_TX_SF_BIT        BIT_3	/* TX CB Flexible Mode */
   7.366 +#define CB_CMD_MASK         BIT_0_3	/* CB 4-bit CMD Mask */
   7.367 +#define CB_CID_DEFAULT      (0x1f << 8)	/* CB 5-bit CID (max value) */
   7.368 +
   7.369 +/*- CB Status Word */
   7.370 +#define CB_STATUS_MASK          BIT_12_15	/* CB Status Mask (4-bits) */
   7.371 +#define CB_STATUS_COMPLETE      BIT_15	/* CB Complete Bit */
   7.372 +#define CB_STATUS_OK            BIT_13	/* CB OK Bit */
   7.373 +#define CB_STATUS_VLAN          BIT_12 /* CB Valn detected Bit */
   7.374 +#define CB_STATUS_FAIL          BIT_11	/* CB Fail (F) Bit */
   7.375 +
   7.376 +/*misc command bits */
   7.377 +#define CB_TX_EOF_BIT           BIT_15	/* TX CB/TBD EOF Bit */
   7.378 +
   7.379 +/* Config params */
   7.380 +#define CB_CFIG_BYTE_COUNT          22	/* 22 config bytes */
   7.381 +#define CB_CFIG_D102_BYTE_COUNT    10
   7.382 +
   7.383 +/* Receive Frame Descriptor Fields */
   7.384 +
   7.385 +/*- RFD Status Bits */
   7.386 +#define RFD_RECEIVE_COLLISION   BIT_0	/* Collision detected on Receive */
   7.387 +#define RFD_IA_MATCH            BIT_1	/* Indv Address Match Bit */
   7.388 +#define RFD_RX_ERR              BIT_4	/* RX_ERR pin on Phy was set */
   7.389 +#define RFD_FRAME_TOO_SHORT     BIT_7	/* Receive Frame Short */
   7.390 +#define RFD_DMA_OVERRUN         BIT_8	/* Receive DMA Overrun */
   7.391 +#define RFD_NO_RESOURCES        BIT_9	/* No Buffer Space */
   7.392 +#define RFD_ALIGNMENT_ERROR     BIT_10	/* Alignment Error */
   7.393 +#define RFD_CRC_ERROR           BIT_11	/* CRC Error */
   7.394 +#define RFD_STATUS_OK           BIT_13	/* RFD OK Bit */
   7.395 +#define RFD_STATUS_COMPLETE     BIT_15	/* RFD Complete Bit */
   7.396 +
   7.397 +/*- RFD Command Bits*/
   7.398 +#define RFD_EL_BIT      BIT_15	/* RFD EL Bit */
   7.399 +#define RFD_S_BIT       BIT_14	/* RFD Suspend Bit */
   7.400 +#define RFD_H_BIT       BIT_4	/* Header RFD Bit */
   7.401 +#define RFD_SF_BIT      BIT_3	/* RFD Flexible Mode */
   7.402 +
   7.403 +/*- RFD misc bits*/
   7.404 +#define RFD_EOF_BIT         BIT_15	/* RFD End-Of-Frame Bit */
   7.405 +#define RFD_F_BIT           BIT_14	/* RFD Buffer Fetch Bit */
   7.406 +#define RFD_ACT_COUNT_MASK  BIT_0_13	/* RFD Actual Count Mask */
   7.407 +
   7.408 +/* Receive Buffer Descriptor Fields*/
   7.409 +#define RBD_EOF_BIT             BIT_15	/* RBD End-Of-Frame Bit */
   7.410 +#define RBD_F_BIT               BIT_14	/* RBD Buffer Fetch Bit */
   7.411 +#define RBD_ACT_COUNT_MASK      BIT_0_13	/* RBD Actual Count Mask */
   7.412 +
   7.413 +#define SIZE_FIELD_MASK     BIT_0_13	/* Size of the associated buffer */
   7.414 +#define RBD_EL_BIT          BIT_15	/* RBD EL Bit */
   7.415 +
   7.416 +/* Self Test Results*/
   7.417 +#define CB_SELFTEST_FAIL_BIT        BIT_12
   7.418 +#define CB_SELFTEST_DIAG_BIT        BIT_5
   7.419 +#define CB_SELFTEST_REGISTER_BIT    BIT_3
   7.420 +#define CB_SELFTEST_ROM_BIT         BIT_2
   7.421 +
   7.422 +#define CB_SELFTEST_ERROR_MASK ( \
   7.423 +                CB_SELFTEST_FAIL_BIT | CB_SELFTEST_DIAG_BIT | \
   7.424 +                CB_SELFTEST_REGISTER_BIT | CB_SELFTEST_ROM_BIT)
   7.425 +
   7.426 +/* adapter vendor & device ids */
   7.427 +#define PCI_OHIO_BOARD   0x10f0	/* subdevice ID, Ohio dual port nic */
   7.428 +
   7.429 +/* Values for PCI_REV_ID_REGISTER values */
   7.430 +#define D101A4_REV_ID      4	/* 82558 A4 stepping */
   7.431 +#define D101B0_REV_ID      5	/* 82558 B0 stepping */
   7.432 +#define D101MA_REV_ID      8	/* 82559 A0 stepping */
   7.433 +#define D101S_REV_ID      9	/* 82559S A-step */
   7.434 +#define D102_REV_ID      12
   7.435 +#define D102C_REV_ID     13	/* 82550 step C */
   7.436 +#define D102E_REV_ID     15
   7.437 +
   7.438 +/* ############Start of 82555 specific defines################## */
   7.439 +
   7.440 +#define PHY_82555_LED_SWITCH_CONTROL    	0x1b	/* 82555 led switch control register */
   7.441 +
   7.442 +/* 82555 led switch control reg. opcodes */
   7.443 +#define PHY_82555_LED_NORMAL_CONTROL    0	// control back to the 8255X
   7.444 +#define PHY_82555_LED_DRIVER_CONTROL    BIT_2	// the driver is in control
   7.445 +#define PHY_82555_LED_OFF               BIT_2	// activity LED is off
   7.446 +#define PHY_82555_LED_ON_559           (BIT_0 | BIT_2)	// activity LED is on for 559 and later
   7.447 +#define PHY_82555_LED_ON_PRE_559       (BIT_0 | BIT_1 | BIT_2)	// activity LED is on for 558 and before
   7.448 +
   7.449 +// Describe the state of the phy led.
   7.450 +// needed for the function : 'e100_blink_timer'
   7.451 +enum led_state_e {
   7.452 +	LED_OFF = 0,
   7.453 +	LED_ON,
   7.454 +};
   7.455 +
   7.456 +/* ############End of 82555 specific defines##################### */
   7.457 +
   7.458 +#define RFD_PARSE_BIT			BIT_3
   7.459 +#define RFD_TCP_PACKET			0x00
   7.460 +#define RFD_UDP_PACKET			0x01
   7.461 +#define TCPUDP_CHECKSUM_BIT_VALID	BIT_4
   7.462 +#define TCPUDP_CHECKSUM_VALID		BIT_5
   7.463 +#define CHECKSUM_PROTOCOL_MASK		0x03
   7.464 +
   7.465 +#define VLAN_SIZE   4
   7.466 +#define CHKSUM_SIZE 2
   7.467 +#define RFD_DATA_SIZE (ETH_FRAME_LEN + CHKSUM_SIZE + VLAN_SIZE)
   7.468 +
   7.469 +/* Bits for bdp->flags */
   7.470 +#define DF_LINK_FC_CAP     0x00000001	/* Link is flow control capable */
   7.471 +#define DF_CSUM_OFFLOAD    0x00000002
   7.472 +#define DF_UCODE_LOADED    0x00000004
   7.473 +#define USE_IPCB           0x00000008	/* set if using ipcb for transmits */
   7.474 +#define IS_BACHELOR        0x00000010	/* set if 82558 or newer board */
   7.475 +#define IS_ICH             0x00000020
   7.476 +#define DF_SPEED_FORCED    0x00000040	/* set if speed is forced */
   7.477 +#define LED_IS_ON	   0x00000080	/* LED is turned ON by the driver */
   7.478 +#define DF_LINK_FC_TX_ONLY 0x00000100	/* Received PAUSE frames are honored*/
   7.479 +
   7.480 +typedef struct net_device_stats net_dev_stats_t;
   7.481 +
   7.482 +/* needed macros */
   7.483 +/* These macros use the bdp pointer. If you use them it better be defined */
   7.484 +#define PREV_TCB_USED(X)  ((X).tail ? (X).tail - 1 : bdp->params.TxDescriptors - 1)
   7.485 +#define NEXT_TCB_TOUSE(X) ((((X) + 1) >= bdp->params.TxDescriptors) ? 0 : (X) + 1)
   7.486 +#define TCB_TO_USE(X)     ((X).tail)
   7.487 +#define TCBS_AVAIL(X)     (NEXT_TCB_TOUSE( NEXT_TCB_TOUSE((X).tail)) != (X).head)
   7.488 +
   7.489 +#define RFD_POINTER(skb,bdp)      ((rfd_t *) (((unsigned char *)((skb)->data))-((bdp)->rfd_size)))
   7.490 +#define SKB_RFD_STATUS(skb,bdp)   ((RFD_POINTER((skb),(bdp)))->rfd_header.cb_status)
   7.491 +
   7.492 +/* ====================================================================== */
   7.493 +/*                              82557                                     */
   7.494 +/* ====================================================================== */
   7.495 +
   7.496 +/* Changed for 82558 enhancement */
   7.497 +typedef struct _d101_scb_ext_t {
   7.498 +	u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.499 +	u8 scb_early_rx_int;	/* Early Rx DMA byte count */
   7.500 +	u8 scb_fc_thld;	/* Flow Control threshold */
   7.501 +	u8 scb_fc_xon_xoff;	/* Flow Control XON/XOFF values */
   7.502 +	u8 scb_pmdr;	/* Power Mgmt. Driver Reg */
   7.503 +} d101_scb_ext __attribute__ ((__packed__));
   7.504 +
   7.505 +/* Changed for 82559 enhancement */
   7.506 +typedef struct _d101m_scb_ext_t {
   7.507 +	u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.508 +	u8 scb_early_rx_int;	/* Early Rx DMA byte count */
   7.509 +	u8 scb_fc_thld;	/* Flow Control threshold */
   7.510 +	u8 scb_fc_xon_xoff;	/* Flow Control XON/XOFF values */
   7.511 +	u8 scb_pmdr;	/* Power Mgmt. Driver Reg */
   7.512 +	u8 scb_gen_ctrl;	/* General Control */
   7.513 +	u8 scb_gen_stat;	/* General Status */
   7.514 +	u16 scb_reserved;	/* Reserved */
   7.515 +	u32 scb_function_event;	/* Cardbus Function Event */
   7.516 +	u32 scb_function_event_mask;	/* Cardbus Function Mask */
   7.517 +	u32 scb_function_present_state;	/* Cardbus Function state */
   7.518 +	u32 scb_force_event;	/* Cardbus Force Event */
   7.519 +} d101m_scb_ext __attribute__ ((__packed__));
   7.520 +
   7.521 +/* Changed for 82550 enhancement */
   7.522 +typedef struct _d102_scb_ext_t {
   7.523 +	u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.524 +	u8 scb_early_rx_int;	/* Early Rx DMA byte count */
   7.525 +	u8 scb_fc_thld;	/* Flow Control threshold */
   7.526 +	u8 scb_fc_xon_xoff;	/* Flow Control XON/XOFF values */
   7.527 +	u8 scb_pmdr;	/* Power Mgmt. Driver Reg */
   7.528 +	u8 scb_gen_ctrl;	/* General Control */
   7.529 +	u8 scb_gen_stat;	/* General Status */
   7.530 +	u8 scb_gen_ctrl2;
   7.531 +	u8 scb_reserved;	/* Reserved */
   7.532 +	u32 scb_scheduling_reg;
   7.533 +	u32 scb_reserved2;
   7.534 +	u32 scb_function_event;	/* Cardbus Function Event */
   7.535 +	u32 scb_function_event_mask;	/* Cardbus Function Mask */
   7.536 +	u32 scb_function_present_state;	/* Cardbus Function state */
   7.537 +	u32 scb_force_event;	/* Cardbus Force Event */
   7.538 +} d102_scb_ext __attribute__ ((__packed__));
   7.539 +
   7.540 +/*
   7.541 + * 82557 status control block. this will be memory mapped & will hang of the
   7.542 + * the bdp, which hangs of the bdp. This is the brain of it.
   7.543 + */
   7.544 +typedef struct _scb_t {
   7.545 +	u16 scb_status;	/* SCB Status register */
   7.546 +	u8 scb_cmd_low;	/* SCB Command register (low byte) */
   7.547 +	u8 scb_cmd_hi;	/* SCB Command register (high byte) */
   7.548 +	u32 scb_gen_ptr;	/* SCB General pointer */
   7.549 +	u32 scb_port;	/* PORT register */
   7.550 +	u16 scb_flsh_cntrl;	/* Flash Control register */
   7.551 +	u16 scb_eprm_cntrl;	/* EEPROM control register */
   7.552 +	u32 scb_mdi_cntrl;	/* MDI Control Register */
   7.553 +	/* Changed for 82558 enhancement */
   7.554 +	union {
   7.555 +		u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.556 +		d101_scb_ext d101_scb;	/* 82558/9 specific fields */
   7.557 +		d101m_scb_ext d101m_scb;	/* 82559 specific fields */
   7.558 +		d102_scb_ext d102_scb;
   7.559 +	} scb_ext;
   7.560 +} scb_t __attribute__ ((__packed__));
   7.561 +
   7.562 +/* Self test
   7.563 + * This is used to dump results of the self test 
   7.564 + */
   7.565 +typedef struct _self_test_t {
   7.566 +	u32 st_sign;	/* Self Test Signature */
   7.567 +	u32 st_result;	/* Self Test Results */
   7.568 +} self_test_t __attribute__ ((__packed__));
   7.569 +
   7.570 +/* 
   7.571 + *  Statistical Counters 
   7.572 + */
   7.573 +/* 82557 counters */
   7.574 +typedef struct _basic_cntr_t {
   7.575 +	u32 xmt_gd_frames;	/* Good frames transmitted */
   7.576 +	u32 xmt_max_coll;	/* Fatal frames -- had max collisions */
   7.577 +	u32 xmt_late_coll;	/* Fatal frames -- had a late coll. */
   7.578 +	u32 xmt_uruns;	/* Xmit underruns (fatal or re-transmit) */
   7.579 +	u32 xmt_lost_crs;	/* Frames transmitted without CRS */
   7.580 +	u32 xmt_deferred;	/* Deferred transmits */
   7.581 +	u32 xmt_sngl_coll;	/* Transmits that had 1 and only 1 coll. */
   7.582 +	u32 xmt_mlt_coll;	/* Transmits that had multiple coll. */
   7.583 +	u32 xmt_ttl_coll;	/* Transmits that had 1+ collisions. */
   7.584 +	u32 rcv_gd_frames;	/* Good frames received */
   7.585 +	u32 rcv_crc_errs;	/* Aligned frames that had a CRC error */
   7.586 +	u32 rcv_algn_errs;	/* Receives that had alignment errors */
   7.587 +	u32 rcv_rsrc_err;	/* Good frame dropped cuz no resources */
   7.588 +	u32 rcv_oruns;	/* Overrun errors - bus was busy */
   7.589 +	u32 rcv_err_coll;	/* Received frms. that encountered coll. */
   7.590 +	u32 rcv_shrt_frames;	/* Received frames that were to short */
   7.591 +} basic_cntr_t;
   7.592 +
   7.593 +/* 82558 extended statistic counters */
   7.594 +typedef struct _ext_cntr_t {
   7.595 +	u32 xmt_fc_frames;
   7.596 +	u32 rcv_fc_frames;
   7.597 +	u32 rcv_fc_unsupported;
   7.598 +} ext_cntr_t;
   7.599 +
   7.600 +/* 82559 TCO statistic counters */
   7.601 +typedef struct _tco_cntr_t {
   7.602 +	u16 xmt_tco_frames;
   7.603 +	u16 rcv_tco_frames;
   7.604 +} tco_cntr_t;
   7.605 +
   7.606 +/* Structures to access thet physical dump area */
   7.607 +/* Use one of these types, according to the statisitcal counters mode,
   7.608 +   to cast the pointer to the physical dump area and access the cmd_complete
   7.609 +   DWORD. */
   7.610 +
   7.611 +/* 557-mode : only basic counters + cmd_complete */
   7.612 +typedef struct _err_cntr_557_t {
   7.613 +	basic_cntr_t basic_stats;
   7.614 +	u32 cmd_complete;
   7.615 +} err_cntr_557_t;
   7.616 +
   7.617 +/* 558-mode : basic + extended counters + cmd_complete */
   7.618 +typedef struct _err_cntr_558_t {
   7.619 +	basic_cntr_t basic_stats;
   7.620 +	ext_cntr_t extended_stats;
   7.621 +	u32 cmd_complete;
   7.622 +} err_cntr_558_t;
   7.623 +
   7.624 +/* 559-mode : basic + extended + TCO counters + cmd_complete */
   7.625 +typedef struct _err_cntr_559_t {
   7.626 +	basic_cntr_t basic_stats;
   7.627 +	ext_cntr_t extended_stats;
   7.628 +	tco_cntr_t tco_stats;
   7.629 +	u32 cmd_complete;
   7.630 +} err_cntr_559_t;
   7.631 +
   7.632 +/* This typedef defines the struct needed to hold the largest number of counters */
   7.633 +typedef err_cntr_559_t max_counters_t;
   7.634 +
   7.635 +/* Different statistical-counters mode the controller may be in */
   7.636 +typedef enum _stat_mode_t {
   7.637 +	E100_BASIC_STATS = 0,	/* 82557 stats : 16 counters / 16 dw */
   7.638 +	E100_EXTENDED_STATS,	/* 82558 stats : 19 counters / 19 dw */
   7.639 +	E100_TCO_STATS		/* 82559 stats : 21 counters / 20 dw */
   7.640 +} stat_mode_t;
   7.641 +
   7.642 +/* dump statistical counters complete codes */
   7.643 +#define DUMP_STAT_COMPLETED	0xA005
   7.644 +#define DUMP_RST_STAT_COMPLETED	0xA007
   7.645 +
   7.646 +/* Command Block (CB) Generic Header Structure*/
   7.647 +typedef struct _cb_header_t {
   7.648 +	u16 cb_status;	/* Command Block Status */
   7.649 +	u16 cb_cmd;	/* Command Block Command */
   7.650 +	u32 cb_lnk_ptr;	/* Link To Next CB */
   7.651 +} cb_header_t __attribute__ ((__packed__));
   7.652 +
   7.653 +//* Individual Address Command Block (IA_CB)*/
   7.654 +typedef struct _ia_cb_t {
   7.655 +	cb_header_t ia_cb_hdr;
   7.656 +	u8 ia_addr[ETH_ALEN];
   7.657 +} ia_cb_t __attribute__ ((__packed__));
   7.658 +
   7.659 +/* Configure Command Block (CONFIG_CB)*/
   7.660 +typedef struct _config_cb_t {
   7.661 +	cb_header_t cfg_cbhdr;
   7.662 +	u8 cfg_byte[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
   7.663 +} config_cb_t __attribute__ ((__packed__));
   7.664 +
   7.665 +/* MultiCast Command Block (MULTICAST_CB)*/
   7.666 +typedef struct _multicast_cb_t {
   7.667 +	cb_header_t mc_cbhdr;
   7.668 +	u16 mc_count;	/* Number of multicast addresses */
   7.669 +	u8 mc_addr[(ETH_ALEN * MAX_MULTICAST_ADDRS)];
   7.670 +} mltcst_cb_t __attribute__ ((__packed__));
   7.671 +
   7.672 +#define UCODE_MAX_DWORDS	134
   7.673 +/* Load Microcode Command Block (LOAD_UCODE_CB)*/
   7.674 +typedef struct _load_ucode_cb_t {
   7.675 +	cb_header_t load_ucode_cbhdr;
   7.676 +	u32 ucode_dword[UCODE_MAX_DWORDS];
   7.677 +} load_ucode_cb_t __attribute__ ((__packed__));
   7.678 +
   7.679 +/* Load Programmable Filter Data*/
   7.680 +typedef struct _filter_cb_t {
   7.681 +	cb_header_t filter_cb_hdr;
   7.682 +	u32 filter_data[MAX_FILTER];
   7.683 +} filter_cb_t __attribute__ ((__packed__));
   7.684 +
   7.685 +/* NON_TRANSMIT_CB -- Generic Non-Transmit Command Block 
   7.686 + */
   7.687 +typedef struct _nxmit_cb_t {
   7.688 +	union {
   7.689 +		config_cb_t config;
   7.690 +		ia_cb_t setup;
   7.691 +		load_ucode_cb_t load_ucode;
   7.692 +		mltcst_cb_t multicast;
   7.693 +		filter_cb_t filter;
   7.694 +	} ntcb;
   7.695 +} nxmit_cb_t __attribute__ ((__packed__));
   7.696 +
   7.697 +/*Block for queuing for postponed execution of the non-transmit commands*/
   7.698 +typedef struct _nxmit_cb_entry_t {
   7.699 +	struct list_head list_elem;
   7.700 +	nxmit_cb_t *non_tx_cmd;
   7.701 +	dma_addr_t dma_addr;
   7.702 +	unsigned long expiration_time;
   7.703 +} nxmit_cb_entry_t;
   7.704 +
   7.705 +/* States for postponed non tx commands execution */
   7.706 +typedef enum _non_tx_cmd_state_t {
   7.707 +	E100_NON_TX_IDLE = 0,	/* No queued NON-TX commands */
   7.708 +	E100_WAIT_TX_FINISH,	/* Wait for completion of the TX activities */
   7.709 +	E100_WAIT_NON_TX_FINISH	/* Wait for completion of the non TX command */
   7.710 +} non_tx_cmd_state_t;
   7.711 +
   7.712 +/* some defines for the ipcb */
   7.713 +#define IPCB_IP_CHECKSUM_ENABLE 	BIT_4
   7.714 +#define IPCB_TCPUDP_CHECKSUM_ENABLE	BIT_5
   7.715 +#define IPCB_TCP_PACKET 		BIT_6
   7.716 +#define IPCB_LARGESEND_ENABLE 		BIT_7
   7.717 +#define IPCB_HARDWAREPARSING_ENABLE	BIT_0
   7.718 +#define IPCB_INSERTVLAN_ENABLE 		BIT_1
   7.719 +#define IPCB_IP_ACTIVATION_DEFAULT      IPCB_HARDWAREPARSING_ENABLE
   7.720 +
   7.721 +/* Transmit Buffer Descriptor (TBD)*/
   7.722 +typedef struct _tbd_t {
   7.723 +	u32 tbd_buf_addr;	/* Physical Transmit Buffer Address */
   7.724 +	u16 tbd_buf_cnt;	/* Actual Count Of Bytes */
   7.725 +	u16 padd;
   7.726 +} tbd_t __attribute__ ((__packed__));
   7.727 +
   7.728 +/* d102 specific fields */
   7.729 +typedef struct _tcb_ipcb_t {
   7.730 +	u16 schedule_low;
   7.731 +	u8 ip_schedule;
   7.732 +	u8 ip_activation_high;
   7.733 +	u16 vlan;
   7.734 +	u8 ip_header_offset;
   7.735 +	u8 tcp_header_offset;
   7.736 +	union {
   7.737 +		u32 sec_rec_phys_addr;
   7.738 +		u32 tbd_zero_address;
   7.739 +	} tbd_sec_addr;
   7.740 +	union {
   7.741 +		u16 sec_rec_size;
   7.742 +		u16 tbd_zero_size;
   7.743 +	} tbd_sec_size;
   7.744 +	u16 total_tcp_payload;
   7.745 +} tcb_ipcb_t __attribute__ ((__packed__));
   7.746 +
   7.747 +#define E100_TBD_ARRAY_SIZE (2+MAX_SKB_FRAGS)
   7.748 +
   7.749 +/* Transmit Command Block (TCB)*/
   7.750 +struct _tcb_t {
   7.751 +	cb_header_t tcb_hdr;
   7.752 +	u32 tcb_tbd_ptr;	/* TBD address */
   7.753 +	u16 tcb_cnt;	/* Data Bytes In TCB past header */
   7.754 +	u8 tcb_thrshld;	/* TX Threshold for FIFO Extender */
   7.755 +	u8 tcb_tbd_num;
   7.756 +
   7.757 +	union {
   7.758 +		tcb_ipcb_t ipcb;	/* d102 ipcb fields */
   7.759 +		tbd_t tbd_array[E100_TBD_ARRAY_SIZE];
   7.760 +	} tcbu;
   7.761 +
   7.762 +	/* From here onward we can dump anything we want as long as the
   7.763 +	 * size of the total structure is a multiple of a paragraph
   7.764 +	 * boundary ( i.e. -16 bit aligned ).
   7.765 +	 */
   7.766 +	tbd_t *tbd_ptr;
   7.767 +
   7.768 +	u32 tcb_tbd_dflt_ptr;	/* TBD address for non-segmented packet */
   7.769 +	u32 tcb_tbd_expand_ptr;	/* TBD address for segmented packet */
   7.770 +
   7.771 +	struct sk_buff *tcb_skb;	/* the associated socket buffer */
   7.772 +	dma_addr_t tcb_phys;	/* phys addr of the TCB */
   7.773 +} __attribute__ ((__packed__));
   7.774 +
   7.775 +#define _TCB_T_
   7.776 +typedef struct _tcb_t tcb_t;
   7.777 +
   7.778 +/* Receive Frame Descriptor (RFD) - will be using the simple model*/
   7.779 +struct _rfd_t {
   7.780 +	/* 8255x */
   7.781 +	cb_header_t rfd_header;
   7.782 +	u32 rfd_rbd_ptr;	/* Receive Buffer Descriptor Addr */
   7.783 +	u16 rfd_act_cnt;	/* Number Of Bytes Received */
   7.784 +	u16 rfd_sz;	/* Number Of Bytes In RFD */
   7.785 +	/* D102 aka Gamla */
   7.786 +	u16 vlanid;
   7.787 +	u8 rcvparserstatus;
   7.788 +	u8 reserved;
   7.789 +	u16 securitystatus;
   7.790 +	u8 checksumstatus;
   7.791 +	u8 zerocopystatus;
   7.792 +	u8 pad[8];	/* data should be 16 byte aligned */
   7.793 +	u8 data[RFD_DATA_SIZE];
   7.794 +
   7.795 +} __attribute__ ((__packed__));
   7.796 +
   7.797 +#define _RFD_T_
   7.798 +typedef struct _rfd_t rfd_t;
   7.799 +
   7.800 +/* Receive Buffer Descriptor (RBD)*/
   7.801 +typedef struct _rbd_t {
   7.802 +	u16 rbd_act_cnt;	/* Number Of Bytes Received */
   7.803 +	u16 rbd_filler;
   7.804 +	u32 rbd_lnk_addr;	/* Link To Next RBD */
   7.805 +	u32 rbd_rcb_addr;	/* Receive Buffer Address */
   7.806 +	u16 rbd_sz;	/* Receive Buffer Size */
   7.807 +	u16 rbd_filler1;
   7.808 +} rbd_t __attribute__ ((__packed__));
   7.809 +
   7.810 +/*
   7.811 + * This structure is used to maintain a FIFO access to a resource that is 
   7.812 + * maintained as a circular queue. The resource to be maintained is pointed
   7.813 + * to by the "data" field in the structure below. In this driver the TCBs', 
   7.814 + * TBDs' & RFDs' are maintained  as a circular queue & are managed thru this
   7.815 + * structure.
   7.816 + */
   7.817 +typedef struct _buf_pool_t {
   7.818 +	unsigned int head;	/* index to first used resource */
   7.819 +	unsigned int tail;	/* index to last used resource */
   7.820 +	void *data;		/* points to resource pool */
   7.821 +} buf_pool_t;
   7.822 +
   7.823 +/*Rx skb holding structure*/
   7.824 +struct rx_list_elem {
   7.825 +	struct list_head list_elem;
   7.826 +	dma_addr_t dma_addr;
   7.827 +	struct sk_buff *skb;
   7.828 +};
   7.829 +
   7.830 +enum next_cu_cmd_e { RESUME_NO_WAIT = 0, RESUME_WAIT, START_WAIT };
   7.831 +enum zlock_state_e { ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING };
   7.832 +enum tx_queue_stop_type { LONG_STOP = 0, SHORT_STOP };
   7.833 +
   7.834 +/* 64 bit aligned size */
   7.835 +#define E100_SIZE_64A(X) ((sizeof(X) + 7) & ~0x7)
   7.836 +
   7.837 +typedef struct _bd_dma_able_t {
   7.838 +	char selftest[E100_SIZE_64A(self_test_t)];
   7.839 +	char stats_counters[E100_SIZE_64A(max_counters_t)];
   7.840 +} bd_dma_able_t;
   7.841 +
   7.842 +/* bit masks for bool parameters */
   7.843 +#define PRM_XSUMRX       0x00000001
   7.844 +#define PRM_UCODE        0x00000002
   7.845 +#define PRM_FC           0x00000004
   7.846 +#define PRM_IFS          0x00000008
   7.847 +#define PRM_BUNDLE_SMALL 0x00000010
   7.848 +
   7.849 +struct cfg_params {
   7.850 +	int e100_speed_duplex;
   7.851 +	int RxDescriptors;
   7.852 +	int TxDescriptors;
   7.853 +	int IntDelay;
   7.854 +	int BundleMax;
   7.855 +	int ber;
   7.856 +	u32 b_params;
   7.857 +};
   7.858 +struct ethtool_lpbk_data{
   7.859 +        dma_addr_t dma_handle;
   7.860 +        tcb_t *tcb;
   7.861 +        rfd_t *rfd;
   7.862 +
   7.863 +};
   7.864 +
   7.865 +struct e100_private {
   7.866 +	struct vlan_group *vlgrp;
   7.867 +	u32 flags;		/* board management flags */
   7.868 +	u32 tx_per_underrun;	/* number of good tx frames per underrun */
   7.869 +	unsigned int tx_count;	/* count of tx frames, so we can request an interrupt */
   7.870 +	u8 tx_thld;		/* stores transmit threshold */
   7.871 +	u16 eeprom_size;
   7.872 +	u32 pwa_no;		/* PWA: xxxxxx-0xx */
   7.873 +	u8 perm_node_address[ETH_ALEN];
   7.874 +	struct list_head active_rx_list;	/* list of rx buffers */
   7.875 +	struct list_head rx_struct_pool;	/* pool of rx buffer struct headers */
   7.876 +	u16 rfd_size;			/* size of the adapter's RFD struct */
   7.877 +	int skb_req;			/* number of skbs neede by the adapter */
   7.878 +	u8 intr_mask;			/* mask for interrupt status */
   7.879 +
   7.880 +	void *dma_able;			/* dma allocated structs */
   7.881 +	dma_addr_t dma_able_phys;
   7.882 +	self_test_t *selftest;		/* pointer to self test area */
   7.883 +	dma_addr_t selftest_phys;	/* phys addr of selftest */
   7.884 +	max_counters_t *stats_counters;	/* pointer to stats table */
   7.885 +	dma_addr_t stat_cnt_phys;	/* phys addr of stat counter area */
   7.886 +
   7.887 +	stat_mode_t stat_mode;	/* statistics mode: extended, TCO, basic */
   7.888 +	scb_t *scb;		/* memory mapped ptr to 82557 scb */
   7.889 +
   7.890 +	tcb_t *last_tcb;	/* pointer to last tcb sent */
   7.891 +	buf_pool_t tcb_pool;	/* adapter's TCB array */
   7.892 +	dma_addr_t tcb_phys;	/* phys addr of start of TCBs */
   7.893 +
   7.894 +	u16 cur_line_speed;
   7.895 +	u16 cur_dplx_mode;
   7.896 +
   7.897 +	struct net_device *device;
   7.898 +	struct pci_dev *pdev;
   7.899 +	struct driver_stats drv_stats;
   7.900 +
   7.901 +	u8 rev_id;		/* adapter PCI revision ID */
   7.902 +
   7.903 +	unsigned int phy_addr;	/* address of PHY component */
   7.904 +	unsigned int PhyId;	/* ID of PHY component */
   7.905 +	unsigned int PhyState;	/* state for the fix squelch algorithm */
   7.906 +	unsigned int PhyDelay;	/* delay for the fix squelch algorithm */
   7.907 +
   7.908 +	/* Lock defintions for the driver */
   7.909 +	spinlock_t bd_lock;		/* board lock */
   7.910 +	spinlock_t bd_non_tx_lock;	/* Non transmit command lock  */
   7.911 +	spinlock_t config_lock;		/* config block lock */
   7.912 +	spinlock_t mdi_access_lock;	/* mdi lock */
   7.913 +
   7.914 +	struct timer_list watchdog_timer;	/* watchdog timer id */
   7.915 +
   7.916 +	/* non-tx commands parameters */
   7.917 +	struct timer_list nontx_timer_id;	/* non-tx timer id */
   7.918 +	struct list_head non_tx_cmd_list;
   7.919 +	non_tx_cmd_state_t non_tx_command_state;
   7.920 +	nxmit_cb_entry_t *same_cmd_entry[CB_MAX_NONTX_CMD];
   7.921 +
   7.922 +	enum next_cu_cmd_e next_cu_cmd;
   7.923 +
   7.924 +	/* Zero Locking Algorithm data members */
   7.925 +	enum zlock_state_e zlock_state;
   7.926 +	u8 zlock_read_data[16];	/* number of times each value 0-15 was read */
   7.927 +	u16 zlock_read_cnt;	/* counts number of reads */
   7.928 +	ulong zlock_sleep_cnt;	/* keeps track of "sleep" time */
   7.929 +
   7.930 +	u8 config[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
   7.931 +
   7.932 +	/* IFS params */
   7.933 +	u8 ifs_state;
   7.934 +	u8 ifs_value;
   7.935 +
   7.936 +	struct cfg_params params;	/* adapter's command line parameters */
   7.937 +
   7.938 +	u32 speed_duplex_caps;	/* adapter's speed/duplex capabilities */
   7.939 +
   7.940 +	/* WOL params for ethtool */
   7.941 +	u32 wolsupported;
   7.942 +	u32 wolopts;
   7.943 +	u16 ip_lbytes;
   7.944 +	struct ethtool_lpbk_data loopback;
   7.945 +	struct timer_list blink_timer;	/* led blink timer id */
   7.946 +
   7.947 +#ifdef CONFIG_PM
   7.948 +	u32 pci_state[16];
   7.949 +#endif
   7.950 +	char ifname[IFNAMSIZ];
   7.951 +#ifdef E100_CU_DEBUG	
   7.952 +	u8 last_cmd;
   7.953 +	u8 last_sub_cmd;
   7.954 +#endif	
   7.955 +};
   7.956 +
   7.957 +#define E100_AUTONEG        0
   7.958 +#define E100_SPEED_10_HALF  1
   7.959 +#define E100_SPEED_10_FULL  2
   7.960 +#define E100_SPEED_100_HALF 3
   7.961 +#define E100_SPEED_100_FULL 4
   7.962 +
   7.963 +/********* function prototypes *************/
   7.964 +extern void e100_isolate_driver(struct e100_private *bdp);
   7.965 +extern void e100_sw_reset(struct e100_private *bdp, u32 reset_cmd);
   7.966 +extern u8 e100_start_cu(struct e100_private *bdp, tcb_t *tcb);
   7.967 +extern void e100_free_non_tx_cmd(struct e100_private *bdp,
   7.968 +				 nxmit_cb_entry_t *non_tx_cmd);
   7.969 +extern nxmit_cb_entry_t *e100_alloc_non_tx_cmd(struct e100_private *bdp);
   7.970 +extern unsigned char e100_exec_non_cu_cmd(struct e100_private *bdp,
   7.971 +					  nxmit_cb_entry_t *cmd);
   7.972 +extern unsigned char e100_selftest(struct e100_private *bdp, u32 *st_timeout,
   7.973 +				   u32 *st_result);
   7.974 +extern unsigned char e100_get_link_state(struct e100_private *bdp);
   7.975 +extern unsigned char e100_wait_scb(struct e100_private *bdp);
   7.976 +
   7.977 +extern void e100_deisolate_driver(struct e100_private *bdp, u8 full_reset);
   7.978 +extern unsigned char e100_configure_device(struct e100_private *bdp);
   7.979 +#ifdef E100_CU_DEBUG
   7.980 +extern unsigned char e100_cu_unknown_state(struct e100_private *bdp);
   7.981 +#endif
   7.982 +
   7.983 +#define ROM_TEST_FAIL		0x01
   7.984 +#define REGISTER_TEST_FAIL	0x02
   7.985 +#define SELF_TEST_FAIL		0x04
   7.986 +#define TEST_TIMEOUT		0x08
   7.987 +
   7.988 +enum test_offsets {
   7.989 +	E100_EEPROM_TEST_FAIL = 0,
   7.990 +	E100_CHIP_TIMEOUT,
   7.991 +	E100_ROM_TEST_FAIL,
   7.992 +	E100_REG_TEST_FAIL,
   7.993 +	E100_MAC_TEST_FAIL,
   7.994 +	E100_LPBK_MAC_FAIL,
   7.995 +	E100_LPBK_PHY_FAIL,
   7.996 +	E100_MAX_TEST_RES
   7.997 +};
   7.998 +
   7.999 +#endif