1.1 --- a/xen/arch/ia64/xen/vcpu.c	Fri Oct 14 14:11:12 2005 -0600
     1.2 +++ b/xen/arch/ia64/xen/vcpu.c	Fri Oct 14 21:09:43 2005 -0600
     1.3 @@ -1274,11 +1274,9 @@ unsigned long vhpt_translate_count = 0;
     1.4  
     1.5  IA64FAULT vcpu_translate(VCPU *vcpu, UINT64 address, BOOLEAN is_data, UINT64 *pteval, UINT64 *itir, UINT64 *iha)
     1.6  {
     1.7 -	unsigned long pta, pta_mask, pte, ps, rid, itir_addr;
     1.8 +	unsigned long pta, pte, rid, rr;
     1.9  	int i;
    1.10  	TR_ENTRY *trp;
    1.11 -	IA64FAULT fault;
    1.12 -	ia64_rr rr;
    1.13  
    1.14  	if (!(address >> 61)) {
    1.15  		if (!PSCB(vcpu,metaphysical_mode)) {
    1.16 @@ -1295,7 +1293,9 @@ IA64FAULT vcpu_translate(VCPU *vcpu, UIN
    1.17  		phys_translate_count++;
    1.18  		return IA64_NO_FAULT;
    1.19  	}
    1.20 -	rid = virtualize_rid(vcpu,get_rr(address) & RR_RID_MASK);
    1.21 +
    1.22 +	rr = PSCB(vcpu,rrs)[address>>61];
    1.23 +	rid = rr & RR_RID_MASK;
    1.24  	if (is_data) {
    1.25  		if (vcpu_quick_region_check(vcpu->arch.dtr_regions,address)) {
    1.26  			for (trp = vcpu->arch.dtrs, i = NDTRS; i; i--, trp++) {
    1.27 @@ -1340,38 +1340,34 @@ IA64FAULT vcpu_translate(VCPU *vcpu, UIN
    1.28  		//return (is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR);
    1.29  	}
    1.30  
    1.31 +	*itir = rr & (RR_RID_MASK | RR_PS_MASK);
    1.32 +	// note: architecturally, iha is optionally set for alt faults but
    1.33 +	// xenlinux depends on it so should document it as part of PV interface
    1.34  	vcpu_thash(vcpu, address, iha);
    1.35 -	rr.rrval = PSCB(vcpu,rrs)[address>>61];
    1.36 -	fault = is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
    1.37 -	if (!rr.ve || !(pta & IA64_PTA_VE)) {
    1.38 -	// architecturally, iha is optionally set for alt faults but xenlinux
    1.39 -	// depends on it so should document it as part of PV interface
    1.40 -		fault += IA64_ALT_INST_TLB_VECTOR - IA64_INST_TLB_VECTOR;
    1.41 -	}
    1.42 +	if (!(rr & RR_VE_MASK) || !(pta & IA64_PTA_VE))
    1.43 +		return (is_data ? IA64_ALT_DATA_TLB_VECTOR : IA64_ALT_INST_TLB_VECTOR);
    1.44  
    1.45  	/* avoid recursively walking (short format) VHPT */
    1.46 -	else if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) != 0) {
    1.47 +	if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) == 0)
    1.48 +		return (is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR);
    1.49  
    1.50 -		if (__copy_from_user(&pte, (void *)(*iha), sizeof(pte)) != 0)
    1.51 -			// virtual VHPT walker "missed" in TLB
    1.52 -			fault = IA64_VHPT_FAULT;
    1.53 +	if (__copy_from_user(&pte, (void *)(*iha), sizeof(pte)) != 0)
    1.54 +		// virtual VHPT walker "missed" in TLB
    1.55 +		return IA64_VHPT_FAULT;
    1.56  
    1.57 -		/*
    1.58 -		* Optimisation: this VHPT walker aborts on not-present pages
    1.59 -		* instead of inserting a not-present translation, this allows
    1.60 -		* vectoring directly to the miss handler.
    1.61 -		*/
    1.62 -		else if (pte & _PAGE_P) {
    1.63 -			*pteval = pte;
    1.64 -			vhpt_translate_count++;
    1.65 -			return IA64_NO_FAULT;
    1.66 -		}
    1.67 -	}
    1.68 +	/*
    1.69 +	* Optimisation: this VHPT walker aborts on not-present pages
    1.70 +	* instead of inserting a not-present translation, this allows
    1.71 +	* vectoring directly to the miss handler.
    1.72 +	*/
    1.73 +	if (!(pte & _PAGE_P))
    1.74 +		return (is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR);
    1.75  
    1.76 -	// for VHPT fault, use itir based on iha, not on fault address
    1.77 -	itir_addr = (fault == IA64_VHPT_FAULT) ? *iha : address;
    1.78 -	*itir = vcpu_get_itir_on_fault(vcpu,itir_addr);
    1.79 -	return fault;
    1.80 +	/* found mapping in guest VHPT! */
    1.81 +	*itir = rr & RR_PS_MASK;
    1.82 +	*pteval = pte;
    1.83 +	vhpt_translate_count++;
    1.84 +	return IA64_NO_FAULT;
    1.85  }
    1.86  
    1.87  IA64FAULT vcpu_tpa(VCPU *vcpu, UINT64 vadr, UINT64 *padr)