ia64/xen-unstable

changeset 14906:3b01a4bd5763

hvm rombios: Do not screw around with the PIT in the BIOS 32-bit
extensions. mdelay() can more easily be implemented by polling the
DRAM refresh bit in port 0x61. And this does not mess with state that
a guest may be relying on.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Tue Apr 24 12:14:57 2007 +0100 (2007-04-24)
parents f71d167a6c6d
children d250c75ea59a
files tools/firmware/rombios/32bit/util.c
line diff
     1.1 --- a/tools/firmware/rombios/32bit/util.c	Tue Apr 24 12:13:58 2007 +0100
     1.2 +++ b/tools/firmware/rombios/32bit/util.c	Tue Apr 24 12:14:57 2007 +0100
     1.3 @@ -394,57 +394,17 @@ int vprintf(const char *fmt, va_list ap)
     1.4      return 0;
     1.5  }
     1.6  
     1.7 -
     1.8 -/*
     1.9 - * sleep by synchronizing with the PIT on channel 2
    1.10 - * http://bochs.sourceforge.net/techspec/intel-82c54-timer.pdf.gz
    1.11 - */
    1.12 -#define PIT_CTR2       0x80
    1.13 -#define PIT_CTR1       0x40
    1.14 -#define PIT_CTR0       0x00
    1.15 -
    1.16 -#define PIT_RW_LSB     0x10
    1.17 -
    1.18 -#define PIT_MODE0      0x0
    1.19 -
    1.20 -#define PIT_CTR_16BIT  0x0
    1.21 -
    1.22 -#define PIT_CMD_LATCH  0x0
    1.23 -
    1.24 -#define PORT_PIT_CMD     0x43
    1.25 -#define PORT_PIT_CTR2    0x42
    1.26 -#define PORT_PIT_CTR1    0x41
    1.27 -#define PORT_PIT_CTR0    0x40
    1.28 -
    1.29 -#define PIT_FREQ         1193182 /* Hz */
    1.30 -
    1.31 -#define PORT_PPI         0x61
    1.32 -
    1.33  void mssleep(uint32_t waittime)
    1.34  {
    1.35 -	long int timeout = 0;
    1.36 -	uint8_t last = 0x0;
    1.37 -	uint8_t old_ppi = inb(PORT_PPI);
    1.38 -
    1.39 -	/* use ctr2; ctr0 is used by the Bochs BIOS */
    1.40 -	/* ctr2 drives speaker -- turn it off */
    1.41 -	outb(PORT_PPI, old_ppi & 0xfc);
    1.42 -
    1.43 -	outb(PORT_PIT_CMD, PIT_CTR2 | PIT_RW_LSB | PIT_MODE0 | PIT_CTR_16BIT);
    1.44 -	outb(PORT_PIT_CTR2, last);         /* start countdown */
    1.45 +    uint32_t i;
    1.46 +    uint8_t  x, y = inb(0x61) & 0x10;
    1.47  
    1.48 -	while (timeout < (waittime * PIT_FREQ / 1000)) {
    1.49 -		uint8_t cur, delta;
    1.50 -		outb(PORT_PIT_CMD, PIT_CTR2 | PIT_CMD_LATCH);
    1.51 -		cur = inb(PORT_PIT_CTR2);
    1.52 -		delta = last - cur;
    1.53 -		timeout += delta;
    1.54 -		last = cur;
    1.55 -	}
    1.56 -	/* turn ctr2 off */
    1.57 -	outb(PORT_PIT_CMD, PIT_CTR2 | PIT_RW_LSB | PIT_MODE0 | PIT_CTR_16BIT);
    1.58 -	outb(PORT_PIT_CTR2, 0xff); /* start countdown */
    1.59 -	outb(PORT_PIT_CTR2, 0x0);  /* stop */
    1.60 -
    1.61 -	outb(PORT_PPI, old_ppi);
    1.62 +    /* Poll the DRAM refresh timer: I/O port 61h, bit 4 toggles every 15us. */
    1.63 +    waittime *= 67; /* Convert milliseconds to multiples of 15us. */
    1.64 +    for ( i = 0; i < waittime; i++ )
    1.65 +    {
    1.66 +        while ( (x = inb(0x61) & 0x10) == y )
    1.67 +            continue;
    1.68 +        y = x;
    1.69 +    }
    1.70  }