1.1 --- a/xen/arch/x86/nmi.c	Tue Nov 15 16:24:31 2005 +0100
     1.2 +++ b/xen/arch/x86/nmi.c	Tue Nov 15 16:57:02 2005 +0100
     1.3 @@ -49,8 +49,6 @@ static unsigned int nmi_timer_ticks[NR_C
     1.4  #define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
     1.5  #define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED
     1.6  
     1.7 -#define MSR_P4_PERFCTR0		0x300
     1.8 -#define MSR_P4_CCCR0		0x360
     1.9  #define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
    1.10  #define P4_CCCR_OVF_PMI0	(1<<26)
    1.11  #define P4_CCCR_OVF_PMI1	(1<<27)
    1.12 @@ -61,13 +59,10 @@ static unsigned int nmi_timer_ticks[NR_C
    1.13  #define P4_CCCR_ESCR_SELECT(N)	((N)<<13)
    1.14  #define P4_CCCR_ENABLE		(1<<12)
    1.15  /* 
    1.16 - * Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
    1.17 + * Set up IQ_PERFCTR0 to behave like a clock, by having IQ_CCCR0 filter
    1.18   * CRU_ESCR0 (with any non-null event selector) through a complemented
    1.19   * max threshold. [IA32-Vol3, Section 14.9.9] 
    1.20   */
    1.21 -#define MSR_P4_IQ_COUNTER0	0x30C
    1.22 -#define MSR_P4_IQ_CCCR0		0x36C
    1.23 -#define MSR_P4_CRU_ESCR0	0x3B8 /* ESCR no. 4 */
    1.24  #define P4_NMI_CRU_ESCR0	P4_ESCR_EVENT_SELECT(0x3F)
    1.25  #define P4_NMI_IQ_CCCR0	\
    1.26      (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
    1.27 @@ -183,7 +178,7 @@ static int __pminit setup_p4_watchdog(vo
    1.28      if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
    1.29          return 0;
    1.30  
    1.31 -    nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
    1.32 +    nmi_perfctr_msr = MSR_P4_IQ_PERFCTR0;
    1.33      nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
    1.34      if ( smp_num_siblings == 2 )
    1.35          nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
    1.36 @@ -196,13 +191,13 @@ static int __pminit setup_p4_watchdog(vo
    1.37      clear_msr_range(0x3C0, 6);
    1.38      clear_msr_range(0x3C8, 6);
    1.39      clear_msr_range(0x3E0, 2);
    1.40 -    clear_msr_range(MSR_P4_CCCR0, 18);
    1.41 -    clear_msr_range(MSR_P4_PERFCTR0, 18);
    1.42 +    clear_msr_range(MSR_P4_BPU_CCCR0, 18);
    1.43 +    clear_msr_range(MSR_P4_BPU_PERFCTR0, 18);
    1.44          
    1.45      wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
    1.46      wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
    1.47 -    Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
    1.48 -    wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
    1.49 +    Dprintk("setting P4_IQ_PERFCTR0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
    1.50 +    wrmsr(MSR_P4_IQ_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
    1.51      apic_write(APIC_LVTPC, APIC_DM_NMI);
    1.52      wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
    1.53  
    1.54 @@ -314,7 +309,7 @@ void nmi_watchdog_tick(struct cpu_user_r
    1.55  
    1.56      if ( nmi_perfctr_msr )
    1.57      {
    1.58 -        if ( nmi_perfctr_msr == MSR_P4_IQ_COUNTER0 )
    1.59 +        if ( nmi_perfctr_msr == MSR_P4_IQ_PERFCTR0 )
    1.60          {
    1.61              /*
    1.62               * P4 quirks:

     2.1 --- a/xen/include/asm-x86/msr.h	Tue Nov 15 16:24:31 2005 +0100
     2.2 +++ b/xen/include/asm-x86/msr.h	Tue Nov 15 16:57:02 2005 +0100
     2.3 @@ -133,36 +133,29 @@
     2.4  #define MSR_IA32_SYSENTER_ESP		0x175
     2.5  #define MSR_IA32_SYSENTER_EIP		0x176
     2.6  
     2.7 -#define MSR_IA32_MCG_CAP       0x179
     2.8 -#define MSR_IA32_MCG_STATUS        0x17a
     2.9 -#define MSR_IA32_MCG_CTL       0x17b
    2.10 -
    2.11 -#define MSR_MTRRfix64K_00000	0x250
    2.12 -#define MSR_MTRRfix16K_80000	0x258
    2.13 -#define MSR_MTRRfix16K_A0000	0x259
    2.14 -#define MSR_MTRRfix4K_C0000	0x268
    2.15 -#define MSR_MTRRfix4K_C8000	0x269
    2.16 -#define MSR_MTRRfix4K_D0000	0x26a
    2.17 -#define MSR_MTRRfix4K_D8000	0x26b
    2.18 -#define MSR_MTRRfix4K_E0000	0x26c
    2.19 -#define MSR_MTRRfix4K_E8000	0x26d
    2.20 -#define MSR_MTRRfix4K_F0000	0x26e
    2.21 -#define MSR_MTRRfix4K_F8000	0x26f
    2.22 -#define MSR_MTRRdefType		0x2ff
    2.23 -
    2.24 -#define MSR_IA32_MC0_CTL       0x400
    2.25 -#define MSR_IA32_MC0_STATUS        0x401
    2.26 -#define MSR_IA32_MC0_ADDR      0x402
    2.27 -#define MSR_IA32_MC0_MISC      0x403
    2.28 -
    2.29 -#define MSR_IA32_DS_AREA	0x600
    2.30 -
    2.31 -#define MSR_IA32_BBL_CR_CTL		0x119
    2.32 -
    2.33  #define MSR_IA32_MCG_CAP		0x179
    2.34  #define MSR_IA32_MCG_STATUS		0x17a
    2.35  #define MSR_IA32_MCG_CTL		0x17b
    2.36  
    2.37 +/* P4/Xeon+ specific */
    2.38 +#define MSR_IA32_MCG_EAX		0x180
    2.39 +#define MSR_IA32_MCG_EBX		0x181
    2.40 +#define MSR_IA32_MCG_ECX		0x182
    2.41 +#define MSR_IA32_MCG_EDX		0x183
    2.42 +#define MSR_IA32_MCG_ESI		0x184
    2.43 +#define MSR_IA32_MCG_EDI		0x185
    2.44 +#define MSR_IA32_MCG_EBP		0x186
    2.45 +#define MSR_IA32_MCG_ESP		0x187
    2.46 +#define MSR_IA32_MCG_EFLAGS		0x188
    2.47 +#define MSR_IA32_MCG_EIP		0x189
    2.48 +#define MSR_IA32_MCG_RESERVED		0x18A
    2.49 +
    2.50 +#define MSR_P6_EVNTSEL0			0x186
    2.51 +#define MSR_P6_EVNTSEL1			0x187
    2.52 +
    2.53 +#define MSR_IA32_PERF_STATUS		0x198
    2.54 +#define MSR_IA32_PERF_CTL		0x199
    2.55 +
    2.56  #define MSR_IA32_THERM_CONTROL		0x19a
    2.57  #define MSR_IA32_THERM_INTERRUPT	0x19b
    2.58  #define MSR_IA32_THERM_STATUS		0x19c
    2.59 @@ -173,47 +166,101 @@
    2.60  #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
    2.61  
    2.62  #define MSR_IA32_DEBUGCTLMSR		0x1d9
    2.63 -#define MSR_IA32_DEBUGCTLMSR_LBR        (1<<0)
    2.64 -#define MSR_IA32_DEBUGCTLMSR_BTF        (1<<1)
    2.65 -#define MSR_IA32_DEBUGCTLMSR_TR		(1<<2)
    2.66 -#define MSR_IA32_DEBUGCTLMSR_BTS        (1<<3)
    2.67 -#define MSR_IA32_DEBUGCTLMSR_BTINT      (1<<4)
    2.68 -
    2.69 -#define MSR_IA32_LASTBRANCH_TOS         0x1da
    2.70 -#define MSR_IA32_LASTBRANCH_0		0x1db
    2.71 -#define MSR_IA32_LASTBRANCH_1		0x1dc
    2.72 -#define MSR_IA32_LASTBRANCH_2		0x1dd
    2.73 -#define MSR_IA32_LASTBRANCH_3		0x1de
    2.74 +#define MSR_IA32_LASTBRANCHFROMIP	0x1db
    2.75 +#define MSR_IA32_LASTBRANCHTOIP		0x1dc
    2.76 +#define MSR_IA32_LASTINTFROMIP		0x1dd
    2.77 +#define MSR_IA32_LASTINTTOIP		0x1de
    2.78  
    2.79  #define MSR_IA32_MC0_CTL		0x400
    2.80  #define MSR_IA32_MC0_STATUS		0x401
    2.81  #define MSR_IA32_MC0_ADDR		0x402
    2.82  #define MSR_IA32_MC0_MISC		0x403
    2.83  
    2.84 -#define MSR_P6_PERFCTR0			0xc1
    2.85 -#define MSR_P6_PERFCTR1			0xc2
    2.86 -#define MSR_P6_EVNTSEL0			0x186
    2.87 -#define MSR_P6_EVNTSEL1			0x187
    2.88 -
    2.89 +/* Pentium IV performance counter MSRs */
    2.90 +#define MSR_P4_BPU_PERFCTR0 		0x300
    2.91 +#define MSR_P4_BPU_PERFCTR1 		0x301
    2.92 +#define MSR_P4_BPU_PERFCTR2 		0x302
    2.93 +#define MSR_P4_BPU_PERFCTR3 		0x303
    2.94 +#define MSR_P4_MS_PERFCTR0 		0x304
    2.95 +#define MSR_P4_MS_PERFCTR1 		0x305
    2.96 +#define MSR_P4_MS_PERFCTR2 		0x306
    2.97 +#define MSR_P4_MS_PERFCTR3 		0x307
    2.98 +#define MSR_P4_FLAME_PERFCTR0 		0x308
    2.99 +#define MSR_P4_FLAME_PERFCTR1 		0x309
   2.100 +#define MSR_P4_FLAME_PERFCTR2 		0x30a
   2.101 +#define MSR_P4_FLAME_PERFCTR3 		0x30b
   2.102 +#define MSR_P4_IQ_PERFCTR0 		0x30c
   2.103 +#define MSR_P4_IQ_PERFCTR1 		0x30d
   2.104 +#define MSR_P4_IQ_PERFCTR2 		0x30e
   2.105 +#define MSR_P4_IQ_PERFCTR3 		0x30f
   2.106 +#define MSR_P4_IQ_PERFCTR4 		0x310
   2.107 +#define MSR_P4_IQ_PERFCTR5 		0x311
   2.108 +#define MSR_P4_BPU_CCCR0 		0x360
   2.109 +#define MSR_P4_BPU_CCCR1 		0x361
   2.110 +#define MSR_P4_BPU_CCCR2 		0x362
   2.111 +#define MSR_P4_BPU_CCCR3 		0x363
   2.112 +#define MSR_P4_MS_CCCR0 		0x364
   2.113 +#define MSR_P4_MS_CCCR1 		0x365
   2.114 +#define MSR_P4_MS_CCCR2 		0x366
   2.115 +#define MSR_P4_MS_CCCR3 		0x367
   2.116 +#define MSR_P4_FLAME_CCCR0 		0x368
   2.117 +#define MSR_P4_FLAME_CCCR1 		0x369
   2.118 +#define MSR_P4_FLAME_CCCR2 		0x36a
   2.119 +#define MSR_P4_FLAME_CCCR3 		0x36b
   2.120 +#define MSR_P4_IQ_CCCR0 		0x36c
   2.121 +#define MSR_P4_IQ_CCCR1 		0x36d
   2.122 +#define MSR_P4_IQ_CCCR2 		0x36e
   2.123 +#define MSR_P4_IQ_CCCR3 		0x36f
   2.124 +#define MSR_P4_IQ_CCCR4 		0x370
   2.125 +#define MSR_P4_IQ_CCCR5 		0x371
   2.126 +#define MSR_P4_ALF_ESCR0 		0x3ca
   2.127 +#define MSR_P4_ALF_ESCR1 		0x3cb
   2.128 +#define MSR_P4_BPU_ESCR0 		0x3b2
   2.129 +#define MSR_P4_BPU_ESCR1 		0x3b3
   2.130 +#define MSR_P4_BSU_ESCR0 		0x3a0
   2.131 +#define MSR_P4_BSU_ESCR1 		0x3a1
   2.132 +#define MSR_P4_CRU_ESCR0 		0x3b8
   2.133 +#define MSR_P4_CRU_ESCR1 		0x3b9
   2.134 +#define MSR_P4_CRU_ESCR2 		0x3cc
   2.135 +#define MSR_P4_CRU_ESCR3 		0x3cd
   2.136 +#define MSR_P4_CRU_ESCR4 		0x3e0
   2.137 +#define MSR_P4_CRU_ESCR5 		0x3e1
   2.138 +#define MSR_P4_DAC_ESCR0 		0x3a8
   2.139 +#define MSR_P4_DAC_ESCR1 		0x3a9
   2.140 +#define MSR_P4_FIRM_ESCR0 		0x3a4
   2.141 +#define MSR_P4_FIRM_ESCR1 		0x3a5
   2.142 +#define MSR_P4_FLAME_ESCR0 		0x3a6
   2.143 +#define MSR_P4_FLAME_ESCR1 		0x3a7
   2.144 +#define MSR_P4_FSB_ESCR0 		0x3a2
   2.145 +#define MSR_P4_FSB_ESCR1 		0x3a3
   2.146 +#define MSR_P4_IQ_ESCR0 		0x3ba
   2.147 +#define MSR_P4_IQ_ESCR1 		0x3bb
   2.148 +#define MSR_P4_IS_ESCR0 		0x3b4
   2.149 +#define MSR_P4_IS_ESCR1 		0x3b5
   2.150 +#define MSR_P4_ITLB_ESCR0 		0x3b6
   2.151 +#define MSR_P4_ITLB_ESCR1 		0x3b7
   2.152 +#define MSR_P4_IX_ESCR0 		0x3c8
   2.153 +#define MSR_P4_IX_ESCR1 		0x3c9
   2.154 +#define MSR_P4_MOB_ESCR0 		0x3aa
   2.155 +#define MSR_P4_MOB_ESCR1 		0x3ab
   2.156 +#define MSR_P4_MS_ESCR0 		0x3c0
   2.157 +#define MSR_P4_MS_ESCR1 		0x3c1
   2.158 +#define MSR_P4_PMH_ESCR0 		0x3ac
   2.159 +#define MSR_P4_PMH_ESCR1 		0x3ad
   2.160 +#define MSR_P4_RAT_ESCR0 		0x3bc
   2.161 +#define MSR_P4_RAT_ESCR1 		0x3bd
   2.162 +#define MSR_P4_SAAT_ESCR0 		0x3ae
   2.163 +#define MSR_P4_SAAT_ESCR1 		0x3af
   2.164 +#define MSR_P4_SSU_ESCR0 		0x3be
   2.165 +#define MSR_P4_SSU_ESCR1 		0x3bf    /* guess: not defined in manual */
   2.166 +#define MSR_P4_TBPU_ESCR0 		0x3c2
   2.167 +#define MSR_P4_TBPU_ESCR1 		0x3c3
   2.168 +#define MSR_P4_TC_ESCR0 		0x3c4
   2.169 +#define MSR_P4_TC_ESCR1 		0x3c5
   2.170 +#define MSR_P4_U2L_ESCR0 		0x3b0
   2.171 +#define MSR_P4_U2L_ESCR1 		0x3b1
   2.172  
   2.173 -/* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
   2.174 -#define MSR_K7_EVNTSEL0            0xC0010000
   2.175 -#define MSR_K7_PERFCTR0            0xC0010004
   2.176 -#define MSR_K7_EVNTSEL1            0xC0010001
   2.177 -#define MSR_K7_PERFCTR1            0xC0010005
   2.178 -#define MSR_K7_EVNTSEL2            0xC0010002
   2.179 -#define MSR_K7_PERFCTR2            0xC0010006
   2.180 -#define MSR_K7_EVNTSEL3            0xC0010003
   2.181 -#define MSR_K7_PERFCTR3            0xC0010007
   2.182 -#define MSR_K8_TOP_MEM1		   0xC001001A
   2.183 -#define MSR_K8_TOP_MEM2		   0xC001001D
   2.184 -#define MSR_K8_SYSCFG		   0xC0000010	
   2.185 -#define MSR_K7_HWCR			0xC0010015
   2.186 -#define MSR_K7_CLK_CTL			0xC001001b
   2.187 -#define MSR_K7_FID_VID_CTL		0xC0010041
   2.188 -#define MSR_K7_VID_STATUS		0xC0010042
   2.189 -
   2.190 -/* K6 MSRs */
   2.191 +/* AMD Defined MSRs */
   2.192  #define MSR_K6_EFER			0xC0000080
   2.193  #define MSR_K6_STAR			0xC0000081
   2.194  #define MSR_K6_WHCR			0xC0000082
   2.195 @@ -222,6 +269,19 @@
   2.196  #define MSR_K6_PSOR			0xC0000087
   2.197  #define MSR_K6_PFIR			0xC0000088
   2.198  
   2.199 +#define MSR_K7_EVNTSEL0			0xC0010000
   2.200 +#define MSR_K7_EVNTSEL1			0xC0010001
   2.201 +#define MSR_K7_EVNTSEL2			0xC0010002
   2.202 +#define MSR_K7_EVNTSEL3			0xC0010003
   2.203 +#define MSR_K7_PERFCTR0			0xC0010004
   2.204 +#define MSR_K7_PERFCTR1			0xC0010005
   2.205 +#define MSR_K7_PERFCTR2			0xC0010006
   2.206 +#define MSR_K7_PERFCTR3			0xC0010007
   2.207 +#define MSR_K7_HWCR			0xC0010015
   2.208 +#define MSR_K7_CLK_CTL			0xC001001b
   2.209 +#define MSR_K7_FID_VID_CTL		0xC0010041
   2.210 +#define MSR_K7_FID_VID_STATUS		0xC0010042
   2.211 +
   2.212  /* Centaur-Hauls/IDT defined MSRs. */
   2.213  #define MSR_IDT_FCR1			0x107
   2.214  #define MSR_IDT_FCR2			0x108