ia64/xen-unstable

changeset 16760:38c73bd5e02d

[IA64] vti fault handler clean up: consolidate vmx_interrupt and vmx_dispatch_interrupt

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Fri Dec 14 13:46:49 2007 -0700 (2007-12-14)
parents 2d0193702170
children fe25c7ec84e8
files xen/arch/ia64/vmx/vmx_ivt.S
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Fri Dec 14 13:44:06 2007 -0700
     1.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Fri Dec 14 13:46:49 2007 -0700
     1.3 @@ -609,151 +609,10 @@ END(vmx_break_fault)
     1.4  /////////////////////////////////////////////////////////////////////////////////////////
     1.5  // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
     1.6  ENTRY(vmx_interrupt)
     1.7 -//    VMX_DBG_FAULT(12)
     1.8 +    VMX_DBG_FAULT(12)
     1.9      mov r31=pr		// prepare to save predicates
    1.10      mov r19=12
    1.11 -    mov r29=cr.ipsr
    1.12 -    ;;
    1.13 -    tbit.z p6,p7=r29,IA64_PSR_VM_BIT
    1.14 -    tbit.z p0,p15=r29,IA64_PSR_I_BIT
    1.15 -    ;;
    1.16 -(p7) br.sptk vmx_dispatch_interrupt
    1.17 -    ;;
    1.18 -    mov r27=ar.rsc		/* M */
    1.19 -    mov r20=r1			/* A */
    1.20 -    mov r25=ar.unat		/* M */
    1.21 -    mov r26=ar.pfs		/* I */
    1.22 -    mov r28=cr.iip		/* M */
    1.23 -    cover			/* B (or nothing) */
    1.24 -    ;;
    1.25 -    mov r1=sp
    1.26 -    ;;
    1.27 -    invala			/* M */
    1.28 -    mov r30=cr.ifs
    1.29 -    ;;
    1.30 -    addl r1=-IA64_PT_REGS_SIZE,r1
    1.31 -    ;;
    1.32 -    adds r17=2*L1_CACHE_BYTES,r1	/* really: biggest cache-line size */
    1.33 -    adds r16=PT(CR_IPSR),r1
    1.34 -    ;;
    1.35 -    lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES
    1.36 -    st8 [r16]=r29			/* save cr.ipsr */
    1.37 -    ;;
    1.38 -    lfetch.fault.excl.nt1 [r17]
    1.39 -    mov r29=b0
    1.40 -    ;;
    1.41 -    adds r16=PT(R8),r1  	/* initialize first base pointer */
    1.42 -    adds r17=PT(R9),r1  	/* initialize second base pointer */
    1.43 -    mov r18=r0      		/* make sure r18 isn't NaT */
    1.44 -    ;;
    1.45 -.mem.offset 0,0; st8.spill [r16]=r8,16
    1.46 -.mem.offset 8,0; st8.spill [r17]=r9,16
    1.47 -        ;;
    1.48 -.mem.offset 0,0; st8.spill [r16]=r10,24
    1.49 -.mem.offset 8,0; st8.spill [r17]=r11,24
    1.50 -        ;;
    1.51 -    st8 [r16]=r28,16		/* save cr.iip */
    1.52 -    st8 [r17]=r30,16		/* save cr.ifs */
    1.53 -    mov r8=ar.fpsr		/* M */
    1.54 -    mov r9=ar.csd
    1.55 -    mov r10=ar.ssd
    1.56 -    movl r11=FPSR_DEFAULT	/* L-unit */
    1.57 -    ;;
    1.58 -    st8 [r16]=r25,16		/* save ar.unat */
    1.59 -    st8 [r17]=r26,16		/* save ar.pfs */
    1.60 -    shl r18=r18,16		/* compute ar.rsc to be used for "loadrs" */
    1.61 -    ;;
    1.62 -    st8 [r16]=r27,16		/* save ar.rsc */
    1.63 -    adds r17=16,r17		/* skip over ar_rnat field */
    1.64 -    ;;
    1.65 -    st8 [r17]=r31,16		/* save predicates */
    1.66 -    adds r16=16,r16		/* skip over ar_bspstore field */
    1.67 -    ;;
    1.68 -    st8 [r16]=r29,16		/* save b0 */
    1.69 -    st8 [r17]=r18,16		/* save ar.rsc value for "loadrs" */
    1.70 -    ;;
    1.71 -.mem.offset 0,0; st8.spill [r16]=r20,16    /* save original r1 */
    1.72 -.mem.offset 8,0; st8.spill [r17]=r12,16
    1.73 -    adds r12=-16,r1    /* switch to kernel memory stack (with 16 bytes of scratch) */
    1.74 -    ;;
    1.75 -.mem.offset 0,0; st8.spill [r16]=r13,16
    1.76 -.mem.offset 8,0; st8.spill [r17]=r8,16 /* save ar.fpsr */
    1.77 -    MINSTATE_GET_CURRENT(r13)
    1.78 -    ;;
    1.79 -.mem.offset 0,0; st8.spill [r16]=r15,16
    1.80 -.mem.offset 8,0; st8.spill [r17]=r14,16
    1.81 -    dep r14=-1,r0,60,4
    1.82 -    ;;
    1.83 -.mem.offset 0,0; st8.spill [r16]=r2,16
    1.84 -.mem.offset 8,0; st8.spill [r17]=r3,16
    1.85 -    adds r2=IA64_PT_REGS_R16_OFFSET,r1
    1.86 -    ;;
    1.87 -    mov r8=ar.ccv
    1.88 -    movl r1=__gp       /* establish kernel global pointer */
    1.89 -    ;;                                          \
    1.90 -    bsw.1
    1.91 -    ;;
    1.92 -    alloc r14=ar.pfs,0,0,2,0	// must be first in an insn group
    1.93 -    mov out0=cr.ivr		// pass cr.ivr as first arg
    1.94 -    add out1=16,sp		// pass pointer to pt_regs as second arg
    1.95 -
    1.96 -    ssm psr.ic
    1.97 -    ;;
    1.98 -    adds r3=8,r2		// set up second base pointer for SAVE_REST
    1.99 -    srlz.i			// ensure everybody knows psr.ic is back on
   1.100 -    ;;
   1.101 -.mem.offset 0,0; st8.spill [r2]=r16,16
   1.102 -.mem.offset 8,0; st8.spill [r3]=r17,16
   1.103 -    ;;
   1.104 -.mem.offset 0,0; st8.spill [r2]=r18,16
   1.105 -.mem.offset 8,0; st8.spill [r3]=r19,16
   1.106 -    ;;
   1.107 -.mem.offset 0,0; st8.spill [r2]=r20,16
   1.108 -.mem.offset 8,0; st8.spill [r3]=r21,16
   1.109 -    mov r18=b6
   1.110 -    ;;
   1.111 -.mem.offset 0,0; st8.spill [r2]=r22,16
   1.112 -.mem.offset 8,0; st8.spill [r3]=r23,16
   1.113 -    mov r19=b7
   1.114 -    ;;
   1.115 -.mem.offset 0,0; st8.spill [r2]=r24,16
   1.116 -.mem.offset 8,0; st8.spill [r3]=r25,16
   1.117 -    ;;
   1.118 -.mem.offset 0,0; st8.spill [r2]=r26,16
   1.119 -.mem.offset 8,0; st8.spill [r3]=r27,16
   1.120 -    ;;
   1.121 -.mem.offset 0,0; st8.spill [r2]=r28,16
   1.122 -.mem.offset 8,0; st8.spill [r3]=r29,16
   1.123 -    ;;
   1.124 -.mem.offset 0,0; st8.spill [r2]=r30,16
   1.125 -.mem.offset 8,0; st8.spill [r3]=r31,32
   1.126 -    ;;
   1.127 -    mov ar.fpsr=r11       /* M-unit */
   1.128 -    st8 [r2]=r8,8         /* ar.ccv */
   1.129 -    adds r24=PT(B6)-PT(F7),r3
   1.130 -    ;;
   1.131 -    stf.spill [r2]=f6,32
   1.132 -    stf.spill [r3]=f7,32
   1.133 -    ;;
   1.134 -    stf.spill [r2]=f8,32
   1.135 -    stf.spill [r3]=f9,32
   1.136 -    ;;
   1.137 -    stf.spill [r2]=f10
   1.138 -    stf.spill [r3]=f11
   1.139 -    adds r25=PT(B7)-PT(F11),r3
   1.140 -    ;;
   1.141 -    st8 [r24]=r18,16       /* b6 */
   1.142 -    st8 [r25]=r19,16       /* b7 */
   1.143 -    ;;
   1.144 -    st8 [r24]=r9           /* ar.csd */
   1.145 -    st8 [r25]=r10          /* ar.ssd */
   1.146 -    ;;
   1.147 -    srlz.d		// make sure we see the effect of cr.ivr
   1.148 -    movl r14=ia64_leave_nested
   1.149 -    ;;
   1.150 -    mov rp=r14
   1.151 -    br.call.sptk.many b6=ia64_handle_irq
   1.152 -    ;;
   1.153 +    br.sptk vmx_dispatch_interrupt
   1.154  END(vmx_interrupt)
   1.155  
   1.156      .org vmx_ia64_ivt+0x3400
   1.157 @@ -1448,21 +1307,20 @@ END(vmx_dispatch_break_fault)
   1.158  
   1.159  
   1.160  ENTRY(vmx_dispatch_interrupt)
   1.161 -    VMX_SAVE_MIN_WITH_COVER	// uses r31; defines r2 and r3
   1.162 +    VMX_SAVE_MIN_WITH_COVER_NO_PANIC	// uses r31; defines r2 and r3
   1.163      ;;
   1.164      alloc r14=ar.pfs,0,0,2,0	// must be first in an insn group
   1.165 +    ssm psr.ic
   1.166      mov out0=cr.ivr		// pass cr.ivr as first arg
   1.167      adds r3=8,r2		// set up second base pointer for SAVE_REST
   1.168      ;;
   1.169 -    ssm psr.ic
   1.170 -    ;;
   1.171 +(pUStk) movl r14=ia64_leave_hypervisor
   1.172      srlz.i
   1.173 -    movl r14=ia64_leave_hypervisor
   1.174      ;;
   1.175 +(pKStk) movl r14=ia64_leave_nested
   1.176      VMX_SAVE_REST
   1.177 +    add out1=16,sp		// pass pointer to pt_regs as second arg
   1.178      mov rp=r14
   1.179 -    ;;
   1.180 -    add out1=16,sp		// pass pointer to pt_regs as second arg
   1.181      br.call.sptk.many b6=ia64_handle_irq
   1.182  END(vmx_dispatch_interrupt)
   1.183