ia64/xen-unstable

changeset 19805:2f1fa2215e60

VT-d: pci code cleanup

This patch moves the pci code from iommu.c to pci.c. Instead of setup
pci hierarchy in array bus2bridge in iommu_context_mapping, use
scan_pci_devices once to add all existed PCI devices in system to
alldevs_list and setup pci hierarchy in array bus2bridge. In addition,
implement find_upstream_bridge to find the upstream PCIe-to-PCI/PCIX
bridge or PCI legacy bridge for a PCI device, therefore it's cleanly
to handle context map/unmap for PCI device, even for source-id
setting.

Signed-off-by: Weidong Han <weidong.han@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 19 08:45:20 2009 +0100 (2009-06-19)
parents e2625f235940
children 703ced548925
files xen/drivers/passthrough/pci.c xen/drivers/passthrough/vtd/iommu.c xen/include/xen/pci.h
line diff
     1.1 --- a/xen/drivers/passthrough/pci.c	Fri Jun 19 08:44:33 2009 +0100
     1.2 +++ b/xen/drivers/passthrough/pci.c	Fri Jun 19 08:45:20 2009 +0100
     1.3 @@ -30,6 +30,16 @@
     1.4  LIST_HEAD(alldevs_list);
     1.5  spinlock_t pcidevs_lock = SPIN_LOCK_UNLOCKED;
     1.6  
     1.7 +#define MAX_BUSES 256
     1.8 +static struct {
     1.9 +    u8 map;
    1.10 +    u8 bus;
    1.11 +    u8 devfn;
    1.12 +} bus2bridge[MAX_BUSES];
    1.13 +
    1.14 +/* bus2bridge_lock protects bus2bridge array */
    1.15 +static DEFINE_SPINLOCK(bus2bridge_lock);
    1.16 +
    1.17  struct pci_dev *alloc_pdev(u8 bus, u8 devfn)
    1.18  {
    1.19      struct pci_dev *pdev;
    1.20 @@ -240,6 +250,149 @@ void pci_release_devices(struct domain *
    1.21      spin_unlock(&pcidevs_lock);
    1.22  }
    1.23  
    1.24 +#define PCI_CLASS_BRIDGE_PCI     0x0604
    1.25 +
    1.26 +int pdev_type(u8 bus, u8 devfn)
    1.27 +{
    1.28 +    u16 class_device;
    1.29 +    u16 status, creg;
    1.30 +    int pos;
    1.31 +    u8 d = PCI_SLOT(devfn), f = PCI_FUNC(devfn);
    1.32 +
    1.33 +    class_device = pci_conf_read16(bus, d, f, PCI_CLASS_DEVICE);
    1.34 +    if ( class_device == PCI_CLASS_BRIDGE_PCI )
    1.35 +    {
    1.36 +        pos = pci_find_next_cap(bus, devfn,
    1.37 +                                PCI_CAPABILITY_LIST, PCI_CAP_ID_EXP);
    1.38 +        if ( !pos )
    1.39 +            return DEV_TYPE_LEGACY_PCI_BRIDGE;
    1.40 +        creg = pci_conf_read16(bus, d, f, pos + PCI_EXP_FLAGS);
    1.41 +        return ((creg & PCI_EXP_FLAGS_TYPE) >> 4) == PCI_EXP_TYPE_PCI_BRIDGE ?
    1.42 +            DEV_TYPE_PCIe2PCI_BRIDGE : DEV_TYPE_PCIe_BRIDGE;
    1.43 +    }
    1.44 +
    1.45 +    status = pci_conf_read16(bus, d, f, PCI_STATUS);
    1.46 +    if ( !(status & PCI_STATUS_CAP_LIST) )
    1.47 +        return DEV_TYPE_PCI;
    1.48 +
    1.49 +    if ( pci_find_next_cap(bus, devfn, PCI_CAPABILITY_LIST, PCI_CAP_ID_EXP) )
    1.50 +        return DEV_TYPE_PCIe_ENDPOINT;
    1.51 +
    1.52 +    return DEV_TYPE_PCI;
    1.53 +}
    1.54 +
    1.55 +/*
    1.56 + * find the upstream PCIe-to-PCI/PCIX bridge or PCI legacy bridge
    1.57 + * return 0: the device is integrated PCI device or PCIe
    1.58 + * return 1: find PCIe-to-PCI/PCIX bridge or PCI legacy bridge
    1.59 + * return -1: fail
    1.60 + */
    1.61 +int find_upstream_bridge(u8 *bus, u8 *devfn, u8 *secbus)
    1.62 +{
    1.63 +    int ret = 0;
    1.64 +    int cnt = 0;
    1.65 +
    1.66 +    if ( *bus == 0 )
    1.67 +        return 0;
    1.68 +
    1.69 +    if ( !bus2bridge[*bus].map )
    1.70 +        return 0;
    1.71 +
    1.72 +    ret = 1;
    1.73 +    spin_lock(&bus2bridge_lock);
    1.74 +    while ( bus2bridge[*bus].map )
    1.75 +    {
    1.76 +        *secbus = *bus;
    1.77 +        *devfn = bus2bridge[*bus].devfn;
    1.78 +        *bus = bus2bridge[*bus].bus;
    1.79 +        if ( cnt++ >= MAX_BUSES )
    1.80 +        {
    1.81 +            ret = -1;
    1.82 +            goto out;
    1.83 +        }
    1.84 +    }
    1.85 +
    1.86 +out:
    1.87 +    spin_unlock(&bus2bridge_lock);
    1.88 +    return ret;
    1.89 +}
    1.90 +
    1.91 +/*
    1.92 + * scan pci devices to add all existed PCI devices to alldevs_list,
    1.93 + * and setup pci hierarchy in array bus2bridge. This function is only
    1.94 + * called in VT-d hardware setup
    1.95 + */
    1.96 +int __init scan_pci_devices(void)
    1.97 +{
    1.98 +    struct pci_dev *pdev;
    1.99 +    int bus, dev, func;
   1.100 +    u8 sec_bus, sub_bus;
   1.101 +    int type;
   1.102 +    u32 l;
   1.103 +
   1.104 +    spin_lock(&pcidevs_lock);
   1.105 +    for ( bus = 0; bus < 256; bus++ )
   1.106 +    {
   1.107 +        for ( dev = 0; dev < 32; dev++ )
   1.108 +        {
   1.109 +            for ( func = 0; func < 8; func++ )
   1.110 +            {
   1.111 +                l = pci_conf_read32(bus, dev, func, PCI_VENDOR_ID);
   1.112 +                /* some broken boards return 0 or ~0 if a slot is empty: */
   1.113 +                if ( (l == 0xffffffff) || (l == 0x00000000) ||
   1.114 +                     (l == 0x0000ffff) || (l == 0xffff0000) )
   1.115 +                    continue;
   1.116 +
   1.117 +                pdev = alloc_pdev(bus, PCI_DEVFN(dev, func));
   1.118 +                if ( !pdev )
   1.119 +                {
   1.120 +                    printk("%s: alloc_pdev failed.\n", __func__);
   1.121 +                    spin_unlock(&pcidevs_lock);
   1.122 +                    return -ENOMEM;
   1.123 +                }
   1.124 +
   1.125 +                /* build bus2bridge */
   1.126 +                type = pdev_type(bus, PCI_DEVFN(dev, func));
   1.127 +                switch ( type )
   1.128 +                {
   1.129 +                    case DEV_TYPE_PCIe_BRIDGE:
   1.130 +                        break;
   1.131 +
   1.132 +                    case DEV_TYPE_PCIe2PCI_BRIDGE:
   1.133 +                    case DEV_TYPE_LEGACY_PCI_BRIDGE:
   1.134 +                        sec_bus = pci_conf_read8(bus, dev, func,
   1.135 +                                                 PCI_SECONDARY_BUS);
   1.136 +                        sub_bus = pci_conf_read8(bus, dev, func,
   1.137 +                                                 PCI_SUBORDINATE_BUS);
   1.138 +
   1.139 +                        spin_lock(&bus2bridge_lock);
   1.140 +                        for ( sub_bus &= 0xff; sec_bus <= sub_bus; sec_bus++ )
   1.141 +                        {
   1.142 +                            bus2bridge[sec_bus].map = 1;
   1.143 +                            bus2bridge[sec_bus].bus =  bus;
   1.144 +                            bus2bridge[sec_bus].devfn =  PCI_DEVFN(dev, func);
   1.145 +                        }
   1.146 +                        spin_unlock(&bus2bridge_lock);
   1.147 +                        break;
   1.148 +
   1.149 +                    case DEV_TYPE_PCIe_ENDPOINT:
   1.150 +                    case DEV_TYPE_PCI:
   1.151 +                        break;
   1.152 +
   1.153 +                    default:
   1.154 +                        printk("%s: unknown type: bdf = %x:%x.%x\n",
   1.155 +                               __func__, bus, dev, func);
   1.156 +                        spin_unlock(&pcidevs_lock);
   1.157 +                        return -EINVAL;
   1.158 +                }
   1.159 +            }
   1.160 +        }
   1.161 +    }
   1.162 +
   1.163 +    spin_unlock(&pcidevs_lock);
   1.164 +    return 0;
   1.165 +}
   1.166 +
   1.167  #ifdef SUPPORT_MSI_REMAPPING
   1.168  static void dump_pci_devices(unsigned char ch)
   1.169  {
     2.1 --- a/xen/drivers/passthrough/vtd/iommu.c	Fri Jun 19 08:44:33 2009 +0100
     2.2 +++ b/xen/drivers/passthrough/vtd/iommu.c	Fri Jun 19 08:45:20 2009 +0100
     2.3 @@ -1066,92 +1066,12 @@ static int domain_context_mapping_one(
     2.4      return 0;
     2.5  }
     2.6  
     2.7 -#define PCI_BASE_CLASS_BRIDGE    0x06
     2.8 -#define PCI_CLASS_BRIDGE_PCI     0x0604
     2.9 -
    2.10 -enum {
    2.11 -    DEV_TYPE_PCIe_ENDPOINT,
    2.12 -    DEV_TYPE_PCIe_BRIDGE,    // PCIe root port, switch
    2.13 -    DEV_TYPE_PCI_BRIDGE,     // PCIe-to-PCI/PCIx bridge, PCI-to-PCI bridge
    2.14 -    DEV_TYPE_PCI,
    2.15 -};
    2.16 -
    2.17 -int pdev_type(u8 bus, u8 devfn)
    2.18 -{
    2.19 -    u16 class_device;
    2.20 -    u16 status, creg;
    2.21 -    int pos;
    2.22 -    u8 d = PCI_SLOT(devfn), f = PCI_FUNC(devfn);
    2.23 -
    2.24 -    class_device = pci_conf_read16(bus, d, f, PCI_CLASS_DEVICE);
    2.25 -    if ( class_device == PCI_CLASS_BRIDGE_PCI )
    2.26 -    {
    2.27 -        pos = pci_find_next_cap(bus, devfn,
    2.28 -                                PCI_CAPABILITY_LIST, PCI_CAP_ID_EXP);
    2.29 -        if ( !pos )
    2.30 -            return DEV_TYPE_PCI_BRIDGE;
    2.31 -        creg = pci_conf_read16(bus, d, f, pos + PCI_EXP_FLAGS);
    2.32 -        return ((creg & PCI_EXP_FLAGS_TYPE) >> 4) == PCI_EXP_TYPE_PCI_BRIDGE ?
    2.33 -            DEV_TYPE_PCI_BRIDGE : DEV_TYPE_PCIe_BRIDGE;
    2.34 -    }
    2.35 -
    2.36 -    status = pci_conf_read16(bus, d, f, PCI_STATUS);
    2.37 -    if ( !(status & PCI_STATUS_CAP_LIST) )
    2.38 -        return DEV_TYPE_PCI;
    2.39 -
    2.40 -    if ( pci_find_next_cap(bus, devfn, PCI_CAPABILITY_LIST, PCI_CAP_ID_EXP) )
    2.41 -        return DEV_TYPE_PCIe_ENDPOINT;
    2.42 -
    2.43 -    return DEV_TYPE_PCI;
    2.44 -}
    2.45 -
    2.46 -#define MAX_BUSES 256
    2.47 -static DEFINE_SPINLOCK(bus2bridge_lock);
    2.48 -static struct { u8 map, bus, devfn; } bus2bridge[MAX_BUSES];
    2.49 -
    2.50 -static int _find_pcie_endpoint(u8 *bus, u8 *devfn, u8 *secbus)
    2.51 -{
    2.52 -    int cnt = 0;
    2.53 -    *secbus = *bus;
    2.54 -
    2.55 -    ASSERT(spin_is_locked(&bus2bridge_lock));
    2.56 -    if ( !bus2bridge[*bus].map )
    2.57 -        return 0;
    2.58 -
    2.59 -    while ( bus2bridge[*bus].map )
    2.60 -    {
    2.61 -        *secbus = *bus;
    2.62 -        *devfn = bus2bridge[*bus].devfn;
    2.63 -        *bus = bus2bridge[*bus].bus;
    2.64 -        if ( cnt++ >= MAX_BUSES )
    2.65 -            return 0;
    2.66 -    }
    2.67 -
    2.68 -    return 1;
    2.69 -}
    2.70 -
    2.71 -static int find_pcie_endpoint(u8 *bus, u8 *devfn, u8 *secbus)
    2.72 -{
    2.73 -    int ret = 0;
    2.74 -
    2.75 -    if ( *bus == 0 )
    2.76 -        /* assume integrated PCI devices in RC have valid requester-id */
    2.77 -        return 1;
    2.78 -
    2.79 -    spin_lock(&bus2bridge_lock);
    2.80 -    ret = _find_pcie_endpoint(bus, devfn, secbus);
    2.81 -    spin_unlock(&bus2bridge_lock);
    2.82 -
    2.83 -    return ret;
    2.84 -}
    2.85 -
    2.86  static int domain_context_mapping(struct domain *domain, u8 bus, u8 devfn)
    2.87  {
    2.88      struct acpi_drhd_unit *drhd;
    2.89      int ret = 0;
    2.90 -    u16 sec_bus, sub_bus;
    2.91      u32 type;
    2.92 -    u8 secbus, secdevfn;
    2.93 +    u8 secbus;
    2.94      struct pci_dev *pdev = pci_get_pdev(bus, devfn);
    2.95  
    2.96      if ( pdev == NULL )
    2.97 @@ -1179,22 +1099,8 @@ static int domain_context_mapping(struct
    2.98      switch ( type )
    2.99      {
   2.100      case DEV_TYPE_PCIe_BRIDGE:
   2.101 -        break;
   2.102 -
   2.103 -    case DEV_TYPE_PCI_BRIDGE:
   2.104 -        sec_bus = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
   2.105 -                                 PCI_SECONDARY_BUS);
   2.106 -        sub_bus = pci_conf_read8(bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
   2.107 -                                 PCI_SUBORDINATE_BUS);
   2.108 -
   2.109 -        spin_lock(&bus2bridge_lock);
   2.110 -        for ( sub_bus &= 0xff; sec_bus <= sub_bus; sec_bus++ )
   2.111 -        {
   2.112 -            bus2bridge[sec_bus].map = 1;
   2.113 -            bus2bridge[sec_bus].bus =  bus;
   2.114 -            bus2bridge[sec_bus].devfn =  devfn;
   2.115 -        }
   2.116 -        spin_unlock(&bus2bridge_lock);
   2.117 +    case DEV_TYPE_PCIe2PCI_BRIDGE:
   2.118 +    case DEV_TYPE_LEGACY_PCI_BRIDGE:
   2.119          break;
   2.120  
   2.121      case DEV_TYPE_PCIe_ENDPOINT:
   2.122 @@ -1211,31 +1117,29 @@ static int domain_context_mapping(struct
   2.123  
   2.124          ret = domain_context_mapping_one(domain, drhd->iommu, bus, devfn);
   2.125          if ( ret )
   2.126 -           break;
   2.127 +            break;
   2.128  
   2.129 -        secbus = bus;
   2.130 -        secdevfn = devfn;
   2.131 -        /* dependent devices mapping */
   2.132 -        while ( bus2bridge[bus].map )
   2.133 +        if ( find_upstream_bridge(&bus, &devfn, &secbus) < 1 )
   2.134 +            break;
   2.135 +
   2.136 +        /* PCIe to PCI/PCIx bridge */
   2.137 +        if ( pdev_type(bus, devfn) == DEV_TYPE_PCIe2PCI_BRIDGE )
   2.138          {
   2.139 -            secbus = bus;
   2.140 -            secdevfn = devfn;
   2.141 -            devfn = bus2bridge[bus].devfn;
   2.142 -            bus = bus2bridge[bus].bus;
   2.143              ret = domain_context_mapping_one(domain, drhd->iommu, bus, devfn);
   2.144              if ( ret )
   2.145                  return ret;
   2.146 -        }
   2.147  
   2.148 -        if ( (secbus != bus) && (secdevfn != 0) )
   2.149              /*
   2.150 -             * The source-id for transactions on non-PCIe buses seem
   2.151 -             * to originate from devfn=0 on the secondary bus behind
   2.152 -             * the bridge.  Map that id as well.  The id to use in
   2.153 -             * these scanarios is not particularly well documented
   2.154 -             * anywhere.
   2.155 +             * Devices behind PCIe-to-PCI/PCIx bridge may generate
   2.156 +             * different requester-id. It may originate from devfn=0
   2.157 +             * on the secondary bus behind the bridge. Map that id
   2.158 +             * as well.
   2.159               */
   2.160              ret = domain_context_mapping_one(domain, drhd->iommu, secbus, 0);
   2.161 +        }
   2.162 +        else /* Legacy PCI bridge */
   2.163 +            ret = domain_context_mapping_one(domain, drhd->iommu, bus, devfn);
   2.164 +
   2.165          break;
   2.166  
   2.167      default:
   2.168 @@ -1296,7 +1200,7 @@ static int domain_context_unmap(struct d
   2.169      struct acpi_drhd_unit *drhd;
   2.170      int ret = 0;
   2.171      u32 type;
   2.172 -    u8 secbus, secdevfn;
   2.173 +    u8 secbus;
   2.174      struct pci_dev *pdev = pci_get_pdev(bus, devfn);
   2.175  
   2.176      BUG_ON(!pdev);
   2.177 @@ -1309,7 +1213,8 @@ static int domain_context_unmap(struct d
   2.178      switch ( type )
   2.179      {
   2.180      case DEV_TYPE_PCIe_BRIDGE:
   2.181 -    case DEV_TYPE_PCI_BRIDGE:
   2.182 +    case DEV_TYPE_PCIe2PCI_BRIDGE:
   2.183 +    case DEV_TYPE_LEGACY_PCI_BRIDGE:
   2.184          break;
   2.185  
   2.186      case DEV_TYPE_PCIe_ENDPOINT:
   2.187 @@ -1327,22 +1232,21 @@ static int domain_context_unmap(struct d
   2.188          if ( ret )
   2.189              break;
   2.190  
   2.191 -        secbus = bus;
   2.192 -        secdevfn = devfn;
   2.193 -        /* dependent devices unmapping */
   2.194 -        while ( bus2bridge[bus].map )
   2.195 +        if ( find_upstream_bridge(&bus, &devfn, &secbus) < 1 )
   2.196 +            break;
   2.197 +
   2.198 +        /* PCIe to PCI/PCIx bridge */
   2.199 +        if ( pdev_type(bus, devfn) == DEV_TYPE_PCIe2PCI_BRIDGE )
   2.200          {
   2.201 -            secbus = bus;
   2.202 -            secdevfn = devfn;
   2.203 -            devfn = bus2bridge[bus].devfn;
   2.204 -            bus = bus2bridge[bus].bus;
   2.205              ret = domain_context_unmap_one(domain, drhd->iommu, bus, devfn);
   2.206              if ( ret )
   2.207                  return ret;
   2.208 -        }
   2.209  
   2.210 -        if ( (secbus != bus) && (secdevfn != 0) )
   2.211              ret = domain_context_unmap_one(domain, drhd->iommu, secbus, 0);
   2.212 +        }
   2.213 +        else /* Legacy PCI bridge */
   2.214 +            ret = domain_context_unmap_one(domain, drhd->iommu, bus, devfn);
   2.215 +
   2.216          break;
   2.217  
   2.218      default:
   2.219 @@ -1584,31 +1488,24 @@ static void setup_dom0_devices(struct do
   2.220  {
   2.221      struct hvm_iommu *hd;
   2.222      struct pci_dev *pdev;
   2.223 -    int bus, dev, func;
   2.224 -    u32 l;
   2.225 +    int bus, devfn;
   2.226  
   2.227      hd = domain_hvm_iommu(d);
   2.228  
   2.229      spin_lock(&pcidevs_lock);
   2.230      for ( bus = 0; bus < 256; bus++ )
   2.231      {
   2.232 -        for ( dev = 0; dev < 32; dev++ )
   2.233 +        for ( devfn = 0; devfn < 256; devfn++ )
   2.234          {
   2.235 -            for ( func = 0; func < 8; func++ )
   2.236 -            {
   2.237 -                l = pci_conf_read32(bus, dev, func, PCI_VENDOR_ID);
   2.238 -                /* some broken boards return 0 or ~0 if a slot is empty: */
   2.239 -                if ( (l == 0xffffffff) || (l == 0x00000000) ||
   2.240 -                     (l == 0x0000ffff) || (l == 0xffff0000) )
   2.241 -                    continue;
   2.242 +            pdev = pci_get_pdev(bus, devfn);
   2.243 +            if ( !pdev )
   2.244 +                continue;
   2.245  
   2.246 -                pdev = alloc_pdev(bus, PCI_DEVFN(dev, func));
   2.247 -                pdev->domain = d;
   2.248 -                list_add(&pdev->domain_list, &d->arch.pdev_list);
   2.249 -                domain_context_mapping(d, pdev->bus, pdev->devfn);
   2.250 -                if ( ats_device(0, pdev->bus, pdev->devfn) )
   2.251 -                    enable_ats_device(0, pdev->bus, pdev->devfn);
   2.252 -            }
   2.253 +            pdev->domain = d;
   2.254 +            list_add(&pdev->domain_list, &d->arch.pdev_list);
   2.255 +            domain_context_mapping(d, pdev->bus, pdev->devfn);
   2.256 +            if ( ats_device(0, pdev->bus, pdev->devfn) )
   2.257 +                enable_ats_device(0, pdev->bus, pdev->devfn);
   2.258          }
   2.259      }
   2.260      spin_unlock(&pcidevs_lock);
   2.261 @@ -1809,6 +1706,8 @@ int intel_vtd_setup(void)
   2.262      memset(domid_bitmap, 0, domid_bitmap_size / 8);
   2.263      set_bit(0, domid_bitmap);
   2.264  
   2.265 +    scan_pci_devices();
   2.266 +
   2.267      if ( init_vtd_hw() )
   2.268          goto error;
   2.269  
   2.270 @@ -1902,10 +1801,10 @@ done:
   2.271  static int intel_iommu_group_id(u8 bus, u8 devfn)
   2.272  {
   2.273      u8 secbus;
   2.274 -    if ( !bus2bridge[bus].map || find_pcie_endpoint(&bus, &devfn, &secbus) )
   2.275 +    if ( find_upstream_bridge(&bus, &devfn, &secbus) < 0 )
   2.276 +        return -1;
   2.277 +    else
   2.278          return PCI_BDF2(bus, devfn);
   2.279 -    else
   2.280 -        return -1;
   2.281  }
   2.282  
   2.283  static u32 iommu_state[MAX_IOMMUS][MAX_IOMMU_REGS];
     3.1 --- a/xen/include/xen/pci.h	Fri Jun 19 08:44:33 2009 +0100
     3.2 +++ b/xen/include/xen/pci.h	Fri Jun 19 08:45:20 2009 +0100
     3.3 @@ -66,6 +66,17 @@ struct pci_dev {
     3.4  
     3.5  extern spinlock_t pcidevs_lock;
     3.6  
     3.7 +enum {
     3.8 +    DEV_TYPE_PCIe_ENDPOINT,
     3.9 +    DEV_TYPE_PCIe_BRIDGE,       // PCIe root port, switch
    3.10 +    DEV_TYPE_PCIe2PCI_BRIDGE,   // PCIe-to-PCI/PCIx bridge
    3.11 +    DEV_TYPE_LEGACY_PCI_BRIDGE, // Legacy PCI bridge
    3.12 +    DEV_TYPE_PCI,
    3.13 +};
    3.14 +
    3.15 +int scan_pci_devices(void);
    3.16 +int pdev_type(u8 bus, u8 devfn);
    3.17 +int find_upstream_bridge(u8 *bus, u8 *devfn, u8 *secbus);
    3.18  struct pci_dev *alloc_pdev(u8 bus, u8 devfn);
    3.19  void free_pdev(struct pci_dev *pdev);
    3.20  struct pci_dev *pci_lock_pdev(int bus, int devfn);