ia64/xen-unstable

changeset 16008:2d1b8ae1548d

[IA64] Fix wrong insertion of TLB entry in region 0

On PV domain with metaphysical mode, emulation of itc.d in region 0
doesn't work well and inserts an wrong TC entry.
Because set_one_rr() doesn't set the machine region register.
i.e. metaphyisical_rr0 is used instead of guest's rr[0].

This bug causes Dom0/U crash when an application uses region 0.
Actually I met the crash when I was building open GFW (java uses
region 0).

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Alex Williamson <alex.williamson@hp.com>
date Mon Oct 01 09:57:50 2007 -0600 (2007-10-01)
parents 3874bdc78204
children d3665dc74a41
files xen/arch/ia64/xen/regionreg.c xen/arch/ia64/xen/vcpu.c xen/include/asm-ia64/regionreg.h
line diff
     1.1 --- a/xen/arch/ia64/xen/regionreg.c	Mon Oct 01 09:53:48 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/regionreg.c	Mon Oct 01 09:57:50 2007 -0600
     1.3 @@ -271,8 +271,16 @@ int set_one_rr(unsigned long rr, unsigne
     1.4  	return 1;
     1.5  }
     1.6  
     1.7 +void set_virtual_rr0(void)
     1.8 +{
     1.9 +	struct vcpu *v = current;
    1.10 +
    1.11 +	ia64_set_rr(0, v->arch.metaphysical_saved_rr0);
    1.12 +	ia64_srlz_d();
    1.13 +}
    1.14 +
    1.15  // set rr0 to the passed rid (for metaphysical mode so don't use domain offset
    1.16 -int set_metaphysical_rr0(void)
    1.17 +void set_metaphysical_rr0(void)
    1.18  {
    1.19  	struct vcpu *v = current;
    1.20  //	ia64_rr rrv;
    1.21 @@ -280,7 +288,6 @@ int set_metaphysical_rr0(void)
    1.22  //	rrv.ve = 1; 	FIXME: TURN ME BACK ON WHEN VHPT IS WORKING
    1.23  	ia64_set_rr(0, v->arch.metaphysical_rid_dt);
    1.24  	ia64_srlz_d();
    1.25 -	return 1;
    1.26  }
    1.27  
    1.28  void init_all_rr(struct vcpu *v)
     2.1 --- a/xen/arch/ia64/xen/vcpu.c	Mon Oct 01 09:53:48 2007 -0600
     2.2 +++ b/xen/arch/ia64/xen/vcpu.c	Mon Oct 01 09:57:50 2007 -0600
     2.3 @@ -280,7 +280,7 @@ static void vcpu_pkr_set_psr_handling(VC
     2.4   VCPU processor status register access routines
     2.5  **************************************************************************/
     2.6  
     2.7 -void vcpu_set_metaphysical_mode(VCPU * vcpu, BOOLEAN newmode)
     2.8 +static void vcpu_set_metaphysical_mode(VCPU * vcpu, BOOLEAN newmode)
     2.9  {
    2.10  	/* only do something if mode changes */
    2.11  	if (!!newmode ^ !!PSCB(vcpu, metaphysical_mode)) {
    2.12 @@ -288,7 +288,7 @@ void vcpu_set_metaphysical_mode(VCPU * v
    2.13  		if (newmode)
    2.14  			set_metaphysical_rr0();
    2.15  		else if (PSCB(vcpu, rrs[0]) != -1)
    2.16 -			set_one_rr(0, PSCB(vcpu, rrs[0]));
    2.17 +			set_virtual_rr0();
    2.18  	}
    2.19  }
    2.20  
    2.21 @@ -1635,7 +1635,7 @@ vcpu_get_domain_bundle(VCPU * vcpu, REGS
    2.22  		// This may cause tlb miss. see vcpu_translate(). Be careful!
    2.23  		swap_rr0 = (!region && PSCB(vcpu, metaphysical_mode));
    2.24  		if (swap_rr0) {
    2.25 -			set_one_rr(0x0, PSCB(vcpu, rrs[0]));
    2.26 +			set_virtual_rr0();
    2.27  		}
    2.28  		*bundle = __get_domain_bundle(gip);
    2.29  		if (swap_rr0) {
    2.30 @@ -2368,7 +2368,7 @@ IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pt
    2.31  	if (!pteval)
    2.32  		return IA64_ILLOP_FAULT;
    2.33  	if (swap_rr0)
    2.34 -		set_one_rr(0x0, PSCB(vcpu, rrs[0]));
    2.35 +		set_virtual_rr0();
    2.36  	vcpu_itc_no_srlz(vcpu, 2, ifa, pteval, pte, _itir.itir, &entry);
    2.37  	if (swap_rr0)
    2.38  		set_metaphysical_rr0();
    2.39 @@ -2396,7 +2396,7 @@ IA64FAULT vcpu_itc_i(VCPU * vcpu, u64 pt
    2.40  	if (!pteval)
    2.41  		return IA64_ILLOP_FAULT;
    2.42  	if (swap_rr0)
    2.43 -		set_one_rr(0x0, PSCB(vcpu, rrs[0]));
    2.44 +		set_virtual_rr0();
    2.45  	vcpu_itc_no_srlz(vcpu, 1, ifa, pteval, pte, _itir.itir, &entry);
    2.46  	if (swap_rr0)
    2.47  		set_metaphysical_rr0();
     3.1 --- a/xen/include/asm-ia64/regionreg.h	Mon Oct 01 09:53:48 2007 -0600
     3.2 +++ b/xen/include/asm-ia64/regionreg.h	Mon Oct 01 09:57:50 2007 -0600
     3.3 @@ -80,7 +80,8 @@ extern int deallocate_rid_range(struct d
     3.4  struct vcpu;
     3.5  extern void init_all_rr(struct vcpu *v);
     3.6  
     3.7 -extern int set_metaphysical_rr0(void);
     3.8 +extern void set_virtual_rr0(void);
     3.9 +extern void set_metaphysical_rr0(void);
    3.10  
    3.11  extern void load_region_regs(struct vcpu *v);
    3.12