ia64/xen-unstable

changeset 15200:2c7154ea7eef

merged
author Jeremy Fitzhardinge <jeremy@xensource.com>
date Thu May 24 13:32:03 2007 +0100 (2007-05-24)
parents f38f7f583f33 2623444e6d33
children 1e418f7e0212
files
line diff
     1.1 --- a/tools/blktap/drivers/blktapctrl.c	Thu May 24 13:25:05 2007 +0100
     1.2 +++ b/tools/blktap/drivers/blktapctrl.c	Thu May 24 13:32:03 2007 +0100
     1.3 @@ -690,8 +690,10 @@ int main(int argc, char *argv[])
     1.4  
     1.5  	/* Attach to blktap0 */
     1.6  	asprintf(&devname,"%s/%s0", BLKTAP_DEV_DIR, BLKTAP_DEV_NAME);
     1.7 -	if ((ret = xc_find_device_number("blktap0")) < 0)
     1.8 +	if ((ret = xc_find_device_number("blktap0")) < 0) {
     1.9 +		DPRINTF("couldn't find device number for 'blktap0'\n");
    1.10  		goto open_failed;
    1.11 +	}
    1.12  	blktap_major = major(ret);
    1.13  	make_blktap_dev(devname,blktap_major,0);
    1.14  	ctlfd = open(devname, O_RDWR);
     2.1 --- a/xen/arch/x86/hvm/svm/svm.c	Thu May 24 13:25:05 2007 +0100
     2.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Thu May 24 13:32:03 2007 +0100
     2.3 @@ -179,6 +179,14 @@ static inline int long_mode_do_msr_write
     2.4  
     2.5          break;
     2.6  
     2.7 +    case MSR_K8_MC4_MISC: /* Threshold register */
     2.8 +        /*
     2.9 +         * MCA/MCE: Threshold register is reported to be locked, so we ignore
    2.10 +         * all write accesses. This behaviour matches real HW, so guests should
    2.11 +         * have no problem with this.
    2.12 +         */
    2.13 +        break;
    2.14 +
    2.15      default:
    2.16          return 0;
    2.17      }
    2.18 @@ -2062,6 +2070,14 @@ static inline void svm_do_msr_access(
    2.19              msr_content = v->arch.hvm_svm.cpu_shadow_efer;
    2.20              break;
    2.21  
    2.22 +        case MSR_K8_MC4_MISC: /* Threshold register */
    2.23 +            /*
    2.24 +             * MCA/MCE: We report that the threshold register is unavailable
    2.25 +             * for OS use (locked by the BIOS).
    2.26 +             */
    2.27 +            msr_content = 1ULL << 61; /* MC4_MISC.Locked */
    2.28 +            break;
    2.29 +
    2.30          default:
    2.31              if ( rdmsr_hypervisor_regs(ecx, &eax, &edx) ||
    2.32                   rdmsr_safe(ecx, eax, edx) == 0 )
     3.1 --- a/xen/arch/x86/hvm/vlapic.c	Thu May 24 13:25:05 2007 +0100
     3.2 +++ b/xen/arch/x86/hvm/vlapic.c	Thu May 24 13:32:03 2007 +0100
     3.3 @@ -918,16 +918,16 @@ int vlapic_init(struct vcpu *v)
     3.4      vlapic->regs_page = alloc_domheap_page(NULL);
     3.5      if ( vlapic->regs_page == NULL )
     3.6      {
     3.7 -        dprintk(XENLOG_ERR, "malloc vlapic regs_page error for vcpu %x\n",
     3.8 -                v->vcpu_id);
     3.9 +        dprintk(XENLOG_ERR, "alloc vlapic regs error: %d/%d\n",
    3.10 +                v->domain->domain_id, v->vcpu_id);
    3.11          return -ENOMEM;
    3.12      }
    3.13  
    3.14      vlapic->regs = map_domain_page_global(page_to_mfn(vlapic->regs_page));
    3.15      if ( vlapic->regs == NULL )
    3.16      {
    3.17 -        dprintk(XENLOG_ERR, "malloc vlapic regs error for vcpu %x\n",
    3.18 -                v->vcpu_id);
    3.19 +        dprintk(XENLOG_ERR, "map vlapic regs error: %d/%d\n",
    3.20 +                v->domain->domain_id, v->vcpu_id);
    3.21  	return -ENOMEM;
    3.22      }
    3.23  
    3.24 @@ -935,7 +935,8 @@ int vlapic_init(struct vcpu *v)
    3.25  
    3.26      vlapic_reset(vlapic);
    3.27  
    3.28 -    vlapic->hw.apic_base_msr = MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
    3.29 +    vlapic->hw.apic_base_msr = (MSR_IA32_APICBASE_ENABLE |
    3.30 +                                APIC_DEFAULT_PHYS_BASE);
    3.31      if ( v->vcpu_id == 0 )
    3.32          vlapic->hw.apic_base_msr |= MSR_IA32_APICBASE_BSP;
    3.33  
     4.1 --- a/xen/arch/x86/mm/shadow/multi.c	Thu May 24 13:25:05 2007 +0100
     4.2 +++ b/xen/arch/x86/mm/shadow/multi.c	Thu May 24 13:32:03 2007 +0100
     4.3 @@ -3487,6 +3487,7 @@ sh_update_cr3(struct vcpu *v, int do_loc
     4.4          v->arch.paging.shadow.guest_vtable = sh_map_domain_page_global(gmfn);
     4.5          /* PAGING_LEVELS==4 implies 64-bit, which means that
     4.6           * map_domain_page_global can't fail */
     4.7 +        BUG_ON(v->arch.paging.shadow.guest_vtable == NULL);
     4.8      }
     4.9      else
    4.10          v->arch.paging.shadow.guest_vtable = __linear_l4_table;
    4.11 @@ -3519,7 +3520,7 @@ sh_update_cr3(struct vcpu *v, int do_loc
    4.12          v->arch.paging.shadow.guest_vtable = sh_map_domain_page_global(gmfn);
    4.13          /* Does this really need map_domain_page_global?  Handle the
    4.14           * error properly if so. */
    4.15 -        ASSERT( v->arch.paging.shadow.guest_vtable );
    4.16 +        BUG_ON(v->arch.paging.shadow.guest_vtable == NULL); /* XXX */
    4.17      }
    4.18      else
    4.19          v->arch.paging.shadow.guest_vtable = __linear_l2_table;
     5.1 --- a/xen/arch/x86/x86_32/domain_page.c	Thu May 24 13:25:05 2007 +0100
     5.2 +++ b/xen/arch/x86/x86_32/domain_page.c	Thu May 24 13:32:03 2007 +0100
     5.3 @@ -98,7 +98,7 @@ void *map_domain_page(unsigned long mfn)
     5.4          cache->tlbflush_timestamp = tlbflush_current_time();
     5.5  
     5.6          idx = find_first_zero_bit(cache->inuse, MAPCACHE_ENTRIES);
     5.7 -        ASSERT(idx < MAPCACHE_ENTRIES);
     5.8 +        BUG_ON(idx >= MAPCACHE_ENTRIES);
     5.9      }
    5.10  
    5.11      set_bit(idx, cache->inuse);
    5.12 @@ -218,25 +218,21 @@ void *map_domain_page_global(unsigned lo
    5.13  
    5.14          idx = find_first_zero_bit(inuse, GLOBALMAP_BITS);
    5.15          va = IOREMAP_VIRT_START + (idx << PAGE_SHIFT);
    5.16 -        if ( va >= FIXADDR_START )
    5.17 +        if ( unlikely(va >= FIXADDR_START) )
    5.18          {
    5.19 -            va = 0;
    5.20 -            goto fail;
    5.21 +            spin_unlock(&globalmap_lock);
    5.22 +            return NULL;
    5.23          }
    5.24      }
    5.25  
    5.26      set_bit(idx, inuse);
    5.27      inuse_cursor = idx + 1;
    5.28  
    5.29 -  fail:
    5.30      spin_unlock(&globalmap_lock);
    5.31  
    5.32 -    if ( likely(va != 0) )
    5.33 -    {
    5.34 -	pl2e = virt_to_xen_l2e(va);
    5.35 -	pl1e = l2e_to_l1e(*pl2e) + l1_table_offset(va);
    5.36 -	l1e_write(pl1e, l1e_from_pfn(mfn, __PAGE_HYPERVISOR));
    5.37 -    }
    5.38 +    pl2e = virt_to_xen_l2e(va);
    5.39 +    pl1e = l2e_to_l1e(*pl2e) + l1_table_offset(va);
    5.40 +    l1e_write(pl1e, l1e_from_pfn(mfn, __PAGE_HYPERVISOR));
    5.41  
    5.42      return (void *)va;
    5.43  }
     6.1 --- a/xen/include/asm-x86/hap.h	Thu May 24 13:25:05 2007 +0100
     6.2 +++ b/xen/include/asm-x86/hap.h	Thu May 24 13:32:03 2007 +0100
     6.3 @@ -48,18 +48,6 @@ hap_unmap_domain_page(void *p)
     6.4      unmap_domain_page(p);
     6.5  }
     6.6  
     6.7 -static inline void *
     6.8 -hap_map_domain_page_global(mfn_t mfn)
     6.9 -{
    6.10 -    return map_domain_page_global(mfn_x(mfn));
    6.11 -}
    6.12 -
    6.13 -static inline void 
    6.14 -hap_unmap_domain_page_global(void *p) 
    6.15 -{
    6.16 -    unmap_domain_page_global(p);
    6.17 -}
    6.18 -
    6.19  /************************************************/
    6.20  /*           locking for hap code               */
    6.21  /************************************************/
     7.1 --- a/xen/include/asm-x86/msr.h	Thu May 24 13:25:05 2007 +0100
     7.2 +++ b/xen/include/asm-x86/msr.h	Thu May 24 13:32:03 2007 +0100
     7.3 @@ -217,6 +217,27 @@ static inline void write_efer(__u64 val)
     7.4  #define MSR_IA32_MC0_ADDR		0x402
     7.5  #define MSR_IA32_MC0_MISC		0x403
     7.6  
     7.7 +/* K8 Machine Check MSRs */
     7.8 +#define MSR_K8_MC1_CTL			0x404
     7.9 +#define MSR_K8_MC1_STATUS		0x405
    7.10 +#define MSR_K8_MC1_ADDR			0x406
    7.11 +#define MSR_K8_MC1_MISC			0x407
    7.12 +
    7.13 +#define MSR_K8_MC2_CTL			0x408
    7.14 +#define MSR_K8_MC2_STATUS		0x409
    7.15 +#define MSR_K8_MC2_ADDR			0x40A
    7.16 +#define MSR_K8_MC2_MISC			0x40B
    7.17 +
    7.18 +#define MSR_K8_MC3_CTL			0x40C
    7.19 +#define MSR_K8_MC3_STATUS		0x40D
    7.20 +#define MSR_K8_MC3_ADDR			0x40E
    7.21 +#define MSR_K8_MC3_MISC			0x40F
    7.22 +
    7.23 +#define MSR_K8_MC4_CTL			0x410
    7.24 +#define MSR_K8_MC4_STATUS		0x411
    7.25 +#define MSR_K8_MC4_ADDR			0x412
    7.26 +#define MSR_K8_MC4_MISC			0x413
    7.27 +
    7.28  /* Pentium IV performance counter MSRs */
    7.29  #define MSR_P4_BPU_PERFCTR0 		0x300
    7.30  #define MSR_P4_BPU_PERFCTR1 		0x301