ia64/xen-unstable

changeset 141:2c1ef70cc49f

bitkeeper revision 1.25 (3e492a23vrV6G7nvPEIWmSIcQxdFNw)

merge with latest changeset
author rn@wyvis.camb.intel-research.net
date Tue Feb 11 16:51:47 2003 +0000 (2003-02-11)
parents 350c8a939f8d 4c6ae683ed61
children 4bd6c4bfc2b3
files .rootkeys xen-2.4.16/Makefile xen-2.4.16/Rules.mk xen-2.4.16/arch/i386/Rules.mk xen-2.4.16/arch/i386/apic.c xen-2.4.16/arch/i386/boot/boot.S xen-2.4.16/arch/i386/entry.S xen-2.4.16/arch/i386/i8259.c xen-2.4.16/arch/i386/io_apic.c xen-2.4.16/arch/i386/ioremap.c xen-2.4.16/arch/i386/mm.c xen-2.4.16/arch/i386/process.c xen-2.4.16/arch/i386/smpboot.c xen-2.4.16/arch/i386/traps.c xen-2.4.16/arch/i386/xeno.lds xen-2.4.16/common/dom0_ops.c xen-2.4.16/common/domain.c xen-2.4.16/common/kernel.c xen-2.4.16/common/memory.c xen-2.4.16/drivers/net/Makefile xen-2.4.16/drivers/net/e1000/LICENSE xen-2.4.16/drivers/net/e1000/Makefile xen-2.4.16/drivers/net/e1000/e1000.h xen-2.4.16/drivers/net/e1000/e1000_ethtool.c xen-2.4.16/drivers/net/e1000/e1000_hw.c xen-2.4.16/drivers/net/e1000/e1000_hw.h xen-2.4.16/drivers/net/e1000/e1000_main.c xen-2.4.16/drivers/net/e1000/e1000_osdep.h xen-2.4.16/drivers/net/e1000/e1000_param.c xen-2.4.16/drivers/net/ne/8390.c xen-2.4.16/drivers/net/ne/8390.h xen-2.4.16/drivers/net/ne/Makefile xen-2.4.16/drivers/net/ne/ne.c xen-2.4.16/drivers/net/tg3.c xen-2.4.16/drivers/net/tg3.h xen-2.4.16/drivers/pci/Makefile xen-2.4.16/drivers/pci/pci.c xen-2.4.16/include/asm-i386/irq.h xen-2.4.16/include/asm-i386/page.h xen-2.4.16/include/asm-i386/param.h xen-2.4.16/include/asm-i386/pci.h xen-2.4.16/include/asm-i386/processor.h xen-2.4.16/include/asm-i386/timex.h xen-2.4.16/include/asm-i386/uaccess.h xen-2.4.16/include/hypervisor-ifs/hypervisor-if.h xen-2.4.16/include/stdarg.h xen-2.4.16/include/xeno/config.h xen-2.4.16/include/xeno/dom0_ops.h xen-2.4.16/include/xeno/ethtool.h xen-2.4.16/include/xeno/if_vlan.h xen-2.4.16/include/xeno/in.h xen-2.4.16/include/xeno/kernel.h xen-2.4.16/include/xeno/mm.h xen-2.4.16/include/xeno/netdevice.h xen-2.4.16/include/xeno/notifier.h xen-2.4.16/include/xeno/pci.h xen-2.4.16/include/xeno/pci_ids.h xen-2.4.16/include/xeno/reboot.h xen-2.4.16/include/xeno/sched.h xen-2.4.16/include/xeno/types.h xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/dom0_core.c xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/dom0_memory.c xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/dom0_ops.h xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/hypervisor_defs.h xenolinux-2.4.16-sparse/arch/xeno/kernel/head.S xenolinux-2.4.16-sparse/arch/xeno/kernel/setup.c xenolinux-2.4.16-sparse/arch/xeno/kernel/traps.c xenolinux-2.4.16-sparse/arch/xeno/mm/fault.c xenolinux-2.4.16-sparse/arch/xeno/mm/get_unmapped_area.c xenolinux-2.4.16-sparse/arch/xeno/mm/hypervisor.c xenolinux-2.4.16-sparse/arch/xeno/mm/init.c xenolinux-2.4.16-sparse/fs/nfs/nfsroot.c xenolinux-2.4.16-sparse/include/asm-xeno/hypervisor.h xenolinux-2.4.16-sparse/include/asm-xeno/page.h
line diff
     1.1 --- a/.rootkeys	Tue Feb 11 16:44:27 2003 +0000
     1.2 +++ b/.rootkeys	Tue Feb 11 16:51:47 2003 +0000
     1.3 @@ -75,10 +75,25 @@ 3ddb79bfl_DWxZQFKiJ2BXrSedV4lg xen-2.4.1
     1.4  3ddb79bfLVGtyXNJS4NQg-lP21rndA xen-2.4.16/drivers/net/8139too.c
     1.5  3ddb79c0tWiE8xIFHszxipeVCGKTSA xen-2.4.16/drivers/net/Makefile
     1.6  3ddb79bfU-H1Hms4BuJEPPydjXUEaQ xen-2.4.16/drivers/net/Space.c
     1.7 +3e4540ccS4bfbx9rLiLElP0F1OVwZA xen-2.4.16/drivers/net/e1000/LICENSE
     1.8 +3e4540ccXG6af_6-u0IiKKvtdGHJyA xen-2.4.16/drivers/net/e1000/Makefile
     1.9 +3e4540ccoY2eo4VIkbR4sCOj0bVzSA xen-2.4.16/drivers/net/e1000/e1000.h
    1.10 +3e4540ccvUz0j2ejQ9Z9djEGc93wRA xen-2.4.16/drivers/net/e1000/e1000_ethtool.c
    1.11 +3e4540ccjqsc94nU3C4w3ZJaxFZFjA xen-2.4.16/drivers/net/e1000/e1000_hw.c
    1.12 +3e4540cczrrQVyyj-s1-viyX1kMUlA xen-2.4.16/drivers/net/e1000/e1000_hw.h
    1.13 +3e4540ccvQ9Dtoh9tV-L3ULUwN9X7g xen-2.4.16/drivers/net/e1000/e1000_main.c
    1.14 +3e4540cc3t7_y-YLeyMG2pX9xtdXPA xen-2.4.16/drivers/net/e1000/e1000_osdep.h
    1.15 +3e4540cct_8Ig-Y1W_vM2gS_u7mC0A xen-2.4.16/drivers/net/e1000/e1000_param.c
    1.16  3ddb79c0GejJrp1U6W4G6dYi-RiH4A xen-2.4.16/drivers/net/eepro100.c
    1.17 +3e465c00t2nochqR27eEY_FBjxsUCw xen-2.4.16/drivers/net/ne/8390.c
    1.18 +3e465c00AIRmk20x1vYETtnL71eGvA xen-2.4.16/drivers/net/ne/8390.h
    1.19 +3e465c00UIvPTAtAcgcQWCVFa2bwww xen-2.4.16/drivers/net/ne/Makefile
    1.20 +3e465c00rWSHiXmHuOWLRf7r2n8S3g xen-2.4.16/drivers/net/ne/ne.c
    1.21  3ddb79bfKvn9mt0kofpkw0QaWjxO6A xen-2.4.16/drivers/net/net_init.c
    1.22  3ddb79c0fQgORkFlqWZdP-6cDHyFIQ xen-2.4.16/drivers/net/pcnet32.c
    1.23  3ddb79bf_CBcu3QWYwq4bNAOnM2RqQ xen-2.4.16/drivers/net/setup.c
    1.24 +3e45a0c6u66EL2AI36eLOmf_abXs7g xen-2.4.16/drivers/net/tg3.c
    1.25 +3e45a0c6yrXj5pmQT0PvVSJ01YLABQ xen-2.4.16/drivers/net/tg3.h
    1.26  3ddb79bfh8ucmq_HqRSaURalpeAmPg xen-2.4.16/drivers/net/tulip/.depend
    1.27  3ddb79bfsJ-hdQ17EXTFiUOHisjNgQ xen-2.4.16/drivers/net/tulip/21142.c
    1.28  3ddb79bf0lzTL-ywAdOO7vctTYAmJA xen-2.4.16/drivers/net/tulip/ChangeLog
    1.29 @@ -149,6 +164,7 @@ 3ddb79c3I98vWcQR8xEo34JMJ4Ahyw xen-2.4.1
    1.30  3ddb79c3n_UbPuxlkNxvvLycClIkxA xen-2.4.16/include/asm-i386/mpspec.h
    1.31  3ddb79c2wa0dA_LGigxOelSGbJ284Q xen-2.4.16/include/asm-i386/msr.h
    1.32  3ddb79c3xjYnrv5t3VqYlR4tNEOl4Q xen-2.4.16/include/asm-i386/page.h
    1.33 +3e450943kzme29HPCtq5HNOVQkddfw xen-2.4.16/include/asm-i386/param.h
    1.34  3ddb79c3ysKUbxZuwKBRK3WXU2TlEg xen-2.4.16/include/asm-i386/pci.h
    1.35  3ddb79c3nm2zdzeO6Mj8g7ex3txgGw xen-2.4.16/include/asm-i386/pgalloc.h
    1.36  3ddb79c2QF5-pZGzuX4QukPCDAl59A xen-2.4.16/include/asm-i386/processor.h
    1.37 @@ -161,6 +177,7 @@ 3ddb79c3e9DCEoR-WzNxcOQDzLu7BQ xen-2.4.1
    1.38  3ddb79c3NiyQE2vQnyGiaBnNjBO1rA xen-2.4.16/include/asm-i386/spinlock.h
    1.39  3ddb79c3ezddh34MdelJpa5tNR00Dw xen-2.4.16/include/asm-i386/system.h
    1.40  3e397e66xPNc8eaSqC9pPbyAtRGzHA xen-2.4.16/include/asm-i386/time.h
    1.41 +3e450943TfE-iovQIY_tMO_VdGsPhA xen-2.4.16/include/asm-i386/timex.h
    1.42  3ddb79c4HugMq7IYGxcQKFBpKwKhzA xen-2.4.16/include/asm-i386/types.h
    1.43  3ddb79c3M2n1ROZH6xk3HbyN4CPDqg xen-2.4.16/include/asm-i386/uaccess.h
    1.44  3ddb79c3uPGcP_l_2xyGgBSWd5aC-Q xen-2.4.16/include/asm-i386/unaligned.h
    1.45 @@ -171,6 +188,7 @@ 3ddb79c4qbCoOFHrv9sCGshbWzBVlQ xen-2.4.1
    1.46  3ddb79c4R4iVwqIIeychVQYmIH4FUg xen-2.4.16/include/scsi/scsi_ioctl.h
    1.47  3ddb79c4yw_mfd4Uikn3v_IOPRpa1Q xen-2.4.16/include/scsi/scsicam.h
    1.48  3ddb79c4HKPMLvDBP9LxzPi_szVxGA xen-2.4.16/include/scsi/sg.h
    1.49 +3e450943xQztorJxTGW3BPZ4LhRHbw xen-2.4.16/include/stdarg.h
    1.50  3e397e66m2tO3s-J8Jnr7Ws_tGoPTg xen-2.4.16/include/xeno/ac_timer.h
    1.51  3ddb79c0nTsjSpVK4ZVTI9WwN24xtQ xen-2.4.16/include/xeno/blk.h
    1.52  3ddb79c0dVhTHLsv6CPTf4baKix4mA xen-2.4.16/include/xeno/blkdev.h
    1.53 @@ -200,6 +218,7 @@ 3ddb79c0MM575N4YvMSiw9EqKH4JDA xen-2.4.1
    1.54  3ddb79c1yHLp08JhgPxIMcZ8DwN9hg xen-2.4.16/include/xeno/if.h
    1.55  3ddb79c1RCWOkWPQRzbYVTX_e-E7CA xen-2.4.16/include/xeno/if_ether.h
    1.56  3ddb79c2IYah7z7hkzPyOiG8szKkyw xen-2.4.16/include/xeno/if_packet.h
    1.57 +3e4540ccefnCkeqtD_dW_CBOjXUSYw xen-2.4.16/include/xeno/if_vlan.h
    1.58  3df0af1c-QrOEqpPHq4uL3NZzCeJCg xen-2.4.16/include/xeno/in.h
    1.59  3ddb79c0GurNF9tDWqQbAwJFH8ugfA xen-2.4.16/include/xeno/init.h
    1.60  3ddb79c1Vi5VleJAOKHAlY0G2zAsgw xen-2.4.16/include/xeno/interrupt.h
    1.61 @@ -208,6 +227,7 @@ 3ddb79c1nzaWu8NoF4xCCMSFJR4MlA xen-2.4.1
    1.62  3ddb79c2qAxCOABlkKtD8Txohe-qEw xen-2.4.16/include/xeno/irq.h
    1.63  3ddb79c2b3qe-6Ann09FqZBF4IrJaQ xen-2.4.16/include/xeno/irq_cpustat.h
    1.64  3ddb79c11w_O7z7YZJnzuDSxaK5LlA xen-2.4.16/include/xeno/kdev_t.h
    1.65 +3e4540ccPHqIIv2pvnQ1gV8LUnoHIg xen-2.4.16/include/xeno/kernel.h
    1.66  3ddb79c1NfYlOrWNqgZkj9EwtFfJow xen-2.4.16/include/xeno/lib.h
    1.67  3ddb79c18Ajy7micDGQQfJ0zWgEHtA xen-2.4.16/include/xeno/list.h
    1.68  3ddb79c0_s2_wgV0cA6tztEaeyy1NA xen-2.4.16/include/xeno/major.h
    1.69 @@ -216,10 +236,12 @@ 3ddb79c1gs2VbLbQlw0dcDUXYIepDA xen-2.4.1
    1.70  3ddb79c13p9iHn1XAp0IS1qvj4yDsg xen-2.4.16/include/xeno/module.h
    1.71  3ddb79c1ieLZfGSFwfvvSQ2NK1BMSg xen-2.4.16/include/xeno/multiboot.h
    1.72  3ddb79c0CLfAlJLg1ohdPD-Jjn-jxg xen-2.4.16/include/xeno/netdevice.h
    1.73 +3e4540ccaugeWGdOuphJKj6WFw1jkw xen-2.4.16/include/xeno/notifier.h
    1.74  3ddb79c2Fg44_PBPVxHSC0gTOMq4Ow xen-2.4.16/include/xeno/pci.h
    1.75  3ddb79c0MOVXq8qZDQRGb6z64_xAwg xen-2.4.16/include/xeno/pci_ids.h
    1.76  3ddb79c2byJwwNNkiES__A9H4Cvc4g xen-2.4.16/include/xeno/pkt_sched.h
    1.77  3ddb79c04nQVR3EYM5L4zxDV_MCo1g xen-2.4.16/include/xeno/prefetch.h
    1.78 +3e4540ccU1sgCx8seIMGlahmMfv7yQ xen-2.4.16/include/xeno/reboot.h
    1.79  3ddb79c0LzqqS0LhAQ50ekgj4oGl7Q xen-2.4.16/include/xeno/sched.h
    1.80  3ddb79c0VDeD-Oft5eNfMneTU3D1dQ xen-2.4.16/include/xeno/skbuff.h
    1.81  3ddb79c14dXIhP7C2ahnoD08K90G_w xen-2.4.16/include/xeno/slab.h
    1.82 @@ -255,7 +277,6 @@ 3ddb79b75eo4PRXkT6Th9popt_SJhg xenolinux
    1.83  3ddb79b7Xyaoep6U0kLvx6Kx7OauDw xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/dom0_core.c
    1.84  3df9ce13K7qSLBtHV-01QHPW62649Q xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/dom0_memory.c
    1.85  3ddb79b7PulSkF9m3c7K5MkxHRf4hA xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/dom0_ops.h
    1.86 -3df9ce13tITy-OuYx_zQemsvqqLTWA xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/hypervisor_defs.h
    1.87  3ddba759XOjcl_OF-52dOYq7sgMykQ xenolinux-2.4.16-sparse/arch/xeno/drivers/dom0/vfr.c
    1.88  3ddb79b7s7yYBioHidSkIoHtQxYmOw xenolinux-2.4.16-sparse/arch/xeno/drivers/network/Makefile
    1.89  3ddb79b7CpLL98ScdpbKkVBktlbCtQ xenolinux-2.4.16-sparse/arch/xeno/drivers/network/network.c
    1.90 @@ -300,7 +321,6 @@ 3ddb79bbx682YH6vR2zbVOXwg73ULg xenolinux
    1.91  3ddb79bcJfHdwrPsjqgI33_OsGdVCg xenolinux-2.4.16-sparse/drivers/block/rd.c
    1.92  3ddb79bcpVu-IbnqwQqpRqsEbLpsuw xenolinux-2.4.16-sparse/drivers/char/tty_io.c
    1.93  3e15d5273gfR2fbcYe05kqBSAvCX_w xenolinux-2.4.16-sparse/fs/exec.c
    1.94 -3ddb79bba_zKpuurHVeWfgDkyPoq8A xenolinux-2.4.16-sparse/fs/nfs/nfsroot.c
    1.95  3ddb79b8VFtfWSCrXKPN2K21zd_vtw xenolinux-2.4.16-sparse/include/asm-xeno/a.out.h
    1.96  3ddb79b8Zzi13p3OAPV25QgiC3THAQ xenolinux-2.4.16-sparse/include/asm-xeno/apic.h
    1.97  3ddb79baZDlsdV_m6C5CXnWMl15p1g xenolinux-2.4.16-sparse/include/asm-xeno/apicdef.h
     2.1 --- a/xen-2.4.16/Makefile	Tue Feb 11 16:44:27 2003 +0000
     2.2 +++ b/xen-2.4.16/Makefile	Tue Feb 11 16:51:47 2003 +0000
     2.3 @@ -5,6 +5,7 @@ include Rules.mk
     2.4  
     2.5  default: $(TARGET)
     2.6  	gzip -f -9 < $(TARGET) > $(TARGET).gz
     2.7 +#	objdump -D -S image >image.s
     2.8  
     2.9  install: $(TARGET)
    2.10  	gzip -f -9 < $(TARGET) > $(TARGET).gz
     3.1 --- a/xen-2.4.16/Rules.mk	Tue Feb 11 16:44:27 2003 +0000
     3.2 +++ b/xen-2.4.16/Rules.mk	Tue Feb 11 16:51:47 2003 +0000
     3.3 @@ -21,10 +21,13 @@ ALL_OBJS += $(BASEDIR)/drivers/block/dri
     3.4  ALL_OBJS += $(BASEDIR)/drivers/ide/driver.o
     3.5  ALL_OBJS += $(BASEDIR)/arch/$(ARCH)/arch.o
     3.6  
     3.7 +HOSTCC     = gcc
     3.8 +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer 
     3.9 +
    3.10  include $(BASEDIR)/arch/$(ARCH)/Rules.mk
    3.11  
    3.12  %.o: %.c $(HDRS) Makefile
    3.13 -	$(CC) $(CFLAGS) -c $< -o $@
    3.14 +	$(CC) -g $(CFLAGS) -c $< -o $@
    3.15  
    3.16  %.o: %.S $(HDRS) Makefile
    3.17  	$(CC) $(CFLAGS) -D__ASSEMBLY__ -c $< -o $@
     4.1 --- a/xen-2.4.16/arch/i386/Rules.mk	Tue Feb 11 16:44:27 2003 +0000
     4.2 +++ b/xen-2.4.16/arch/i386/Rules.mk	Tue Feb 11 16:51:47 2003 +0000
     4.3 @@ -4,11 +4,11 @@
     4.4  CC := gcc
     4.5  LD := ld
     4.6  # Linker should relocate monitor to this address
     4.7 -MONITOR_BASE := 0xFC100000
     4.8 +MONITOR_BASE := 0xFC500000
     4.9  # Bootloader should load monitor to this real address
    4.10  LOAD_BASE    := 0x00100000
    4.11 -CFLAGS  := -fno-builtin -O3 -Wall -DMONITOR_BASE=$(MONITOR_BASE) 
    4.12 -CFLAGS  += -I$(BASEDIR)/include -D__KERNEL__ -DNDEBUG
    4.13 +CFLAGS  := -nostdinc -fno-builtin -O3 -Wall -DMONITOR_BASE=$(MONITOR_BASE) 
    4.14 +CFLAGS  += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__ -DNDEBUG
    4.15  LDFLAGS := -T xeno.lds -N
    4.16  
    4.17  
     5.1 --- a/xen-2.4.16/arch/i386/apic.c	Tue Feb 11 16:44:27 2003 +0000
     5.2 +++ b/xen-2.4.16/arch/i386/apic.c	Tue Feb 11 16:51:47 2003 +0000
     5.3 @@ -231,45 +231,16 @@ void __init sync_Arb_IDs(void)
     5.4  extern void __error_in_apic_c (void);
     5.5  
     5.6  /*
     5.7 - * An initial setup of the virtual wire mode.
     5.8 + * WAS: An initial setup of the virtual wire mode.
     5.9 + * NOW: We don't bother doing anything. All we need at this point
    5.10 + * is to receive timer ticks, so that 'jiffies' is incremented.
    5.11 + * If we're SMP, then we can assume BIOS did setup for us.
    5.12 + * If we're UP, then the APIC should be disabled (it is at reset).
    5.13 + * If we're UP and APIC is enabled, then BIOS is clever and has 
    5.14 + * probably done initial interrupt routing for us.
    5.15   */
    5.16  void __init init_bsp_APIC(void)
    5.17  {
    5.18 -    unsigned long value, ver;
    5.19 -
    5.20 -    /*
    5.21 -     * Don't do the setup now if we have a SMP BIOS as the
    5.22 -     * through-I/O-APIC virtual wire mode might be active.
    5.23 -     */
    5.24 -    if (smp_found_config || !cpu_has_apic)
    5.25 -        return;
    5.26 -
    5.27 -    value = apic_read(APIC_LVR);
    5.28 -    ver = GET_APIC_VERSION(value);
    5.29 -
    5.30 -    /*
    5.31 -     * Do not trust the local APIC being empty at bootup.
    5.32 -     */
    5.33 -    clear_local_APIC();
    5.34 -
    5.35 -    /*
    5.36 -     * Enable APIC.
    5.37 -     */
    5.38 -    value = apic_read(APIC_SPIV);
    5.39 -    value &= ~APIC_VECTOR_MASK;
    5.40 -    value |= APIC_SPIV_APIC_ENABLED;
    5.41 -    value |= APIC_SPIV_FOCUS_DISABLED;
    5.42 -    value |= SPURIOUS_APIC_VECTOR;
    5.43 -    apic_write_around(APIC_SPIV, value);
    5.44 -
    5.45 -    /*
    5.46 -     * Set up the virtual wire mode.
    5.47 -     */
    5.48 -    apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
    5.49 -    value = APIC_DM_NMI;
    5.50 -    if (!APIC_INTEGRATED(ver))		/* 82489DX */
    5.51 -        value |= APIC_LVT_LEVEL_TRIGGER;
    5.52 -    apic_write_around(APIC_LVT1, value);
    5.53  }
    5.54  
    5.55  void __init setup_local_APIC (void)
    5.56 @@ -429,10 +400,8 @@ static int __init detect_init_APIC (void
    5.57              wrmsr(MSR_IA32_APICBASE, l, h);
    5.58          }
    5.59      }
    5.60 -    /*
    5.61 -     * The APIC feature bit should now be enabled
    5.62 -     * in `cpuid'
    5.63 -     */
    5.64 +
    5.65 +    /* The APIC feature bit should now be enabled in `cpuid' */
    5.66      features = cpuid_edx(1);
    5.67      if (!(features & (1 << X86_FEATURE_APIC))) {
    5.68          printk("Could not enable APIC!\n");
     6.1 --- a/xen-2.4.16/arch/i386/boot/boot.S	Tue Feb 11 16:44:27 2003 +0000
     6.2 +++ b/xen-2.4.16/arch/i386/boot/boot.S	Tue Feb 11 16:51:47 2003 +0000
     6.3 @@ -216,13 +216,15 @@ nopaging_gdt_descr:
     6.4          .long   SYMBOL_NAME(gdt_table)-__PAGE_OFFSET
     6.5          
     6.6          ALIGN
     6.7 +/* NB. Rings != 0 get access up to 0xFC400000. This allows access to the */
     6.8 +/*     machine->physical mapping table. Ring 0 can access all memory.    */
     6.9  ENTRY(gdt_table)
    6.10          .quad 0x0000000000000000     /* NULL descriptor */
    6.11          .quad 0x0000000000000000     /* not used */
    6.12 -        .quad 0x00cfba000000bfff     /* 0x11 ring 1 3.95GB code at 0x0 */
    6.13 -        .quad 0x00cfb2000000bfff     /* 0x19 ring 1 3.95GB data at 0x0 */
    6.14 -        .quad 0x00cffa000000bfff     /* 0x23 ring 3 3.95GB code at 0x0 */
    6.15 -        .quad 0x00cff2000000bfff     /* 0x2b ring 3 3.95GB data at 0x0 */
    6.16 +        .quad 0x00cfba000000c3ff     /* 0x11 ring 1 3.95GB code at 0x0 */
    6.17 +        .quad 0x00cfb2000000c3ff     /* 0x19 ring 1 3.95GB data at 0x0 */
    6.18 +        .quad 0x00cffa000000c3ff     /* 0x23 ring 3 3.95GB code at 0x0 */
    6.19 +        .quad 0x00cff2000000c3ff     /* 0x2b ring 3 3.95GB data at 0x0 */
    6.20          .quad 0x00cf9a000000ffff     /* 0x30 ring 0 4.00GB code at 0x0 */
    6.21          .quad 0x00cf92000000ffff     /* 0x38 ring 0 4.00GB data at 0x0 */
    6.22          .fill NR_CPUS,8,0             /* space for TSS's */
     7.1 --- a/xen-2.4.16/arch/i386/entry.S	Tue Feb 11 16:44:27 2003 +0000
     7.2 +++ b/xen-2.4.16/arch/i386/entry.S	Tue Feb 11 16:51:47 2003 +0000
     7.3 @@ -102,7 +102,7 @@ PROCESSOR       =  0
     7.4  STATE           =  4
     7.5  HYP_EVENTS      =  8
     7.6  DOMAIN          = 12        
     7.7 -SHARED_INFO     = 24
     7.8 +SHARED_INFO     = 16
     7.9  
    7.10  /* Offsets in shared_info_t */
    7.11  EVENTS          =  0
    7.12 @@ -527,6 +527,7 @@ ENTRY(hypervisor_call_table)
    7.13          .long SYMBOL_NAME(do_set_debugreg)
    7.14          .long SYMBOL_NAME(do_get_debugreg)
    7.15          .long SYMBOL_NAME(do_update_descriptor)
    7.16 +        .long SYMBOL_NAME(do_set_fast_trap)
    7.17          .rept NR_syscalls-(.-hypervisor_call_table)/4
    7.18          .long SYMBOL_NAME(sys_ni_syscall)
    7.19  	.endr
     8.1 --- a/xen-2.4.16/arch/i386/i8259.c	Tue Feb 11 16:44:27 2003 +0000
     8.2 +++ b/xen-2.4.16/arch/i386/i8259.c	Tue Feb 11 16:51:47 2003 +0000
     8.3 @@ -46,7 +46,7 @@ BUILD_COMMON_IRQ()
     8.4  
     8.5  /*
     8.6   * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
     8.7 - * (these are usually mapped to vectors 0x20-0x2f)
     8.8 + * (these are usually mapped to vectors 0x30-0x3f)
     8.9   */
    8.10      BUILD_16_IRQS(0x0)
    8.11  
    8.12 @@ -64,7 +64,7 @@ BUILD_COMMON_IRQ()
    8.13      BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
    8.14      BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
    8.15      BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
    8.16 -    BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
    8.17 +    BUILD_16_IRQS(0xc)
    8.18  #endif
    8.19  
    8.20  #undef BUILD_16_IRQS
    8.21 @@ -111,7 +111,7 @@ BUILD_COMMON_IRQ()
    8.22          IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
    8.23  	IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
    8.24  	IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
    8.25 -	IRQLIST_16(0xc), IRQLIST_16(0xd)
    8.26 +	IRQLIST_16(0xc)
    8.27  #endif
    8.28      };
    8.29  
    8.30 @@ -344,7 +344,7 @@ void __init init_8259A(int auto_eoi)
    8.31       * outb_p - this has to work on a wide range of PC hardware.
    8.32       */
    8.33      outb_p(0x11, 0x20);	/* ICW1: select 8259A-1 init */
    8.34 -    outb_p(0x20 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
    8.35 +    outb_p(0x30 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
    8.36      outb_p(0x04, 0x21);	/* 8259A-1 (the master) has a slave on IR2 */
    8.37      if (auto_eoi)
    8.38          outb_p(0x03, 0x21);	/* master does Auto EOI */
    8.39 @@ -352,7 +352,7 @@ void __init init_8259A(int auto_eoi)
    8.40          outb_p(0x01, 0x21);	/* master expects normal EOI */
    8.41  
    8.42      outb_p(0x11, 0xA0);	/* ICW1: select 8259A-2 init */
    8.43 -    outb_p(0x20 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
    8.44 +    outb_p(0x30 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
    8.45      outb_p(0x02, 0xA1);	/* 8259A-2 is a slave on master's IR2 */
    8.46      outb_p(0x01, 0xA1);	/* (slave's support for AEOI in flat mode
    8.47                             is to be investigated) */
     9.1 --- a/xen-2.4.16/arch/i386/io_apic.c	Tue Feb 11 16:44:27 2003 +0000
     9.2 +++ b/xen-2.4.16/arch/i386/io_apic.c	Tue Feb 11 16:51:47 2003 +0000
     9.3 @@ -495,8 +495,10 @@ static int __init assign_irq_vector(int 
     9.4  		return IO_APIC_VECTOR(irq);
     9.5  next:
     9.6  	current_vector += 8;
     9.7 -	if (current_vector == HYPERVISOR_CALL_VECTOR)
     9.8 -		goto next;
     9.9 +        /* XXX Skip the guestOS -> Xen syscall vector! XXX */
    9.10 +	if (current_vector == HYPERVISOR_CALL_VECTOR) goto next;
    9.11 +        /* XXX Skip the Linux/BSD fast-trap vector! XXX */
    9.12 +        if (current_vector == 0x80) goto next;
    9.13  
    9.14  	if (current_vector > FIRST_SYSTEM_VECTOR) {
    9.15  		offset++;
    10.1 --- a/xen-2.4.16/arch/i386/ioremap.c	Tue Feb 11 16:44:27 2003 +0000
    10.2 +++ b/xen-2.4.16/arch/i386/ioremap.c	Tue Feb 11 16:51:47 2003 +0000
    10.3 @@ -15,8 +15,8 @@
    10.4  
    10.5  static unsigned long remap_base = 0;
    10.6  
    10.7 -#define L2_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED)
    10.8 -#define L1_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED|_PAGE_DIRTY)
    10.9 +#define L1_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED)
   10.10 +#define L2_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED|_PAGE_DIRTY)
   10.11  
   10.12  #define PAGE_ALIGN(addr)    (((addr)+PAGE_SIZE-1)&PAGE_MASK)
   10.13  
    11.1 --- a/xen-2.4.16/arch/i386/mm.c	Tue Feb 11 16:44:27 2003 +0000
    11.2 +++ b/xen-2.4.16/arch/i386/mm.c	Tue Feb 11 16:51:47 2003 +0000
    11.3 @@ -73,8 +73,14 @@ void __init paging_init(void)
    11.4      /* Create page table for ioremap(). */
    11.5      ioremap_pt = (void *)get_free_page(GFP_KERNEL);
    11.6      clear_page(ioremap_pt);
    11.7 -    idle0_pg_table[MAPCACHE_VIRT_START >> L2_PAGETABLE_SHIFT] = 
    11.8 +    idle0_pg_table[IOREMAP_VIRT_START >> L2_PAGETABLE_SHIFT] = 
    11.9          mk_l2_pgentry(__pa(ioremap_pt) | PAGE_HYPERVISOR);
   11.10 +
   11.11 +    /* Create read-only mapping of MPT for guest-OS use. */
   11.12 +    idle0_pg_table[READONLY_MPT_VIRT_START >> L2_PAGETABLE_SHIFT] =
   11.13 +        idle0_pg_table[RDWR_MPT_VIRT_START >> L2_PAGETABLE_SHIFT];
   11.14 +    mk_l2_readonly(idle0_pg_table + 
   11.15 +                   (READONLY_MPT_VIRT_START >> L2_PAGETABLE_SHIFT));
   11.16  }
   11.17  
   11.18  void __init zap_low_mappings (void)
    12.1 --- a/xen-2.4.16/arch/i386/process.c	Tue Feb 11 16:44:27 2003 +0000
    12.2 +++ b/xen-2.4.16/arch/i386/process.c	Tue Feb 11 16:51:47 2003 +0000
    12.3 @@ -12,8 +12,6 @@
    12.4   */
    12.5  
    12.6  #define __KERNEL_SYSCALLS__
    12.7 -#include <stdarg.h>
    12.8 -
    12.9  #include <xeno/config.h>
   12.10  #include <xeno/lib.h>
   12.11  #include <xeno/errno.h>
   12.12 @@ -326,6 +324,9 @@ void new_thread(struct task_struct *p,
   12.13  
   12.14      __save_flags(regs->eflags);
   12.15      regs->eflags |= X86_EFLAGS_IF;
   12.16 +
   12.17 +    /* No fast trap at start of day. */
   12.18 +    SET_DEFAULT_FAST_TRAP(&p->thread);
   12.19  }
   12.20  
   12.21  
   12.22 @@ -363,12 +364,17 @@ void new_thread(struct task_struct *p,
   12.23  /* NB. prev_p passed in %eax, next_p passed in %edx */
   12.24  void __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
   12.25  {
   12.26 +    extern struct desc_struct idt_table[];
   12.27      struct thread_struct *prev = &prev_p->thread,
   12.28          *next = &next_p->thread;
   12.29      struct tss_struct *tss = init_tss + smp_processor_id();
   12.30  
   12.31      unlazy_fpu(prev_p);
   12.32  
   12.33 +    /* Switch the fast-trap handler. */
   12.34 +    CLEAR_FAST_TRAP(&prev_p->thread);
   12.35 +    SET_FAST_TRAP(&next_p->thread);
   12.36 +
   12.37      tss->esp0 = next->esp0;
   12.38      tss->esp1 = next->esp1;
   12.39      tss->ss1  = next->ss1;
    13.1 --- a/xen-2.4.16/arch/i386/smpboot.c	Tue Feb 11 16:44:27 2003 +0000
    13.2 +++ b/xen-2.4.16/arch/i386/smpboot.c	Tue Feb 11 16:51:47 2003 +0000
    13.3 @@ -685,6 +685,8 @@ static void __init do_boot_cpu (int apic
    13.4      idle->thread.esp = idle->thread.esp0 = (unsigned long)idle + THREAD_SIZE;
    13.5      idle->thread.eip = (unsigned long) start_secondary;
    13.6  
    13.7 +    SET_DEFAULT_FAST_TRAP(&idle->thread);
    13.8 +
    13.9      /* start_eip had better be page-aligned! */
   13.10      start_eip = setup_trampoline();
   13.11  
    14.1 --- a/xen-2.4.16/arch/i386/traps.c	Tue Feb 11 16:44:27 2003 +0000
    14.2 +++ b/xen-2.4.16/arch/i386/traps.c	Tue Feb 11 16:51:47 2003 +0000
    14.3 @@ -277,20 +277,21 @@ asmlinkage void do_general_protection(st
    14.4       * Cunning trick to allow arbitrary "INT n" handling.
    14.5       * 
    14.6       * We set DPL == 0 on all vectors in the IDT. This prevents any INT <n>
    14.7 -     * instruction from trapping to the appropriate vector, when that might not 
    14.8 +     * instruction from trapping to the appropriate vector, when that might not
    14.9       * be expected by Xen or the guest OS. For example, that entry might be for
   14.10       * a fault handler (unlike traps, faults don't increment EIP), or might
   14.11       * expect an error code on the stack (which a software trap never
   14.12       * provides), or might be a hardware interrupt handler that doesn't like
   14.13 -     * being called spuriously.  
   14.14 +     * being called spuriously.
   14.15       * 
   14.16       * Instead, a GPF occurs with the faulting IDT vector in the error code.
   14.17 -     * Bit 1 is set to indicate that an IDT entry caused the fault.
   14.18 -     * Bit 0 is clear to indicate that it's a software fault, not hardware.
   14.19 +     * Bit 1 is set to indicate that an IDT entry caused the fault. Bit 0 is 
   14.20 +     * clear to indicate that it's a software fault, not hardware.
   14.21       * 
   14.22 -     * NOTE: Vectors 3 and 4 are dealt with from their own handler. This is okay
   14.23 -     * because they can only be triggered by an explicit DPL-checked instruction.
   14.24 -     * The DPL specified by the guest OS for these vectors is NOT CHECKED!!
   14.25 +     * NOTE: Vectors 3 and 4 are dealt with from their own handler. This is
   14.26 +     * okay because they can only be triggered by an explicit DPL-checked
   14.27 +     * instruction. The DPL specified by the guest OS for these vectors is NOT
   14.28 +     * CHECKED!!
   14.29       */
   14.30      if ( (error_code & 3) == 2 )
   14.31      {
   14.32 @@ -298,6 +299,7 @@ asmlinkage void do_general_protection(st
   14.33          ti = current->thread.traps + (error_code>>3);
   14.34          if ( ti->dpl >= (regs->xcs & 3) )
   14.35          {
   14.36 +            if ( (error_code>>3)==0x80 ) { printk("!!!\n"); BUG(); }
   14.37              gtb->flags = GTBF_TRAP_NOCODE;
   14.38              gtb->cs    = ti->cs;
   14.39              gtb->eip   = ti->address;
   14.40 @@ -570,6 +572,40 @@ long do_set_trap_table(trap_info_t *trap
   14.41  }
   14.42  
   14.43  
   14.44 +long do_set_fast_trap(int idx)
   14.45 +{
   14.46 +    trap_info_t *ti;
   14.47 +
   14.48 +    /* Index 0 is special: it disables fast traps. */
   14.49 +    if ( idx == 0 )
   14.50 +    {
   14.51 +        CLEAR_FAST_TRAP(&current->thread);
   14.52 +        SET_DEFAULT_FAST_TRAP(&current->thread);
   14.53 +        return 0;
   14.54 +    }
   14.55 +
   14.56 +    /*
   14.57 +     * We only fast-trap vectors 0x20-0x2f, and vector 0x80.
   14.58 +     * The former range is used by Windows and MS-DOS.
   14.59 +     * Vector 0x80 is used by Linux and the BSD variants.
   14.60 +     */
   14.61 +    if ( (idx != 0x80) && ((idx < 0x20) || (idx > 0x2f)) ) return -1;
   14.62 +
   14.63 +    ti = current->thread.traps + idx;
   14.64 +
   14.65 +    CLEAR_FAST_TRAP(&current->thread);
   14.66 +
   14.67 +    current->thread.fast_trap_idx    = idx;
   14.68 +    current->thread.fast_trap_desc.a = (ti->cs << 16) | (ti->address & 0xffff);
   14.69 +    current->thread.fast_trap_desc.b = 
   14.70 +        (ti->address & 0xffff0000) | 0x8f00 | (ti->dpl&3)<<13;
   14.71 +
   14.72 +    SET_FAST_TRAP(&current->thread);
   14.73 +
   14.74 +    return 0;
   14.75 +}
   14.76 +
   14.77 +
   14.78  long do_fpu_taskswitch(void)
   14.79  {
   14.80      current->flags |= PF_GUEST_STTS;
    15.1 --- a/xen-2.4.16/arch/i386/xeno.lds	Tue Feb 11 16:44:27 2003 +0000
    15.2 +++ b/xen-2.4.16/arch/i386/xeno.lds	Tue Feb 11 16:51:47 2003 +0000
    15.3 @@ -6,7 +6,7 @@ OUTPUT_ARCH(i386)
    15.4  ENTRY(start)
    15.5  SECTIONS
    15.6  {
    15.7 -  . = 0xFC000000 + 0x100000;
    15.8 +  . = 0xFC400000 + 0x100000;
    15.9    _text = .;			/* Text and read-only data */
   15.10    .text : {
   15.11  	*(.text)
    16.1 --- a/xen-2.4.16/common/dom0_ops.c	Tue Feb 11 16:44:27 2003 +0000
    16.2 +++ b/xen-2.4.16/common/dom0_ops.c	Tue Feb 11 16:51:47 2003 +0000
    16.3 @@ -1,4 +1,3 @@
    16.4 -
    16.5  /******************************************************************************
    16.6   * dom0_ops.c
    16.7   * 
    16.8 @@ -33,24 +32,27 @@ static unsigned int get_domnr(void)
    16.9  
   16.10  static void build_page_list(struct task_struct *p)
   16.11  {
   16.12 -    unsigned long * list;
   16.13 +    unsigned long *list;
   16.14      unsigned long curr;
   16.15 -    unsigned long page;
   16.16 +    struct list_head *list_ent;
   16.17 +
   16.18 +    curr = list_entry(p->pg_head.next, struct pfn_info, list) - frame_table;
   16.19 +    list = (unsigned long *)map_domain_mem(curr << PAGE_SHIFT);
   16.20  
   16.21 -    list = (unsigned long *)map_domain_mem(p->pg_head << PAGE_SHIFT);
   16.22 -    curr = p->pg_head;
   16.23 -    *list++ = p->pg_head;
   16.24 -    page = (frame_table + p->pg_head)->next;
   16.25 -    while(page != p->pg_head){
   16.26 -        if(!((unsigned long)list & (PAGE_SIZE-1))){
   16.27 -            curr = (frame_table + curr)->next;
   16.28 -            unmap_domain_mem((unsigned long)(list-1) & PAGE_MASK);
   16.29 +    list_for_each(list_ent, &p->pg_head)
   16.30 +    {
   16.31 +        *list++ = list_entry(list_ent, struct pfn_info, list) - frame_table;
   16.32 +
   16.33 +        if( ((unsigned long)list & ~PAGE_MASK) == 0 )
   16.34 +        {
   16.35 +            struct list_head *ent = frame_table[curr].list.next;
   16.36 +            curr = list_entry(ent, struct pfn_info, list) - frame_table;
   16.37 +            unmap_domain_mem(list-1);
   16.38              list = (unsigned long *)map_domain_mem(curr << PAGE_SHIFT);
   16.39          }
   16.40 -        *list++ = page;
   16.41 -        page = (frame_table + page)->next;
   16.42      }
   16.43 -    unmap_domain_mem((unsigned long)(list-1) & PAGE_MASK);
   16.44 +
   16.45 +    unmap_domain_mem(list);
   16.46  }
   16.47      
   16.48  long do_dom0_op(dom0_op_t *u_dom0_op)
   16.49 @@ -95,37 +97,20 @@ long do_dom0_op(dom0_op_t *u_dom0_op)
   16.50          pro = (pro+1) % smp_num_cpus;
   16.51          p->processor = pro;
   16.52  
   16.53 -        /* if we are not booting dom 0 than only mem 
   16.54 -         * needs to be allocated
   16.55 -         */
   16.56 -        if(dom != 0){
   16.57 +        if ( dom == 0 ) BUG();
   16.58  
   16.59 -            if(alloc_new_dom_mem(p, op.u.newdomain.memory_kb) != 0){
   16.60 -                ret = -1;
   16.61 -                break;
   16.62 -            }
   16.63 -            build_page_list(p);
   16.64 -            
   16.65 -            ret = p->domain;
   16.66 +        ret = alloc_new_dom_mem(p, op.u.newdomain.memory_kb);
   16.67 +        if ( ret != 0 ) break;
   16.68  
   16.69 -            op.u.newdomain.domain = ret;
   16.70 -            op.u.newdomain.pg_head = p->pg_head;
   16.71 -            copy_to_user(u_dom0_op, &op, sizeof(op));
   16.72 -
   16.73 -            break;
   16.74 -        }
   16.75 -
   16.76 -        /* executed only in case of domain 0 */
   16.77 -        ret = setup_guestos(p, &op.u.newdomain);    /* Load guest OS into @p */
   16.78 -        if ( ret != 0 ) 
   16.79 -        {
   16.80 -            p->state = TASK_DYING;
   16.81 -            release_task(p);
   16.82 -            break;
   16.83 -        }
   16.84 -        wake_up(p);          /* Put @p on runqueue */
   16.85 -        reschedule(p);       /* Force a scheduling decision on @p's CPU */
   16.86 +        build_page_list(p);
   16.87 +        
   16.88          ret = p->domain;
   16.89 +        
   16.90 +        op.u.newdomain.domain = ret;
   16.91 +        op.u.newdomain.pg_head = 
   16.92 +            list_entry(p->pg_head.next, struct pfn_info, list) -
   16.93 +            frame_table;
   16.94 +        copy_to_user(u_dom0_op, &op, sizeof(op));
   16.95      }
   16.96      break;
   16.97  
   16.98 @@ -143,13 +128,20 @@ long do_dom0_op(dom0_op_t *u_dom0_op)
   16.99      }
  16.100      break;
  16.101  
  16.102 -    case DOM0_MAPTASK:
  16.103 +    case DOM0_GETMEMLIST:
  16.104      {
  16.105 -        unsigned int dom = op.u.mapdomts.domain;
  16.106 -        
  16.107 -        op.u.mapdomts.ts_phy_addr = __pa(find_domain_by_id(dom));
  16.108 -        copy_to_user(u_dom0_op, &op, sizeof(op));
  16.109 +        int i;
  16.110 +        unsigned long pfn = op.u.getmemlist.start_pfn;
  16.111 +        unsigned long *buffer = op.u.getmemlist.buffer;
  16.112 +        struct list_head *list_ent;
  16.113  
  16.114 +        for ( i = 0; i < op.u.getmemlist.num_pfns; i++ )
  16.115 +        {
  16.116 +            /* XXX We trust DOM0 to give us a safe buffer. XXX */
  16.117 +            *buffer++ = pfn;
  16.118 +            list_ent = frame_table[pfn].list.next;
  16.119 +            pfn = list_entry(list_ent, struct pfn_info, list) - frame_table;
  16.120 +        }
  16.121      }
  16.122      break;
  16.123  
    17.1 --- a/xen-2.4.16/common/domain.c	Tue Feb 11 16:44:27 2003 +0000
    17.2 +++ b/xen-2.4.16/common/domain.c	Tue Feb 11 16:51:47 2003 +0000
    17.3 @@ -15,10 +15,8 @@
    17.4  #include <asm/msr.h>
    17.5  #include <xeno/multiboot.h>
    17.6  
    17.7 -#define L2_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_ACCESSED)
    17.8 -#define L1_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_ACCESSED|_PAGE_DIRTY)
    17.9 -
   17.10 -extern int do_process_page_updates_bh(page_update_request_t *, int);
   17.11 +#define L1_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_ACCESSED)
   17.12 +#define L2_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_ACCESSED|_PAGE_DIRTY)
   17.13  
   17.14  extern int nr_mods;
   17.15  extern module_t *mod;
   17.16 @@ -57,7 +55,8 @@ struct task_struct *do_newdomain(void)
   17.17       */
   17.18      p->blk_ring_base = (blk_ring_t *)(p->shared_info + 1);
   17.19      p->net_ring_base = (net_ring_t *)(p->blk_ring_base + 1);
   17.20 -    p->pg_head = p->tot_pages = 0;
   17.21 +    INIT_LIST_HEAD(&p->pg_head);
   17.22 +    p->tot_pages = 0;
   17.23      write_lock_irqsave(&tasklist_lock, flags);
   17.24      SET_LINKS(p);
   17.25      write_unlock_irqrestore(&tasklist_lock, flags);
   17.26 @@ -140,7 +139,7 @@ long kill_other_domain(unsigned int dom)
   17.27  /* Release resources belonging to task @p. */
   17.28  void release_task(struct task_struct *p)
   17.29  {
   17.30 -    //ASSERT(!__task_on_runqueue(p));
   17.31 +    struct list_head *list_ent, *tmp;
   17.32      ASSERT(p->state == TASK_DYING);
   17.33      ASSERT(!p->has_cpu);
   17.34      write_lock_irq(&tasklist_lock);
   17.35 @@ -158,13 +157,22 @@ void release_task(struct task_struct *p)
   17.36      }
   17.37      if ( p->mm.perdomain_pt ) free_page((unsigned long)p->mm.perdomain_pt);
   17.38      free_page((unsigned long)p->shared_info);
   17.39 +
   17.40 +    list_for_each_safe(list_ent, tmp, &p->pg_head)
   17.41 +    {
   17.42 +        struct pfn_info *pf = list_entry(list_ent, struct pfn_info, list);
   17.43 +        pf->type_count = pf->tot_count = pf->flags = 0;
   17.44 +        list_del(list_ent);
   17.45 +        list_add(list_ent, &free_list);
   17.46 +    }
   17.47 +
   17.48      free_task_struct(p);
   17.49  }
   17.50  
   17.51  unsigned int alloc_new_dom_mem(struct task_struct *p, unsigned int kbytes)
   17.52  {
   17.53      struct list_head *temp;
   17.54 -    struct pfn_info *pf, *pf_head;
   17.55 +    struct pfn_info *pf;
   17.56      unsigned int alloc_pfns;
   17.57      unsigned int req_pages;
   17.58  
   17.59 @@ -172,35 +180,18 @@ unsigned int alloc_new_dom_mem(struct ta
   17.60      req_pages = kbytes >> (PAGE_SHIFT - 10);
   17.61  
   17.62      /* is there enough mem to serve the request? */   
   17.63 -    if(req_pages > free_pfns)
   17.64 -        return -1;
   17.65 +    if ( req_pages > free_pfns ) return -1;
   17.66      
   17.67      /* allocate pages and build a thread through frame_table */
   17.68      temp = free_list.next;
   17.69 -
   17.70 -    /* allocate first page */
   17.71 -    pf = list_entry(temp, struct pfn_info, list);
   17.72 -    pf->flags |= p->domain;
   17.73 -    temp = temp->next;
   17.74 -    list_del(&pf->list);
   17.75 -    pf->next = pf->prev = p->pg_head = (pf - frame_table);
   17.76 -    pf->type_count = pf->tot_count = 0;
   17.77 -    free_pfns--;
   17.78 -    pf_head = pf;
   17.79 -
   17.80 -    /* allocate the rest */
   17.81 -    for(alloc_pfns = req_pages - 1; alloc_pfns; alloc_pfns--){
   17.82 +    for ( alloc_pfns = 0; alloc_pfns < req_pages; alloc_pfns++ )
   17.83 +    {
   17.84          pf = list_entry(temp, struct pfn_info, list);
   17.85          pf->flags |= p->domain;
   17.86 +        pf->type_count = pf->tot_count = 0;
   17.87          temp = temp->next;
   17.88          list_del(&pf->list);
   17.89 -
   17.90 -        pf->next = p->pg_head;
   17.91 -        pf->prev = pf_head->prev;
   17.92 -        (frame_table + pf_head->prev)->next = (pf - frame_table);
   17.93 -        pf_head->prev = (pf - frame_table);
   17.94 -        pf->type_count = pf->tot_count = 0;
   17.95 -
   17.96 +        list_add_tail(&pf->list, &p->pg_head);
   17.97          free_pfns--;
   17.98      }
   17.99      
  17.100 @@ -233,31 +224,13 @@ int final_setup_guestos(struct task_stru
  17.101      l1_pgentry_t * l1tab;
  17.102      start_info_t * virt_startinfo_addr;
  17.103      unsigned long virt_stack_addr;
  17.104 +    unsigned long long time;
  17.105      unsigned long phys_l2tab;
  17.106 -    page_update_request_t * pgt_updates;
  17.107 -    unsigned long curr_update_phys;
  17.108 -    unsigned long count;
  17.109      net_ring_t *net_ring;
  17.110      net_vif_t *net_vif;
  17.111      char *dst;    // temporary
  17.112      int i;        // temporary
  17.113  
  17.114 -    /* first of all, set up domain pagetables */
  17.115 -    pgt_updates = (page_update_request_t *)
  17.116 -        map_domain_mem(meminfo->pgt_update_arr);
  17.117 -    curr_update_phys = meminfo->pgt_update_arr;
  17.118 -    for(count = 0; count < meminfo->num_pgt_updates; count++){
  17.119 -        do_process_page_updates_bh(pgt_updates, 1);
  17.120 -        pgt_updates++;
  17.121 -        if(!((unsigned long)pgt_updates & (PAGE_SIZE-1))){
  17.122 -            unmap_domain_mem((void *)((unsigned long)(pgt_updates-1) & PAGE_MASK));
  17.123 -            curr_update_phys = (frame_table + (curr_update_phys >> PAGE_SHIFT))->next 
  17.124 -                << PAGE_SHIFT;
  17.125 -            pgt_updates = (page_update_request_t *)map_domain_mem(curr_update_phys);
  17.126 -        }
  17.127 -    }
  17.128 -    unmap_domain_mem((void *)((unsigned long)(pgt_updates-1) & PAGE_MASK));
  17.129 -
  17.130      /* entries 0xe0000000 onwards in page table must contain hypervisor
  17.131       * mem mappings - set them up.
  17.132       */
  17.133 @@ -304,11 +277,6 @@ int final_setup_guestos(struct task_stru
  17.134      virt_startinfo_addr->shared_info = (shared_info_t *)meminfo->virt_shinfo_addr;
  17.135      virt_startinfo_addr->pt_base = meminfo->virt_load_addr + 
  17.136                      ((p->tot_pages - 1) << PAGE_SHIFT);
  17.137 -
  17.138 -    /* now, this is just temprorary before we switch to pseudo phys
  17.139 -     * addressing. this works only for contiguous chunks of memory!!!
  17.140 -     */
  17.141 -    virt_startinfo_addr->phys_base = p->pg_head << PAGE_SHIFT;
  17.142      
  17.143      /* Add virtual network interfaces and point to them in startinfo. */
  17.144      while (meminfo->num_vifs-- > 0) {
  17.145 @@ -370,9 +338,12 @@ int final_setup_guestos(struct task_stru
  17.146  static unsigned long alloc_page_from_domain(unsigned long * cur_addr, 
  17.147      unsigned long * index)
  17.148  {
  17.149 -    *cur_addr = (frame_table + (*cur_addr >> PAGE_SHIFT))->prev << PAGE_SHIFT;
  17.150 +    unsigned long ret = *cur_addr;
  17.151 +    struct list_head *ent = frame_table[ret >> PAGE_SHIFT].list.prev;
  17.152 +    *cur_addr = list_entry(ent, struct pfn_info, list) - frame_table;
  17.153 +    *cur_addr <<= PAGE_SHIFT;
  17.154      (*index)--;    
  17.155 -    return *cur_addr;
  17.156 +    return ret;
  17.157  }
  17.158  
  17.159  /* setup_guestos is used for building dom0 solely. other domains are built in
  17.160 @@ -380,6 +351,7 @@ static unsigned long alloc_page_from_dom
  17.161   */
  17.162  int setup_guestos(struct task_struct *p, dom0_newdomain_t *params)
  17.163  {
  17.164 +    struct list_head *list_ent;
  17.165      char *src, *dst;
  17.166      int i, dom = p->domain;
  17.167      unsigned long phys_l1tab, phys_l2tab;
  17.168 @@ -387,15 +359,18 @@ int setup_guestos(struct task_struct *p,
  17.169      unsigned long virt_load_address, virt_stack_address, virt_shinfo_address;
  17.170      unsigned long virt_ftable_start, virt_ftable_end, ft_mapping;
  17.171      start_info_t  *virt_startinfo_address;
  17.172 +    unsigned long long time;
  17.173      unsigned long count;
  17.174      unsigned long alloc_index;
  17.175 -    unsigned long ft_pages;
  17.176      l2_pgentry_t *l2tab, *l2start;
  17.177      l1_pgentry_t *l1tab = NULL, *l1start = NULL;
  17.178      struct pfn_info *page = NULL;
  17.179      net_ring_t *net_ring;
  17.180      net_vif_t *net_vif;
  17.181  
  17.182 +    /* Sanity! */
  17.183 +    if ( p->domain != 0 ) BUG();
  17.184 +
  17.185      if ( strncmp(__va(mod[0].mod_start), "XenoGues", 8) )
  17.186      {
  17.187          printk("DOM%d: Invalid guest OS image\n", dom);
  17.188 @@ -411,7 +386,9 @@ int setup_guestos(struct task_struct *p,
  17.189      }
  17.190  
  17.191      if ( alloc_new_dom_mem(p, params->memory_kb) ) return -ENOMEM;
  17.192 -    alloc_address = p->pg_head << PAGE_SHIFT;
  17.193 +    alloc_address = list_entry(p->pg_head.prev, struct pfn_info, list) -
  17.194 +        frame_table;
  17.195 +    alloc_address <<= PAGE_SHIFT;
  17.196      alloc_index = p->tot_pages;
  17.197  
  17.198      if ( (mod[nr_mods-1].mod_end-mod[0].mod_start) > 
  17.199 @@ -443,17 +420,15 @@ int setup_guestos(struct task_struct *p,
  17.200      p->mm.pagetable = mk_pagetable(phys_l2tab);
  17.201  
  17.202      /*
  17.203 -     * NB. The upper limit on this loop does one extra page + pages for frame table. 
  17.204 -     * This is to make sure a pte exists when we want to map the shared_info struct
  17.205 -     * and frame table struct.
  17.206 +     * NB. The upper limit on this loop does one extra page. This is to make 
  17.207 +     * sure a pte exists when we want to map the shared_info struct.
  17.208       */
  17.209  
  17.210 -    ft_pages = frame_table_size >> PAGE_SHIFT;
  17.211      l2tab += l2_table_offset(virt_load_address);
  17.212 -    cur_address = p->pg_head << PAGE_SHIFT;
  17.213 -    for ( count  = 0;
  17.214 -          count < p->tot_pages + 1 + ft_pages;
  17.215 -          count++)
  17.216 +    cur_address = list_entry(p->pg_head.next, struct pfn_info, list) -
  17.217 +        frame_table;
  17.218 +    cur_address <<= PAGE_SHIFT;
  17.219 +    for ( count = 0; count < p->tot_pages + 1; count++ )
  17.220      {
  17.221          if ( !((unsigned long)l1tab & (PAGE_SIZE-1)) )
  17.222          {
  17.223 @@ -467,23 +442,32 @@ int setup_guestos(struct task_struct *p,
  17.224          }
  17.225          *l1tab++ = mk_l1_pgentry(cur_address|L1_PROT);
  17.226          
  17.227 -        if(count < p->tot_pages)
  17.228 +        if ( count < p->tot_pages )
  17.229          {
  17.230              page = frame_table + (cur_address >> PAGE_SHIFT);
  17.231              page->flags = dom | PGT_writeable_page;
  17.232              page->type_count = page->tot_count = 1;
  17.233 +            /* Set up the MPT entry. */
  17.234 +            machine_to_phys_mapping[cur_address >> PAGE_SHIFT] = count;
  17.235          }
  17.236  
  17.237 -        cur_address = ((frame_table + (cur_address >> PAGE_SHIFT))->next) << PAGE_SHIFT;
  17.238 +        list_ent = frame_table[cur_address >> PAGE_SHIFT].list.next;
  17.239 +        cur_address = list_entry(list_ent, struct pfn_info, list) -
  17.240 +            frame_table;
  17.241 +        cur_address <<= PAGE_SHIFT;
  17.242      }
  17.243      unmap_domain_mem(l1start);
  17.244  
  17.245      /* pages that are part of page tables must be read only */
  17.246 -    cur_address = p->pg_head << PAGE_SHIFT;
  17.247 -    for(count = 0;
  17.248 -        count < alloc_index;
  17.249 -        count++){
  17.250 -        cur_address = ((frame_table + (cur_address >> PAGE_SHIFT))->next) << PAGE_SHIFT;
  17.251 +    cur_address = list_entry(p->pg_head.next, struct pfn_info, list) -
  17.252 +        frame_table;
  17.253 +    cur_address <<= PAGE_SHIFT;
  17.254 +    for ( count = 0; count < alloc_index; count++ ) 
  17.255 +    {
  17.256 +        list_ent = frame_table[cur_address >> PAGE_SHIFT].list.next;
  17.257 +        cur_address = list_entry(list_ent, struct pfn_info, list) -
  17.258 +            frame_table;
  17.259 +        cur_address <<= PAGE_SHIFT;
  17.260      }
  17.261  
  17.262      l2tab = l2start + l2_table_offset(virt_load_address + 
  17.263 @@ -491,11 +475,11 @@ int setup_guestos(struct task_struct *p,
  17.264      l1start = l1tab = map_domain_mem(l2_pgentry_to_phys(*l2tab));
  17.265      l1tab += l1_table_offset(virt_load_address + (alloc_index << PAGE_SHIFT));
  17.266      l2tab++;
  17.267 -    for(count = alloc_index;
  17.268 -        count < p->tot_pages;
  17.269 -        count++){
  17.270 +    for ( count = alloc_index; count < p->tot_pages; count++ ) 
  17.271 +    {
  17.272          *l1tab++ = mk_l1_pgentry(l1_pgentry_val(*l1tab) & ~_PAGE_RW);
  17.273 -        if(!((unsigned long)l1tab & (PAGE_SIZE - 1))){
  17.274 +        if( !((unsigned long)l1tab & (PAGE_SIZE - 1)) )
  17.275 +        {
  17.276              unmap_domain_mem(l1start);
  17.277              l1start = l1tab = map_domain_mem(l2_pgentry_to_phys(*l2tab));
  17.278              l2tab++;
  17.279 @@ -504,7 +488,10 @@ int setup_guestos(struct task_struct *p,
  17.280          page->flags = dom | PGT_l1_page_table;
  17.281          page->tot_count++;
  17.282          
  17.283 -        cur_address = ((frame_table + (cur_address >> PAGE_SHIFT))->next) << PAGE_SHIFT;
  17.284 +        list_ent = frame_table[cur_address >> PAGE_SHIFT].list.next;
  17.285 +        cur_address = list_entry(list_ent, struct pfn_info, list) -
  17.286 +            frame_table;
  17.287 +        cur_address <<= PAGE_SHIFT;
  17.288      }
  17.289      page->flags = dom | PGT_l2_page_table;
  17.290      unmap_domain_mem(l1start);
  17.291 @@ -526,21 +513,6 @@ int setup_guestos(struct task_struct *p,
  17.292      virt_startinfo_address = (start_info_t *)
  17.293          (virt_load_address + ((alloc_index - 1) << PAGE_SHIFT));
  17.294      virt_stack_address  = (unsigned long)virt_startinfo_address;
  17.295 -
  17.296 -    /* set up frame_table mapping */
  17.297 -    ft_mapping = (unsigned long)frame_table;
  17.298 -    virt_ftable_start = virt_shinfo_address + PAGE_SIZE; 
  17.299 -    virt_ftable_end = virt_ftable_start + frame_table_size;
  17.300 -    for(cur_address = virt_ftable_start;
  17.301 -        cur_address < virt_ftable_end;
  17.302 -        cur_address += PAGE_SIZE){
  17.303 -        l2tab = l2start + l2_table_offset(cur_address);
  17.304 -        l1start = l1tab = map_domain_mem(l2_pgentry_to_phys(*l2tab));
  17.305 -        l1tab += l1_table_offset(cur_address);
  17.306 -        *l1tab = mk_l1_pgentry(__pa(ft_mapping)|L1_PROT);
  17.307 -        unmap_domain_mem(l1start);
  17.308 -        ft_mapping += PAGE_SIZE;
  17.309 -    }
  17.310      
  17.311      unmap_domain_mem(l2start);
  17.312  
  17.313 @@ -561,8 +533,6 @@ int setup_guestos(struct task_struct *p,
  17.314          (shared_info_t *)virt_shinfo_address;
  17.315      virt_startinfo_address->pt_base = virt_load_address + 
  17.316          ((p->tot_pages - 1) << PAGE_SHIFT); 
  17.317 -    virt_startinfo_address->phys_base = p->pg_head << PAGE_SHIFT;
  17.318 -    virt_startinfo_address->frame_table = virt_ftable_start;
  17.319  
  17.320      /* Add virtual network interfaces and point to them in startinfo. */
  17.321      while (params->num_vifs-- > 0) {
    18.1 --- a/xen-2.4.16/common/kernel.c	Tue Feb 11 16:44:27 2003 +0000
    18.2 +++ b/xen-2.4.16/common/kernel.c	Tue Feb 11 16:51:47 2003 +0000
    18.3 @@ -43,6 +43,7 @@ void start_of_day(void);
    18.4  unsigned long opt_ipbase=0, opt_nfsserv=0, opt_gateway=0, opt_netmask=0;
    18.5  unsigned char opt_nfsroot[50]="";
    18.6  unsigned int opt_dom0_mem = 16000; /* default kbytes for DOM0 */
    18.7 +unsigned int opt_ne_base = 0; /* NE2k NICs cannot be probed */
    18.8  enum { OPT_IP, OPT_STR, OPT_UINT };
    18.9  static struct {
   18.10      unsigned char *name;
   18.11 @@ -55,6 +56,7 @@ static struct {
   18.12      { "netmask",  OPT_IP,   &opt_netmask },
   18.13      { "nfsroot",  OPT_STR,  &opt_nfsroot },
   18.14      { "dom0_mem", OPT_UINT, &opt_dom0_mem }, 
   18.15 +    { "ne_base",  OPT_UINT, &opt_ne_base },
   18.16      { NULL,       0,        NULL     }
   18.17  };
   18.18  
   18.19 @@ -143,7 +145,8 @@ void cmain (unsigned long magic, multibo
   18.20                      }
   18.21                      else /* opts[i].type == OPT_UINT */
   18.22                      {
   18.23 -                        *(unsigned int *)opts[i].var = simple_strtol(opt, (char **)&opt, 10);
   18.24 +                        *(unsigned int *)opts[i].var =
   18.25 +                            simple_strtol(opt, (char **)&opt, 0);
   18.26                      }
   18.27                      break;
   18.28                  }
    19.1 --- a/xen-2.4.16/common/memory.c	Tue Feb 11 16:44:27 2003 +0000
    19.2 +++ b/xen-2.4.16/common/memory.c	Tue Feb 11 16:51:47 2003 +0000
    19.3 @@ -224,20 +224,20 @@ void __init init_frametable(unsigned lon
    19.4      max_page = nr_pages;
    19.5      frame_table_size = nr_pages * sizeof(struct pfn_info);
    19.6      frame_table_size = (frame_table_size + PAGE_SIZE - 1) & PAGE_MASK;
    19.7 -    free_pfns = nr_pages - 
    19.8 -        ((MAX_MONITOR_ADDRESS + frame_table_size) >> PAGE_SHIFT);
    19.9 +    frame_table = (frame_table_t *)FRAMETABLE_VIRT_START;
   19.10 +    memset(frame_table, 0, frame_table_size);
   19.11  
   19.12 -    frame_table = phys_to_virt(MAX_MONITOR_ADDRESS);
   19.13 -    memset(frame_table, 0, frame_table_size);
   19.14 +    free_pfns = 0;
   19.15  
   19.16      /* Put all domain-allocatable memory on a free list. */
   19.17      INIT_LIST_HEAD(&free_list);
   19.18 -    for( page_index = (MAX_MONITOR_ADDRESS + frame_table_size) >> PAGE_SHIFT; 
   19.19 -         page_index < nr_pages; 
   19.20 +    for( page_index = (__pa(frame_table) + frame_table_size) >> PAGE_SHIFT; 
   19.21 +         page_index < nr_pages;
   19.22           page_index++ )      
   19.23      {
   19.24          pf = list_entry(&frame_table[page_index].list, struct pfn_info, list);
   19.25          list_add_tail(&pf->list, &free_list);
   19.26 +        free_pfns++;
   19.27      }
   19.28  }
   19.29  
   19.30 @@ -697,34 +697,22 @@ static int do_extended_command(unsigned 
   19.31      return err;
   19.32  }
   19.33  
   19.34 -/* functions to handle page table updates: upper half is invoked in case pt updates
   19.35 - * are requested by a domain and it invokes copy_from_user. bottom half is invoked
   19.36 - * both in case of domain downcall and domain building by hypervisor.
   19.37 - */
   19.38 -page_update_request_t * do_process_page_updates_uh(page_update_request_t *updates,
   19.39 -    int count)
   19.40 +
   19.41 +int do_process_page_updates(page_update_request_t *ureqs, int count)
   19.42  {
   19.43 -    page_update_request_t * ret = kmalloc(sizeof(page_update_request_t) * count, 
   19.44 -        GFP_KERNEL);
   19.45 -
   19.46 -    if ( copy_from_user(ret, updates, sizeof(page_update_request_t) * count) )
   19.47 -    {
   19.48 -        kill_domain_with_errmsg("Cannot read page update request");
   19.49 -    }
   19.50 -    
   19.51 -    return ret;
   19.52 -}
   19.53 -
   19.54 -/* Apply updates to page table @pagetable_id within the current domain. */
   19.55 -int do_process_page_updates_bh(page_update_request_t * cur, int count)
   19.56 -{
   19.57 +    page_update_request_t req;
   19.58      unsigned long flags, pfn;
   19.59      struct pfn_info *page;
   19.60      int err = 0, i;
   19.61  
   19.62      for ( i = 0; i < count; i++ )
   19.63      {
   19.64 -        pfn = cur->ptr >> PAGE_SHIFT;
   19.65 +        if ( copy_from_user(&req, ureqs, sizeof(req)) )
   19.66 +        {
   19.67 +            kill_domain_with_errmsg("Cannot read page update request");
   19.68 +        } 
   19.69 +
   19.70 +        pfn = req.ptr >> PAGE_SHIFT;
   19.71          if ( pfn >= max_page )
   19.72          {
   19.73              MEM_LOG("Page out of range (%08lx > %08lx)", pfn, max_page);
   19.74 @@ -734,9 +722,8 @@ int do_process_page_updates_bh(page_upda
   19.75          err = 1;
   19.76  
   19.77          /* Least significant bits of 'ptr' demux the operation type. */
   19.78 -        switch ( cur->ptr & (sizeof(l1_pgentry_t)-1) )
   19.79 +        switch ( req.ptr & (sizeof(l1_pgentry_t)-1) )
   19.80          {
   19.81 -
   19.82              /*
   19.83               * PGREQ_NORMAL: Normal update to any level of page table.
   19.84               */
   19.85 @@ -749,17 +736,35 @@ int do_process_page_updates_bh(page_upda
   19.86                  switch ( (flags & PG_type_mask) )
   19.87                  {
   19.88                  case PGT_l1_page_table: 
   19.89 -                    err = mod_l1_entry(cur->ptr, mk_l1_pgentry(cur->val)); 
   19.90 +                    err = mod_l1_entry(req.ptr, mk_l1_pgentry(req.val)); 
   19.91                      break;
   19.92                  case PGT_l2_page_table: 
   19.93 -                    err = mod_l2_entry(cur->ptr, mk_l2_pgentry(cur->val)); 
   19.94 +                    err = mod_l2_entry(req.ptr, mk_l2_pgentry(req.val)); 
   19.95                      break;
   19.96                  default:
   19.97 -                    MEM_LOG("Update to non-pt page %08lx", cur->ptr);
   19.98 +                    MEM_LOG("Update to non-pt page %08lx", req.ptr);
   19.99                      break;
  19.100                  }
  19.101              }
  19.102 +            else
  19.103 +            {
  19.104 +                MEM_LOG("Bad domain normal update (dom %d, pfn %ld)",
  19.105 +                        current->domain, pfn);
  19.106 +            }
  19.107 +            break;
  19.108  
  19.109 +        case PGREQ_MPT_UPDATE:
  19.110 +            page = frame_table + pfn;
  19.111 +            if ( DOMAIN_OKAY(page->flags) )
  19.112 +            {
  19.113 +                machine_to_phys_mapping[pfn] = req.val;
  19.114 +                err = 0;
  19.115 +            }
  19.116 +            else
  19.117 +            {
  19.118 +                MEM_LOG("Bad domain MPT update (dom %d, pfn %ld)",
  19.119 +                        current->domain, pfn);
  19.120 +            }
  19.121              break;
  19.122  
  19.123              /*
  19.124 @@ -767,12 +772,27 @@ int do_process_page_updates_bh(page_upda
  19.125               * in the least-siginificant bits of the 'value' field.
  19.126               */
  19.127          case PGREQ_EXTENDED_COMMAND:
  19.128 -            cur->ptr &= ~(sizeof(l1_pgentry_t) - 1);
  19.129 -            err = do_extended_command(cur->ptr, cur->val);
  19.130 +            req.ptr &= ~(sizeof(l1_pgentry_t) - 1);
  19.131 +            err = do_extended_command(req.ptr, req.val);
  19.132              break;
  19.133  
  19.134 +        case PGREQ_UNCHECKED_UPDATE:
  19.135 +            req.ptr &= ~(sizeof(l1_pgentry_t) - 1);
  19.136 +            if ( current->domain == 0 )
  19.137 +            {
  19.138 +                unsigned long *ptr = map_domain_mem(req.ptr);
  19.139 +                *ptr = req.val;
  19.140 +                unmap_domain_mem(ptr);
  19.141 +                err = 0;
  19.142 +            }
  19.143 +            else
  19.144 +            {
  19.145 +                MEM_LOG("Bad unchecked update attempt");
  19.146 +            }
  19.147 +            break;
  19.148 +            
  19.149          default:
  19.150 -            MEM_LOG("Invalid page update command %08lx", cur->ptr);
  19.151 +            MEM_LOG("Invalid page update command %08lx", req.ptr);
  19.152              break;
  19.153          }
  19.154  
  19.155 @@ -781,7 +801,7 @@ int do_process_page_updates_bh(page_upda
  19.156              kill_domain_with_errmsg("Illegal page update request");
  19.157          }
  19.158  
  19.159 -        cur++;
  19.160 +        ureqs++;
  19.161      }
  19.162  
  19.163      if ( tlb_flush[smp_processor_id()] )
  19.164 @@ -790,20 +810,8 @@ int do_process_page_updates_bh(page_upda
  19.165          __asm__ __volatile__ (
  19.166              "movl %%eax,%%cr3" : : 
  19.167              "a" (pagetable_val(current->mm.pagetable)));
  19.168 +
  19.169      }
  19.170  
  19.171      return(0);
  19.172  }
  19.173 -
  19.174 -/* Apply updates to page table @pagetable_id within the current domain. */
  19.175 -int do_process_page_updates(page_update_request_t *updates, int count)
  19.176 -{
  19.177 -    page_update_request_t * pg_updates;
  19.178 -    int ret;
  19.179 -
  19.180 -    pg_updates = do_process_page_updates_uh(updates, count);
  19.181 -    ret = do_process_page_updates_bh(pg_updates, count);
  19.182 -    kfree(pg_updates);
  19.183 -
  19.184 -    return ret;
  19.185 -}
    20.1 --- a/xen-2.4.16/drivers/net/Makefile	Tue Feb 11 16:44:27 2003 +0000
    20.2 +++ b/xen-2.4.16/drivers/net/Makefile	Tue Feb 11 16:51:47 2003 +0000
    20.3 @@ -2,9 +2,15 @@
    20.4  include $(BASEDIR)/Rules.mk
    20.5  
    20.6  default: $(OBJS)
    20.7 +	$(MAKE) -C ne
    20.8  	$(MAKE) -C tulip
    20.9 -	$(LD) -r -o driver.o $(OBJS) tulip/tulip.o 
   20.10 +	$(MAKE) -C e1000
   20.11 +	$(LD) -r -o driver.o $(OBJS) tulip/tulip.o e1000/e1000.o ne/ne_drv.o
   20.12  
   20.13  clean:
   20.14 +	$(MAKE) -C ne clean
   20.15  	$(MAKE) -C tulip clean
   20.16 +	$(MAKE) -C e1000 clean
   20.17  	rm -f *.o *~ core
   20.18 +
   20.19 +.PHONY: default clean
    21.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.2 +++ b/xen-2.4.16/drivers/net/e1000/LICENSE	Tue Feb 11 16:51:47 2003 +0000
    21.3 @@ -0,0 +1,339 @@
    21.4 +
    21.5 +"This software program is licensed subject to the GNU General Public License 
    21.6 +(GPL). Version 2, June 1991, available at 
    21.7 +<http://www.fsf.org/copyleft/gpl.html>"
    21.8 +
    21.9 +GNU General Public License 
   21.10 +
   21.11 +Version 2, June 1991
   21.12 +
   21.13 +Copyright (C) 1989, 1991 Free Software Foundation, Inc.  
   21.14 +59 Temple Place - Suite 330, Boston, MA  02111-1307, USA
   21.15 +
   21.16 +Everyone is permitted to copy and distribute verbatim copies of this license
   21.17 +document, but changing it is not allowed.
   21.18 +
   21.19 +Preamble
   21.20 +
   21.21 +The licenses for most software are designed to take away your freedom to 
   21.22 +share and change it. By contrast, the GNU General Public License is intended
   21.23 +to guarantee your freedom to share and change free software--to make sure 
   21.24 +the software is free for all its users. This General Public License applies 
   21.25 +to most of the Free Software Foundation's software and to any other program 
   21.26 +whose authors commit to using it. (Some other Free Software Foundation 
   21.27 +software is covered by the GNU Library General Public License instead.) You 
   21.28 +can apply it to your programs, too.
   21.29 +
   21.30 +When we speak of free software, we are referring to freedom, not price. Our
   21.31 +General Public Licenses are designed to make sure that you have the freedom 
   21.32 +to distribute copies of free software (and charge for this service if you 
   21.33 +wish), that you receive source code or can get it if you want it, that you 
   21.34 +can change the software or use pieces of it in new free programs; and that 
   21.35 +you know you can do these things.
   21.36 +
   21.37 +To protect your rights, we need to make restrictions that forbid anyone to 
   21.38 +deny you these rights or to ask you to surrender the rights. These 
   21.39 +restrictions translate to certain responsibilities for you if you distribute
   21.40 +copies of the software, or if you modify it.
   21.41 +
   21.42 +For example, if you distribute copies of such a program, whether gratis or 
   21.43 +for a fee, you must give the recipients all the rights that you have. You 
   21.44 +must make sure that they, too, receive or can get the source code. And you 
   21.45 +must show them these terms so they know their rights.
   21.46 + 
   21.47 +We protect your rights with two steps: (1) copyright the software, and (2) 
   21.48 +offer you this license which gives you legal permission to copy, distribute 
   21.49 +and/or modify the software. 
   21.50 +
   21.51 +Also, for each author's protection and ours, we want to make certain that 
   21.52 +everyone understands that there is no warranty for this free software. If 
   21.53 +the software is modified by someone else and passed on, we want its 
   21.54 +recipients to know that what they have is not the original, so that any 
   21.55 +problems introduced by others will not reflect on the original authors' 
   21.56 +reputations. 
   21.57 +
   21.58 +Finally, any free program is threatened constantly by software patents. We 
   21.59 +wish to avoid the danger that redistributors of a free program will 
   21.60 +individually obtain patent licenses, in effect making the program 
   21.61 +proprietary. To prevent this, we have made it clear that any patent must be 
   21.62 +licensed for everyone's free use or not licensed at all. 
   21.63 +
   21.64 +The precise terms and conditions for copying, distribution and modification 
   21.65 +follow. 
   21.66 +
   21.67 +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
   21.68 +
   21.69 +0. This License applies to any program or other work which contains a notice
   21.70 +   placed by the copyright holder saying it may be distributed under the 
   21.71 +   terms of this General Public License. The "Program", below, refers to any
   21.72 +   such program or work, and a "work based on the Program" means either the 
   21.73 +   Program or any derivative work under copyright law: that is to say, a 
   21.74 +   work containing the Program or a portion of it, either verbatim or with 
   21.75 +   modifications and/or translated into another language. (Hereinafter, 
   21.76 +   translation is included without limitation in the term "modification".) 
   21.77 +   Each licensee is addressed as "you". 
   21.78 +
   21.79 +   Activities other than copying, distribution and modification are not 
   21.80 +   covered by this License; they are outside its scope. The act of running 
   21.81 +   the Program is not restricted, and the output from the Program is covered 
   21.82 +   only if its contents constitute a work based on the Program (independent 
   21.83 +   of having been made by running the Program). Whether that is true depends
   21.84 +   on what the Program does. 
   21.85 +
   21.86 +1. You may copy and distribute verbatim copies of the Program's source code 
   21.87 +   as you receive it, in any medium, provided that you conspicuously and 
   21.88 +   appropriately publish on each copy an appropriate copyright notice and 
   21.89 +   disclaimer of warranty; keep intact all the notices that refer to this 
   21.90 +   License and to the absence of any warranty; and give any other recipients 
   21.91 +   of the Program a copy of this License along with the Program. 
   21.92 +
   21.93 +   You may charge a fee for the physical act of transferring a copy, and you 
   21.94 +   may at your option offer warranty protection in exchange for a fee. 
   21.95 +
   21.96 +2. You may modify your copy or copies of the Program or any portion of it, 
   21.97 +   thus forming a work based on the Program, and copy and distribute such 
   21.98 +   modifications or work under the terms of Section 1 above, provided that 
   21.99 +   you also meet all of these conditions: 
  21.100 +
  21.101 +   * a) You must cause the modified files to carry prominent notices stating 
  21.102 +        that you changed the files and the date of any change. 
  21.103 +
  21.104 +   * b) You must cause any work that you distribute or publish, that in 
  21.105 +        whole or in part contains or is derived from the Program or any part 
  21.106 +        thereof, to be licensed as a whole at no charge to all third parties
  21.107 +        under the terms of this License. 
  21.108 +
  21.109 +   * c) If the modified program normally reads commands interactively when 
  21.110 +        run, you must cause it, when started running for such interactive 
  21.111 +        use in the most ordinary way, to print or display an announcement 
  21.112 +        including an appropriate copyright notice and a notice that there is
  21.113 +        no warranty (or else, saying that you provide a warranty) and that 
  21.114 +        users may redistribute the program under these conditions, and 
  21.115 +        telling the user how to view a copy of this License. (Exception: if 
  21.116 +        the Program itself is interactive but does not normally print such 
  21.117 +        an announcement, your work based on the Program is not required to 
  21.118 +        print an announcement.) 
  21.119 +
  21.120 +   These requirements apply to the modified work as a whole. If identifiable 
  21.121 +   sections of that work are not derived from the Program, and can be 
  21.122 +   reasonably considered independent and separate works in themselves, then 
  21.123 +   this License, and its terms, do not apply to those sections when you 
  21.124 +   distribute them as separate works. But when you distribute the same 
  21.125 +   sections as part of a whole which is a work based on the Program, the 
  21.126 +   distribution of the whole must be on the terms of this License, whose 
  21.127 +   permissions for other licensees extend to the entire whole, and thus to 
  21.128 +   each and every part regardless of who wrote it. 
  21.129 +
  21.130 +   Thus, it is not the intent of this section to claim rights or contest 
  21.131 +   your rights to work written entirely by you; rather, the intent is to 
  21.132 +   exercise the right to control the distribution of derivative or 
  21.133 +   collective works based on the Program. 
  21.134 +
  21.135 +   In addition, mere aggregation of another work not based on the Program 
  21.136 +   with the Program (or with a work based on the Program) on a volume of a 
  21.137 +   storage or distribution medium does not bring the other work under the 
  21.138 +   scope of this License. 
  21.139 +
  21.140 +3. You may copy and distribute the Program (or a work based on it, under 
  21.141 +   Section 2) in object code or executable form under the terms of Sections 
  21.142 +   1 and 2 above provided that you also do one of the following: 
  21.143 +
  21.144 +   * a) Accompany it with the complete corresponding machine-readable source 
  21.145 +        code, which must be distributed under the terms of Sections 1 and 2 
  21.146 +        above on a medium customarily used for software interchange; or, 
  21.147 +
  21.148 +   * b) Accompany it with a written offer, valid for at least three years, 
  21.149 +        to give any third party, for a charge no more than your cost of 
  21.150 +        physically performing source distribution, a complete machine-
  21.151 +        readable copy of the corresponding source code, to be distributed 
  21.152 +        under the terms of Sections 1 and 2 above on a medium customarily 
  21.153 +        used for software interchange; or, 
  21.154 +
  21.155 +   * c) Accompany it with the information you received as to the offer to 
  21.156 +        distribute corresponding source code. (This alternative is allowed 
  21.157 +        only for noncommercial distribution and only if you received the 
  21.158 +        program in object code or executable form with such an offer, in 
  21.159 +        accord with Subsection b above.) 
  21.160 +
  21.161 +   The source code for a work means the preferred form of the work for 
  21.162 +   making modifications to it. For an executable work, complete source code 
  21.163 +   means all the source code for all modules it contains, plus any 
  21.164 +   associated interface definition files, plus the scripts used to control 
  21.165 +   compilation and installation of the executable. However, as a special 
  21.166 +   exception, the source code distributed need not include anything that is 
  21.167 +   normally distributed (in either source or binary form) with the major 
  21.168 +   components (compiler, kernel, and so on) of the operating system on which
  21.169 +   the executable runs, unless that component itself accompanies the 
  21.170 +   executable. 
  21.171 +
  21.172 +   If distribution of executable or object code is made by offering access 
  21.173 +   to copy from a designated place, then offering equivalent access to copy 
  21.174 +   the source code from the same place counts as distribution of the source 
  21.175 +   code, even though third parties are not compelled to copy the source 
  21.176 +   along with the object code. 
  21.177 +
  21.178 +4. You may not copy, modify, sublicense, or distribute the Program except as
  21.179 +   expressly provided under this License. Any attempt otherwise to copy, 
  21.180 +   modify, sublicense or distribute the Program is void, and will 
  21.181 +   automatically terminate your rights under this License. However, parties 
  21.182 +   who have received copies, or rights, from you under this License will not
  21.183 +   have their licenses terminated so long as such parties remain in full 
  21.184 +   compliance. 
  21.185 +
  21.186 +5. You are not required to accept this License, since you have not signed 
  21.187 +   it. However, nothing else grants you permission to modify or distribute 
  21.188 +   the Program or its derivative works. These actions are prohibited by law 
  21.189 +   if you do not accept this License. Therefore, by modifying or 
  21.190 +   distributing the Program (or any work based on the Program), you 
  21.191 +   indicate your acceptance of this License to do so, and all its terms and
  21.192 +   conditions for copying, distributing or modifying the Program or works 
  21.193 +   based on it. 
  21.194 +
  21.195 +6. Each time you redistribute the Program (or any work based on the 
  21.196 +   Program), the recipient automatically receives a license from the 
  21.197 +   original licensor to copy, distribute or modify the Program subject to 
  21.198 +   these terms and conditions. You may not impose any further restrictions 
  21.199 +   on the recipients' exercise of the rights granted herein. You are not 
  21.200 +   responsible for enforcing compliance by third parties to this License. 
  21.201 +
  21.202 +7. If, as a consequence of a court judgment or allegation of patent 
  21.203 +   infringement or for any other reason (not limited to patent issues), 
  21.204 +   conditions are imposed on you (whether by court order, agreement or 
  21.205 +   otherwise) that contradict the conditions of this License, they do not 
  21.206 +   excuse you from the conditions of this License. If you cannot distribute 
  21.207 +   so as to satisfy simultaneously your obligations under this License and 
  21.208 +   any other pertinent obligations, then as a consequence you may not 
  21.209 +   distribute the Program at all. For example, if a patent license would 
  21.210 +   not permit royalty-free redistribution of the Program by all those who 
  21.211 +   receive copies directly or indirectly through you, then the only way you 
  21.212 +   could satisfy both it and this License would be to refrain entirely from 
  21.213 +   distribution of the Program. 
  21.214 +
  21.215 +   If any portion of this section is held invalid or unenforceable under any
  21.216 +   particular circumstance, the balance of the section is intended to apply
  21.217 +   and the section as a whole is intended to apply in other circumstances. 
  21.218 +
  21.219 +   It is not the purpose of this section to induce you to infringe any 
  21.220 +   patents or other property right claims or to contest validity of any 
  21.221 +   such claims; this section has the sole purpose of protecting the 
  21.222 +   integrity of the free software distribution system, which is implemented 
  21.223 +   by public license practices. Many people have made generous contributions
  21.224 +   to the wide range of software distributed through that system in 
  21.225 +   reliance on consistent application of that system; it is up to the 
  21.226 +   author/donor to decide if he or she is willing to distribute software 
  21.227 +   through any other system and a licensee cannot impose that choice. 
  21.228 +
  21.229 +   This section is intended to make thoroughly clear what is believed to be 
  21.230 +   a consequence of the rest of this License. 
  21.231 +
  21.232 +8. If the distribution and/or use of the Program is restricted in certain 
  21.233 +   countries either by patents or by copyrighted interfaces, the original 
  21.234 +   copyright holder who places the Program under this License may add an 
  21.235 +   explicit geographical distribution limitation excluding those countries, 
  21.236 +   so that distribution is permitted only in or among countries not thus 
  21.237 +   excluded. In such case, this License incorporates the limitation as if 
  21.238 +   written in the body of this License. 
  21.239 +
  21.240 +9. The Free Software Foundation may publish revised and/or new versions of 
  21.241 +   the General Public License from time to time. Such new versions will be 
  21.242 +   similar in spirit to the present version, but may differ in detail to 
  21.243 +   address new problems or concerns. 
  21.244 +
  21.245 +   Each version is given a distinguishing version number. If the Program 
  21.246 +   specifies a version number of this License which applies to it and "any 
  21.247 +   later version", you have the option of following the terms and 
  21.248 +   conditions either of that version or of any later version published by 
  21.249 +   the Free Software Foundation. If the Program does not specify a version 
  21.250 +   number of this License, you may choose any version ever published by the 
  21.251 +   Free Software Foundation. 
  21.252 +
  21.253 +10. If you wish to incorporate parts of the Program into other free programs
  21.254 +    whose distribution conditions are different, write to the author to ask 
  21.255 +    for permission. For software which is copyrighted by the Free Software 
  21.256 +    Foundation, write to the Free Software Foundation; we sometimes make 
  21.257 +    exceptions for this. Our decision will be guided by the two goals of 
  21.258 +    preserving the free status of all derivatives of our free software and 
  21.259 +    of promoting the sharing and reuse of software generally. 
  21.260 +
  21.261 +   NO WARRANTY
  21.262 +
  21.263 +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY 
  21.264 +    FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN 
  21.265 +    OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES 
  21.266 +    PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER 
  21.267 +    EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
  21.268 +    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE 
  21.269 +    ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH 
  21.270 +    YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL 
  21.271 +    NECESSARY SERVICING, REPAIR OR CORRECTION. 
  21.272 +
  21.273 +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 
  21.274 +    WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR 
  21.275 +    REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR 
  21.276 +    DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL 
  21.277 +    DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM 
  21.278 +    (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED 
  21.279 +    INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF 
  21.280 +    THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR 
  21.281 +    OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
  21.282 +
  21.283 +END OF TERMS AND CONDITIONS
  21.284 +
  21.285 +How to Apply These Terms to Your New Programs
  21.286 +
  21.287 +If you develop a new program, and you want it to be of the greatest 
  21.288 +possible use to the public, the best way to achieve this is to make it free 
  21.289 +software which everyone can redistribute and change under these terms. 
  21.290 +
  21.291 +To do so, attach the following notices to the program. It is safest to 
  21.292 +attach them to the start of each source file to most effectively convey the
  21.293 +exclusion of warranty; and each file should have at least the "copyright" 
  21.294 +line and a pointer to where the full notice is found. 
  21.295 +
  21.296 +one line to give the program's name and an idea of what it does.
  21.297 +Copyright (C) yyyy  name of author
  21.298 +
  21.299 +This program is free software; you can redistribute it and/or modify it 
  21.300 +under the terms of the GNU General Public License as published by the Free 
  21.301 +Software Foundation; either version 2 of the License, or (at your option) 
  21.302 +any later version.
  21.303 +
  21.304 +This program is distributed in the hope that it will be useful, but WITHOUT 
  21.305 +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
  21.306 +FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
  21.307 +more details.
  21.308 +
  21.309 +You should have received a copy of the GNU General Public License along with
  21.310 +this program; if not, write to the Free Software Foundation, Inc., 59 
  21.311 +Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  21.312 +
  21.313 +Also add information on how to contact you by electronic and paper mail. 
  21.314 +
  21.315 +If the program is interactive, make it output a short notice like this when 
  21.316 +it starts in an interactive mode: 
  21.317 +
  21.318 +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes 
  21.319 +with ABSOLUTELY NO WARRANTY; for details type 'show w'.  This is free 
  21.320 +software, and you are welcome to redistribute it under certain conditions; 
  21.321 +type 'show c' for details.
  21.322 +
  21.323 +The hypothetical commands 'show w' and 'show c' should show the appropriate 
  21.324 +parts of the General Public License. Of course, the commands you use may be 
  21.325 +called something other than 'show w' and 'show c'; they could even be 
  21.326 +mouse-clicks or menu items--whatever suits your program. 
  21.327 +
  21.328 +You should also get your employer (if you work as a programmer) or your 
  21.329 +school, if any, to sign a "copyright disclaimer" for the program, if 
  21.330 +necessary. Here is a sample; alter the names: 
  21.331 +
  21.332 +Yoyodyne, Inc., hereby disclaims all copyright interest in the program 
  21.333 +'Gnomovision' (which makes passes at compilers) written by James Hacker.
  21.334 +
  21.335 +signature of Ty Coon, 1 April 1989
  21.336 +Ty Coon, President of Vice
  21.337 +
  21.338 +This General Public License does not permit incorporating your program into 
  21.339 +proprietary programs. If your program is a subroutine library, you may 
  21.340 +consider it more useful to permit linking proprietary applications with the 
  21.341 +library. If this is what you want to do, use the GNU Library General Public 
  21.342 +License instead of this License.
    22.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.2 +++ b/xen-2.4.16/drivers/net/e1000/Makefile	Tue Feb 11 16:51:47 2003 +0000
    22.3 @@ -0,0 +1,39 @@
    22.4 +################################################################################
    22.5 +#
    22.6 +# 
    22.7 +# Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    22.8 +# 
    22.9 +# This program is free software; you can redistribute it and/or modify it 
   22.10 +# under the terms of the GNU General Public License as published by the Free 
   22.11 +# Software Foundation; either version 2 of the License, or (at your option) 
   22.12 +# any later version.
   22.13 +# 
   22.14 +# This program is distributed in the hope that it will be useful, but WITHOUT 
   22.15 +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   22.16 +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   22.17 +# more details.
   22.18 +# 
   22.19 +# You should have received a copy of the GNU General Public License along with
   22.20 +# this program; if not, write to the Free Software Foundation, Inc., 59 
   22.21 +# Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   22.22 +# 
   22.23 +# The full GNU General Public License is included in this distribution in the
   22.24 +# file called LICENSE.
   22.25 +# 
   22.26 +# Contact Information:
   22.27 +# Linux NICS <linux.nics@intel.com>
   22.28 +# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   22.29 +#
   22.30 +################################################################################
   22.31 +
   22.32 +#
   22.33 +# Makefile for the Intel(R) PRO/1000 ethernet driver
   22.34 +#
   22.35 +
   22.36 +include $(BASEDIR)/Rules.mk
   22.37 +
   22.38 +default: $(OBJS)
   22.39 +	$(LD) -r -o e1000.o $(OBJS)
   22.40 +
   22.41 +clean:
   22.42 +	rm -f *.o *~ core
    23.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000.h	Tue Feb 11 16:51:47 2003 +0000
    23.3 @@ -0,0 +1,209 @@
    23.4 +/*******************************************************************************
    23.5 +
    23.6 +  
    23.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    23.8 +  
    23.9 +  This program is free software; you can redistribute it and/or modify it 
   23.10 +  under the terms of the GNU General Public License as published by the Free 
   23.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   23.12 +  any later version.
   23.13 +  
   23.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   23.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   23.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   23.17 +  more details.
   23.18 +  
   23.19 +  You should have received a copy of the GNU General Public License along with
   23.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   23.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   23.22 +  
   23.23 +  The full GNU General Public License is included in this distribution in the
   23.24 +  file called LICENSE.
   23.25 +  
   23.26 +  Contact Information:
   23.27 +  Linux NICS <linux.nics@intel.com>
   23.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   23.29 +
   23.30 +*******************************************************************************/
   23.31 +
   23.32 +
   23.33 +/* Linux PRO/1000 Ethernet Driver main header file */
   23.34 +
   23.35 +#ifndef _E1000_H_
   23.36 +#define _E1000_H_
   23.37 +
   23.38 +//#include <linux/stddef.h>
   23.39 +#include <linux/config.h>
   23.40 +#include <linux/module.h>
   23.41 +#include <linux/types.h>
   23.42 +#include <asm/byteorder.h>
   23.43 +#include <linux/init.h>
   23.44 +#include <linux/mm.h>
   23.45 +#include <linux/errno.h>
   23.46 +#include <linux/ioport.h>
   23.47 +#include <linux/pci.h>
   23.48 +#include <linux/kernel.h>
   23.49 +#include <linux/netdevice.h>
   23.50 +#include <linux/etherdevice.h>
   23.51 +#include <linux/skbuff.h>
   23.52 +#include <linux/delay.h>
   23.53 +#include <linux/timer.h>
   23.54 +#include <linux/slab.h>
   23.55 +#include <linux/interrupt.h>
   23.56 +//#include <linux/string.h>
   23.57 +//#include <linux/pagemap.h>
   23.58 +#include <asm/bitops.h>
   23.59 +#include <asm/io.h>
   23.60 +#include <asm/irq.h>
   23.61 +//#include <linux/capability.h>
   23.62 +#include <linux/in.h>
   23.63 +//#include <linux/ip.h>
   23.64 +//#include <linux/tcp.h>
   23.65 +//#include <linux/udp.h>
   23.66 +//#include <net/pkt_sched.h>
   23.67 +#include <linux/list.h>
   23.68 +#include <linux/reboot.h>
   23.69 +#include <linux/tqueue.h>
   23.70 +#include <linux/ethtool.h>
   23.71 +#include <linux/if_vlan.h>
   23.72 +
   23.73 +#define BAR_0		0
   23.74 +#define BAR_1		1
   23.75 +#define BAR_5		5
   23.76 +#define PCI_DMA_64BIT	0xffffffffffffffffULL
   23.77 +#define PCI_DMA_32BIT	0x00000000ffffffffULL
   23.78 +
   23.79 +
   23.80 +struct e1000_adapter;
   23.81 +
   23.82 +// XEN XXX
   23.83 +#define DBG 1
   23.84 +
   23.85 +#include "e1000_hw.h"
   23.86 +
   23.87 +#if DBG
   23.88 +#define E1000_DBG(args...) printk(KERN_DEBUG "e1000: " args)
   23.89 +#else
   23.90 +XXX
   23.91 +#define E1000_DBG(args...)
   23.92 +#endif
   23.93 +
   23.94 +#define E1000_ERR(args...) printk(KERN_ERR "e1000: " args)
   23.95 +
   23.96 +#define E1000_MAX_INTR 10
   23.97 +
   23.98 +/* Supported Rx Buffer Sizes */
   23.99 +#define E1000_RXBUFFER_2048  2048
  23.100 +#define E1000_RXBUFFER_4096  4096
  23.101 +#define E1000_RXBUFFER_8192  8192
  23.102 +#define E1000_RXBUFFER_16384 16384
  23.103 +
  23.104 +/* Flow Control High-Watermark: 43464 bytes */
  23.105 +#define E1000_FC_HIGH_THRESH 0xA9C8
  23.106 +
  23.107 +/* Flow Control Low-Watermark: 43456 bytes */
  23.108 +#define E1000_FC_LOW_THRESH 0xA9C0
  23.109 +
  23.110 +/* Flow Control Pause Time: 858 usec */
  23.111 +#define E1000_FC_PAUSE_TIME 0x0680
  23.112 +
  23.113 +/* How many Tx Descriptors do we need to call netif_wake_queue ? */
  23.114 +#define E1000_TX_QUEUE_WAKE	16
  23.115 +/* How many Rx Buffers do we bundle into one write to the hardware ? */
  23.116 +#define E1000_RX_BUFFER_WRITE	16
  23.117 +
  23.118 +#define E1000_JUMBO_PBA      0x00000028
  23.119 +#define E1000_DEFAULT_PBA    0x00000030
  23.120 +
  23.121 +#define AUTO_ALL_MODES       0
  23.122 +#define E1000_EEPROM_APME    4
  23.123 +
  23.124 +/* only works for sizes that are powers of 2 */
  23.125 +#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
  23.126 +
  23.127 +/* wrapper around a pointer to a socket buffer,
  23.128 + * so a DMA handle can be stored along with the buffer */
  23.129 +struct e1000_buffer {
  23.130 +	struct sk_buff *skb;
  23.131 +	uint64_t dma;
  23.132 +	unsigned long length;
  23.133 +	unsigned long time_stamp;
  23.134 +};
  23.135 +
  23.136 +struct e1000_desc_ring {
  23.137 +	/* pointer to the descriptor ring memory */
  23.138 +	void *desc;
  23.139 +	/* physical address of the descriptor ring */
  23.140 +	dma_addr_t dma;
  23.141 +	/* length of descriptor ring in bytes */
  23.142 +	unsigned int size;
  23.143 +	/* number of descriptors in the ring */
  23.144 +	unsigned int count;
  23.145 +	/* next descriptor to associate a buffer with */
  23.146 +	unsigned int next_to_use;
  23.147 +	/* next descriptor to check for DD status bit */
  23.148 +	unsigned int next_to_clean;
  23.149 +	/* array of buffer information structs */
  23.150 +	struct e1000_buffer *buffer_info;
  23.151 +};
  23.152 +
  23.153 +#define E1000_DESC_UNUSED(R) \
  23.154 +((((R)->next_to_clean + (R)->count) - ((R)->next_to_use + 1)) % ((R)->count))
  23.155 +
  23.156 +#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
  23.157 +#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
  23.158 +#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
  23.159 +#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
  23.160 +
  23.161 +/* board specific private data structure */
  23.162 +
  23.163 +struct e1000_adapter {
  23.164 +	struct timer_list watchdog_timer;
  23.165 +	struct timer_list phy_info_timer;
  23.166 +	struct vlan_group *vlgrp;
  23.167 +	char *id_string;
  23.168 +	uint32_t bd_number;
  23.169 +	uint32_t rx_buffer_len;
  23.170 +	uint32_t part_num;
  23.171 +	uint32_t wol;
  23.172 +	uint16_t link_speed;
  23.173 +	uint16_t link_duplex;
  23.174 +	spinlock_t stats_lock;
  23.175 +	atomic_t irq_sem;
  23.176 +	struct tq_struct tx_timeout_task;
  23.177 +
  23.178 +	struct timer_list blink_timer;
  23.179 +	unsigned long led_status;
  23.180 +
  23.181 +	/* TX */
  23.182 +	struct e1000_desc_ring tx_ring;
  23.183 +	uint32_t txd_cmd;
  23.184 +	uint32_t tx_int_delay;
  23.185 +	uint32_t tx_abs_int_delay;
  23.186 +	int max_data_per_txd;
  23.187 +
  23.188 +	/* RX */
  23.189 +	struct e1000_desc_ring rx_ring;
  23.190 +	uint64_t hw_csum_err;
  23.191 +	uint64_t hw_csum_good;
  23.192 +	uint32_t rx_int_delay;
  23.193 +	uint32_t rx_abs_int_delay;
  23.194 +	boolean_t rx_csum;
  23.195 +
  23.196 +	/* OS defined structs */
  23.197 +	struct net_device *netdev;
  23.198 +	struct pci_dev *pdev;
  23.199 +	struct net_device_stats net_stats;
  23.200 +
  23.201 +	/* structs defined in e1000_hw.h */
  23.202 +	struct e1000_hw hw;
  23.203 +	struct e1000_hw_stats stats;
  23.204 +	struct e1000_phy_info phy_info;
  23.205 +	struct e1000_phy_stats phy_stats;
  23.206 +
  23.207 +
  23.208 +
  23.209 +	uint32_t pci_state[16];
  23.210 +	char ifname[IFNAMSIZ];
  23.211 +};
  23.212 +#endif /* _E1000_H_ */
    24.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_ethtool.c	Tue Feb 11 16:51:47 2003 +0000
    24.3 @@ -0,0 +1,611 @@
    24.4 +/*******************************************************************************
    24.5 +
    24.6 +  
    24.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    24.8 +  
    24.9 +  This program is free software; you can redistribute it and/or modify it 
   24.10 +  under the terms of the GNU General Public License as published by the Free 
   24.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   24.12 +  any later version.
   24.13 +  
   24.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   24.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   24.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   24.17 +  more details.
   24.18 +  
   24.19 +  You should have received a copy of the GNU General Public License along with
   24.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   24.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   24.22 +  
   24.23 +  The full GNU General Public License is included in this distribution in the
   24.24 +  file called LICENSE.
   24.25 +  
   24.26 +  Contact Information:
   24.27 +  Linux NICS <linux.nics@intel.com>
   24.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   24.29 +
   24.30 +*******************************************************************************/
   24.31 +
   24.32 +/* ethtool support for e1000 */
   24.33 +
   24.34 +#include "e1000.h"
   24.35 +
   24.36 +#include <asm/uaccess.h>
   24.37 +
   24.38 +extern char e1000_driver_name[];
   24.39 +extern char e1000_driver_version[];
   24.40 +
   24.41 +extern int e1000_up(struct e1000_adapter *adapter);
   24.42 +extern void e1000_down(struct e1000_adapter *adapter);
   24.43 +extern void e1000_reset(struct e1000_adapter *adapter);
   24.44 +
   24.45 +static char e1000_gstrings_stats[][ETH_GSTRING_LEN] = {
   24.46 +	"rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
   24.47 +	"tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
   24.48 +	"rx_length_errors", "rx_over_errors", "rx_crc_errors",
   24.49 +	"rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
   24.50 +	"tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
   24.51 +	"tx_heartbeat_errors", "tx_window_errors",
   24.52 +};
   24.53 +#define E1000_STATS_LEN	sizeof(e1000_gstrings_stats) / ETH_GSTRING_LEN
   24.54 +
   24.55 +static void
   24.56 +e1000_ethtool_gset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
   24.57 +{
   24.58 +	struct e1000_hw *hw = &adapter->hw;
   24.59 +
   24.60 +	if(hw->media_type == e1000_media_type_copper) {
   24.61 +
   24.62 +		ecmd->supported = (SUPPORTED_10baseT_Half |
   24.63 +		                   SUPPORTED_10baseT_Full |
   24.64 +		                   SUPPORTED_100baseT_Half |
   24.65 +		                   SUPPORTED_100baseT_Full |
   24.66 +		                   SUPPORTED_1000baseT_Full|
   24.67 +		                   SUPPORTED_Autoneg |
   24.68 +		                   SUPPORTED_TP);
   24.69 +
   24.70 +		ecmd->advertising = ADVERTISED_TP;
   24.71 +
   24.72 +		if(hw->autoneg == 1) {
   24.73 +			ecmd->advertising |= ADVERTISED_Autoneg;
   24.74 +
   24.75 +			/* the e1000 autoneg seems to match ethtool nicely */
   24.76 +
   24.77 +			ecmd->advertising |= hw->autoneg_advertised;
   24.78 +		}
   24.79 +
   24.80 +		ecmd->port = PORT_TP;
   24.81 +		ecmd->phy_address = hw->phy_addr;
   24.82 +
   24.83 +		if(hw->mac_type == e1000_82543)
   24.84 +			ecmd->transceiver = XCVR_EXTERNAL;
   24.85 +		else
   24.86 +			ecmd->transceiver = XCVR_INTERNAL;
   24.87 +
   24.88 +	} else {
   24.89 +		ecmd->supported   = (SUPPORTED_1000baseT_Full |
   24.90 +				     SUPPORTED_FIBRE |
   24.91 +				     SUPPORTED_Autoneg);
   24.92 +
   24.93 +		ecmd->advertising = (SUPPORTED_1000baseT_Full |
   24.94 +				     SUPPORTED_FIBRE |
   24.95 +				     SUPPORTED_Autoneg);
   24.96 +
   24.97 +		ecmd->port = PORT_FIBRE;
   24.98 +
   24.99 +		if(hw->mac_type >= e1000_82545)
  24.100 +			ecmd->transceiver = XCVR_INTERNAL;
  24.101 +		else
  24.102 +			ecmd->transceiver = XCVR_EXTERNAL;
  24.103 +	}
  24.104 +
  24.105 +	if(netif_carrier_ok(adapter->netdev)) {
  24.106 +
  24.107 +		e1000_get_speed_and_duplex(hw, &adapter->link_speed,
  24.108 +		                                   &adapter->link_duplex);
  24.109 +		ecmd->speed = adapter->link_speed;
  24.110 +
  24.111 +		/* unfortunatly FULL_DUPLEX != DUPLEX_FULL
  24.112 +		 *          and HALF_DUPLEX != DUPLEX_HALF */
  24.113 +
  24.114 +		if(adapter->link_duplex == FULL_DUPLEX)
  24.115 +			ecmd->duplex = DUPLEX_FULL;
  24.116 +		else
  24.117 +			ecmd->duplex = DUPLEX_HALF;
  24.118 +	} else {
  24.119 +		ecmd->speed = -1;
  24.120 +		ecmd->duplex = -1;
  24.121 +	}
  24.122 +
  24.123 +	ecmd->autoneg = (hw->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
  24.124 +}
  24.125 +
  24.126 +static int
  24.127 +e1000_ethtool_sset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
  24.128 +{
  24.129 +	struct e1000_hw *hw = &adapter->hw;
  24.130 +
  24.131 +	if(ecmd->autoneg == AUTONEG_ENABLE) {
  24.132 +		hw->autoneg = 1;
  24.133 +		hw->autoneg_advertised = 0x002F;
  24.134 +		ecmd->advertising = 0x002F;
  24.135 +	} else {
  24.136 +		hw->autoneg = 0;
  24.137 +		switch(ecmd->speed + ecmd->duplex) {
  24.138 +		case SPEED_10 + DUPLEX_HALF:
  24.139 +			hw->forced_speed_duplex = e1000_10_half;
  24.140 +			break;
  24.141 +		case SPEED_10 + DUPLEX_FULL:
  24.142 +			hw->forced_speed_duplex = e1000_10_full;
  24.143 +			break;
  24.144 +		case SPEED_100 + DUPLEX_HALF:
  24.145 +			hw->forced_speed_duplex = e1000_100_half;
  24.146 +			break;
  24.147 +		case SPEED_100 + DUPLEX_FULL:
  24.148 +			hw->forced_speed_duplex = e1000_100_full;
  24.149 +			break;
  24.150 +		case SPEED_1000 + DUPLEX_FULL:
  24.151 +			hw->autoneg = 1;
  24.152 +			hw->autoneg_advertised = ADVERTISE_1000_FULL;
  24.153 +			break;
  24.154 +		case SPEED_1000 + DUPLEX_HALF: /* not supported */
  24.155 +		default:
  24.156 +			return -EINVAL;
  24.157 +		}
  24.158 +	}
  24.159 +
  24.160 +	/* reset the link */
  24.161 +
  24.162 +	if(netif_running(adapter->netdev)) {
  24.163 +		e1000_down(adapter);
  24.164 +		e1000_up(adapter);
  24.165 +	} else
  24.166 +		e1000_reset(adapter);
  24.167 +
  24.168 +	return 0;
  24.169 +}
  24.170 +
  24.171 +static inline int
  24.172 +e1000_eeprom_size(struct e1000_hw *hw)
  24.173 +{
  24.174 +	if((hw->mac_type > e1000_82544) &&
  24.175 +	   (E1000_READ_REG(hw, EECD) & E1000_EECD_SIZE))
  24.176 +		return 512;
  24.177 +	else
  24.178 +		return 128;
  24.179 +}
  24.180 +
  24.181 +static void
  24.182 +e1000_ethtool_gdrvinfo(struct e1000_adapter *adapter,
  24.183 +                       struct ethtool_drvinfo *drvinfo)
  24.184 +{
  24.185 +	strncpy(drvinfo->driver,  e1000_driver_name, 32);
  24.186 +	strncpy(drvinfo->version, e1000_driver_version, 32);
  24.187 +	strncpy(drvinfo->fw_version, "N/A", 32);
  24.188 +	strncpy(drvinfo->bus_info, adapter->pdev->slot_name, 32);
  24.189 +	drvinfo->n_stats = E1000_STATS_LEN;
  24.190 +#define E1000_REGS_LEN 32
  24.191 +	drvinfo->regdump_len  = E1000_REGS_LEN * sizeof(uint32_t);
  24.192 +	drvinfo->eedump_len  = e1000_eeprom_size(&adapter->hw);
  24.193 +}
  24.194 +
  24.195 +static void
  24.196 +e1000_ethtool_gregs(struct e1000_adapter *adapter,
  24.197 +                    struct ethtool_regs *regs, uint32_t *regs_buff)
  24.198 +{
  24.199 +	struct e1000_hw *hw = &adapter->hw;
  24.200 +
  24.201 +	regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
  24.202 +
  24.203 +	regs_buff[0]  = E1000_READ_REG(hw, CTRL);
  24.204 +	regs_buff[1]  = E1000_READ_REG(hw, STATUS);
  24.205 +
  24.206 +	regs_buff[2]  = E1000_READ_REG(hw, RCTL);
  24.207 +	regs_buff[3]  = E1000_READ_REG(hw, RDLEN);
  24.208 +	regs_buff[4]  = E1000_READ_REG(hw, RDH);
  24.209 +	regs_buff[5]  = E1000_READ_REG(hw, RDT);
  24.210 +	regs_buff[6]  = E1000_READ_REG(hw, RDTR);
  24.211 +
  24.212 +	regs_buff[7]  = E1000_READ_REG(hw, TCTL);
  24.213 +	regs_buff[8]  = E1000_READ_REG(hw, TDLEN);
  24.214 +	regs_buff[9]  = E1000_READ_REG(hw, TDH);
  24.215 +	regs_buff[10] = E1000_READ_REG(hw, TDT);
  24.216 +	regs_buff[11] = E1000_READ_REG(hw, TIDV);
  24.217 +
  24.218 +	return;
  24.219 +}
  24.220 +
  24.221 +static int
  24.222 +e1000_ethtool_geeprom(struct e1000_adapter *adapter,
  24.223 +                      struct ethtool_eeprom *eeprom, uint16_t *eeprom_buff)
  24.224 +{
  24.225 +	struct e1000_hw *hw = &adapter->hw;
  24.226 +	int max_len, first_word, last_word;
  24.227 +	int ret_val = 0;
  24.228 +	int i;
  24.229 +
  24.230 +	if(eeprom->len == 0) {
  24.231 +		ret_val = -EINVAL;
  24.232 +		goto geeprom_error;
  24.233 +	}
  24.234 +
  24.235 +	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
  24.236 +
  24.237 +	max_len = e1000_eeprom_size(hw);
  24.238 +
  24.239 +	if(eeprom->offset > eeprom->offset + eeprom->len) {
  24.240 +		ret_val = -EINVAL;
  24.241 +		goto geeprom_error;
  24.242 +	}
  24.243 +
  24.244 +	if((eeprom->offset + eeprom->len) > max_len)
  24.245 +		eeprom->len = (max_len - eeprom->offset);
  24.246 +
  24.247 +	first_word = eeprom->offset >> 1;
  24.248 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  24.249 +
  24.250 +	for(i = 0; i <= (last_word - first_word); i++)
  24.251 +		e1000_read_eeprom(hw, first_word + i, &eeprom_buff[i]);
  24.252 +
  24.253 +geeprom_error:
  24.254 +	return ret_val;
  24.255 +}
  24.256 +
  24.257 +static int
  24.258 +e1000_ethtool_seeprom(struct e1000_adapter *adapter,
  24.259 +                      struct ethtool_eeprom *eeprom, void *user_data)
  24.260 +{
  24.261 +	struct e1000_hw *hw = &adapter->hw;
  24.262 +	uint16_t *eeprom_buff;
  24.263 +	int max_len, first_word, last_word;
  24.264 +	void *ptr;
  24.265 +	int i;
  24.266 +
  24.267 +	if(eeprom->len == 0)
  24.268 +		return -EOPNOTSUPP;
  24.269 +
  24.270 +	if(eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
  24.271 +		return -EFAULT;
  24.272 +
  24.273 +	max_len = e1000_eeprom_size(hw);
  24.274 +
  24.275 +	if((eeprom->offset + eeprom->len) > max_len)
  24.276 +		eeprom->len = (max_len - eeprom->offset);
  24.277 +
  24.278 +	first_word = eeprom->offset >> 1;
  24.279 +	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  24.280 +	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
  24.281 +	if(eeprom_buff == NULL)
  24.282 +		return -ENOMEM;
  24.283 +
  24.284 +	ptr = (void *)eeprom_buff;
  24.285 +
  24.286 +	if(eeprom->offset & 1) {
  24.287 +		/* need read/modify/write of first changed EEPROM word */
  24.288 +		/* only the second byte of the word is being modified */
  24.289 +		e1000_read_eeprom(hw, first_word, &eeprom_buff[0]);
  24.290 +		ptr++;
  24.291 +	}
  24.292 +	if((eeprom->offset + eeprom->len) & 1) {
  24.293 +		/* need read/modify/write of last changed EEPROM word */
  24.294 +		/* only the first byte of the word is being modified */
  24.295 +		e1000_read_eeprom(hw, last_word,
  24.296 +		                  &eeprom_buff[last_word - first_word]);
  24.297 +	}
  24.298 +	if(copy_from_user(ptr, user_data, eeprom->len)) {
  24.299 +		kfree(eeprom_buff);
  24.300 +		return -EFAULT;
  24.301 +	}
  24.302 +
  24.303 +	for(i = 0; i <= (last_word - first_word); i++)
  24.304 +		e1000_write_eeprom(hw, first_word + i, eeprom_buff[i]);
  24.305 +
  24.306 +	/* Update the checksum over the first part of the EEPROM if needed */
  24.307 +	if(first_word <= EEPROM_CHECKSUM_REG)
  24.308 +		e1000_update_eeprom_checksum(hw);
  24.309 +
  24.310 +	kfree(eeprom_buff);
  24.311 +
  24.312 +	return 0;
  24.313 +}
  24.314 +
  24.315 +static void
  24.316 +e1000_ethtool_gwol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
  24.317 +{
  24.318 +	struct e1000_hw *hw = &adapter->hw;
  24.319 +
  24.320 +	switch(adapter->hw.device_id) {
  24.321 +	case E1000_DEV_ID_82542:
  24.322 +	case E1000_DEV_ID_82543GC_FIBER:
  24.323 +	case E1000_DEV_ID_82543GC_COPPER:
  24.324 +	case E1000_DEV_ID_82544EI_FIBER:
  24.325 +		wol->supported = 0;
  24.326 +		wol->wolopts   = 0;
  24.327 +		return;
  24.328 +
  24.329 +	case E1000_DEV_ID_82546EB_FIBER:
  24.330 +		/* Wake events only supported on port A for dual fiber */
  24.331 +		if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
  24.332 +			wol->supported = 0;
  24.333 +			wol->wolopts   = 0;
  24.334 +			return;
  24.335 +		}
  24.336 +		/* Fall Through */
  24.337 +
  24.338 +	default:
  24.339 +		wol->supported = WAKE_UCAST | WAKE_MCAST
  24.340 +			         | WAKE_BCAST | WAKE_MAGIC;
  24.341 +
  24.342 +		wol->wolopts = 0;
  24.343 +		if(adapter->wol & E1000_WUFC_EX)
  24.344 +			wol->wolopts |= WAKE_UCAST;
  24.345 +		if(adapter->wol & E1000_WUFC_MC)
  24.346 +			wol->wolopts |= WAKE_MCAST;
  24.347 +		if(adapter->wol & E1000_WUFC_BC)
  24.348 +			wol->wolopts |= WAKE_BCAST;
  24.349 +		if(adapter->wol & E1000_WUFC_MAG)
  24.350 +			wol->wolopts |= WAKE_MAGIC;
  24.351 +		return;
  24.352 +	}
  24.353 +}
  24.354 +
  24.355 +static int
  24.356 +e1000_ethtool_swol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
  24.357 +{
  24.358 +	struct e1000_hw *hw = &adapter->hw;
  24.359 +
  24.360 +	switch(adapter->hw.device_id) {
  24.361 +	case E1000_DEV_ID_82542:
  24.362 +	case E1000_DEV_ID_82543GC_FIBER:
  24.363 +	case E1000_DEV_ID_82543GC_COPPER:
  24.364 +	case E1000_DEV_ID_82544EI_FIBER:
  24.365 +		return wol->wolopts ? -EOPNOTSUPP : 0;
  24.366 +
  24.367 +	case E1000_DEV_ID_82546EB_FIBER:
  24.368 +		/* Wake events only supported on port A for dual fiber */
  24.369 +		if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  24.370 +			return wol->wolopts ? -EOPNOTSUPP : 0;
  24.371 +		/* Fall Through */
  24.372 +
  24.373 +	default:
  24.374 +		if(wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY))
  24.375 +			return -EOPNOTSUPP;
  24.376 +
  24.377 +		adapter->wol = 0;
  24.378 +
  24.379 +		if(wol->wolopts & WAKE_UCAST)
  24.380 +			adapter->wol |= E1000_WUFC_EX;
  24.381 +		if(wol->wolopts & WAKE_MCAST)
  24.382 +			adapter->wol |= E1000_WUFC_MC;
  24.383 +		if(wol->wolopts & WAKE_BCAST)
  24.384 +			adapter->wol |= E1000_WUFC_BC;
  24.385 +		if(wol->wolopts & WAKE_MAGIC)
  24.386 +			adapter->wol |= E1000_WUFC_MAG;
  24.387 +	}
  24.388 +
  24.389 +	return 0;
  24.390 +}
  24.391 +
  24.392 +
  24.393 +/* toggle LED 4 times per second = 2 "blinks" per second */
  24.394 +#define E1000_ID_INTERVAL	(HZ/4)
  24.395 +
  24.396 +/* bit defines for adapter->led_status */
  24.397 +#define E1000_LED_ON		0
  24.398 +
  24.399 +static void
  24.400 +e1000_led_blink_callback(unsigned long data)
  24.401 +{
  24.402 +	struct e1000_adapter *adapter = (struct e1000_adapter *) data;
  24.403 +
  24.404 +	if(test_and_change_bit(E1000_LED_ON, &adapter->led_status))
  24.405 +		e1000_led_off(&adapter->hw);
  24.406 +	else
  24.407 +		e1000_led_on(&adapter->hw);
  24.408 +
  24.409 +	mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
  24.410 +}
  24.411 +
  24.412 +static int
  24.413 +e1000_ethtool_led_blink(struct e1000_adapter *adapter, struct ethtool_value *id)
  24.414 +{
  24.415 +	if(!adapter->blink_timer.function) {
  24.416 +		init_timer(&adapter->blink_timer);
  24.417 +		adapter->blink_timer.function = e1000_led_blink_callback;
  24.418 +		adapter->blink_timer.data = (unsigned long) adapter;
  24.419 +	}
  24.420 +
  24.421 +	e1000_setup_led(&adapter->hw);
  24.422 +	mod_timer(&adapter->blink_timer, jiffies);
  24.423 +
  24.424 +	set_current_state(TASK_INTERRUPTIBLE);
  24.425 +	if(id->data)
  24.426 +		schedule_timeout(id->data * HZ);
  24.427 +	else
  24.428 +		schedule_timeout(MAX_SCHEDULE_TIMEOUT);
  24.429 +
  24.430 +	del_timer_sync(&adapter->blink_timer);
  24.431 +	e1000_led_off(&adapter->hw);
  24.432 +	clear_bit(E1000_LED_ON, &adapter->led_status);
  24.433 +	e1000_cleanup_led(&adapter->hw);
  24.434 +
  24.435 +	return 0;
  24.436 +}
  24.437 +
  24.438 +int
  24.439 +e1000_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr)
  24.440 +{
  24.441 +	struct e1000_adapter *adapter = netdev->priv;
  24.442 +	void *addr = ifr->ifr_data;
  24.443 +	uint32_t cmd;
  24.444 +
  24.445 +	if(get_user(cmd, (uint32_t *) addr))
  24.446 +		return -EFAULT;
  24.447 +
  24.448 +	switch(cmd) {
  24.449 +	case ETHTOOL_GSET: {
  24.450 +		struct ethtool_cmd ecmd = {ETHTOOL_GSET};
  24.451 +		e1000_ethtool_gset(adapter, &ecmd);
  24.452 +		if(copy_to_user(addr, &ecmd, sizeof(ecmd)))
  24.453 +			return -EFAULT;
  24.454 +		return 0;
  24.455 +	}
  24.456 +	case ETHTOOL_SSET: {
  24.457 +		struct ethtool_cmd ecmd;
  24.458 +		if(!capable(CAP_NET_ADMIN))
  24.459 +			return -EPERM;
  24.460 +		if(copy_from_user(&ecmd, addr, sizeof(ecmd)))
  24.461 +			return -EFAULT;
  24.462 +		return e1000_ethtool_sset(adapter, &ecmd);
  24.463 +	}
  24.464 +	case ETHTOOL_GDRVINFO: {
  24.465 +		struct ethtool_drvinfo drvinfo = {ETHTOOL_GDRVINFO};
  24.466 +		e1000_ethtool_gdrvinfo(adapter, &drvinfo);
  24.467 +		if(copy_to_user(addr, &drvinfo, sizeof(drvinfo)))
  24.468 +			return -EFAULT;
  24.469 +		return 0;
  24.470 +	}
  24.471 +	case ETHTOOL_GSTRINGS: {
  24.472 +		struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS };
  24.473 +		char *strings = NULL;
  24.474 +
  24.475 +		if(copy_from_user(&gstrings, addr, sizeof(gstrings)))
  24.476 +			return -EFAULT;
  24.477 +		switch(gstrings.string_set) {
  24.478 +		case ETH_SS_STATS:
  24.479 +			gstrings.len = E1000_STATS_LEN;
  24.480 +			strings = *e1000_gstrings_stats;
  24.481 +			break;
  24.482 +		default:
  24.483 +			return -EOPNOTSUPP;
  24.484 +		}
  24.485 +		if(copy_to_user(addr, &gstrings, sizeof(gstrings)))
  24.486 +			return -EFAULT;
  24.487 +		addr += offsetof(struct ethtool_gstrings, data);
  24.488 +		if(copy_to_user(addr, strings,
  24.489 +		   gstrings.len * ETH_GSTRING_LEN))
  24.490 +			return -EFAULT;
  24.491 +		return 0;
  24.492 +	}
  24.493 +	case ETHTOOL_GREGS: {
  24.494 +		struct ethtool_regs regs = {ETHTOOL_GREGS};
  24.495 +		uint32_t regs_buff[E1000_REGS_LEN];
  24.496 +
  24.497 +		if(copy_from_user(&regs, addr, sizeof(regs)))
  24.498 +			return -EFAULT;
  24.499 +		e1000_ethtool_gregs(adapter, &regs, regs_buff);
  24.500 +		if(copy_to_user(addr, &regs, sizeof(regs)))
  24.501 +			return -EFAULT;
  24.502 +
  24.503 +		addr += offsetof(struct ethtool_regs, data);
  24.504 +		if(copy_to_user(addr, regs_buff, regs.len))
  24.505 +			return -EFAULT;
  24.506 +
  24.507 +		return 0;
  24.508 +	}
  24.509 +	case ETHTOOL_NWAY_RST: {
  24.510 +		if(!capable(CAP_NET_ADMIN))
  24.511 +			return -EPERM;
  24.512 +		if(netif_running(netdev)) {
  24.513 +			e1000_down(adapter);
  24.514 +			e1000_up(adapter);
  24.515 +		}
  24.516 +		return 0;
  24.517 +	}
  24.518 +	case ETHTOOL_PHYS_ID: {
  24.519 +		struct ethtool_value id;
  24.520 +		if(copy_from_user(&id, addr, sizeof(id)))
  24.521 +			return -EFAULT;
  24.522 +		return e1000_ethtool_led_blink(adapter, &id);
  24.523 +	}
  24.524 +	case ETHTOOL_GLINK: {
  24.525 +		struct ethtool_value link = {ETHTOOL_GLINK};
  24.526 +		link.data = netif_carrier_ok(netdev);
  24.527 +		if(copy_to_user(addr, &link, sizeof(link)))
  24.528 +			return -EFAULT;
  24.529 +		return 0;
  24.530 +	}
  24.531 +	case ETHTOOL_GWOL: {
  24.532 +		struct ethtool_wolinfo wol = {ETHTOOL_GWOL};
  24.533 +		e1000_ethtool_gwol(adapter, &wol);
  24.534 +		if(copy_to_user(addr, &wol, sizeof(wol)) != 0)
  24.535 +			return -EFAULT;
  24.536 +		return 0;
  24.537 +	}
  24.538 +	case ETHTOOL_SWOL: {
  24.539 +		struct ethtool_wolinfo wol;
  24.540 +		if(!capable(CAP_NET_ADMIN))
  24.541 +			return -EPERM;
  24.542 +		if(copy_from_user(&wol, addr, sizeof(wol)) != 0)
  24.543 +			return -EFAULT;
  24.544 +		return e1000_ethtool_swol(adapter, &wol);
  24.545 +	}
  24.546 +	case ETHTOOL_GEEPROM: {
  24.547 +		struct ethtool_eeprom eeprom = {ETHTOOL_GEEPROM};
  24.548 +		uint16_t *eeprom_buff;
  24.549 +		void *ptr;
  24.550 +		int max_len, err = 0;
  24.551 +
  24.552 +		max_len = e1000_eeprom_size(&adapter->hw);
  24.553 +
  24.554 +		eeprom_buff = kmalloc(max_len, GFP_KERNEL);
  24.555 +
  24.556 +		if(eeprom_buff == NULL)
  24.557 +			return -ENOMEM;
  24.558 +
  24.559 +		if(copy_from_user(&eeprom, addr, sizeof(eeprom))) {
  24.560 +			err = -EFAULT;
  24.561 +			goto err_geeprom_ioctl;
  24.562 +		}
  24.563 +
  24.564 +		if((err = e1000_ethtool_geeprom(adapter, &eeprom,
  24.565 +						eeprom_buff)))
  24.566 +			goto err_geeprom_ioctl;
  24.567 +
  24.568 +		if(copy_to_user(addr, &eeprom, sizeof(eeprom))) {
  24.569 +			err = -EFAULT;
  24.570 +			goto err_geeprom_ioctl;
  24.571 +		}
  24.572 +
  24.573 +		addr += offsetof(struct ethtool_eeprom, data);
  24.574 +		ptr = ((void *)eeprom_buff) + (eeprom.offset & 1);
  24.575 +
  24.576 +		if(copy_to_user(addr, ptr, eeprom.len))
  24.577 +			err = -EFAULT;
  24.578 +
  24.579 +err_geeprom_ioctl:
  24.580 +		kfree(eeprom_buff);
  24.581 +		return err;
  24.582 +	}
  24.583 +	case ETHTOOL_SEEPROM: {
  24.584 +		struct ethtool_eeprom eeprom;
  24.585 +
  24.586 +		if(!capable(CAP_NET_ADMIN))
  24.587 +			return -EPERM;
  24.588 +
  24.589 +		if(copy_from_user(&eeprom, addr, sizeof(eeprom)))
  24.590 +			return -EFAULT;
  24.591 +
  24.592 +		addr += offsetof(struct ethtool_eeprom, data);
  24.593 +		return e1000_ethtool_seeprom(adapter, &eeprom, addr);
  24.594 +	}
  24.595 +	case ETHTOOL_GSTATS: {
  24.596 +		struct {
  24.597 +			struct ethtool_stats cmd;
  24.598 +			uint64_t data[E1000_STATS_LEN];
  24.599 +		} stats = { {ETHTOOL_GSTATS, E1000_STATS_LEN} };
  24.600 +		int i;
  24.601 +
  24.602 +		for(i = 0; i < E1000_STATS_LEN; i++)
  24.603 +			stats.data[i] =
  24.604 +				((unsigned long *)&adapter->net_stats)[i];
  24.605 +		if(copy_to_user(addr, &stats, sizeof(stats)))
  24.606 +			return -EFAULT;
  24.607 +		return 0;
  24.608 +	}
  24.609 +	default:
  24.610 +		return -EOPNOTSUPP;
  24.611 +	}
  24.612 +}
  24.613 +
  24.614 +
    25.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_hw.c	Tue Feb 11 16:51:47 2003 +0000
    25.3 @@ -0,0 +1,3610 @@
    25.4 +/*******************************************************************************
    25.5 +
    25.6 +  
    25.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    25.8 +  
    25.9 +  This program is free software; you can redistribute it and/or modify it 
   25.10 +  under the terms of the GNU General Public License as published by the Free 
   25.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   25.12 +  any later version.
   25.13 +  
   25.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   25.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   25.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   25.17 +  more details.
   25.18 +  
   25.19 +  You should have received a copy of the GNU General Public License along with
   25.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   25.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   25.22 +  
   25.23 +  The full GNU General Public License is included in this distribution in the
   25.24 +  file called LICENSE.
   25.25 +  
   25.26 +  Contact Information:
   25.27 +  Linux NICS <linux.nics@intel.com>
   25.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   25.29 +
   25.30 +*******************************************************************************/
   25.31 +
   25.32 +/* e1000_hw.c
   25.33 + * Shared functions for accessing and configuring the MAC
   25.34 + */
   25.35 +
   25.36 +#include "e1000_hw.h"
   25.37 +
   25.38 +static int32_t e1000_setup_fiber_link(struct e1000_hw *hw);
   25.39 +static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
   25.40 +static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
   25.41 +static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
   25.42 +static int32_t e1000_force_mac_fc(struct e1000_hw *hw);
   25.43 +static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
   25.44 +static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
   25.45 +static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count);
   25.46 +static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
   25.47 +static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
   25.48 +static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
   25.49 +static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
   25.50 +static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count);
   25.51 +static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw);
   25.52 +static void e1000_setup_eeprom(struct e1000_hw *hw);
   25.53 +static void e1000_clock_eeprom(struct e1000_hw *hw);
   25.54 +static void e1000_cleanup_eeprom(struct e1000_hw *hw);
   25.55 +static void e1000_standby_eeprom(struct e1000_hw *hw);
   25.56 +static int32_t e1000_id_led_init(struct e1000_hw * hw);
   25.57 +
   25.58 +/******************************************************************************
   25.59 + * Set the mac type member in the hw struct.
   25.60 + * 
   25.61 + * hw - Struct containing variables accessed by shared code
   25.62 + *****************************************************************************/
   25.63 +int32_t
   25.64 +e1000_set_mac_type(struct e1000_hw *hw)
   25.65 +{
   25.66 +    DEBUGFUNC("e1000_set_mac_type");
   25.67 +
   25.68 +    switch (hw->device_id) {
   25.69 +    case E1000_DEV_ID_82542:
   25.70 +        switch (hw->revision_id) {
   25.71 +        case E1000_82542_2_0_REV_ID:
   25.72 +            hw->mac_type = e1000_82542_rev2_0;
   25.73 +            break;
   25.74 +        case E1000_82542_2_1_REV_ID:
   25.75 +            hw->mac_type = e1000_82542_rev2_1;
   25.76 +            break;
   25.77 +        default:
   25.78 +            /* Invalid 82542 revision ID */
   25.79 +            return -E1000_ERR_MAC_TYPE;
   25.80 +        }
   25.81 +        break;
   25.82 +    case E1000_DEV_ID_82543GC_FIBER:
   25.83 +    case E1000_DEV_ID_82543GC_COPPER:
   25.84 +        hw->mac_type = e1000_82543;
   25.85 +        break;
   25.86 +    case E1000_DEV_ID_82544EI_COPPER:
   25.87 +    case E1000_DEV_ID_82544EI_FIBER:
   25.88 +    case E1000_DEV_ID_82544GC_COPPER:
   25.89 +    case E1000_DEV_ID_82544GC_LOM:
   25.90 +        hw->mac_type = e1000_82544;
   25.91 +        break;
   25.92 +    case E1000_DEV_ID_82540EM:
   25.93 +    case E1000_DEV_ID_82540EM_LOM:
   25.94 +    case E1000_DEV_ID_82540EP:
   25.95 +    case E1000_DEV_ID_82540EP_LOM:
   25.96 +    case E1000_DEV_ID_82540EP_LP:
   25.97 +        hw->mac_type = e1000_82540;
   25.98 +        break;
   25.99 +    case E1000_DEV_ID_82545EM_COPPER:
  25.100 +    case E1000_DEV_ID_82545EM_FIBER:
  25.101 +        hw->mac_type = e1000_82545;
  25.102 +        break;
  25.103 +    case E1000_DEV_ID_82546EB_COPPER:
  25.104 +    case E1000_DEV_ID_82546EB_FIBER:
  25.105 +        hw->mac_type = e1000_82546;
  25.106 +        break;
  25.107 +    default:
  25.108 +        /* Should never have loaded on this device */
  25.109 +        return -E1000_ERR_MAC_TYPE;
  25.110 +    }
  25.111 +    return E1000_SUCCESS;
  25.112 +}
  25.113 +/******************************************************************************
  25.114 + * Reset the transmit and receive units; mask and clear all interrupts.
  25.115 + *
  25.116 + * hw - Struct containing variables accessed by shared code
  25.117 + *****************************************************************************/
  25.118 +void
  25.119 +e1000_reset_hw(struct e1000_hw *hw)
  25.120 +{
  25.121 +    uint32_t ctrl;
  25.122 +    uint32_t ctrl_ext;
  25.123 +    uint32_t icr;
  25.124 +    uint32_t manc;
  25.125 +
  25.126 +    DEBUGFUNC("e1000_reset_hw");
  25.127 +    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  25.128 +    if(hw->mac_type == e1000_82542_rev2_0) {
  25.129 +        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  25.130 +        e1000_pci_clear_mwi(hw);
  25.131 +    }
  25.132 +
  25.133 +    /* Clear interrupt mask to stop board from generating interrupts */
  25.134 +    DEBUGOUT("Masking off all interrupts\n");
  25.135 +    E1000_WRITE_REG(hw, IMC, 0xffffffff);
  25.136 +
  25.137 +    /* Disable the Transmit and Receive units.  Then delay to allow
  25.138 +     * any pending transactions to complete before we hit the MAC with
  25.139 +     * the global reset.
  25.140 +     */
  25.141 +    E1000_WRITE_REG(hw, RCTL, 0);
  25.142 +    E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  25.143 +    E1000_WRITE_FLUSH(hw);
  25.144 +
  25.145 +    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  25.146 +    hw->tbi_compatibility_on = FALSE;
  25.147 +
  25.148 +    /* Delay to allow any outstanding PCI transactions to complete before
  25.149 +     * resetting the device
  25.150 +     */ 
  25.151 +    DEBUGOUT("Before delay\n");
  25.152 +    msec_delay(10);
  25.153 +
  25.154 +    /* Issue a global reset to the MAC.  This will reset the chip's
  25.155 +     * transmit, receive, DMA, and link units.  It will not effect
  25.156 +     * the current PCI configuration.  The global reset bit is self-
  25.157 +     * clearing, and should clear within a microsecond.
  25.158 +     */
  25.159 +    DEBUGOUT("Issuing a global reset to MAC\n");
  25.160 +    ctrl = E1000_READ_REG(hw, CTRL);
  25.161 +
  25.162 +    if(hw->mac_type > e1000_82543)
  25.163 +        E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
  25.164 +    else
  25.165 +        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  25.166 +
  25.167 +    /* Force a reload from the EEPROM if necessary */
  25.168 +    if(hw->mac_type < e1000_82540) {
  25.169 +        /* Wait for reset to complete */
  25.170 +        udelay(10);
  25.171 +        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  25.172 +        ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  25.173 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  25.174 +        E1000_WRITE_FLUSH(hw);
  25.175 +        /* Wait for EEPROM reload */
  25.176 +        msec_delay(2);
  25.177 +    } else {
  25.178 +        /* Wait for EEPROM reload (it happens automatically) */
  25.179 +        msec_delay(4);
  25.180 +        /* Dissable HW ARPs on ASF enabled adapters */
  25.181 +        manc = E1000_READ_REG(hw, MANC);
  25.182 +        manc &= ~(E1000_MANC_ARP_EN);
  25.183 +        E1000_WRITE_REG(hw, MANC, manc);
  25.184 +    }
  25.185 +    
  25.186 +    /* Clear interrupt mask to stop board from generating interrupts */
  25.187 +    DEBUGOUT("Masking off all interrupts\n");
  25.188 +    E1000_WRITE_REG(hw, IMC, 0xffffffff);
  25.189 +
  25.190 +    /* Clear any pending interrupt events. */
  25.191 +    icr = E1000_READ_REG(hw, ICR);
  25.192 +
  25.193 +    /* If MWI was previously enabled, reenable it. */
  25.194 +    if(hw->mac_type == e1000_82542_rev2_0) {
  25.195 +        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
  25.196 +            e1000_pci_set_mwi(hw);
  25.197 +    }
  25.198 +}
  25.199 +
  25.200 +/******************************************************************************
  25.201 + * Performs basic configuration of the adapter.
  25.202 + *
  25.203 + * hw - Struct containing variables accessed by shared code
  25.204 + * 
  25.205 + * Assumes that the controller has previously been reset and is in a 
  25.206 + * post-reset uninitialized state. Initializes the receive address registers,
  25.207 + * multicast table, and VLAN filter table. Calls routines to setup link
  25.208 + * configuration and flow control settings. Clears all on-chip counters. Leaves
  25.209 + * the transmit and receive units disabled and uninitialized.
  25.210 + *****************************************************************************/
  25.211 +int32_t
  25.212 +e1000_init_hw(struct e1000_hw *hw)
  25.213 +{
  25.214 +    uint32_t ctrl, status;
  25.215 +    uint32_t i;
  25.216 +    int32_t ret_val;
  25.217 +    uint16_t pcix_cmd_word;
  25.218 +    uint16_t pcix_stat_hi_word;
  25.219 +    uint16_t cmd_mmrbc;
  25.220 +    uint16_t stat_mmrbc;
  25.221 +
  25.222 +    DEBUGFUNC("e1000_init_hw");
  25.223 +
  25.224 +    /* Initialize Identification LED */
  25.225 +    ret_val = e1000_id_led_init(hw);
  25.226 +    if(ret_val < 0) {
  25.227 +        DEBUGOUT("Error Initializing Identification LED\n");
  25.228 +        return ret_val;
  25.229 +    }
  25.230 +    
  25.231 +    /* Set the Media Type and exit with error if it is not valid. */
  25.232 +    if(hw->mac_type != e1000_82543) {
  25.233 +        /* tbi_compatibility is only valid on 82543 */
  25.234 +        hw->tbi_compatibility_en = FALSE;
  25.235 +    }
  25.236 +
  25.237 +    if(hw->mac_type >= e1000_82543) {
  25.238 +        status = E1000_READ_REG(hw, STATUS);
  25.239 +        if(status & E1000_STATUS_TBIMODE) {
  25.240 +            hw->media_type = e1000_media_type_fiber;
  25.241 +            /* tbi_compatibility not valid on fiber */
  25.242 +            hw->tbi_compatibility_en = FALSE;
  25.243 +        } else {
  25.244 +            hw->media_type = e1000_media_type_copper;
  25.245 +        }
  25.246 +    } else {
  25.247 +        /* This is an 82542 (fiber only) */
  25.248 +        hw->media_type = e1000_media_type_fiber;
  25.249 +    }
  25.250 +
  25.251 +    /* Disabling VLAN filtering. */
  25.252 +    DEBUGOUT("Initializing the IEEE VLAN\n");
  25.253 +    E1000_WRITE_REG(hw, VET, 0);
  25.254 +
  25.255 +    e1000_clear_vfta(hw);
  25.256 +
  25.257 +    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  25.258 +    if(hw->mac_type == e1000_82542_rev2_0) {
  25.259 +        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  25.260 +        e1000_pci_clear_mwi(hw);
  25.261 +        E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  25.262 +        E1000_WRITE_FLUSH(hw);
  25.263 +        msec_delay(5);
  25.264 +    }
  25.265 +
  25.266 +    /* Setup the receive address. This involves initializing all of the Receive
  25.267 +     * Address Registers (RARs 0 - 15).
  25.268 +     */
  25.269 +    e1000_init_rx_addrs(hw);
  25.270 +
  25.271 +    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  25.272 +    if(hw->mac_type == e1000_82542_rev2_0) {
  25.273 +        E1000_WRITE_REG(hw, RCTL, 0);
  25.274 +        E1000_WRITE_FLUSH(hw);
  25.275 +        msec_delay(1);
  25.276 +        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
  25.277 +            e1000_pci_set_mwi(hw);
  25.278 +    }
  25.279 +
  25.280 +    /* Zero out the Multicast HASH table */
  25.281 +    DEBUGOUT("Zeroing the MTA\n");
  25.282 +    for(i = 0; i < E1000_MC_TBL_SIZE; i++)
  25.283 +        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  25.284 +
  25.285 +    /* Set the PCI priority bit correctly in the CTRL register.  This
  25.286 +     * determines if the adapter gives priority to receives, or if it
  25.287 +     * gives equal priority to transmits and receives.
  25.288 +     */
  25.289 +    if(hw->dma_fairness) {
  25.290 +        ctrl = E1000_READ_REG(hw, CTRL);
  25.291 +        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
  25.292 +    }
  25.293 +
  25.294 +    /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  25.295 +    if(hw->bus_type == e1000_bus_type_pcix) {
  25.296 +        e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
  25.297 +        e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
  25.298 +        cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  25.299 +            PCIX_COMMAND_MMRBC_SHIFT;
  25.300 +        stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  25.301 +            PCIX_STATUS_HI_MMRBC_SHIFT;
  25.302 +        if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  25.303 +            stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  25.304 +        if(cmd_mmrbc > stat_mmrbc) {
  25.305 +            pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  25.306 +            pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  25.307 +            e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
  25.308 +        }
  25.309 +    }
  25.310 +
  25.311 +    /* Call a subroutine to configure the link and setup flow control. */
  25.312 +    ret_val = e1000_setup_link(hw);
  25.313 +
  25.314 +    /* Set the transmit descriptor write-back policy */
  25.315 +    if(hw->mac_type > e1000_82544) {
  25.316 +        ctrl = E1000_READ_REG(hw, TXDCTL);
  25.317 +        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
  25.318 +        E1000_WRITE_REG(hw, TXDCTL, ctrl);
  25.319 +    }
  25.320 +
  25.321 +    /* Clear all of the statistics registers (clear on read).  It is
  25.322 +     * important that we do this after we have tried to establish link
  25.323 +     * because the symbol error count will increment wildly if there
  25.324 +     * is no link.
  25.325 +     */
  25.326 +    e1000_clear_hw_cntrs(hw);
  25.327 +
  25.328 +    return ret_val;
  25.329 +}
  25.330 +
  25.331 +/******************************************************************************
  25.332 + * Configures flow control and link settings.
  25.333 + * 
  25.334 + * hw - Struct containing variables accessed by shared code
  25.335 + * 
  25.336 + * Determines which flow control settings to use. Calls the apropriate media-
  25.337 + * specific link configuration function. Configures the flow control settings.
  25.338 + * Assuming the adapter has a valid link partner, a valid link should be
  25.339 + * established. Assumes the hardware has previously been reset and the 
  25.340 + * transmitter and receiver are not enabled.
  25.341 + *****************************************************************************/
  25.342 +int32_t
  25.343 +e1000_setup_link(struct e1000_hw *hw)
  25.344 +{
  25.345 +    uint32_t ctrl_ext;
  25.346 +    int32_t ret_val;
  25.347 +    uint16_t eeprom_data;
  25.348 +
  25.349 +    DEBUGFUNC("e1000_setup_link");
  25.350 +
  25.351 +    /* Read and store word 0x0F of the EEPROM. This word contains bits
  25.352 +     * that determine the hardware's default PAUSE (flow control) mode,
  25.353 +     * a bit that determines whether the HW defaults to enabling or
  25.354 +     * disabling auto-negotiation, and the direction of the
  25.355 +     * SW defined pins. If there is no SW over-ride of the flow
  25.356 +     * control setting, then the variable hw->fc will
  25.357 +     * be initialized based on a value in the EEPROM.
  25.358 +     */
  25.359 +    if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
  25.360 +        DEBUGOUT("EEPROM Read Error\n");
  25.361 +        return -E1000_ERR_EEPROM;
  25.362 +    }
  25.363 +
  25.364 +    if(hw->fc == e1000_fc_default) {
  25.365 +        if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  25.366 +            hw->fc = e1000_fc_none;
  25.367 +        else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
  25.368 +                EEPROM_WORD0F_ASM_DIR)
  25.369 +            hw->fc = e1000_fc_tx_pause;
  25.370 +        else
  25.371 +            hw->fc = e1000_fc_full;
  25.372 +    }
  25.373 +
  25.374 +    /* We want to save off the original Flow Control configuration just
  25.375 +     * in case we get disconnected and then reconnected into a different
  25.376 +     * hub or switch with different Flow Control capabilities.
  25.377 +     */
  25.378 +    if(hw->mac_type == e1000_82542_rev2_0)
  25.379 +        hw->fc &= (~e1000_fc_tx_pause);
  25.380 +
  25.381 +    if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  25.382 +        hw->fc &= (~e1000_fc_rx_pause);
  25.383 +
  25.384 +    hw->original_fc = hw->fc;
  25.385 +
  25.386 +    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
  25.387 +
  25.388 +    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  25.389 +     * polarity value for the SW controlled pins, and setup the
  25.390 +     * Extended Device Control reg with that info.
  25.391 +     * This is needed because one of the SW controlled pins is used for
  25.392 +     * signal detection.  So this should be done before e1000_setup_pcs_link()
  25.393 +     * or e1000_phy_setup() is called.
  25.394 +     */
  25.395 +    if(hw->mac_type == e1000_82543) {
  25.396 +        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
  25.397 +                    SWDPIO__EXT_SHIFT);
  25.398 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  25.399 +    }
  25.400 +
  25.401 +    /* Call the necessary subroutine to configure the link. */
  25.402 +    ret_val = (hw->media_type == e1000_media_type_fiber) ?
  25.403 +              e1000_setup_fiber_link(hw) :
  25.404 +              e1000_setup_copper_link(hw);
  25.405 +
  25.406 +    /* Initialize the flow control address, type, and PAUSE timer
  25.407 +     * registers to their default values.  This is done even if flow
  25.408 +     * control is disabled, because it does not hurt anything to
  25.409 +     * initialize these registers.
  25.410 +     */
  25.411 +    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
  25.412 +
  25.413 +    E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  25.414 +    E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  25.415 +    E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  25.416 +    E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  25.417 +
  25.418 +    /* Set the flow control receive threshold registers.  Normally,
  25.419 +     * these registers will be set to a default threshold that may be
  25.420 +     * adjusted later by the driver's runtime code.  However, if the
  25.421 +     * ability to transmit pause frames in not enabled, then these
  25.422 +     * registers will be set to 0. 
  25.423 +     */
  25.424 +    if(!(hw->fc & e1000_fc_tx_pause)) {
  25.425 +        E1000_WRITE_REG(hw, FCRTL, 0);
  25.426 +        E1000_WRITE_REG(hw, FCRTH, 0);
  25.427 +    } else {
  25.428 +        /* We need to set up the Receive Threshold high and low water marks
  25.429 +         * as well as (optionally) enabling the transmission of XON frames.
  25.430 +         */
  25.431 +        if(hw->fc_send_xon) {
  25.432 +            E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
  25.433 +            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  25.434 +        } else {
  25.435 +            E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  25.436 +            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  25.437 +        }
  25.438 +    }
  25.439 +    return ret_val;
  25.440 +}
  25.441 +
  25.442 +/******************************************************************************
  25.443 + * Sets up link for a fiber based adapter
  25.444 + *
  25.445 + * hw - Struct containing variables accessed by shared code
  25.446 + *
  25.447 + * Manipulates Physical Coding Sublayer functions in order to configure
  25.448 + * link. Assumes the hardware has been previously reset and the transmitter
  25.449 + * and receiver are not enabled.
  25.450 + *****************************************************************************/
  25.451 +static int32_t 
  25.452 +e1000_setup_fiber_link(struct e1000_hw *hw)
  25.453 +{
  25.454 +    uint32_t ctrl;
  25.455 +    uint32_t status;
  25.456 +    uint32_t txcw = 0;
  25.457 +    uint32_t i;
  25.458 +    uint32_t signal;
  25.459 +    int32_t ret_val;
  25.460 +
  25.461 +    DEBUGFUNC("e1000_setup_fiber_link");
  25.462 +
  25.463 +    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
  25.464 +     * set when the optics detect a signal. On older adapters, it will be 
  25.465 +     * cleared when there is a signal
  25.466 +     */
  25.467 +    ctrl = E1000_READ_REG(hw, CTRL);
  25.468 +    if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
  25.469 +    else signal = 0;
  25.470 +   
  25.471 +    /* Take the link out of reset */
  25.472 +    ctrl &= ~(E1000_CTRL_LRST);
  25.473 +    
  25.474 +    e1000_config_collision_dist(hw);
  25.475 +
  25.476 +    /* Check for a software override of the flow control settings, and setup
  25.477 +     * the device accordingly.  If auto-negotiation is enabled, then software
  25.478 +     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  25.479 +     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
  25.480 +     * auto-negotiation is disabled, then software will have to manually 
  25.481 +     * configure the two flow control enable bits in the CTRL register.
  25.482 +     *
  25.483 +     * The possible values of the "fc" parameter are:
  25.484 +     *      0:  Flow control is completely disabled
  25.485 +     *      1:  Rx flow control is enabled (we can receive pause frames, but 
  25.486 +     *          not send pause frames).
  25.487 +     *      2:  Tx flow control is enabled (we can send pause frames but we do
  25.488 +     *          not support receiving pause frames).
  25.489 +     *      3:  Both Rx and TX flow control (symmetric) are enabled.
  25.490 +     */
  25.491 +    switch (hw->fc) {
  25.492 +    case e1000_fc_none:
  25.493 +        /* Flow control is completely disabled by a software over-ride. */
  25.494 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  25.495 +        break;
  25.496 +    case e1000_fc_rx_pause:
  25.497 +        /* RX Flow control is enabled and TX Flow control is disabled by a 
  25.498 +         * software over-ride. Since there really isn't a way to advertise 
  25.499 +         * that we are capable of RX Pause ONLY, we will advertise that we
  25.500 +         * support both symmetric and asymmetric RX PAUSE. Later, we will
  25.501 +         *  disable the adapter's ability to send PAUSE frames.
  25.502 +         */
  25.503 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  25.504 +        break;
  25.505 +    case e1000_fc_tx_pause:
  25.506 +        /* TX Flow control is enabled, and RX Flow control is disabled, by a 
  25.507 +         * software over-ride.
  25.508 +         */
  25.509 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  25.510 +        break;
  25.511 +    case e1000_fc_full:
  25.512 +        /* Flow control (both RX and TX) is enabled by a software over-ride. */
  25.513 +        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  25.514 +        break;
  25.515 +    default:
  25.516 +        DEBUGOUT("Flow control param set incorrectly\n");
  25.517 +        return -E1000_ERR_CONFIG;
  25.518 +        break;
  25.519 +    }
  25.520 +
  25.521 +    /* Since auto-negotiation is enabled, take the link out of reset (the link
  25.522 +     * will be in reset, because we previously reset the chip). This will
  25.523 +     * restart auto-negotiation.  If auto-neogtiation is successful then the
  25.524 +     * link-up status bit will be set and the flow control enable bits (RFCE
  25.525 +     * and TFCE) will be set according to their negotiated value.
  25.526 +     */
  25.527 +    DEBUGOUT("Auto-negotiation enabled\n");
  25.528 +
  25.529 +    E1000_WRITE_REG(hw, TXCW, txcw);
  25.530 +    E1000_WRITE_REG(hw, CTRL, ctrl);
  25.531 +    E1000_WRITE_FLUSH(hw);
  25.532 +
  25.533 +    hw->txcw = txcw;
  25.534 +    msec_delay(1);
  25.535 +
  25.536 +    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  25.537 +     * indication in the Device Status Register.  Time-out if a link isn't 
  25.538 +     * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
  25.539 +     * less than 500 milliseconds even if the other end is doing it in SW).
  25.540 +     */
  25.541 +    if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  25.542 +        DEBUGOUT("Looking for Link\n");
  25.543 +        for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  25.544 +            msec_delay(10);
  25.545 +            status = E1000_READ_REG(hw, STATUS);
  25.546 +            if(status & E1000_STATUS_LU) break;
  25.547 +        }
  25.548 +        if(i == (LINK_UP_TIMEOUT / 10)) {
  25.549 +            /* AutoNeg failed to achieve a link, so we'll call 
  25.550 +             * e1000_check_for_link. This routine will force the link up if we
  25.551 +             * detect a signal. This will allow us to communicate with
  25.552 +             * non-autonegotiating link partners.
  25.553 +             */
  25.554 +            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  25.555 +            hw->autoneg_failed = 1;
  25.556 +            ret_val = e1000_check_for_link(hw);
  25.557 +            if(ret_val < 0) {
  25.558 +                DEBUGOUT("Error while checking for link\n");
  25.559 +                return ret_val;
  25.560 +            }
  25.561 +            hw->autoneg_failed = 0;
  25.562 +        } else {
  25.563 +            hw->autoneg_failed = 0;
  25.564 +            DEBUGOUT("Valid Link Found\n");
  25.565 +        }
  25.566 +    } else {
  25.567 +        DEBUGOUT("No Signal Detected\n");
  25.568 +    }
  25.569 +    return 0;
  25.570 +}
  25.571 +
  25.572 +/******************************************************************************
  25.573 +* Detects which PHY is present and the speed and duplex
  25.574 +*
  25.575 +* hw - Struct containing variables accessed by shared code
  25.576 +******************************************************************************/
  25.577 +static int32_t 
  25.578 +e1000_setup_copper_link(struct e1000_hw *hw)
  25.579 +{
  25.580 +    uint32_t ctrl;
  25.581 +    int32_t ret_val;
  25.582 +    uint16_t i;
  25.583 +    uint16_t phy_data;
  25.584 +
  25.585 +    DEBUGFUNC("e1000_setup_copper_link");
  25.586 +
  25.587 +    ctrl = E1000_READ_REG(hw, CTRL);
  25.588 +    /* With 82543, we need to force speed and duplex on the MAC equal to what
  25.589 +     * the PHY speed and duplex configuration is. In addition, we need to
  25.590 +     * perform a hardware reset on the PHY to take it out of reset.
  25.591 +     */
  25.592 +    if(hw->mac_type > e1000_82543) {
  25.593 +        ctrl |= E1000_CTRL_SLU;
  25.594 +        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  25.595 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  25.596 +    } else {
  25.597 +        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
  25.598 +        E1000_WRITE_REG(hw, CTRL, ctrl);
  25.599 +        e1000_phy_hw_reset(hw);
  25.600 +    }
  25.601 +
  25.602 +    /* Make sure we have a valid PHY */
  25.603 +    ret_val = e1000_detect_gig_phy(hw);
  25.604 +    if(ret_val < 0) {
  25.605 +        DEBUGOUT("Error, did not detect valid phy.\n");
  25.606 +        return ret_val;
  25.607 +    }
  25.608 +    DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
  25.609 +
  25.610 +    /* Enable CRS on TX. This must be set for half-duplex operation. */
  25.611 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
  25.612 +        DEBUGOUT("PHY Read Error\n");
  25.613 +        return -E1000_ERR_PHY;
  25.614 +    }
  25.615 +    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  25.616 +
  25.617 +    /* Options:
  25.618 +     *   MDI/MDI-X = 0 (default)
  25.619 +     *   0 - Auto for all speeds
  25.620 +     *   1 - MDI mode
  25.621 +     *   2 - MDI-X mode
  25.622 +     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  25.623 +     */
  25.624 +    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  25.625 +
  25.626 +    switch (hw->mdix) {
  25.627 +    case 1:
  25.628 +        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  25.629 +        break;
  25.630 +    case 2:
  25.631 +        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  25.632 +        break;
  25.633 +    case 3:
  25.634 +        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  25.635 +        break;
  25.636 +    case 0:
  25.637 +    default:
  25.638 +        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  25.639 +        break;
  25.640 +    }
  25.641 +
  25.642 +    /* Options:
  25.643 +     *   disable_polarity_correction = 0 (default)
  25.644 +     *       Automatic Correction for Reversed Cable Polarity
  25.645 +     *   0 - Disabled
  25.646 +     *   1 - Enabled
  25.647 +     */
  25.648 +    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  25.649 +    if(hw->disable_polarity_correction == 1)
  25.650 +        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
  25.651 +    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
  25.652 +        DEBUGOUT("PHY Write Error\n");
  25.653 +        return -E1000_ERR_PHY;
  25.654 +    }
  25.655 +
  25.656 +    /* Force TX_CLK in the Extended PHY Specific Control Register
  25.657 +     * to 25MHz clock.
  25.658 +     */
  25.659 +    if(e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
  25.660 +        DEBUGOUT("PHY Read Error\n");
  25.661 +        return -E1000_ERR_PHY;
  25.662 +    }
  25.663 +    phy_data |= M88E1000_EPSCR_TX_CLK_25;
  25.664 +
  25.665 +    if (hw->phy_revision < M88E1011_I_REV_4) {
  25.666 +        /* Configure Master and Slave downshift values */
  25.667 +        phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
  25.668 +                      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  25.669 +        phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
  25.670 +                     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  25.671 +        if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
  25.672 +            DEBUGOUT("PHY Write Error\n");
  25.673 +            return -E1000_ERR_PHY;
  25.674 +        }
  25.675 +    }
  25.676 +
  25.677 +    /* SW Reset the PHY so all changes take effect */
  25.678 +    ret_val = e1000_phy_reset(hw);
  25.679 +    if(ret_val < 0) {
  25.680 +        DEBUGOUT("Error Resetting the PHY\n");
  25.681 +        return ret_val;
  25.682 +    }
  25.683 +    
  25.684 +    /* Options:
  25.685 +     *   autoneg = 1 (default)
  25.686 +     *      PHY will advertise value(s) parsed from
  25.687 +     *      autoneg_advertised and fc
  25.688 +     *   autoneg = 0
  25.689 +     *      PHY will be set to 10H, 10F, 100H, or 100F
  25.690 +     *      depending on value parsed from forced_speed_duplex.
  25.691 +     */
  25.692 +
  25.693 +    /* Is autoneg enabled?  This is enabled by default or by software override.
  25.694 +     * If so, call e1000_phy_setup_autoneg routine to parse the
  25.695 +     * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
  25.696 +     * user should have provided a speed/duplex override.  If so, then call
  25.697 +     * e1000_phy_force_speed_duplex to parse and set this up.
  25.698 +     */
  25.699 +    if(hw->autoneg) {
  25.700 +        /* Perform some bounds checking on the hw->autoneg_advertised
  25.701 +         * parameter.  If this variable is zero, then set it to the default.
  25.702 +         */
  25.703 +        hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  25.704 +
  25.705 +        /* If autoneg_advertised is zero, we assume it was not defaulted
  25.706 +         * by the calling code so we set to advertise full capability.
  25.707 +         */
  25.708 +        if(hw->autoneg_advertised == 0)
  25.709 +            hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  25.710 +
  25.711 +        DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  25.712 +        ret_val = e1000_phy_setup_autoneg(hw);
  25.713 +        if(ret_val < 0) {
  25.714 +            DEBUGOUT("Error Setting up Auto-Negotiation\n");
  25.715 +            return ret_val;
  25.716 +        }
  25.717 +        DEBUGOUT("Restarting Auto-Neg\n");
  25.718 +
  25.719 +        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  25.720 +         * the Auto Neg Restart bit in the PHY control register.
  25.721 +         */
  25.722 +        if(e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
  25.723 +            DEBUGOUT("PHY Read Error\n");
  25.724 +            return -E1000_ERR_PHY;
  25.725 +        }
  25.726 +        phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  25.727 +        if(e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
  25.728 +            DEBUGOUT("PHY Write Error\n");
  25.729 +            return -E1000_ERR_PHY;
  25.730 +        }
  25.731 +
  25.732 +        /* Does the user want to wait for Auto-Neg to complete here, or
  25.733 +         * check at a later time (for example, callback routine).
  25.734 +         */
  25.735 +        if(hw->wait_autoneg_complete) {
  25.736 +            ret_val = e1000_wait_autoneg(hw);
  25.737 +            if(ret_val < 0) {
  25.738 +                DEBUGOUT("Error while waiting for autoneg to complete\n");
  25.739 +                return ret_val;
  25.740 +            }
  25.741 +        }
  25.742 +    } else {
  25.743 +        DEBUGOUT("Forcing speed and duplex\n");
  25.744 +        ret_val = e1000_phy_force_speed_duplex(hw);
  25.745 +        if(ret_val < 0) {
  25.746 +            DEBUGOUT("Error Forcing Speed and Duplex\n");
  25.747 +            return ret_val;
  25.748 +        }
  25.749 +    }
  25.750 +
  25.751 +    /* Check link status. Wait up to 100 microseconds for link to become
  25.752 +     * valid.
  25.753 +     */
  25.754 +    for(i = 0; i < 10; i++) {
  25.755 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  25.756 +            DEBUGOUT("PHY Read Error\n");
  25.757 +            return -E1000_ERR_PHY;
  25.758 +        }
  25.759 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  25.760 +            DEBUGOUT("PHY Read Error\n");
  25.761 +            return -E1000_ERR_PHY;
  25.762 +        }
  25.763 +        if(phy_data & MII_SR_LINK_STATUS) {
  25.764 +            /* We have link, so we need to finish the config process:
  25.765 +             *   1) Set up the MAC to the current PHY speed/duplex
  25.766 +             *      if we are on 82543.  If we
  25.767 +             *      are on newer silicon, we only need to configure
  25.768 +             *      collision distance in the Transmit Control Register.
  25.769 +             *   2) Set up flow control on the MAC to that established with
  25.770 +             *      the link partner.
  25.771 +             */
  25.772 +            if(hw->mac_type >= e1000_82544) {
  25.773 +                e1000_config_collision_dist(hw);
  25.774 +            } else {
  25.775 +                ret_val = e1000_config_mac_to_phy(hw);
  25.776 +                if(ret_val < 0) {
  25.777 +                    DEBUGOUT("Error configuring MAC to PHY settings\n");
  25.778 +                    return ret_val;
  25.779 +                  }
  25.780 +            }
  25.781 +            ret_val = e1000_config_fc_after_link_up(hw);
  25.782 +            if(ret_val < 0) {
  25.783 +                DEBUGOUT("Error Configuring Flow Control\n");
  25.784 +                return ret_val;
  25.785 +            }
  25.786 +            DEBUGOUT("Valid link established!!!\n");
  25.787 +            return 0;
  25.788 +        }
  25.789 +        udelay(10);
  25.790 +    }
  25.791 +
  25.792 +    DEBUGOUT("Unable to establish link!!!\n");
  25.793 +    return 0;
  25.794 +}
  25.795 +
  25.796 +/******************************************************************************
  25.797 +* Configures PHY autoneg and flow control advertisement settings
  25.798 +*
  25.799 +* hw - Struct containing variables accessed by shared code
  25.800 +******************************************************************************/
  25.801 +int32_t
  25.802 +e1000_phy_setup_autoneg(struct e1000_hw *hw)
  25.803 +{
  25.804 +    uint16_t mii_autoneg_adv_reg;
  25.805 +    uint16_t mii_1000t_ctrl_reg;
  25.806 +
  25.807 +    DEBUGFUNC("e1000_phy_setup_autoneg");
  25.808 +
  25.809 +    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  25.810 +    if(e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
  25.811 +        DEBUGOUT("PHY Read Error\n");
  25.812 +        return -E1000_ERR_PHY;
  25.813 +    }
  25.814 +
  25.815 +    /* Read the MII 1000Base-T Control Register (Address 9). */
  25.816 +    if(e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
  25.817 +        DEBUGOUT("PHY Read Error\n");
  25.818 +        return -E1000_ERR_PHY;
  25.819 +    }
  25.820 +
  25.821 +    /* Need to parse both autoneg_advertised and fc and set up
  25.822 +     * the appropriate PHY registers.  First we will parse for
  25.823 +     * autoneg_advertised software override.  Since we can advertise
  25.824 +     * a plethora of combinations, we need to check each bit
  25.825 +     * individually.
  25.826 +     */
  25.827 +
  25.828 +    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  25.829 +     * Advertisement Register (Address 4) and the 1000 mb speed bits in
  25.830 +     * the  1000Base-T Control Register (Address 9).
  25.831 +     */
  25.832 +    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  25.833 +    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  25.834 +
  25.835 +    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
  25.836 +
  25.837 +    /* Do we want to advertise 10 Mb Half Duplex? */
  25.838 +    if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
  25.839 +        DEBUGOUT("Advertise 10mb Half duplex\n");
  25.840 +        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  25.841 +    }
  25.842 +
  25.843 +    /* Do we want to advertise 10 Mb Full Duplex? */
  25.844 +    if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
  25.845 +        DEBUGOUT("Advertise 10mb Full duplex\n");
  25.846 +        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  25.847 +    }
  25.848 +
  25.849 +    /* Do we want to advertise 100 Mb Half Duplex? */
  25.850 +    if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
  25.851 +        DEBUGOUT("Advertise 100mb Half duplex\n");
  25.852 +        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  25.853 +    }
  25.854 +
  25.855 +    /* Do we want to advertise 100 Mb Full Duplex? */
  25.856 +    if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
  25.857 +        DEBUGOUT("Advertise 100mb Full duplex\n");
  25.858 +        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  25.859 +    }
  25.860 +
  25.861 +    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  25.862 +    if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  25.863 +        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
  25.864 +    }
  25.865 +
  25.866 +    /* Do we want to advertise 1000 Mb Full Duplex? */
  25.867 +    if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  25.868 +        DEBUGOUT("Advertise 1000mb Full duplex\n");
  25.869 +        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  25.870 +    }
  25.871 +
  25.872 +    /* Check for a software override of the flow control settings, and
  25.873 +     * setup the PHY advertisement registers accordingly.  If
  25.874 +     * auto-negotiation is enabled, then software will have to set the
  25.875 +     * "PAUSE" bits to the correct value in the Auto-Negotiation
  25.876 +     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  25.877 +     *
  25.878 +     * The possible values of the "fc" parameter are:
  25.879 +     *      0:  Flow control is completely disabled
  25.880 +     *      1:  Rx flow control is enabled (we can receive pause frames
  25.881 +     *          but not send pause frames).
  25.882 +     *      2:  Tx flow control is enabled (we can send pause frames
  25.883 +     *          but we do not support receiving pause frames).
  25.884 +     *      3:  Both Rx and TX flow control (symmetric) are enabled.
  25.885 +     *  other:  No software override.  The flow control configuration
  25.886 +     *          in the EEPROM is used.
  25.887 +     */
  25.888 +    switch (hw->fc) {
  25.889 +    case e1000_fc_none: /* 0 */
  25.890 +        /* Flow control (RX & TX) is completely disabled by a
  25.891 +         * software over-ride.
  25.892 +         */
  25.893 +        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  25.894 +        break;
  25.895 +    case e1000_fc_rx_pause: /* 1 */
  25.896 +        /* RX Flow control is enabled, and TX Flow control is
  25.897 +         * disabled, by a software over-ride.
  25.898 +         */
  25.899 +        /* Since there really isn't a way to advertise that we are
  25.900 +         * capable of RX Pause ONLY, we will advertise that we
  25.901 +         * support both symmetric and asymmetric RX PAUSE.  Later
  25.902 +         * (in e1000_config_fc_after_link_up) we will disable the
  25.903 +         *hw's ability to send PAUSE frames.
  25.904 +         */
  25.905 +        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  25.906 +        break;
  25.907 +    case e1000_fc_tx_pause: /* 2 */
  25.908 +        /* TX Flow control is enabled, and RX Flow control is
  25.909 +         * disabled, by a software over-ride.
  25.910 +         */
  25.911 +        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  25.912 +        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  25.913 +        break;
  25.914 +    case e1000_fc_full: /* 3 */
  25.915 +        /* Flow control (both RX and TX) is enabled by a software
  25.916 +         * over-ride.
  25.917 +         */
  25.918 +        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  25.919 +        break;
  25.920 +    default:
  25.921 +        DEBUGOUT("Flow control param set incorrectly\n");
  25.922 +        return -E1000_ERR_CONFIG;
  25.923 +    }
  25.924 +
  25.925 +    if(e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
  25.926 +        DEBUGOUT("PHY Write Error\n");
  25.927 +        return -E1000_ERR_PHY;
  25.928 +    }
  25.929 +
  25.930 +    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  25.931 +
  25.932 +    if(e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
  25.933 +        DEBUGOUT("PHY Write Error\n");
  25.934 +        return -E1000_ERR_PHY;
  25.935 +    }
  25.936 +    return 0;
  25.937 +}
  25.938 +
  25.939 +/******************************************************************************
  25.940 +* Force PHY speed and duplex settings to hw->forced_speed_duplex
  25.941 +*
  25.942 +* hw - Struct containing variables accessed by shared code
  25.943 +******************************************************************************/
  25.944 +static int32_t
  25.945 +e1000_phy_force_speed_duplex(struct e1000_hw *hw)
  25.946 +{
  25.947 +    uint32_t ctrl;
  25.948 +    int32_t ret_val;
  25.949 +    uint16_t mii_ctrl_reg;
  25.950 +    uint16_t mii_status_reg;
  25.951 +    uint16_t phy_data;
  25.952 +    uint16_t i;
  25.953 +
  25.954 +    DEBUGFUNC("e1000_phy_force_speed_duplex");
  25.955 +
  25.956 +    /* Turn off Flow control if we are forcing speed and duplex. */
  25.957 +    hw->fc = e1000_fc_none;
  25.958 +
  25.959 +    DEBUGOUT1("hw->fc = %d\n", hw->fc);
  25.960 +
  25.961 +    /* Read the Device Control Register. */
  25.962 +    ctrl = E1000_READ_REG(hw, CTRL);
  25.963 +
  25.964 +    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
  25.965 +    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  25.966 +    ctrl &= ~(DEVICE_SPEED_MASK);
  25.967 +
  25.968 +    /* Clear the Auto Speed Detect Enable bit. */
  25.969 +    ctrl &= ~E1000_CTRL_ASDE;
  25.970 +
  25.971 +    /* Read the MII Control Register. */
  25.972 +    if(e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
  25.973 +        DEBUGOUT("PHY Read Error\n");
  25.974 +        return -E1000_ERR_PHY;
  25.975 +    }
  25.976 +
  25.977 +    /* We need to disable autoneg in order to force link and duplex. */
  25.978 +
  25.979 +    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
  25.980 +
  25.981 +    /* Are we forcing Full or Half Duplex? */
  25.982 +    if(hw->forced_speed_duplex == e1000_100_full ||
  25.983 +       hw->forced_speed_duplex == e1000_10_full) {
  25.984 +        /* We want to force full duplex so we SET the full duplex bits in the
  25.985 +         * Device and MII Control Registers.
  25.986 +         */
  25.987 +        ctrl |= E1000_CTRL_FD;
  25.988 +        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
  25.989 +        DEBUGOUT("Full Duplex\n");
  25.990 +    } else {
  25.991 +        /* We want to force half duplex so we CLEAR the full duplex bits in
  25.992 +         * the Device and MII Control Registers.
  25.993 +         */
  25.994 +        ctrl &= ~E1000_CTRL_FD;
  25.995 +        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
  25.996 +        DEBUGOUT("Half Duplex\n");
  25.997 +    }
  25.998 +
  25.999 +    /* Are we forcing 100Mbps??? */
 25.1000 +    if(hw->forced_speed_duplex == e1000_100_full ||
 25.1001 +       hw->forced_speed_duplex == e1000_100_half) {
 25.1002 +        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
 25.1003 +        ctrl |= E1000_CTRL_SPD_100;
 25.1004 +        mii_ctrl_reg |= MII_CR_SPEED_100;
 25.1005 +        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
 25.1006 +        DEBUGOUT("Forcing 100mb ");
 25.1007 +    } else {
 25.1008 +        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
 25.1009 +        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
 25.1010 +        mii_ctrl_reg |= MII_CR_SPEED_10;
 25.1011 +        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
 25.1012 +        DEBUGOUT("Forcing 10mb ");
 25.1013 +    }
 25.1014 +
 25.1015 +    e1000_config_collision_dist(hw);
 25.1016 +
 25.1017 +    /* Write the configured values back to the Device Control Reg. */
 25.1018 +    E1000_WRITE_REG(hw, CTRL, ctrl);
 25.1019 +
 25.1020 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
 25.1021 +        DEBUGOUT("PHY Read Error\n");
 25.1022 +        return -E1000_ERR_PHY;
 25.1023 +    }
 25.1024 +
 25.1025 +    /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
 25.1026 +     * forced whenever speed are duplex are forced.
 25.1027 +     */
 25.1028 +    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
 25.1029 +    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
 25.1030 +        DEBUGOUT("PHY Write Error\n");
 25.1031 +        return -E1000_ERR_PHY;
 25.1032 +    }
 25.1033 +    DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
 25.1034 +
 25.1035 +    /* Need to reset the PHY or these changes will be ignored */
 25.1036 +    mii_ctrl_reg |= MII_CR_RESET;
 25.1037 +
 25.1038 +    /* Write back the modified PHY MII control register. */
 25.1039 +    if(e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
 25.1040 +        DEBUGOUT("PHY Write Error\n");
 25.1041 +        return -E1000_ERR_PHY;
 25.1042 +    }
 25.1043 +    udelay(1);
 25.1044 +
 25.1045 +    /* The wait_autoneg_complete flag may be a little misleading here.
 25.1046 +     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
 25.1047 +     * But we do want to delay for a period while forcing only so we
 25.1048 +     * don't generate false No Link messages.  So we will wait here
 25.1049 +     * only if the user has set wait_autoneg_complete to 1, which is
 25.1050 +     * the default.
 25.1051 +     */
 25.1052 +    if(hw->wait_autoneg_complete) {
 25.1053 +        /* We will wait for autoneg to complete. */
 25.1054 +        DEBUGOUT("Waiting for forced speed/duplex link.\n");
 25.1055 +        mii_status_reg = 0;
 25.1056 +
 25.1057 +        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
 25.1058 +        for(i = PHY_FORCE_TIME; i > 0; i--) {
 25.1059 +            /* Read the MII Status Register and wait for Auto-Neg Complete bit
 25.1060 +             * to be set.
 25.1061 +             */
 25.1062 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
 25.1063 +                DEBUGOUT("PHY Read Error\n");
 25.1064 +                return -E1000_ERR_PHY;
 25.1065 +            }
 25.1066 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
 25.1067 +                DEBUGOUT("PHY Read Error\n");
 25.1068 +                return -E1000_ERR_PHY;
 25.1069 +            }
 25.1070 +            if(mii_status_reg & MII_SR_LINK_STATUS) break;
 25.1071 +            msec_delay(100);
 25.1072 +        }
 25.1073 +        if(i == 0) { /* We didn't get link */
 25.1074 +            /* Reset the DSP and wait again for link. */
 25.1075 +            
 25.1076 +            ret_val = e1000_phy_reset_dsp(hw);
 25.1077 +            if(ret_val < 0) {
 25.1078 +                DEBUGOUT("Error Resetting PHY DSP\n");
 25.1079 +                return ret_val;
 25.1080 +            }
 25.1081 +        }
 25.1082 +        /* This loop will early-out if the link condition has been met.  */
 25.1083 +        for(i = PHY_FORCE_TIME; i > 0; i--) {
 25.1084 +            if(mii_status_reg & MII_SR_LINK_STATUS) break;
 25.1085 +            msec_delay(100);
 25.1086 +            /* Read the MII Status Register and wait for Auto-Neg Complete bit
 25.1087 +             * to be set.
 25.1088 +             */
 25.1089 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
 25.1090 +                DEBUGOUT("PHY Read Error\n");
 25.1091 +                return -E1000_ERR_PHY;
 25.1092 +            }
 25.1093 +            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
 25.1094 +                DEBUGOUT("PHY Read Error\n");
 25.1095 +                return -E1000_ERR_PHY;
 25.1096 +            }
 25.1097 +        }
 25.1098 +    }
 25.1099 +    
 25.1100 +    /* Because we reset the PHY above, we need to re-force TX_CLK in the
 25.1101 +     * Extended PHY Specific Control Register to 25MHz clock.  This value
 25.1102 +     * defaults back to a 2.5MHz clock when the PHY is reset.
 25.1103 +     */
 25.1104 +    if(e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
 25.1105 +        DEBUGOUT("PHY Read Error\n");
 25.1106 +        return -E1000_ERR_PHY;
 25.1107 +    }
 25.1108 +    phy_data |= M88E1000_EPSCR_TX_CLK_25;
 25.1109 +    if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
 25.1110 +        DEBUGOUT("PHY Write Error\n");
 25.1111 +        return -E1000_ERR_PHY;
 25.1112 +    }
 25.1113 +
 25.1114 +    /* In addition, because of the s/w reset above, we need to enable CRS on
 25.1115 +     * TX.  This must be set for both full and half duplex operation.
 25.1116 +     */
 25.1117 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
 25.1118 +        DEBUGOUT("PHY Read Error\n");
 25.1119 +        return -E1000_ERR_PHY;
 25.1120 +    }
 25.1121 +    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
 25.1122 +    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
 25.1123 +        DEBUGOUT("PHY Write Error\n");
 25.1124 +        return -E1000_ERR_PHY;
 25.1125 +    }
 25.1126 +    return 0;
 25.1127 +}
 25.1128 +
 25.1129 +/******************************************************************************
 25.1130 +* Sets the collision distance in the Transmit Control register
 25.1131 +*
 25.1132 +* hw - Struct containing variables accessed by shared code
 25.1133 +*
 25.1134 +* Link should have been established previously. Reads the speed and duplex
 25.1135 +* information from the Device Status register.
 25.1136 +******************************************************************************/
 25.1137 +void
 25.1138 +e1000_config_collision_dist(struct e1000_hw *hw)
 25.1139 +{
 25.1140 +    uint32_t tctl;
 25.1141 +
 25.1142 +    tctl = E1000_READ_REG(hw, TCTL);
 25.1143 +
 25.1144 +    tctl &= ~E1000_TCTL_COLD;
 25.1145 +    tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
 25.1146 +
 25.1147 +    E1000_WRITE_REG(hw, TCTL, tctl);
 25.1148 +    E1000_WRITE_FLUSH(hw);
 25.1149 +}
 25.1150 +
 25.1151 +/******************************************************************************
 25.1152 +* Sets MAC speed and duplex settings to reflect the those in the PHY
 25.1153 +*
 25.1154 +* hw - Struct containing variables accessed by shared code
 25.1155 +* mii_reg - data to write to the MII control register
 25.1156 +*
 25.1157 +* The contents of the PHY register containing the needed information need to
 25.1158 +* be passed in.
 25.1159 +******************************************************************************/
 25.1160 +static int32_t
 25.1161 +e1000_config_mac_to_phy(struct e1000_hw *hw)
 25.1162 +{
 25.1163 +    uint32_t ctrl;
 25.1164 +    uint16_t phy_data;
 25.1165 +
 25.1166 +    DEBUGFUNC("e1000_config_mac_to_phy");
 25.1167 +
 25.1168 +    /* Read the Device Control Register and set the bits to Force Speed
 25.1169 +     * and Duplex.
 25.1170 +     */
 25.1171 +    ctrl = E1000_READ_REG(hw, CTRL);
 25.1172 +    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 25.1173 +    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
 25.1174 +
 25.1175 +    /* Set up duplex in the Device Control and Transmit Control
 25.1176 +     * registers depending on negotiated values.
 25.1177 +     */
 25.1178 +    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
 25.1179 +        DEBUGOUT("PHY Read Error\n");
 25.1180 +        return -E1000_ERR_PHY;
 25.1181 +    }
 25.1182 +    if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
 25.1183 +    else ctrl &= ~E1000_CTRL_FD;
 25.1184 +
 25.1185 +    e1000_config_collision_dist(hw);
 25.1186 +
 25.1187 +    /* Set up speed in the Device Control register depending on
 25.1188 +     * negotiated values.
 25.1189 +     */
 25.1190 +    if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
 25.1191 +        ctrl |= E1000_CTRL_SPD_1000;
 25.1192 +    else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
 25.1193 +        ctrl |= E1000_CTRL_SPD_100;
 25.1194 +    /* Write the configured values back to the Device Control Reg. */
 25.1195 +    E1000_WRITE_REG(hw, CTRL, ctrl);
 25.1196 +    return 0;
 25.1197 +}
 25.1198 +
 25.1199 +/******************************************************************************
 25.1200 + * Forces the MAC's flow control settings.
 25.1201 + * 
 25.1202 + * hw - Struct containing variables accessed by shared code
 25.1203 + *
 25.1204 + * Sets the TFCE and RFCE bits in the device control register to reflect
 25.1205 + * the adapter settings. TFCE and RFCE need to be explicitly set by
 25.1206 + * software when a Copper PHY is used because autonegotiation is managed
 25.1207 + * by the PHY rather than the MAC. Software must also configure these
 25.1208 + * bits when link is forced on a fiber connection.
 25.1209 + *****************************************************************************/
 25.1210 +static int32_t
 25.1211 +e1000_force_mac_fc(struct e1000_hw *hw)
 25.1212 +{
 25.1213 +    uint32_t ctrl;
 25.1214 +
 25.1215 +    DEBUGFUNC("e1000_force_mac_fc");
 25.1216 +
 25.1217 +    /* Get the current configuration of the Device Control Register */
 25.1218 +    ctrl = E1000_READ_REG(hw, CTRL);
 25.1219 +
 25.1220 +    /* Because we didn't get link via the internal auto-negotiation
 25.1221 +     * mechanism (we either forced link or we got link via PHY
 25.1222 +     * auto-neg), we have to manually enable/disable transmit an
 25.1223 +     * receive flow control.
 25.1224 +     *
 25.1225 +     * The "Case" statement below enables/disable flow control
 25.1226 +     * according to the "hw->fc" parameter.
 25.1227 +     *
 25.1228 +     * The possible values of the "fc" parameter are:
 25.1229 +     *      0:  Flow control is completely disabled
 25.1230 +     *      1:  Rx flow control is enabled (we can receive pause
 25.1231 +     *          frames but not send pause frames).
 25.1232 +     *      2:  Tx flow control is enabled (we can send pause frames
 25.1233 +     *          frames but we do not receive pause frames).
 25.1234 +     *      3:  Both Rx and TX flow control (symmetric) is enabled.
 25.1235 +     *  other:  No other values should be possible at this point.
 25.1236 +     */
 25.1237 +
 25.1238 +    switch (hw->fc) {
 25.1239 +    case e1000_fc_none:
 25.1240 +        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
 25.1241 +        break;
 25.1242 +    case e1000_fc_rx_pause:
 25.1243 +        ctrl &= (~E1000_CTRL_TFCE);
 25.1244 +        ctrl |= E1000_CTRL_RFCE;
 25.1245 +        break;
 25.1246 +    case e1000_fc_tx_pause:
 25.1247 +        ctrl &= (~E1000_CTRL_RFCE);
 25.1248 +        ctrl |= E1000_CTRL_TFCE;
 25.1249 +        break;
 25.1250 +    case e1000_fc_full:
 25.1251 +        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
 25.1252 +        break;
 25.1253 +    default:
 25.1254 +        DEBUGOUT("Flow control param set incorrectly\n");
 25.1255 +        return -E1000_ERR_CONFIG;
 25.1256 +    }
 25.1257 +
 25.1258 +    /* Disable TX Flow Control for 82542 (rev 2.0) */
 25.1259 +    if(hw->mac_type == e1000_82542_rev2_0)
 25.1260 +        ctrl &= (~E1000_CTRL_TFCE);
 25.1261 +
 25.1262 +    E1000_WRITE_REG(hw, CTRL, ctrl);
 25.1263 +    return 0;
 25.1264 +}
 25.1265 +
 25.1266 +/******************************************************************************
 25.1267 + * Configures flow control settings after link is established
 25.1268 + * 
 25.1269 + * hw - Struct containing variables accessed by shared code
 25.1270 + *
 25.1271 + * Should be called immediately after a valid link has been established.
 25.1272 + * Forces MAC flow control settings if link was forced. When in MII/GMII mode
 25.1273 + * and autonegotiation is enabled, the MAC flow control settings will be set
 25.1274 + * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
 25.1275 + * and RFCE bits will be automaticaly set to the negotiated flow control mode.
 25.1276 + *****************************************************************************/
 25.1277 +int32_t
 25.1278 +e1000_config_fc_after_link_up(struct e1000_hw *hw)
 25.1279 +{
 25.1280 +    int32_t ret_val;
 25.1281 +    uint16_t mii_status_reg;
 25.1282 +    uint16_t mii_nway_adv_reg;
 25.1283 +    uint16_t mii_nway_lp_ability_reg;
 25.1284 +    uint16_t speed;
 25.1285 +    uint16_t duplex;
 25.1286 +
 25.1287 +    DEBUGFUNC("e1000_config_fc_after_link_up");
 25.1288 +
 25.1289 +    /* Check for the case where we have fiber media and auto-neg failed
 25.1290 +     * so we had to force link.  In this case, we need to force the
 25.1291 +     * configuration of the MAC to match the "fc" parameter.
 25.1292 +     */
 25.1293 +    if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
 25.1294 +       ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
 25.1295 +        ret_val = e1000_force_mac_fc(hw);
 25.1296 +        if(ret_val < 0) {
 25.1297 +            DEBUGOUT("Error forcing flow control settings\n");
 25.1298 +            return ret_val;
 25.1299 +        }
 25.1300 +    }
 25.1301 +
 25.1302 +    /* Check for the case where we have copper media and auto-neg is
 25.1303 +     * enabled.  In this case, we need to check and see if Auto-Neg
 25.1304 +     * has completed, and if so, how the PHY and link partner has
 25.1305 +     * flow control configured.
 25.1306 +     */
 25.1307 +    if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
 25.1308 +        /* Read the MII Status Register and check to see if AutoNeg
 25.1309 +         * has completed.  We read this twice because this reg has
 25.1310 +         * some "sticky" (latched) bits.
 25.1311 +         */
 25.1312 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
 25.1313 +            DEBUGOUT("PHY Read Error \n");
 25.1314 +            return -E1000_ERR_PHY;
 25.1315 +        }
 25.1316 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
 25.1317 +            DEBUGOUT("PHY Read Error \n");
 25.1318 +            return -E1000_ERR_PHY;
 25.1319 +        }
 25.1320 +
 25.1321 +        if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
 25.1322 +            /* The AutoNeg process has completed, so we now need to
 25.1323 +             * read both the Auto Negotiation Advertisement Register
 25.1324 +             * (Address 4) and the Auto_Negotiation Base Page Ability
 25.1325 +             * Register (Address 5) to determine how flow control was
 25.1326 +             * negotiated.
 25.1327 +             */
 25.1328 +            if(e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
 25.1329 +                DEBUGOUT("PHY Read Error\n");
 25.1330 +                return -E1000_ERR_PHY;
 25.1331 +            }
 25.1332 +            if(e1000_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
 25.1333 +                DEBUGOUT("PHY Read Error\n");
 25.1334 +                return -E1000_ERR_PHY;
 25.1335 +            }
 25.1336 +
 25.1337 +            /* Two bits in the Auto Negotiation Advertisement Register
 25.1338 +             * (Address 4) and two bits in the Auto Negotiation Base
 25.1339 +             * Page Ability Register (Address 5) determine flow control
 25.1340 +             * for both the PHY and the link partner.  The following
 25.1341 +             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
 25.1342 +             * 1999, describes these PAUSE resolution bits and how flow
 25.1343 +             * control is determined based upon these settings.
 25.1344 +             * NOTE:  DC = Don't Care
 25.1345 +             *
 25.1346 +             *   LOCAL DEVICE  |   LINK PARTNER
 25.1347 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
 25.1348 +             *-------|---------|-------|---------|--------------------
 25.1349 +             *   0   |    0    |  DC   |   DC    | e1000_fc_none
 25.1350 +             *   0   |    1    |   0   |   DC    | e1000_fc_none
 25.1351 +             *   0   |    1    |   1   |    0    | e1000_fc_none
 25.1352 +             *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
 25.1353 +             *   1   |    0    |   0   |   DC    | e1000_fc_none
 25.1354 +             *   1   |   DC    |   1   |   DC    | e1000_fc_full
 25.1355 +             *   1   |    1    |   0   |    0    | e1000_fc_none
 25.1356 +             *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
 25.1357 +             *
 25.1358 +             */
 25.1359 +            /* Are both PAUSE bits set to 1?  If so, this implies
 25.1360 +             * Symmetric Flow Control is enabled at both ends.  The
 25.1361 +             * ASM_DIR bits are irrelevant per the spec.
 25.1362 +             *
 25.1363 +             * For Symmetric Flow Control:
 25.1364 +             *
 25.1365 +             *   LOCAL DEVICE  |   LINK PARTNER
 25.1366 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 25.1367 +             *-------|---------|-------|---------|--------------------
 25.1368 +             *   1   |   DC    |   1   |   DC    | e1000_fc_full
 25.1369 +             *
 25.1370 +             */
 25.1371 +            if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 25.1372 +               (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
 25.1373 +                /* Now we need to check if the user selected RX ONLY
 25.1374 +                 * of pause frames.  In this case, we had to advertise
 25.1375 +                 * FULL flow control because we could not advertise RX
 25.1376 +                 * ONLY. Hence, we must now check to see if we need to
 25.1377 +                 * turn OFF  the TRANSMISSION of PAUSE frames.
 25.1378 +                 */
 25.1379 +                if(hw->original_fc == e1000_fc_full) {
 25.1380 +                    hw->fc = e1000_fc_full;
 25.1381 +                    DEBUGOUT("Flow Control = FULL.\r\n");
 25.1382 +                } else {
 25.1383 +                    hw->fc = e1000_fc_rx_pause;
 25.1384 +                    DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
 25.1385 +                }
 25.1386 +            }
 25.1387 +            /* For receiving PAUSE frames ONLY.
 25.1388 +             *
 25.1389 +             *   LOCAL DEVICE  |   LINK PARTNER
 25.1390 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 25.1391 +             *-------|---------|-------|---------|--------------------
 25.1392 +             *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
 25.1393 +             *
 25.1394 +             */
 25.1395 +            else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 25.1396 +                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
 25.1397 +                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
 25.1398 +                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 25.1399 +                hw->fc = e1000_fc_tx_pause;
 25.1400 +                DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
 25.1401 +            }
 25.1402 +            /* For transmitting PAUSE frames ONLY.
 25.1403 +             *
 25.1404 +             *   LOCAL DEVICE  |   LINK PARTNER
 25.1405 +             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 25.1406 +             *-------|---------|-------|---------|--------------------
 25.1407 +             *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
 25.1408 +             *
 25.1409 +             */
 25.1410 +            else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 25.1411 +                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
 25.1412 +                    !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
 25.1413 +                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 25.1414 +                hw->fc = e1000_fc_rx_pause;
 25.1415 +                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
 25.1416 +            }
 25.1417 +            /* Per the IEEE spec, at this point flow control should be
 25.1418 +             * disabled.  However, we want to consider that we could
 25.1419 +             * be connected to a legacy switch that doesn't advertise
 25.1420 +             * desired flow control, but can be forced on the link
 25.1421 +             * partner.  So if we advertised no flow control, that is
 25.1422 +             * what we will resolve to.  If we advertised some kind of
 25.1423 +             * receive capability (Rx Pause Only or Full Flow Control)
 25.1424 +             * and the link partner advertised none, we will configure
 25.1425 +             * ourselves to enable Rx Flow Control only.  We can do
 25.1426 +             * this safely for two reasons:  If the link partner really
 25.1427 +             * didn't want flow control enabled, and we enable Rx, no
 25.1428 +             * harm done since we won't be receiving any PAUSE frames
 25.1429 +             * anyway.  If the intent on the link partner was to have
 25.1430 +             * flow control enabled, then by us enabling RX only, we
 25.1431 +             * can at least receive pause frames and process them.
 25.1432 +             * This is a good idea because in most cases, since we are
 25.1433 +             * predominantly a server NIC, more times than not we will
 25.1434 +             * be asked to delay transmission of packets than asking
 25.1435 +             * our link partner to pause transmission of frames.
 25.1436 +             */
 25.1437 +            else if(hw->original_fc == e1000_fc_none ||
 25.1438 +                    hw->original_fc == e1000_fc_tx_pause) {
 25.1439 +                hw->fc = e1000_fc_none;
 25.1440 +                DEBUGOUT("Flow Control = NONE.\r\n");
 25.1441 +            } else {
 25.1442 +                hw->fc = e1000_fc_rx_pause;
 25.1443 +                DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
 25.1444 +            }
 25.1445 +
 25.1446 +            /* Now we need to do one last check...  If we auto-
 25.1447 +             * negotiated to HALF DUPLEX, flow control should not be
 25.1448 +             * enabled per IEEE 802.3 spec.
 25.1449 +             */
 25.1450 +            e1000_get_speed_and_duplex(hw, &speed, &duplex);
 25.1451 +
 25.1452 +            if(duplex == HALF_DUPLEX)
 25.1453 +                hw->fc = e1000_fc_none;
 25.1454 +
 25.1455 +            /* Now we call a subroutine to actually force the MAC
 25.1456 +             * controller to use the correct flow control settings.
 25.1457 +             */
 25.1458 +            ret_val = e1000_force_mac_fc(hw);
 25.1459 +            if(ret_val < 0) {
 25.1460 +                DEBUGOUT("Error forcing flow control settings\n");
 25.1461 +                return ret_val;
 25.1462 +             }
 25.1463 +        } else {
 25.1464 +            DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
 25.1465 +        }
 25.1466 +    }
 25.1467 +    return 0;
 25.1468 +}
 25.1469 +
 25.1470 +/******************************************************************************
 25.1471 + * Checks to see if the link status of the hardware has changed.
 25.1472 + *
 25.1473 + * hw - Struct containing variables accessed by shared code
 25.1474 + *
 25.1475 + * Called by any function that needs to check the link status of the adapter.
 25.1476 + *****************************************************************************/
 25.1477 +int32_t
 25.1478 +e1000_check_for_link(struct e1000_hw *hw)
 25.1479 +{
 25.1480 +    uint32_t rxcw;
 25.1481 +    uint32_t ctrl;
 25.1482 +    uint32_t status;
 25.1483 +    uint32_t rctl;
 25.1484 +    uint32_t signal;
 25.1485 +    int32_t ret_val;
 25.1486 +    uint16_t phy_data;
 25.1487 +    uint16_t lp_capability;
 25.1488 +
 25.1489 +    DEBUGFUNC("e1000_check_for_link");
 25.1490 +    
 25.1491 +    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
 25.1492 +     * set when the optics detect a signal. On older adapters, it will be 
 25.1493 +     * cleared when there is a signal
 25.1494 +     */
 25.1495 +    if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
 25.1496 +    else signal = 0;
 25.1497 +
 25.1498 +    ctrl = E1000_READ_REG(hw, CTRL);
 25.1499 +    status = E1000_READ_REG(hw, STATUS);
 25.1500 +    rxcw = E1000_READ_REG(hw, RXCW);
 25.1501 +
 25.1502 +    /* If we have a copper PHY then we only want to go out to the PHY
 25.1503 +     * registers to see if Auto-Neg has completed and/or if our link
 25.1504 +     * status has changed.  The get_link_status flag will be set if we
 25.1505 +     * receive a Link Status Change interrupt or we have Rx Sequence
 25.1506 +     * Errors.
 25.1507 +     */
 25.1508 +    if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
 25.1509 +        /* First we want to see if the MII Status Register reports
 25.1510 +         * link.  If so, then we want to get the current speed/duplex
 25.1511 +         * of the PHY.
 25.1512 +         * Read the register twice since the link bit is sticky.
 25.1513 +         */
 25.1514 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
 25.1515 +            DEBUGOUT("PHY Read Error\n");
 25.1516 +            return -E1000_ERR_PHY;
 25.1517 +        }
 25.1518 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
 25.1519 +            DEBUGOUT("PHY Read Error\n");
 25.1520 +            return -E1000_ERR_PHY;
 25.1521 +        }
 25.1522 +
 25.1523 +        if(phy_data & MII_SR_LINK_STATUS) {
 25.1524 +            hw->get_link_status = FALSE;
 25.1525 +        } else {
 25.1526 +            /* No link detected */
 25.1527 +            return 0;
 25.1528 +        }
 25.1529 +
 25.1530 +        /* If we are forcing speed/duplex, then we simply return since
 25.1531 +         * we have already determined whether we have link or not.
 25.1532 +         */
 25.1533 +        if(!hw->autoneg) return -E1000_ERR_CONFIG;
 25.1534 +
 25.1535 +        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
 25.1536 +         * have Si on board that is 82544 or newer, Auto
 25.1537 +         * Speed Detection takes care of MAC speed/duplex
 25.1538 +         * configuration.  So we only need to configure Collision
 25.1539 +         * Distance in the MAC.  Otherwise, we need to force
 25.1540 +         * speed/duplex on the MAC to the current PHY speed/duplex
 25.1541 +         * settings.
 25.1542 +         */
 25.1543 +        if(hw->mac_type >= e1000_82544)
 25.1544 +            e1000_config_collision_dist(hw);
 25.1545 +        else {
 25.1546 +            ret_val = e1000_config_mac_to_phy(hw);
 25.1547 +            if(ret_val < 0) {
 25.1548 +                DEBUGOUT("Error configuring MAC to PHY settings\n");
 25.1549 +                return ret_val;
 25.1550 +            }
 25.1551 +        }
 25.1552 +
 25.1553 +        /* Configure Flow Control now that Auto-Neg has completed. First, we 
 25.1554 +         * need to restore the desired flow control settings because we may
 25.1555 +         * have had to re-autoneg with a different link partner.
 25.1556 +         */
 25.1557 +        ret_val = e1000_config_fc_after_link_up(hw);
 25.1558 +        if(ret_val < 0) {
 25.1559 +            DEBUGOUT("Error configuring flow control\n");
 25.1560 +            return ret_val;
 25.1561 +        }
 25.1562 +
 25.1563 +        /* At this point we know that we are on copper and we have
 25.1564 +         * auto-negotiated link.  These are conditions for checking the link
 25.1565 +         * parter capability register.  We use the link partner capability to
 25.1566 +         * determine if TBI Compatibility needs to be turned on or off.  If
 25.1567 +         * the link partner advertises any speed in addition to Gigabit, then
 25.1568 +         * we assume that they are GMII-based, and TBI compatibility is not
 25.1569 +         * needed. If no other speeds are advertised, we assume the link
 25.1570 +         * partner is TBI-based, and we turn on TBI Compatibility.
 25.1571 +         */
 25.1572 +        if(hw->tbi_compatibility_en) {
 25.1573 +            if(e1000_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
 25.1574 +                DEBUGOUT("PHY Read Error\n");
 25.1575 +                return -E1000_ERR_PHY;
 25.1576 +            }
 25.1577 +            if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
 25.1578 +                                NWAY_LPAR_10T_FD_CAPS |
 25.1579 +                                NWAY_LPAR_100TX_HD_CAPS |
 25.1580 +                                NWAY_LPAR_100TX_FD_CAPS |
 25.1581 +                                NWAY_LPAR_100T4_CAPS)) {
 25.1582 +                /* If our link partner advertises anything in addition to 
 25.1583 +                 * gigabit, we do not need to enable TBI compatibility.
 25.1584 +                 */
 25.1585 +                if(hw->tbi_compatibility_on) {
 25.1586 +                    /* If we previously were in the mode, turn it off. */
 25.1587 +                    rctl = E1000_READ_REG(hw, RCTL);
 25.1588 +                    rctl &= ~E1000_RCTL_SBP;
 25.1589 +                    E1000_WRITE_REG(hw, RCTL, rctl);
 25.1590 +                    hw->tbi_compatibility_on = FALSE;
 25.1591 +                }
 25.1592 +            } else {
 25.1593 +                /* If TBI compatibility is was previously off, turn it on. For
 25.1594 +                 * compatibility with a TBI link partner, we will store bad
 25.1595 +                 * packets. Some frames have an additional byte on the end and
 25.1596 +                 * will look like CRC errors to to the hardware.
 25.1597 +                 */
 25.1598 +                if(!hw->tbi_compatibility_on) {
 25.1599 +                    hw->tbi_compatibility_on = TRUE;
 25.1600 +                    rctl = E1000_READ_REG(hw, RCTL);
 25.1601 +                    rctl |= E1000_RCTL_SBP;
 25.1602 +                    E1000_WRITE_REG(hw, RCTL, rctl);
 25.1603 +                }
 25.1604 +            }
 25.1605 +        }
 25.1606 +    }
 25.1607 +    /* If we don't have link (auto-negotiation failed or link partner cannot
 25.1608 +     * auto-negotiate), the cable is plugged in (we have signal), and our
 25.1609 +     * link partner is not trying to auto-negotiate with us (we are receiving
 25.1610 +     * idles or data), we need to force link up. We also need to give
 25.1611 +     * auto-negotiation time to complete, in case the cable was just plugged
 25.1612 +     * in. The autoneg_failed flag does this.
 25.1613 +     */
 25.1614 +    else if((hw->media_type == e1000_media_type_fiber) &&
 25.1615 +            (!(status & E1000_STATUS_LU)) &&
 25.1616 +            ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
 25.1617 +            (!(rxcw & E1000_RXCW_C))) {
 25.1618 +        if(hw->autoneg_failed == 0) {
 25.1619 +            hw->autoneg_failed = 1;
 25.1620 +            return 0;
 25.1621 +        }
 25.1622 +        DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
 25.1623 +
 25.1624 +        /* Disable auto-negotiation in the TXCW register */
 25.1625 +        E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
 25.1626 +
 25.1627 +        /* Force link-up and also force full-duplex. */
 25.1628 +        ctrl = E1000_READ_REG(hw, CTRL);
 25.1629 +        ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
 25.1630 +        E1000_WRITE_REG(hw, CTRL, ctrl);
 25.1631 +
 25.1632 +        /* Configure Flow Control after forcing link up. */
 25.1633 +        ret_val = e1000_config_fc_after_link_up(hw);
 25.1634 +        if(ret_val < 0) {
 25.1635 +            DEBUGOUT("Error configuring flow control\n");
 25.1636 +            return ret_val;
 25.1637 +        }
 25.1638 +    }
 25.1639 +    /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
 25.1640 +     * auto-negotiation in the TXCW register and disable forced link in the
 25.1641 +     * Device Control register in an attempt to auto-negotiate with our link
 25.1642 +     * partner.
 25.1643 +     */
 25.1644 +    else if((hw->media_type == e1000_media_type_fiber) &&
 25.1645 +              (ctrl & E1000_CTRL_SLU) &&
 25.1646 +              (rxcw & E1000_RXCW_C)) {
 25.1647 +        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
 25.1648 +        E1000_WRITE_REG(hw, TXCW, hw->txcw);
 25.1649 +        E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
 25.1650 +    }
 25.1651 +    return 0;
 25.1652 +}
 25.1653 +
 25.1654 +/******************************************************************************
 25.1655 + * Detects the current speed and duplex settings of the hardware.
 25.1656 + *
 25.1657 + * hw - Struct containing variables accessed by shared code
 25.1658 + * speed - Speed of the connection
 25.1659 + * duplex - Duplex setting of the connection
 25.1660 + *****************************************************************************/
 25.1661 +void
 25.1662 +e1000_get_speed_and_duplex(struct e1000_hw *hw,
 25.1663 +                           uint16_t *speed,
 25.1664 +                           uint16_t *duplex)
 25.1665 +{
 25.1666 +    uint32_t status;
 25.1667 +
 25.1668 +    DEBUGFUNC("e1000_get_speed_and_duplex");
 25.1669 +
 25.1670 +    if(hw->mac_type >= e1000_82543) {
 25.1671 +        status = E1000_READ_REG(hw, STATUS);
 25.1672 +        if(status & E1000_STATUS_SPEED_1000) {
 25.1673 +            *speed = SPEED_1000;
 25.1674 +            DEBUGOUT("1000 Mbs, ");
 25.1675 +        } else if(status & E1000_STATUS_SPEED_100) {
 25.1676 +            *speed = SPEED_100;
 25.1677 +            DEBUGOUT("100 Mbs, ");
 25.1678 +        } else {
 25.1679 +            *speed = SPEED_10;
 25.1680 +            DEBUGOUT("10 Mbs, ");
 25.1681 +        }
 25.1682 +
 25.1683 +        if(status & E1000_STATUS_FD) {
 25.1684 +            *duplex = FULL_DUPLEX;
 25.1685 +            DEBUGOUT("Full Duplex\r\n");
 25.1686 +        } else {
 25.1687 +            *duplex = HALF_DUPLEX;
 25.1688 +            DEBUGOUT(" Half Duplex\r\n");
 25.1689 +        }
 25.1690 +    } else {
 25.1691 +        DEBUGOUT("1000 Mbs, Full Duplex\r\n");
 25.1692 +        *speed = SPEED_1000;
 25.1693 +        *duplex = FULL_DUPLEX;
 25.1694 +    }
 25.1695 +}
 25.1696 +
 25.1697 +/******************************************************************************
 25.1698 +* Blocks until autoneg completes or times out (~4.5 seconds)
 25.1699 +*
 25.1700 +* hw - Struct containing variables accessed by shared code
 25.1701 +******************************************************************************/
 25.1702 +int32_t
 25.1703 +e1000_wait_autoneg(struct e1000_hw *hw)
 25.1704 +{
 25.1705 +    uint16_t i;
 25.1706 +    uint16_t phy_data;
 25.1707 +
 25.1708 +    DEBUGFUNC("e1000_wait_autoneg");
 25.1709 +    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
 25.1710 +
 25.1711 +    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
 25.1712 +    for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
 25.1713 +        /* Read the MII Status Register and wait for Auto-Neg
 25.1714 +         * Complete bit to be set.
 25.1715 +         */
 25.1716 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
 25.1717 +            DEBUGOUT("PHY Read Error\n");
 25.1718 +            return -E1000_ERR_PHY;
 25.1719 +        }
 25.1720 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
 25.1721 +            DEBUGOUT("PHY Read Error\n");
 25.1722 +            return -E1000_ERR_PHY;
 25.1723 +        }
 25.1724 +        if(phy_data & MII_SR_AUTONEG_COMPLETE) {
 25.1725 +            return 0;
 25.1726 +        }
 25.1727 +        msec_delay(100);
 25.1728 +    }
 25.1729 +    return 0;
 25.1730 +}
 25.1731 +
 25.1732 +/******************************************************************************
 25.1733 +* Raises the Management Data Clock
 25.1734 +*
 25.1735 +* hw - Struct containing variables accessed by shared code
 25.1736 +* ctrl - Device control register's current value
 25.1737 +******************************************************************************/
 25.1738 +static void
 25.1739 +e1000_raise_mdi_clk(struct e1000_hw *hw,
 25.1740 +                    uint32_t *ctrl)
 25.1741 +{
 25.1742 +    /* Raise the clock input to the Management Data Clock (by setting the MDC
 25.1743 +     * bit), and then delay 2 microseconds.
 25.1744 +     */
 25.1745 +    E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
 25.1746 +    E1000_WRITE_FLUSH(hw);
 25.1747 +    udelay(2);
 25.1748 +}
 25.1749 +
 25.1750 +/******************************************************************************
 25.1751 +* Lowers the Management Data Clock
 25.1752 +*
 25.1753 +* hw - Struct containing variables accessed by shared code
 25.1754 +* ctrl - Device control register's current value
 25.1755 +******************************************************************************/
 25.1756 +static void
 25.1757 +e1000_lower_mdi_clk(struct e1000_hw *hw,
 25.1758 +                    uint32_t *ctrl)
 25.1759 +{
 25.1760 +    /* Lower the clock input to the Management Data Clock (by clearing the MDC
 25.1761 +     * bit), and then delay 2 microseconds.
 25.1762 +     */
 25.1763 +    E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
 25.1764 +    E1000_WRITE_FLUSH(hw);
 25.1765 +    udelay(2);
 25.1766 +}
 25.1767 +
 25.1768 +/******************************************************************************
 25.1769 +* Shifts data bits out to the PHY
 25.1770 +*
 25.1771 +* hw - Struct containing variables accessed by shared code
 25.1772 +* data - Data to send out to the PHY
 25.1773 +* count - Number of bits to shift out
 25.1774 +*
 25.1775 +* Bits are shifted out in MSB to LSB order.
 25.1776 +******************************************************************************/
 25.1777 +static void
 25.1778 +e1000_shift_out_mdi_bits(struct e1000_hw *hw,
 25.1779 +                         uint32_t data,
 25.1780 +                         uint16_t count)
 25.1781 +{
 25.1782 +    uint32_t ctrl;
 25.1783 +    uint32_t mask;
 25.1784 +
 25.1785 +    /* We need to shift "count" number of bits out to the PHY. So, the value
 25.1786 +     * in the "data" parameter will be shifted out to the PHY one bit at a 
 25.1787 +     * time. In order to do this, "data" must be broken down into bits.
 25.1788 +     */
 25.1789 +    mask = 0x01;
 25.1790 +    mask <<= (count - 1);
 25.1791 +
 25.1792 +    ctrl = E1000_READ_REG(hw, CTRL);
 25.1793 +
 25.1794 +    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
 25.1795 +    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
 25.1796 +
 25.1797 +    while(mask) {
 25.1798 +        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
 25.1799 +         * then raising and lowering the Management Data Clock. A "0" is
 25.1800 +         * shifted out to the PHY by setting the MDIO bit to "0" and then
 25.1801 +         * raising and lowering the clock.
 25.1802 +         */
 25.1803 +        if(data & mask) ctrl |= E1000_CTRL_MDIO;
 25.1804 +        else ctrl &= ~E1000_CTRL_MDIO;
 25.1805 +
 25.1806 +        E1000_WRITE_REG(hw, CTRL, ctrl);
 25.1807 +        E1000_WRITE_FLUSH(hw);
 25.1808 +
 25.1809 +        udelay(2);
 25.1810 +
 25.1811 +        e1000_raise_mdi_clk(hw, &ctrl);
 25.1812 +        e1000_lower_mdi_clk(hw, &ctrl);
 25.1813 +
 25.1814 +        mask = mask >> 1;
 25.1815 +    }
 25.1816 +}
 25.1817 +
 25.1818 +/******************************************************************************
 25.1819 +* Shifts data bits in from the PHY
 25.1820 +*
 25.1821 +* hw - Struct containing variables accessed by shared code
 25.1822 +*
 25.1823 +* Bits are shifted in in MSB to LSB order. 
 25.1824 +******************************************************************************/
 25.1825 +static uint16_t
 25.1826 +e1000_shift_in_mdi_bits(struct e1000_hw *hw)
 25.1827 +{
 25.1828 +    uint32_t ctrl;
 25.1829 +    uint16_t data = 0;
 25.1830 +    uint8_t i;
 25.1831 +
 25.1832 +    /* In order to read a register from the PHY, we need to shift in a total
 25.1833 +     * of 18 bits from the PHY. The first two bit (turnaround) times are used
 25.1834 +     * to avoid contention on the MDIO pin when a read operation is performed.
 25.1835 +     * These two bits are ignored by us and thrown away. Bits are "shifted in"
 25.1836 +     * by raising the input to the Management Data Clock (setting the MDC bit),
 25.1837 +     * and then reading the value of the MDIO bit.
 25.1838 +     */ 
 25.1839 +    ctrl = E1000_READ_REG(hw, CTRL);
 25.1840 +
 25.1841 +    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
 25.1842 +    ctrl &= ~E1000_CTRL_MDIO_DIR;
 25.1843 +    ctrl &= ~E1000_CTRL_MDIO;
 25.1844 +
 25.1845 +    E1000_WRITE_REG(hw, CTRL, ctrl);
 25.1846 +    E1000_WRITE_FLUSH(hw);
 25.1847 +
 25.1848 +    /* Raise and Lower the clock before reading in the data. This accounts for
 25.1849 +     * the turnaround bits. The first clock occurred when we clocked out the
 25.1850 +     * last bit of the Register Address.
 25.1851 +     */
 25.1852 +    e1000_raise_mdi_clk(hw, &ctrl);
 25.1853 +    e1000_lower_mdi_clk(hw, &ctrl);
 25.1854 +
 25.1855 +    for(data = 0, i = 0; i < 16; i++) {
 25.1856 +        data = data << 1;
 25.1857 +        e1000_raise_mdi_clk(hw, &ctrl);
 25.1858 +        ctrl = E1000_READ_REG(hw, CTRL);
 25.1859 +        /* Check to see if we shifted in a "1". */
 25.1860 +        if(ctrl & E1000_CTRL_MDIO) data |= 1;
 25.1861 +        e1000_lower_mdi_clk(hw, &ctrl);
 25.1862 +    }
 25.1863 +
 25.1864 +    e1000_raise_mdi_clk(hw, &ctrl);
 25.1865 +    e1000_lower_mdi_clk(hw, &ctrl);
 25.1866 +
 25.1867 +    return data;
 25.1868 +}
 25.1869 +
 25.1870 +/*****************************************************************************
 25.1871 +* Reads the value from a PHY register
 25.1872 +*
 25.1873 +* hw - Struct containing variables accessed by shared code
 25.1874 +* reg_addr - address of the PHY register to read
 25.1875 +******************************************************************************/
 25.1876 +int32_t
 25.1877 +e1000_read_phy_reg(struct e1000_hw *hw,
 25.1878 +                   uint32_t reg_addr,
 25.1879 +                   uint16_t *phy_data)
 25.1880 +{
 25.1881 +    uint32_t i;
 25.1882 +    uint32_t mdic = 0;
 25.1883 +    const uint32_t phy_addr = 1;
 25.1884 +
 25.1885 +    DEBUGFUNC("e1000_read_phy_reg");
 25.1886 +
 25.1887 +    if(reg_addr > MAX_PHY_REG_ADDRESS) {
 25.1888 +        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
 25.1889 +        return -E1000_ERR_PARAM;
 25.1890 +    }
 25.1891 +
 25.1892 +    if(hw->mac_type > e1000_82543) {
 25.1893 +        /* Set up Op-code, Phy Address, and register address in the MDI
 25.1894 +         * Control register.  The MAC will take care of interfacing with the
 25.1895 +         * PHY to retrieve the desired data.
 25.1896 +         */
 25.1897 +        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
 25.1898 +                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
 25.1899 +                (E1000_MDIC_OP_READ));
 25.1900 +
 25.1901 +        E1000_WRITE_REG(hw, MDIC, mdic);
 25.1902 +
 25.1903 +        /* Poll the ready bit to see if the MDI read completed */
 25.1904 +        for(i = 0; i < 64; i++) {
 25.1905 +            udelay(10);
 25.1906 +            mdic = E1000_READ_REG(hw, MDIC);
 25.1907 +            if(mdic & E1000_MDIC_READY) break;
 25.1908 +        }
 25.1909 +        if(!(mdic & E1000_MDIC_READY)) {
 25.1910 +            DEBUGOUT("MDI Read did not complete\n");
 25.1911 +            return -E1000_ERR_PHY;
 25.1912 +        }
 25.1913 +        if(mdic & E1000_MDIC_ERROR) {
 25.1914 +            DEBUGOUT("MDI Error\n");
 25.1915 +            return -E1000_ERR_PHY;
 25.1916 +        }
 25.1917 +        *phy_data = (uint16_t) mdic;
 25.1918 +    } else {
 25.1919 +        /* We must first send a preamble through the MDIO pin to signal the
 25.1920 +         * beginning of an MII instruction.  This is done by sending 32
 25.1921 +         * consecutive "1" bits.
 25.1922 +         */
 25.1923 +        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
 25.1924 +
 25.1925 +        /* Now combine the next few fields that are required for a read
 25.1926 +         * operation.  We use this method instead of calling the
 25.1927 +         * e1000_shift_out_mdi_bits routine five different times. The format of
 25.1928 +         * a MII read instruction consists of a shift out of 14 bits and is
 25.1929 +         * defined as follows:
 25.1930 +         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
 25.1931 +         * followed by a shift in of 18 bits.  This first two bits shifted in
 25.1932 +         * are TurnAround bits used to avoid contention on the MDIO pin when a
 25.1933 +         * READ operation is performed.  These two bits are thrown away
 25.1934 +         * followed by a shift in of 16 bits which contains the desired data.
 25.1935 +         */
 25.1936 +        mdic = ((reg_addr) | (phy_addr << 5) | 
 25.1937 +                (PHY_OP_READ << 10) | (PHY_SOF << 12));
 25.1938 +
 25.1939 +        e1000_shift_out_mdi_bits(hw, mdic, 14);
 25.1940 +
 25.1941 +        /* Now that we've shifted out the read command to the MII, we need to
 25.1942 +         * "shift in" the 16-bit value (18 total bits) of the requested PHY
 25.1943 +         * register address.
 25.1944 +         */
 25.1945 +        *phy_data = e1000_shift_in_mdi_bits(hw);
 25.1946 +    }
 25.1947 +    return 0;
 25.1948 +}
 25.1949 +
 25.1950 +/******************************************************************************
 25.1951 +* Writes a value to a PHY register
 25.1952 +*
 25.1953 +* hw - Struct containing variables accessed by shared code
 25.1954 +* reg_addr - address of the PHY register to write
 25.1955 +* data - data to write to the PHY
 25.1956 +******************************************************************************/
 25.1957 +int32_t
 25.1958 +e1000_write_phy_reg(struct e1000_hw *hw,
 25.1959 +                    uint32_t reg_addr,
 25.1960 +                    uint16_t phy_data)
 25.1961 +{
 25.1962 +    uint32_t i;
 25.1963 +    uint32_t mdic = 0;
 25.1964 +    const uint32_t phy_addr = 1;
 25.1965 +
 25.1966 +    DEBUGFUNC("e1000_write_phy_reg");
 25.1967 +
 25.1968 +    if(reg_addr > MAX_PHY_REG_ADDRESS) {
 25.1969 +        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
 25.1970 +        return -E1000_ERR_PARAM;
 25.1971 +    }
 25.1972 +
 25.1973 +    if(hw->mac_type > e1000_82543) {
 25.1974 +        /* Set up Op-code, Phy Address, register address, and data intended
 25.1975 +         * for the PHY register in the MDI Control register.  The MAC will take
 25.1976 +         * care of interfacing with the PHY to send the desired data.
 25.1977 +         */
 25.1978 +        mdic = (((uint32_t) phy_data) |
 25.1979 +                (reg_addr << E1000_MDIC_REG_SHIFT) |
 25.1980 +                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
 25.1981 +                (E1000_MDIC_OP_WRITE));
 25.1982 +
 25.1983 +        E1000_WRITE_REG(hw, MDIC, mdic);
 25.1984 +
 25.1985 +        /* Poll the ready bit to see if the MDI read completed */
 25.1986 +        for(i = 0; i < 64; i++) {
 25.1987 +            udelay(10);
 25.1988 +            mdic = E1000_READ_REG(hw, MDIC);
 25.1989 +            if(mdic & E1000_MDIC_READY) break;
 25.1990 +        }
 25.1991 +        if(!(mdic & E1000_MDIC_READY)) {
 25.1992 +            DEBUGOUT("MDI Write did not complete\n");
 25.1993 +            return -E1000_ERR_PHY;
 25.1994 +        }
 25.1995 +    } else {
 25.1996 +        /* We'll need to use the SW defined pins to shift the write command
 25.1997 +         * out to the PHY. We first send a preamble to the PHY to signal the
 25.1998 +         * beginning of the MII instruction.  This is done by sending 32 
 25.1999 +         * consecutive "1" bits.
 25.2000 +         */
 25.2001 +        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
 25.2002 +
 25.2003 +        /* Now combine the remaining required fields that will indicate a 
 25.2004 +         * write operation. We use this method instead of calling the
 25.2005 +         * e1000_shift_out_mdi_bits routine for each field in the command. The
 25.2006 +         * format of a MII write instruction is as follows:
 25.2007 +         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
 25.2008 +         */
 25.2009 +        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
 25.2010 +                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
 25.2011 +        mdic <<= 16;
 25.2012 +        mdic |= (uint32_t) phy_data;
 25.2013 +
 25.2014 +        e1000_shift_out_mdi_bits(hw, mdic, 32);
 25.2015 +    }
 25.2016 +    return 0;
 25.2017 +}
 25.2018 +
 25.2019 +/******************************************************************************
 25.2020 +* Returns the PHY to the power-on reset state
 25.2021 +*
 25.2022 +* hw - Struct containing variables accessed by shared code
 25.2023 +******************************************************************************/
 25.2024 +void
 25.2025 +e1000_phy_hw_reset(struct e1000_hw *hw)
 25.2026 +{
 25.2027 +    uint32_t ctrl;
 25.2028 +    uint32_t ctrl_ext;
 25.2029 +
 25.2030 +    DEBUGFUNC("e1000_phy_hw_reset");
 25.2031 +
 25.2032 +    DEBUGOUT("Resetting Phy...\n");
 25.2033 +
 25.2034 +    if(hw->mac_type > e1000_82543) {
 25.2035 +        /* Read the device control register and assert the E1000_CTRL_PHY_RST
 25.2036 +         * bit. Then, take it out of reset.
 25.2037 +         */
 25.2038 +        ctrl = E1000_READ_REG(hw, CTRL);
 25.2039 +        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
 25.2040 +        E1000_WRITE_FLUSH(hw);
 25.2041 +        msec_delay(10);
 25.2042 +        E1000_WRITE_REG(hw, CTRL, ctrl);
 25.2043 +        E1000_WRITE_FLUSH(hw);
 25.2044 +    } else {
 25.2045 +        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
 25.2046 +         * bit to put the PHY into reset. Then, take it out of reset.
 25.2047 +         */
 25.2048 +        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
 25.2049 +        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
 25.2050 +        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
 25.2051 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
 25.2052 +        E1000_WRITE_FLUSH(hw);
 25.2053 +        msec_delay(10);
 25.2054 +        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
 25.2055 +        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
 25.2056 +        E1000_WRITE_FLUSH(hw);
 25.2057 +    }
 25.2058 +    udelay(150);
 25.2059 +}
 25.2060 +
 25.2061 +/******************************************************************************
 25.2062 +* Resets the PHY
 25.2063 +*
 25.2064 +* hw - Struct containing variables accessed by shared code
 25.2065 +*
 25.2066 +* Sets bit 15 of the MII Control regiser
 25.2067 +******************************************************************************/
 25.2068 +int32_t
 25.2069 +e1000_phy_reset(struct e1000_hw *hw)
 25.2070 +{
 25.2071 +    uint16_t phy_data;
 25.2072 +
 25.2073 +    DEBUGFUNC("e1000_phy_reset");
 25.2074 +
 25.2075 +    if(e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
 25.2076 +        DEBUGOUT("PHY Read Error\n");
 25.2077 +        return -E1000_ERR_PHY;
 25.2078 +    }
 25.2079 +    phy_data |= MII_CR_RESET;
 25.2080 +    if(e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
 25.2081 +        DEBUGOUT("PHY Write Error\n");
 25.2082 +        return -E1000_ERR_PHY;
 25.2083 +    }
 25.2084 +    udelay(1);
 25.2085 +    return 0;
 25.2086 +}
 25.2087 +
 25.2088 +/******************************************************************************
 25.2089 +* Probes the expected PHY address for known PHY IDs
 25.2090 +*
 25.2091 +* hw - Struct containing variables accessed by shared code
 25.2092 +******************************************************************************/
 25.2093 +int32_t
 25.2094 +e1000_detect_gig_phy(struct e1000_hw *hw)
 25.2095 +{
 25.2096 +    uint16_t phy_id_high, phy_id_low;
 25.2097 +    boolean_t match = FALSE;
 25.2098 +
 25.2099 +    DEBUGFUNC("e1000_detect_gig_phy");
 25.2100 +
 25.2101 +    /* Read the PHY ID Registers to identify which PHY is onboard. */
 25.2102 +    if(e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
 25.2103 +        DEBUGOUT("PHY Read Error\n");
 25.2104 +        return -E1000_ERR_PHY;
 25.2105 +    }
 25.2106 +    hw->phy_id = (uint32_t) (phy_id_high << 16);
 25.2107 +    udelay(2);
 25.2108 +    if(e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
 25.2109 +        DEBUGOUT("PHY Read Error\n");
 25.2110 +        return -E1000_ERR_PHY;
 25.2111 +    }
 25.2112 +    hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
 25.2113 +    hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
 25.2114 +
 25.2115 +    switch(hw->mac_type) {
 25.2116 +    case e1000_82543:
 25.2117 +        if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
 25.2118 +        break;
 25.2119 +    case e1000_82544:
 25.2120 +        if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
 25.2121 +        break;
 25.2122 +    case e1000_82540:
 25.2123 +    case e1000_82545:
 25.2124 +    case e1000_82546:
 25.2125 +        if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
 25.2126 +        break;
 25.2127 +    default:
 25.2128 +        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
 25.2129 +        return -E1000_ERR_CONFIG;
 25.2130 +    }
 25.2131 +    if(match) {
 25.2132 +        DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
 25.2133 +        return 0;
 25.2134 +    }
 25.2135 +    DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
 25.2136 +    return -E1000_ERR_PHY;
 25.2137 +}
 25.2138 +
 25.2139 +/******************************************************************************
 25.2140 +* Resets the PHY's DSP
 25.2141 +*
 25.2142 +* hw - Struct containing variables accessed by shared code
 25.2143 +******************************************************************************/
 25.2144 +static int32_t
 25.2145 +e1000_phy_reset_dsp(struct e1000_hw *hw)
 25.2146 +{
 25.2147 +    int32_t ret_val = -E1000_ERR_PHY;
 25.2148 +    DEBUGFUNC("e1000_phy_reset_dsp");
 25.2149 +    
 25.2150 +    do {
 25.2151 +        if(e1000_write_phy_reg(hw, 29, 0x001d) < 0) break;
 25.2152 +        if(e1000_write_phy_reg(hw, 30, 0x00c1) < 0) break;
 25.2153 +        if(e1000_write_phy_reg(hw, 30, 0x0000) < 0) break;
 25.2154 +        ret_val = 0;
 25.2155 +    } while(0);
 25.2156 +
 25.2157 +    if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
 25.2158 +    return ret_val;
 25.2159 +}
 25.2160 +
 25.2161 +/******************************************************************************
 25.2162 +* Get PHY information from various PHY registers
 25.2163 +*
 25.2164 +* hw - Struct containing variables accessed by shared code
 25.2165 +* phy_info - PHY information structure
 25.2166 +******************************************************************************/
 25.2167 +int32_t
 25.2168 +e1000_phy_get_info(struct e1000_hw *hw,
 25.2169 +                   struct e1000_phy_info *phy_info)
 25.2170 +{
 25.2171 +    int32_t ret_val = -E1000_ERR_PHY;
 25.2172 +    uint16_t phy_data;
 25.2173 +
 25.2174 +    DEBUGFUNC("e1000_phy_get_info");
 25.2175 +
 25.2176 +    phy_info->cable_length = e1000_cable_length_undefined;
 25.2177 +    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
 25.2178 +    phy_info->cable_polarity = e1000_rev_polarity_undefined;
 25.2179 +    phy_info->polarity_correction = e1000_polarity_reversal_undefined;
 25.2180 +    phy_info->mdix_mode = e1000_auto_x_mode_undefined;
 25.2181 +    phy_info->local_rx = e1000_1000t_rx_status_undefined;
 25.2182 +    phy_info->remote_rx = e1000_1000t_rx_status_undefined;
 25.2183 +
 25.2184 +    if(hw->media_type != e1000_media_type_copper) {
 25.2185 +        DEBUGOUT("PHY info is only valid for copper media\n");
 25.2186 +        return -E1000_ERR_CONFIG;
 25.2187 +    }
 25.2188 +
 25.2189 +    do {
 25.2190 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
 25.2191 +        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
 25.2192 +        if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
 25.2193 +            DEBUGOUT("PHY info is only valid if link is up\n");
 25.2194 +            return -E1000_ERR_CONFIG;
 25.2195 +        }
 25.2196 +
 25.2197 +        if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
 25.2198 +            break;
 25.2199 +        phy_info->extended_10bt_distance =
 25.2200 +            (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
 25.2201 +            M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
 25.2202 +        phy_info->polarity_correction =
 25.2203 +            (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
 25.2204 +            M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
 25.2205 +
 25.2206 +        if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
 25.2207 +            break;
 25.2208 +        phy_info->cable_polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
 25.2209 +            M88E1000_PSSR_REV_POLARITY_SHIFT;
 25.2210 +        phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
 25.2211 +            M88E1000_PSSR_MDIX_SHIFT;
 25.2212 +        if(phy_data & M88E1000_PSSR_1000MBS) {
 25.2213 +            /* Cable Length Estimation and Local/Remote Receiver Informatoion
 25.2214 +             * are only valid at 1000 Mbps
 25.2215 +             */
 25.2216 +            phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
 25.2217 +                                      M88E1000_PSSR_CABLE_LENGTH_SHIFT);
 25.2218 +            if(e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0) 
 25.2219 +                break;
 25.2220 +            phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
 25.2221 +                SR_1000T_LOCAL_RX_STATUS_SHIFT;
 25.2222 +            phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
 25.2223 +                SR_1000T_REMOTE_RX_STATUS_SHIFT;
 25.2224 +        }
 25.2225 +        ret_val = 0;
 25.2226 +    } while(0);
 25.2227 +
 25.2228 +    if(ret_val < 0) DEBUGOUT("PHY Read Error\n");
 25.2229 +    return ret_val;
 25.2230 +}
 25.2231 +
 25.2232 +int32_t
 25.2233 +e1000_validate_mdi_setting(struct e1000_hw *hw)
 25.2234 +{
 25.2235 +    DEBUGFUNC("e1000_validate_mdi_settings");
 25.2236 +
 25.2237 +    if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
 25.2238 +        DEBUGOUT("Invalid MDI setting detected\n");
 25.2239 +        hw->mdix = 1;
 25.2240 +        return -E1000_ERR_CONFIG;
 25.2241 +    }
 25.2242 +    return 0;
 25.2243 +}
 25.2244 +
 25.2245 +/******************************************************************************
 25.2246 + * Raises the EEPROM's clock input.
 25.2247 + *
 25.2248 + * hw - Struct containing variables accessed by shared code
 25.2249 + * eecd - EECD's current value
 25.2250 + *****************************************************************************/
 25.2251 +static void
 25.2252 +e1000_raise_ee_clk(struct e1000_hw *hw,
 25.2253 +                   uint32_t *eecd)
 25.2254 +{
 25.2255 +    /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 25.2256 +     * wait <delay> microseconds.
 25.2257 +     */
 25.2258 +    *eecd = *eecd | E1000_EECD_SK;
 25.2259 +    E1000_WRITE_REG(hw, EECD, *eecd);
 25.2260 +    E1000_WRITE_FLUSH(hw);
 25.2261 +    udelay(50);
 25.2262 +}
 25.2263 +
 25.2264 +/******************************************************************************
 25.2265 + * Lowers the EEPROM's clock input.
 25.2266 + *
 25.2267 + * hw - Struct containing variables accessed by shared code 
 25.2268 + * eecd - EECD's current value
 25.2269 + *****************************************************************************/
 25.2270 +static void
 25.2271 +e1000_lower_ee_clk(struct e1000_hw *hw,
 25.2272 +                   uint32_t *eecd)
 25.2273 +{
 25.2274 +    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
 25.2275 +     * wait 50 microseconds. 
 25.2276 +     */
 25.2277 +    *eecd = *eecd & ~E1000_EECD_SK;
 25.2278 +    E1000_WRITE_REG(hw, EECD, *eecd);
 25.2279 +    E1000_WRITE_FLUSH(hw);
 25.2280 +    udelay(50);
 25.2281 +}
 25.2282 +
 25.2283 +/******************************************************************************
 25.2284 + * Shift data bits out to the EEPROM.
 25.2285 + *
 25.2286 + * hw - Struct containing variables accessed by shared code
 25.2287 + * data - data to send to the EEPROM
 25.2288 + * count - number of bits to shift out
 25.2289 + *****************************************************************************/
 25.2290 +static void
 25.2291 +e1000_shift_out_ee_bits(struct e1000_hw *hw,
 25.2292 +                        uint16_t data,
 25.2293 +                        uint16_t count)
 25.2294 +{
 25.2295 +    uint32_t eecd;
 25.2296 +    uint32_t mask;
 25.2297 +
 25.2298 +    /* We need to shift "count" bits out to the EEPROM. So, value in the
 25.2299 +     * "data" parameter will be shifted out to the EEPROM one bit at a time.
 25.2300 +     * In order to do this, "data" must be broken down into bits. 
 25.2301 +     */
 25.2302 +    mask = 0x01 << (count - 1);
 25.2303 +    eecd = E1000_READ_REG(hw, EECD);
 25.2304 +    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 25.2305 +    do {
 25.2306 +        /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 25.2307 +         * and then raising and then lowering the clock (the SK bit controls
 25.2308 +         * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 25.2309 +         * by setting "DI" to "0" and then raising and then lowering the clock.
 25.2310 +         */
 25.2311 +        eecd &= ~E1000_EECD_DI;
 25.2312 +
 25.2313 +        if(data & mask)
 25.2314 +            eecd |= E1000_EECD_DI;
 25.2315 +
 25.2316 +        E1000_WRITE_REG(hw, EECD, eecd);
 25.2317 +        E1000_WRITE_FLUSH(hw);
 25.2318 +
 25.2319 +        udelay(50);
 25.2320 +
 25.2321 +        e1000_raise_ee_clk(hw, &eecd);
 25.2322 +        e1000_lower_ee_clk(hw, &eecd);
 25.2323 +
 25.2324 +        mask = mask >> 1;
 25.2325 +
 25.2326 +    } while(mask);
 25.2327 +
 25.2328 +    /* We leave the "DI" bit set to "0" when we leave this routine. */
 25.2329 +    eecd &= ~E1000_EECD_DI;
 25.2330 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2331 +}
 25.2332 +
 25.2333 +/******************************************************************************
 25.2334 + * Shift data bits in from the EEPROM
 25.2335 + *
 25.2336 + * hw - Struct containing variables accessed by shared code
 25.2337 + *****************************************************************************/
 25.2338 +static uint16_t
 25.2339 +e1000_shift_in_ee_bits(struct e1000_hw *hw)
 25.2340 +{
 25.2341 +    uint32_t eecd;
 25.2342 +    uint32_t i;
 25.2343 +    uint16_t data;
 25.2344 +
 25.2345 +    /* In order to read a register from the EEPROM, we need to shift 'count'
 25.2346 +     * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 25.2347 +     * input to the EEPROM (setting the SK bit), and then reading the value of
 25.2348 +     * the "DO" bit.  During this "shifting in" process the "DI" bit should
 25.2349 +     * always be clear.
 25.2350 +     */
 25.2351 +
 25.2352 +    eecd = E1000_READ_REG(hw, EECD);
 25.2353 +
 25.2354 +    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 25.2355 +    data = 0;
 25.2356 +
 25.2357 +    for(i = 0; i < 16; i++) {
 25.2358 +        data = data << 1;
 25.2359 +        e1000_raise_ee_clk(hw, &eecd);
 25.2360 +
 25.2361 +        eecd = E1000_READ_REG(hw, EECD);
 25.2362 +
 25.2363 +        eecd &= ~(E1000_EECD_DI);
 25.2364 +        if(eecd & E1000_EECD_DO)
 25.2365 +            data |= 1;
 25.2366 +
 25.2367 +        e1000_lower_ee_clk(hw, &eecd);
 25.2368 +    }
 25.2369 +
 25.2370 +    return data;
 25.2371 +}
 25.2372 +
 25.2373 +/******************************************************************************
 25.2374 + * Prepares EEPROM for access
 25.2375 + *
 25.2376 + * hw - Struct containing variables accessed by shared code
 25.2377 + *
 25.2378 + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
 25.2379 + * function should be called before issuing a command to the EEPROM.
 25.2380 + *****************************************************************************/
 25.2381 +static void
 25.2382 +e1000_setup_eeprom(struct e1000_hw *hw)
 25.2383 +{
 25.2384 +    uint32_t eecd;
 25.2385 +
 25.2386 +    eecd = E1000_READ_REG(hw, EECD);
 25.2387 +
 25.2388 +    /* Clear SK and DI */
 25.2389 +    eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
 25.2390 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2391 +
 25.2392 +    /* Set CS */
 25.2393 +    eecd |= E1000_EECD_CS;
 25.2394 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2395 +}
 25.2396 +
 25.2397 +/******************************************************************************
 25.2398 + * Returns EEPROM to a "standby" state
 25.2399 + * 
 25.2400 + * hw - Struct containing variables accessed by shared code
 25.2401 + *****************************************************************************/
 25.2402 +static void
 25.2403 +e1000_standby_eeprom(struct e1000_hw *hw)
 25.2404 +{
 25.2405 +    uint32_t eecd;
 25.2406 +
 25.2407 +    eecd = E1000_READ_REG(hw, EECD);
 25.2408 +
 25.2409 +    /* Deselct EEPROM */
 25.2410 +    eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 25.2411 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2412 +    E1000_WRITE_FLUSH(hw);
 25.2413 +    udelay(50);
 25.2414 +
 25.2415 +    /* Clock high */
 25.2416 +    eecd |= E1000_EECD_SK;
 25.2417 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2418 +    E1000_WRITE_FLUSH(hw);
 25.2419 +    udelay(50);
 25.2420 +
 25.2421 +    /* Select EEPROM */
 25.2422 +    eecd |= E1000_EECD_CS;
 25.2423 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2424 +    E1000_WRITE_FLUSH(hw);
 25.2425 +    udelay(50);
 25.2426 +
 25.2427 +    /* Clock low */
 25.2428 +    eecd &= ~E1000_EECD_SK;
 25.2429 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2430 +    E1000_WRITE_FLUSH(hw);
 25.2431 +    udelay(50);
 25.2432 +}
 25.2433 +
 25.2434 +/******************************************************************************
 25.2435 + * Raises then lowers the EEPROM's clock pin
 25.2436 + *
 25.2437 + * hw - Struct containing variables accessed by shared code
 25.2438 + *****************************************************************************/
 25.2439 +static void
 25.2440 +e1000_clock_eeprom(struct e1000_hw *hw)
 25.2441 +{
 25.2442 +    uint32_t eecd;
 25.2443 +
 25.2444 +    eecd = E1000_READ_REG(hw, EECD);
 25.2445 +
 25.2446 +    /* Rising edge of clock */
 25.2447 +    eecd |= E1000_EECD_SK;
 25.2448 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2449 +    E1000_WRITE_FLUSH(hw);
 25.2450 +    udelay(50);
 25.2451 +
 25.2452 +    /* Falling edge of clock */
 25.2453 +    eecd &= ~E1000_EECD_SK;
 25.2454 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2455 +    E1000_WRITE_FLUSH(hw);
 25.2456 +    udelay(50);
 25.2457 +}
 25.2458 +
 25.2459 +/******************************************************************************
 25.2460 + * Terminates a command by lowering the EEPROM's chip select pin
 25.2461 + *
 25.2462 + * hw - Struct containing variables accessed by shared code
 25.2463 + *****************************************************************************/
 25.2464 +static void
 25.2465 +e1000_cleanup_eeprom(struct e1000_hw *hw)
 25.2466 +{
 25.2467 +    uint32_t eecd;
 25.2468 +
 25.2469 +    eecd = E1000_READ_REG(hw, EECD);
 25.2470 +
 25.2471 +    eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 25.2472 +
 25.2473 +    E1000_WRITE_REG(hw, EECD, eecd);
 25.2474 +
 25.2475 +    e1000_clock_eeprom(hw);
 25.2476 +}
 25.2477 +
 25.2478 +/******************************************************************************
 25.2479 + * Reads a 16 bit word from the EEPROM.
 25.2480 + *
 25.2481 + * hw - Struct containing variables accessed by shared code
 25.2482 + * offset - offset of  word in the EEPROM to read
 25.2483 + * data - word read from the EEPROM 
 25.2484 + *****************************************************************************/
 25.2485 +int32_t
 25.2486 +e1000_read_eeprom(struct e1000_hw *hw,
 25.2487 +                  uint16_t offset,
 25.2488 +                  uint16_t *data)
 25.2489 +{
 25.2490 +    uint32_t eecd;
 25.2491 +    uint32_t i = 0;
 25.2492 +    boolean_t large_eeprom = FALSE;
 25.2493 +
 25.2494 +    DEBUGFUNC("e1000_read_eeprom");
 25.2495 +
 25.2496 +    /* Request EEPROM Access */
 25.2497 +    if(hw->mac_type > e1000_82544) {
 25.2498 +        eecd = E1000_READ_REG(hw, EECD);
 25.2499 +        if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
 25.2500 +        eecd |= E1000_EECD_REQ;
 25.2501 +        E1000_WRITE_REG(hw, EECD, eecd);
 25.2502 +        eecd = E1000_READ_REG(hw, EECD);
 25.2503 +        while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
 25.2504 +            i++;
 25.2505 +            udelay(5);
 25.2506 +            eecd = E1000_READ_REG(hw, EECD);
 25.2507 +        }
 25.2508 +        if(!(eecd & E1000_EECD_GNT)) {
 25.2509 +            eecd &= ~E1000_EECD_REQ;
 25.2510 +            E1000_WRITE_REG(hw, EECD, eecd);
 25.2511 +            DEBUGOUT("Could not acquire EEPROM grant\n");
 25.2512 +            return -E1000_ERR_EEPROM;
 25.2513 +        }
 25.2514 +    }
 25.2515 +
 25.2516 +    /*  Prepare the EEPROM for reading  */
 25.2517 +    e1000_setup_eeprom(hw);
 25.2518 +
 25.2519 +    /*  Send the READ command (opcode + addr)  */
 25.2520 +    e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
 25.2521 +    if(large_eeprom) {
 25.2522 +        /* If we have a 256 word EEPROM, there are 8 address bits */
 25.2523 +        e1000_shift_out_ee_bits(hw, offset, 8);
 25.2524 +    } else {
 25.2525 +        /* If we have a 64 word EEPROM, there are 6 address bits */
 25.2526 +        e1000_shift_out_ee_bits(hw, offset, 6);
 25.2527 +    }
 25.2528 +
 25.2529 +    /* Read the data */
 25.2530 +    *data = e1000_shift_in_ee_bits(hw);
 25.2531 +
 25.2532 +    /* End this read operation */
 25.2533 +    e1000_standby_eeprom(hw);
 25.2534 +
 25.2535 +    /* Stop requesting EEPROM access */
 25.2536 +    if(hw->mac_type > e1000_82544) {
 25.2537 +        eecd = E1000_READ_REG(hw, EECD);
 25.2538 +        eecd &= ~E1000_EECD_REQ;
 25.2539 +        E1000_WRITE_REG(hw, EECD, eecd);
 25.2540 +    }
 25.2541 +
 25.2542 +    return 0;
 25.2543 +}
 25.2544 +
 25.2545 +/******************************************************************************
 25.2546 + * Verifies that the EEPROM has a valid checksum
 25.2547 + * 
 25.2548 + * hw - Struct containing variables accessed by shared code
 25.2549 + *
 25.2550 + * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 25.2551 + * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 25.2552 + * valid.
 25.2553 + *****************************************************************************/
 25.2554 +int32_t
 25.2555 +e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 25.2556 +{
 25.2557 +    uint16_t checksum = 0;
 25.2558 +    uint16_t i, eeprom_data;
 25.2559 +
 25.2560 +    DEBUGFUNC("e1000_validate_eeprom_checksum");
 25.2561 +
 25.2562 +    for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
 25.2563 +        if(e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
 25.2564 +            DEBUGOUT("EEPROM Read Error\n");
 25.2565 +            return -E1000_ERR_EEPROM;
 25.2566 +        }
 25.2567 +        checksum += eeprom_data;
 25.2568 +    }
 25.2569 +
 25.2570 +    if(checksum == (uint16_t) EEPROM_SUM) {
 25.2571 +        return 0;
 25.2572 +    } else {
 25.2573 +        DEBUGOUT("EEPROM Checksum Invalid\n");    
 25.2574 +        return -E1000_ERR_EEPROM;
 25.2575 +    }
 25.2576 +}
 25.2577 +
 25.2578 +/******************************************************************************
 25.2579 + * Calculates the EEPROM checksum and writes it to the EEPROM
 25.2580 + *
 25.2581 + * hw - Struct containing variables accessed by shared code
 25.2582 + *
 25.2583 + * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
 25.2584 + * Writes the difference to word offset 63 of the EEPROM.
 25.2585 + *****************************************************************************/
 25.2586 +int32_t
 25.2587 +e1000_update_eeprom_checksum(struct e1000_hw *hw)
 25.2588 +{
 25.2589 +    uint16_t checksum = 0;
 25.2590 +    uint16_t i, eeprom_data;
 25.2591 +
 25.2592 +    DEBUGFUNC("e1000_update_eeprom_checksum");
 25.2593 +
 25.2594 +    for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
 25.2595 +        if(e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
 25.2596 +            DEBUGOUT("EEPROM Read Error\n");
 25.2597 +            return -E1000_ERR_EEPROM;
 25.2598 +        }
 25.2599 +        checksum += eeprom_data;
 25.2600 +    }
 25.2601 +    checksum = (uint16_t) EEPROM_SUM - checksum;
 25.2602 +    if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum) < 0) {
 25.2603 +        DEBUGOUT("EEPROM Write Error\n");
 25.2604 +        return -E1000_ERR_EEPROM;
 25.2605 +    }
 25.2606 +    return 0;
 25.2607 +}
 25.2608 +
 25.2609 +/******************************************************************************
 25.2610 + * Writes a 16 bit word to a given offset in the EEPROM.
 25.2611 + *
 25.2612 + * hw - Struct containing variables accessed by shared code
 25.2613 + * offset - offset within the EEPROM to be written to
 25.2614 + * data - 16 bit word to be writen to the EEPROM
 25.2615 + *
 25.2616 + * If e1000_update_eeprom_checksum is not called after this function, the 
 25.2617 + * EEPROM will most likely contain an invalid checksum.
 25.2618 + *****************************************************************************/
 25.2619 +int32_t
 25.2620 +e1000_write_eeprom(struct e1000_hw *hw,
 25.2621 +                   uint16_t offset,
 25.2622 +                   uint16_t data)
 25.2623 +{
 25.2624 +    uint32_t eecd;
 25.2625 +    uint32_t i = 0;
 25.2626 +    int32_t status = 0;
 25.2627 +    boolean_t large_eeprom = FALSE;
 25.2628 +
 25.2629 +    DEBUGFUNC("e1000_write_eeprom");
 25.2630 +
 25.2631 +    /* Request EEPROM Access */
 25.2632 +    if(hw->mac_type > e1000_82544) {
 25.2633 +        eecd = E1000_READ_REG(hw, EECD);
 25.2634 +        if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
 25.2635 +        eecd |= E1000_EECD_REQ;
 25.2636 +        E1000_WRITE_REG(hw, EECD, eecd);
 25.2637 +        eecd = E1000_READ_REG(hw, EECD);
 25.2638 +        while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
 25.2639 +            i++;
 25.2640 +            udelay(5);
 25.2641 +            eecd = E1000_READ_REG(hw, EECD);
 25.2642 +        }
 25.2643 +        if(!(eecd & E1000_EECD_GNT)) {
 25.2644 +            eecd &= ~E1000_EECD_REQ;
 25.2645 +            E1000_WRITE_REG(hw, EECD, eecd);
 25.2646 +            DEBUGOUT("Could not acquire EEPROM grant\n");
 25.2647 +            return -E1000_ERR_EEPROM;
 25.2648 +        }
 25.2649 +    }
 25.2650 +
 25.2651 +    /* Prepare the EEPROM for writing  */
 25.2652 +    e1000_setup_eeprom(hw);
 25.2653 +
 25.2654 +    /* Send the 9-bit (or 11-bit on large EEPROM) EWEN (write enable) command
 25.2655 +     * to the EEPROM (5-bit opcode plus 4/6-bit dummy). This puts the EEPROM
 25.2656 +     * into write/erase mode. 
 25.2657 +     */
 25.2658 +    e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5);
 25.2659 +    if(large_eeprom) 
 25.2660 +        e1000_shift_out_ee_bits(hw, 0, 6);
 25.2661 +    else
 25.2662 +        e1000_shift_out_ee_bits(hw, 0, 4);
 25.2663 +
 25.2664 +    /* Prepare the EEPROM */
 25.2665 +    e1000_standby_eeprom(hw);
 25.2666 +
 25.2667 +    /* Send the Write command (3-bit opcode + addr) */
 25.2668 +    e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3);
 25.2669 +    if(large_eeprom) 
 25.2670 +        /* If we have a 256 word EEPROM, there are 8 address bits */
 25.2671 +        e1000_shift_out_ee_bits(hw, offset, 8);
 25.2672 +    else
 25.2673 +        /* If we have a 64 word EEPROM, there are 6 address bits */
 25.2674 +        e1000_shift_out_ee_bits(hw, offset, 6);
 25.2675 +
 25.2676 +    /* Send the data */
 25.2677 +    e1000_shift_out_ee_bits(hw, data, 16);
 25.2678 +
 25.2679 +    /* Toggle the CS line.  This in effect tells to EEPROM to actually execute 
 25.2680 +     * the command in question.
 25.2681 +     */
 25.2682 +    e1000_standby_eeprom(hw);
 25.2683 +
 25.2684 +    /* Now read DO repeatedly until is high (equal to '1').  The EEEPROM will
 25.2685 +     * signal that the command has been completed by raising the DO signal.
 25.2686 +     * If DO does not go high in 10 milliseconds, then error out.
 25.2687 +     */
 25.2688 +    for(i = 0; i < 200; i++) {
 25.2689 +        eecd = E1000_READ_REG(hw, EECD);
 25.2690 +        if(eecd & E1000_EECD_DO) break;
 25.2691 +        udelay(50);
 25.2692 +    }
 25.2693 +    if(i == 200) {
 25.2694 +        DEBUGOUT("EEPROM Write did not complete\n");
 25.2695 +        status = -E1000_ERR_EEPROM;
 25.2696 +    }
 25.2697 +
 25.2698 +    /* Recover from write */
 25.2699 +    e1000_standby_eeprom(hw);
 25.2700 +
 25.2701 +    /* Send the 9-bit (or 11-bit on large EEPROM) EWDS (write disable) command
 25.2702 +     * to the EEPROM (5-bit opcode plus 4/6-bit dummy). This takes the EEPROM
 25.2703 +     * out of write/erase mode.
 25.2704 +     */
 25.2705 +    e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5);
 25.2706 +    if(large_eeprom) 
 25.2707 +        e1000_shift_out_ee_bits(hw, 0, 6);
 25.2708 +    else
 25.2709 +        e1000_shift_out_ee_bits(hw, 0, 4);
 25.2710 +
 25.2711 +    /* Done with writing */
 25.2712 +    e1000_cleanup_eeprom(hw);
 25.2713 +
 25.2714 +    /* Stop requesting EEPROM access */
 25.2715 +    if(hw->mac_type > e1000_82544) {
 25.2716 +        eecd = E1000_READ_REG(hw, EECD);
 25.2717 +        eecd &= ~E1000_EECD_REQ;
 25.2718 +        E1000_WRITE_REG(hw, EECD, eecd);
 25.2719 +    }
 25.2720 +
 25.2721 +    return status;
 25.2722 +}
 25.2723 +
 25.2724 +/******************************************************************************
 25.2725 + * Reads the adapter's part number from the EEPROM
 25.2726 + *
 25.2727 + * hw - Struct containing variables accessed by shared code
 25.2728 + * part_num - Adapter's part number
 25.2729 + *****************************************************************************/
 25.2730 +int32_t
 25.2731 +e1000_read_part_num(struct e1000_hw *hw,
 25.2732 +                    uint32_t *part_num)
 25.2733 +{
 25.2734 +    uint16_t offset = EEPROM_PBA_BYTE_1;
 25.2735 +    uint16_t eeprom_data;
 25.2736 +
 25.2737 +    DEBUGFUNC("e1000_read_part_num");
 25.2738 +
 25.2739 +    /* Get word 0 from EEPROM */
 25.2740 +    if(e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
 25.2741 +        DEBUGOUT("EEPROM Read Error\n");
 25.2742 +        return -E1000_ERR_EEPROM;
 25.2743 +    }
 25.2744 +    /* Save word 0 in upper half of part_num */
 25.2745 +    *part_num = (uint32_t) (eeprom_data << 16);
 25.2746 +
 25.2747 +    /* Get word 1 from EEPROM */
 25.2748 +    if(e1000_read_eeprom(hw, ++offset, &eeprom_data) < 0) {
 25.2749 +        DEBUGOUT("EEPROM Read Error\n");
 25.2750 +        return -E1000_ERR_EEPROM;
 25.2751 +    }
 25.2752 +    /* Save word 1 in lower half of part_num */
 25.2753 +    *part_num |= eeprom_data;
 25.2754 +
 25.2755 +    return 0;
 25.2756 +}
 25.2757 +
 25.2758 +/******************************************************************************
 25.2759 + * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
 25.2760 + * second function of dual function devices
 25.2761 + *
 25.2762 + * hw - Struct containing variables accessed by shared code
 25.2763 + *****************************************************************************/
 25.2764 +int32_t
 25.2765 +e1000_read_mac_addr(struct e1000_hw * hw)
 25.2766 +{
 25.2767 +    uint16_t offset;
 25.2768 +    uint16_t eeprom_data, i;
 25.2769 +
 25.2770 +    DEBUGFUNC("e1000_read_mac_addr");
 25.2771 +
 25.2772 +    for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
 25.2773 +        offset = i >> 1;
 25.2774 +        if(e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
 25.2775 +            DEBUGOUT("EEPROM Read Error\n");
 25.2776 +            return -E1000_ERR_EEPROM;
 25.2777 +        }
 25.2778 +        hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
 25.2779 +        hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
 25.2780 +    }
 25.2781 +    if((hw->mac_type == e1000_82546) &&
 25.2782 +       (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
 25.2783 +        if(hw->perm_mac_addr[5] & 0x01)
 25.2784 +            hw->perm_mac_addr[5] &= ~(0x01);
 25.2785 +        else
 25.2786 +            hw->perm_mac_addr[5] |= 0x01;
 25.2787 +    }
 25.2788 +    for(i = 0; i < NODE_ADDRESS_SIZE; i++)
 25.2789 +        hw->mac_addr[i] = hw->perm_mac_addr[i];
 25.2790 +    return 0;
 25.2791 +}
 25.2792 +
 25.2793 +/******************************************************************************
 25.2794 + * Initializes receive address filters.
 25.2795 + *
 25.2796 + * hw - Struct containing variables accessed by shared code 
 25.2797 + *
 25.2798 + * Places the MAC address in receive address register 0 and clears the rest
 25.2799 + * of the receive addresss registers. Clears the multicast table. Assumes
 25.2800 + * the receiver is in reset when the routine is called.
 25.2801 + *****************************************************************************/
 25.2802 +void
 25.2803 +e1000_init_rx_addrs(struct e1000_hw *hw)
 25.2804 +{
 25.2805 +    uint32_t i;
 25.2806 +    uint32_t addr_low;
 25.2807 +    uint32_t addr_high;
 25.2808 +
 25.2809 +    DEBUGFUNC("e1000_init_rx_addrs");
 25.2810 +
 25.2811 +    /* Setup the receive address. */
 25.2812 +    DEBUGOUT("Programming MAC Address into RAR[0]\n");
 25.2813 +    addr_low = (hw->mac_addr[0] |
 25.2814 +                (hw->mac_addr[1] << 8) |
 25.2815 +                (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
 25.2816 +
 25.2817 +    addr_high = (hw->mac_addr[4] |
 25.2818 +                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
 25.2819 +
 25.2820 +    E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
 25.2821 +    E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
 25.2822 +
 25.2823 +    /* Zero out the other 15 receive addresses. */
 25.2824 +    DEBUGOUT("Clearing RAR[1-15]\n");
 25.2825 +    for(i = 1; i < E1000_RAR_ENTRIES; i++) {
 25.2826 +        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
 25.2827 +        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
 25.2828 +    }
 25.2829 +}
 25.2830 +
 25.2831 +/******************************************************************************
 25.2832 + * Updates the MAC's list of multicast addresses.
 25.2833 + *
 25.2834 + * hw - Struct containing variables accessed by shared code
 25.2835 + * mc_addr_list - the list of new multicast addresses
 25.2836 + * mc_addr_count - number of addresses
 25.2837 + * pad - number of bytes between addresses in the list
 25.2838 + *
 25.2839 + * The given list replaces any existing list. Clears the last 15 receive
 25.2840 + * address registers and the multicast table. Uses receive address registers
 25.2841 + * for the first 15 multicast addresses, and hashes the rest into the 
 25.2842 + * multicast table.
 25.2843 + *****************************************************************************/
 25.2844 +void
 25.2845 +e1000_mc_addr_list_update(struct e1000_hw *hw,
 25.2846 +                          uint8_t *mc_addr_list,
 25.2847 +                          uint32_t mc_addr_count,
 25.2848 +                          uint32_t pad)
 25.2849 +{
 25.2850 +    uint32_t hash_value;
 25.2851 +    uint32_t i;
 25.2852 +    uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
 25.2853 +
 25.2854 +    DEBUGFUNC("e1000_mc_addr_list_update");
 25.2855 +
 25.2856 +    /* Set the new number of MC addresses that we are being requested to use. */
 25.2857 +    hw->num_mc_addrs = mc_addr_count;
 25.2858 +
 25.2859 +    /* Clear RAR[1-15] */
 25.2860 +    DEBUGOUT(" Clearing RAR[1-15]\n");
 25.2861 +    for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
 25.2862 +        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
 25.2863 +        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
 25.2864 +    }
 25.2865 +
 25.2866 +    /* Clear the MTA */
 25.2867 +    DEBUGOUT(" Clearing MTA\n");
 25.2868 +    for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
 25.2869 +        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
 25.2870 +    }
 25.2871 +
 25.2872 +    /* Add the new addresses */
 25.2873 +    for(i = 0; i < mc_addr_count; i++) {
 25.2874 +        DEBUGOUT(" Adding the multicast addresses:\n");
 25.2875 +        DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
 25.2876 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
 25.2877 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
 25.2878 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
 25.2879 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
 25.2880 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
 25.2881 +                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
 25.2882 +
 25.2883 +        hash_value = e1000_hash_mc_addr(hw,
 25.2884 +                                        mc_addr_list +
 25.2885 +                                        (i * (ETH_LENGTH_OF_ADDRESS + pad)));
 25.2886 +
 25.2887 +        DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
 25.2888 +
 25.2889 +        /* Place this multicast address in the RAR if there is room, *
 25.2890 +         * else put it in the MTA            
 25.2891 +         */
 25.2892 +        if(rar_used_count < E1000_RAR_ENTRIES) {
 25.2893 +            e1000_rar_set(hw,
 25.2894 +                          mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
 25.2895 +                          rar_used_count);
 25.2896 +            rar_used_count++;
 25.2897 +        } else {
 25.2898 +            e1000_mta_set(hw, hash_value);
 25.2899 +        }
 25.2900 +    }
 25.2901 +    DEBUGOUT("MC Update Complete\n");
 25.2902 +}
 25.2903 +
 25.2904 +/******************************************************************************
 25.2905 + * Hashes an address to determine its location in the multicast table
 25.2906 + *
 25.2907 + * hw - Struct containing variables accessed by shared code
 25.2908 + * mc_addr - the multicast address to hash 
 25.2909 + *****************************************************************************/
 25.2910 +uint32_t
 25.2911 +e1000_hash_mc_addr(struct e1000_hw *hw,
 25.2912 +                   uint8_t *mc_addr)
 25.2913 +{
 25.2914 +    uint32_t hash_value = 0;
 25.2915 +
 25.2916 +    /* The portion of the address that is used for the hash table is
 25.2917 +     * determined by the mc_filter_type setting.  
 25.2918 +     */
 25.2919 +    switch (hw->mc_filter_type) {
 25.2920 +    /* [0] [1] [2] [3] [4] [5]
 25.2921 +     * 01  AA  00  12  34  56
 25.2922 +     * LSB                 MSB
 25.2923 +     */
 25.2924 +    case 0:
 25.2925 +        /* [47:36] i.e. 0x563 for above example address */
 25.2926 +        hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
 25.2927 +        break;
 25.2928 +    case 1:
 25.2929 +        /* [46:35] i.e. 0xAC6 for above example address */
 25.2930 +        hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
 25.2931 +        break;
 25.2932 +    case 2:
 25.2933 +        /* [45:34] i.e. 0x5D8 for above example address */
 25.2934 +        hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
 25.2935 +        break;
 25.2936 +    case 3:
 25.2937 +        /* [43:32] i.e. 0x634 for above example address */
 25.2938 +        hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
 25.2939 +        break;
 25.2940 +    }
 25.2941 +
 25.2942 +    hash_value &= 0xFFF;
 25.2943 +    return hash_value;
 25.2944 +}
 25.2945 +
 25.2946 +/******************************************************************************
 25.2947 + * Sets the bit in the multicast table corresponding to the hash value.
 25.2948 + *
 25.2949 + * hw - Struct containing variables accessed by shared code
 25.2950 + * hash_value - Multicast address hash value
 25.2951 + *****************************************************************************/
 25.2952 +void
 25.2953 +e1000_mta_set(struct e1000_hw *hw,
 25.2954 +              uint32_t hash_value)
 25.2955 +{
 25.2956 +    uint32_t hash_bit, hash_reg;
 25.2957 +    uint32_t mta;
 25.2958 +    uint32_t temp;
 25.2959 +
 25.2960 +    /* The MTA is a register array of 128 32-bit registers.  
 25.2961 +     * It is treated like an array of 4096 bits.  We want to set 
 25.2962 +     * bit BitArray[hash_value]. So we figure out what register
 25.2963 +     * the bit is in, read it, OR in the new bit, then write
 25.2964 +     * back the new value.  The register is determined by the 
 25.2965 +     * upper 7 bits of the hash value and the bit within that 
 25.2966 +     * register are determined by the lower 5 bits of the value.
 25.2967 +     */
 25.2968 +    hash_reg = (hash_value >> 5) & 0x7F;
 25.2969 +    hash_bit = hash_value & 0x1F;
 25.2970 +
 25.2971 +    mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
 25.2972 +
 25.2973 +    mta |= (1 << hash_bit);
 25.2974 +
 25.2975 +    /* If we are on an 82544 and we are trying to write an odd offset
 25.2976 +     * in the MTA, save off the previous entry before writing and
 25.2977 +     * restore the old value after writing.
 25.2978 +     */
 25.2979 +    if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
 25.2980 +        temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
 25.2981 +        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
 25.2982 +        E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
 25.2983 +    } else {
 25.2984 +        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
 25.2985 +    }
 25.2986 +}
 25.2987 +
 25.2988 +/******************************************************************************
 25.2989 + * Puts an ethernet address into a receive address register.
 25.2990 + *
 25.2991 + * hw - Struct containing variables accessed by shared code
 25.2992 + * addr - Address to put into receive address register
 25.2993 + * index - Receive address register to write
 25.2994 + *****************************************************************************/
 25.2995 +void
 25.2996 +e1000_rar_set(struct e1000_hw *hw,
 25.2997 +              uint8_t *addr,
 25.2998 +              uint32_t index)
 25.2999 +{
 25.3000 +    uint32_t rar_low, rar_high;
 25.3001 +
 25.3002 +    /* HW expects these in little endian so we reverse the byte order
 25.3003 +     * from network order (big endian) to little endian              
 25.3004 +     */
 25.3005 +    rar_low = ((uint32_t) addr[0] |
 25.3006 +               ((uint32_t) addr[1] << 8) |
 25.3007 +               ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
 25.3008 +
 25.3009 +    rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
 25.3010 +
 25.3011 +    E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
 25.3012 +    E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
 25.3013 +}
 25.3014 +
 25.3015 +/******************************************************************************
 25.3016 + * Writes a value to the specified offset in the VLAN filter table.
 25.3017 + *
 25.3018 + * hw - Struct containing variables accessed by shared code
 25.3019 + * offset - Offset in VLAN filer table to write
 25.3020 + * value - Value to write into VLAN filter table
 25.3021 + *****************************************************************************/
 25.3022 +void
 25.3023 +e1000_write_vfta(struct e1000_hw *hw,
 25.3024 +                 uint32_t offset,
 25.3025 +                 uint32_t value)
 25.3026 +{
 25.3027 +    uint32_t temp;
 25.3028 +
 25.3029 +    if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
 25.3030 +        temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
 25.3031 +        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
 25.3032 +        E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
 25.3033 +    } else {
 25.3034 +        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
 25.3035 +    }
 25.3036 +}
 25.3037 +
 25.3038 +/******************************************************************************
 25.3039 + * Clears the VLAN filer table
 25.3040 + *
 25.3041 + * hw - Struct containing variables accessed by shared code
 25.3042 + *****************************************************************************/
 25.3043 +void
 25.3044 +e1000_clear_vfta(struct e1000_hw *hw)
 25.3045 +{
 25.3046 +    uint32_t offset;
 25.3047 +
 25.3048 +    for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
 25.3049 +        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
 25.3050 +}
 25.3051 +
 25.3052 +static int32_t
 25.3053 +e1000_id_led_init(struct e1000_hw * hw)
 25.3054 +{
 25.3055 +    uint32_t ledctl;
 25.3056 +    const uint32_t ledctl_mask = 0x000000FF;
 25.3057 +    const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
 25.3058 +    const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
 25.3059 +    uint16_t eeprom_data, i, temp;
 25.3060 +    const uint16_t led_mask = 0x0F;
 25.3061 +        
 25.3062 +    DEBUGFUNC("e1000_id_led_init");
 25.3063 +    
 25.3064 +    if(hw->mac_type < e1000_82540) {
 25.3065 +        /* Nothing to do */
 25.3066 +        return 0;
 25.3067 +    }
 25.3068 +    
 25.3069 +    ledctl = E1000_READ_REG(hw, LEDCTL);
 25.3070 +    hw->ledctl_default = ledctl;
 25.3071 +    hw->ledctl_mode1 = hw->ledctl_default;
 25.3072 +    hw->ledctl_mode2 = hw->ledctl_default;
 25.3073 +        
 25.3074 +    if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, &eeprom_data) < 0) {
 25.3075 +        DEBUGOUT("EEPROM Read Error\n");
 25.3076 +        return -E1000_ERR_EEPROM;
 25.3077 +    }
 25.3078 +    if((eeprom_data== ID_LED_RESERVED_0000) || 
 25.3079 +       (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
 25.3080 +    for(i = 0; i < 4; i++) {
 25.3081 +        temp = (eeprom_data >> (i << 2)) & led_mask;
 25.3082 +        switch(temp) {
 25.3083 +        case ID_LED_ON1_DEF2:
 25.3084 +        case ID_LED_ON1_ON2:
 25.3085 +        case ID_LED_ON1_OFF2:
 25.3086 +            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
 25.3087 +            hw->ledctl_mode1 |= ledctl_on << (i << 3);
 25.3088 +            break;
 25.3089 +        case ID_LED_OFF1_DEF2:
 25.3090 +        case ID_LED_OFF1_ON2:
 25.3091 +        case ID_LED_OFF1_OFF2:
 25.3092 +            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
 25.3093 +            hw->ledctl_mode1 |= ledctl_off << (i << 3);
 25.3094 +            break;
 25.3095 +        default:
 25.3096 +            /* Do nothing */
 25.3097 +            break;
 25.3098 +        }
 25.3099 +        switch(temp) {
 25.3100 +        case ID_LED_DEF1_ON2:
 25.3101 +        case ID_LED_ON1_ON2:
 25.3102 +        case ID_LED_OFF1_ON2:
 25.3103 +            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
 25.3104 +            hw->ledctl_mode2 |= ledctl_on << (i << 3);
 25.3105 +            break;
 25.3106 +        case ID_LED_DEF1_OFF2:
 25.3107 +        case ID_LED_ON1_OFF2:
 25.3108 +        case ID_LED_OFF1_OFF2:
 25.3109 +            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
 25.3110 +            hw->ledctl_mode2 |= ledctl_off << (i << 3);
 25.3111 +            break;
 25.3112 +        default:
 25.3113 +            /* Do nothing */
 25.3114 +            break;
 25.3115 +        }
 25.3116 +    }
 25.3117 +    return 0;
 25.3118 +}
 25.3119 +
 25.3120 +/******************************************************************************
 25.3121 + * Prepares SW controlable LED for use and saves the current state of the LED.
 25.3122 + *
 25.3123 + * hw - Struct containing variables accessed by shared code
 25.3124 + *****************************************************************************/
 25.3125 +int32_t
 25.3126 +e1000_setup_led(struct e1000_hw *hw)
 25.3127 +{
 25.3128 +    uint32_t ledctl;
 25.3129 + 
 25.3130 +    DEBUGFUNC("e1000_setup_led");
 25.3131 +   
 25.3132 +    switch(hw->device_id) {
 25.3133 +    case E1000_DEV_ID_82542:
 25.3134 +    case E1000_DEV_ID_82543GC_FIBER:
 25.3135 +    case E1000_DEV_ID_82543GC_COPPER:
 25.3136 +    case E1000_DEV_ID_82544EI_COPPER:
 25.3137 +    case E1000_DEV_ID_82544EI_FIBER:
 25.3138 +    case E1000_DEV_ID_82544GC_COPPER:
 25.3139 +    case E1000_DEV_ID_82544GC_LOM:
 25.3140 +        /* No setup necessary */
 25.3141 +        break;
 25.3142 +    case E1000_DEV_ID_82545EM_FIBER:
 25.3143 +    case E1000_DEV_ID_82546EB_FIBER:
 25.3144 +        ledctl = E1000_READ_REG(hw, LEDCTL);
 25.3145 +        /* Save current LEDCTL settings */
 25.3146 +        hw->ledctl_default = ledctl;
 25.3147 +        /* Turn off LED0 */
 25.3148 +        ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
 25.3149 +                    E1000_LEDCTL_LED0_BLINK | 
 25.3150 +                    E1000_LEDCTL_LED0_MODE_MASK);
 25.3151 +        ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
 25.3152 +        E1000_WRITE_REG(hw, LEDCTL, ledctl);
 25.3153 +        break;
 25.3154 +    case E1000_DEV_ID_82540EP:
 25.3155 +    case E1000_DEV_ID_82540EP_LOM:
 25.3156 +    case E1000_DEV_ID_82540EP_LP:
 25.3157 +    case E1000_DEV_ID_82540EM:
 25.3158 +    case E1000_DEV_ID_82540EM_LOM:
 25.3159 +    case E1000_DEV_ID_82545EM_COPPER:
 25.3160 +    case E1000_DEV_ID_82546EB_COPPER:
 25.3161 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
 25.3162 +        break;
 25.3163 +    default:
 25.3164 +        DEBUGOUT("Invalid device ID\n");
 25.3165 +        return -E1000_ERR_CONFIG;
 25.3166 +    }
 25.3167 +    return 0;
 25.3168 +}
 25.3169 +
 25.3170 +/******************************************************************************
 25.3171 + * Restores the saved state of the SW controlable LED.
 25.3172 + *
 25.3173 + * hw - Struct containing variables accessed by shared code
 25.3174 + *****************************************************************************/
 25.3175 +int32_t
 25.3176 +e1000_cleanup_led(struct e1000_hw *hw)
 25.3177 +{
 25.3178 +    DEBUGFUNC("e1000_cleanup_led");
 25.3179 +
 25.3180 +    switch(hw->device_id) {
 25.3181 +    case E1000_DEV_ID_82542:
 25.3182 +    case E1000_DEV_ID_82543GC_FIBER:
 25.3183 +    case E1000_DEV_ID_82543GC_COPPER:
 25.3184 +    case E1000_DEV_ID_82544EI_COPPER:
 25.3185 +    case E1000_DEV_ID_82544EI_FIBER:
 25.3186 +    case E1000_DEV_ID_82544GC_COPPER:
 25.3187 +    case E1000_DEV_ID_82544GC_LOM:
 25.3188 +        /* No cleanup necessary */
 25.3189 +        break;
 25.3190 +    case E1000_DEV_ID_82540EP:
 25.3191 +    case E1000_DEV_ID_82540EP_LOM:
 25.3192 +    case E1000_DEV_ID_82540EP_LP:
 25.3193 +    case E1000_DEV_ID_82540EM:
 25.3194 +    case E1000_DEV_ID_82540EM_LOM:
 25.3195 +    case E1000_DEV_ID_82545EM_COPPER:
 25.3196 +    case E1000_DEV_ID_82545EM_FIBER:
 25.3197 +    case E1000_DEV_ID_82546EB_COPPER:
 25.3198 +    case E1000_DEV_ID_82546EB_FIBER:
 25.3199 +        /* Restore LEDCTL settings */
 25.3200 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
 25.3201 +        break;
 25.3202 +    default:
 25.3203 +        DEBUGOUT("Invalid device ID\n");
 25.3204 +        return -E1000_ERR_CONFIG;
 25.3205 +    }
 25.3206 +    return 0;
 25.3207 +}
 25.3208 +    
 25.3209 +/******************************************************************************
 25.3210 + * Turns on the software controllable LED
 25.3211 + *
 25.3212 + * hw - Struct containing variables accessed by shared code
 25.3213 + *****************************************************************************/
 25.3214 +int32_t
 25.3215 +e1000_led_on(struct e1000_hw *hw)
 25.3216 +{
 25.3217 +    uint32_t ctrl;
 25.3218 +
 25.3219 +    DEBUGFUNC("e1000_led_on");
 25.3220 +
 25.3221 +    switch(hw->device_id) {
 25.3222 +    case E1000_DEV_ID_82542:
 25.3223 +    case E1000_DEV_ID_82543GC_FIBER:
 25.3224 +    case E1000_DEV_ID_82543GC_COPPER:
 25.3225 +    case E1000_DEV_ID_82544EI_FIBER:
 25.3226 +        ctrl = E1000_READ_REG(hw, CTRL);
 25.3227 +        /* Set SW Defineable Pin 0 to turn on the LED */
 25.3228 +        ctrl |= E1000_CTRL_SWDPIN0;
 25.3229 +        ctrl |= E1000_CTRL_SWDPIO0;
 25.3230 +        E1000_WRITE_REG(hw, CTRL, ctrl);
 25.3231 +        break;
 25.3232 +    case E1000_DEV_ID_82544EI_COPPER:
 25.3233 +    case E1000_DEV_ID_82544GC_COPPER:
 25.3234 +    case E1000_DEV_ID_82544GC_LOM:
 25.3235 +    case E1000_DEV_ID_82545EM_FIBER:
 25.3236 +    case E1000_DEV_ID_82546EB_FIBER:
 25.3237 +        ctrl = E1000_READ_REG(hw, CTRL);
 25.3238 +        /* Clear SW Defineable Pin 0 to turn on the LED */
 25.3239 +        ctrl &= ~E1000_CTRL_SWDPIN0;
 25.3240 +        ctrl |= E1000_CTRL_SWDPIO0;
 25.3241 +        E1000_WRITE_REG(hw, CTRL, ctrl);
 25.3242 +        break;
 25.3243 +    case E1000_DEV_ID_82540EP:
 25.3244 +    case E1000_DEV_ID_82540EP_LOM:
 25.3245 +    case E1000_DEV_ID_82540EP_LP:
 25.3246 +    case E1000_DEV_ID_82540EM:
 25.3247 +    case E1000_DEV_ID_82540EM_LOM:
 25.3248 +    case E1000_DEV_ID_82545EM_COPPER:
 25.3249 +    case E1000_DEV_ID_82546EB_COPPER:
 25.3250 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
 25.3251 +        break;
 25.3252 +    default:
 25.3253 +        DEBUGOUT("Invalid device ID\n");
 25.3254 +        return -E1000_ERR_CONFIG;
 25.3255 +    }
 25.3256 +    return 0;
 25.3257 +}
 25.3258 +
 25.3259 +/******************************************************************************
 25.3260 + * Turns off the software controllable LED
 25.3261 + *
 25.3262 + * hw - Struct containing variables accessed by shared code
 25.3263 + *****************************************************************************/
 25.3264 +int32_t
 25.3265 +e1000_led_off(struct e1000_hw *hw)
 25.3266 +{
 25.3267 +    uint32_t ctrl;
 25.3268 +
 25.3269 +    DEBUGFUNC("e1000_led_off");
 25.3270 +
 25.3271 +    switch(hw->device_id) {
 25.3272 +    case E1000_DEV_ID_82542:
 25.3273 +    case E1000_DEV_ID_82543GC_FIBER:
 25.3274 +    case E1000_DEV_ID_82543GC_COPPER:
 25.3275 +    case E1000_DEV_ID_82544EI_FIBER:
 25.3276 +        ctrl = E1000_READ_REG(hw, CTRL);
 25.3277 +        /* Clear SW Defineable Pin 0 to turn off the LED */
 25.3278 +        ctrl &= ~E1000_CTRL_SWDPIN0;
 25.3279 +        ctrl |= E1000_CTRL_SWDPIO0;
 25.3280 +        E1000_WRITE_REG(hw, CTRL, ctrl);
 25.3281 +        break;
 25.3282 +    case E1000_DEV_ID_82544EI_COPPER:
 25.3283 +    case E1000_DEV_ID_82544GC_COPPER:
 25.3284 +    case E1000_DEV_ID_82544GC_LOM:
 25.3285 +    case E1000_DEV_ID_82545EM_FIBER:
 25.3286 +    case E1000_DEV_ID_82546EB_FIBER:
 25.3287 +        ctrl = E1000_READ_REG(hw, CTRL);
 25.3288 +        /* Set SW Defineable Pin 0 to turn off the LED */
 25.3289 +        ctrl |= E1000_CTRL_SWDPIN0;
 25.3290 +        ctrl |= E1000_CTRL_SWDPIO0;
 25.3291 +        E1000_WRITE_REG(hw, CTRL, ctrl);
 25.3292 +        break;
 25.3293 +    case E1000_DEV_ID_82540EP:
 25.3294 +    case E1000_DEV_ID_82540EP_LOM:
 25.3295 +    case E1000_DEV_ID_82540EP_LP:
 25.3296 +    case E1000_DEV_ID_82540EM:
 25.3297 +    case E1000_DEV_ID_82540EM_LOM:
 25.3298 +    case E1000_DEV_ID_82545EM_COPPER:
 25.3299 +    case E1000_DEV_ID_82546EB_COPPER:
 25.3300 +        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
 25.3301 +        break;
 25.3302 +    default:
 25.3303 +        DEBUGOUT("Invalid device ID\n");
 25.3304 +        return -E1000_ERR_CONFIG;
 25.3305 +    }
 25.3306 +    return 0;
 25.3307 +}
 25.3308 +
 25.3309 +/******************************************************************************
 25.3310 + * Clears all hardware statistics counters. 
 25.3311 + *
 25.3312 + * hw - Struct containing variables accessed by shared code
 25.3313 + *****************************************************************************/
 25.3314 +void
 25.3315 +e1000_clear_hw_cntrs(struct e1000_hw *hw)
 25.3316 +{
 25.3317 +    volatile uint32_t temp;
 25.3318 +
 25.3319 +    temp = E1000_READ_REG(hw, CRCERRS);
 25.3320 +    temp = E1000_READ_REG(hw, SYMERRS);
 25.3321 +    temp = E1000_READ_REG(hw, MPC);
 25.3322 +    temp = E1000_READ_REG(hw, SCC);
 25.3323 +    temp = E1000_READ_REG(hw, ECOL);
 25.3324 +    temp = E1000_READ_REG(hw, MCC);
 25.3325 +    temp = E1000_READ_REG(hw, LATECOL);
 25.3326 +    temp = E1000_READ_REG(hw, COLC);
 25.3327 +    temp = E1000_READ_REG(hw, DC);
 25.3328 +    temp = E1000_READ_REG(hw, SEC);
 25.3329 +    temp = E1000_READ_REG(hw, RLEC);
 25.3330 +    temp = E1000_READ_REG(hw, XONRXC);
 25.3331 +    temp = E1000_READ_REG(hw, XONTXC);
 25.3332 +    temp = E1000_READ_REG(hw, XOFFRXC);
 25.3333 +    temp = E1000_READ_REG(hw, XOFFTXC);
 25.3334 +    temp = E1000_READ_REG(hw, FCRUC);
 25.3335 +    temp = E1000_READ_REG(hw, PRC64);
 25.3336 +    temp = E1000_READ_REG(hw, PRC127);
 25.3337 +    temp = E1000_READ_REG(hw, PRC255);
 25.3338 +    temp = E1000_READ_REG(hw, PRC511);
 25.3339 +    temp = E1000_READ_REG(hw, PRC1023);
 25.3340 +    temp = E1000_READ_REG(hw, PRC1522);
 25.3341 +    temp = E1000_READ_REG(hw, GPRC);
 25.3342 +    temp = E1000_READ_REG(hw, BPRC);
 25.3343 +    temp = E1000_READ_REG(hw, MPRC);
 25.3344 +    temp = E1000_READ_REG(hw, GPTC);
 25.3345 +    temp = E1000_READ_REG(hw, GORCL);
 25.3346 +    temp = E1000_READ_REG(hw, GORCH);
 25.3347 +    temp = E1000_READ_REG(hw, GOTCL);
 25.3348 +    temp = E1000_READ_REG(hw, GOTCH);
 25.3349 +    temp = E1000_READ_REG(hw, RNBC);
 25.3350 +    temp = E1000_READ_REG(hw, RUC);
 25.3351 +    temp = E1000_READ_REG(hw, RFC);
 25.3352 +    temp = E1000_READ_REG(hw, ROC);
 25.3353 +    temp = E1000_READ_REG(hw, RJC);
 25.3354 +    temp = E1000_READ_REG(hw, TORL);
 25.3355 +    temp = E1000_READ_REG(hw, TORH);
 25.3356 +    temp = E1000_READ_REG(hw, TOTL);
 25.3357 +    temp = E1000_READ_REG(hw, TOTH);
 25.3358 +    temp = E1000_READ_REG(hw, TPR);
 25.3359 +    temp = E1000_READ_REG(hw, TPT);
 25.3360 +    temp = E1000_READ_REG(hw, PTC64);
 25.3361 +    temp = E1000_READ_REG(hw, PTC127);
 25.3362 +    temp = E1000_READ_REG(hw, PTC255);
 25.3363 +    temp = E1000_READ_REG(hw, PTC511);
 25.3364 +    temp = E1000_READ_REG(hw, PTC1023);
 25.3365 +    temp = E1000_READ_REG(hw, PTC1522);
 25.3366 +    temp = E1000_READ_REG(hw, MPTC);
 25.3367 +    temp = E1000_READ_REG(hw, BPTC);
 25.3368 +
 25.3369 +    if(hw->mac_type < e1000_82543) return;
 25.3370 +
 25.3371 +    temp = E1000_READ_REG(hw, ALGNERRC);
 25.3372 +    temp = E1000_READ_REG(hw, RXERRC);
 25.3373 +    temp = E1000_READ_REG(hw, TNCRS);
 25.3374 +    temp = E1000_READ_REG(hw, CEXTERR);
 25.3375 +    temp = E1000_READ_REG(hw, TSCTC);
 25.3376 +    temp = E1000_READ_REG(hw, TSCTFC);
 25.3377 +
 25.3378 +    if(hw->mac_type <= e1000_82544) return;
 25.3379 +
 25.3380 +    temp = E1000_READ_REG(hw, MGTPRC);
 25.3381 +    temp = E1000_READ_REG(hw, MGTPDC);
 25.3382 +    temp = E1000_READ_REG(hw, MGTPTC);
 25.3383 +}
 25.3384 +
 25.3385 +/******************************************************************************
 25.3386 + * Resets Adaptive IFS to its default state.
 25.3387 + *
 25.3388 + * hw - Struct containing variables accessed by shared code
 25.3389 + *
 25.3390 + * Call this after e1000_init_hw. You may override the IFS defaults by setting
 25.3391 + * hw->ifs_params_forced to TRUE. However, you must initialize hw->
 25.3392 + * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
 25.3393 + * before calling this function.
 25.3394 + *****************************************************************************/
 25.3395 +void
 25.3396 +e1000_reset_adaptive(struct e1000_hw *hw)
 25.3397 +{
 25.3398 +    DEBUGFUNC("e1000_reset_adaptive");
 25.3399 +
 25.3400 +    if(hw->adaptive_ifs) {
 25.3401 +        if(!hw->ifs_params_forced) {
 25.3402 +            hw->current_ifs_val = 0;
 25.3403 +            hw->ifs_min_val = IFS_MIN;
 25.3404 +            hw->ifs_max_val = IFS_MAX;
 25.3405 +            hw->ifs_step_size = IFS_STEP;
 25.3406 +            hw->ifs_ratio = IFS_RATIO;
 25.3407 +        }
 25.3408 +        hw->in_ifs_mode = FALSE;
 25.3409 +        E1000_WRITE_REG(hw, AIT, 0);
 25.3410 +    } else {
 25.3411 +        DEBUGOUT("Not in Adaptive IFS mode!\n");
 25.3412 +    }
 25.3413 +}
 25.3414 +
 25.3415 +/******************************************************************************
 25.3416 + * Called during the callback/watchdog routine to update IFS value based on
 25.3417 + * the ratio of transmits to collisions.
 25.3418 + *
 25.3419 + * hw - Struct containing variables accessed by shared code
 25.3420 + * tx_packets - Number of transmits since last callback
 25.3421 + * total_collisions - Number of collisions since last callback
 25.3422 + *****************************************************************************/
 25.3423 +void
 25.3424 +e1000_update_adaptive(struct e1000_hw *hw)
 25.3425 +{
 25.3426 +    DEBUGFUNC("e1000_update_adaptive");
 25.3427 +
 25.3428 +    if(hw->adaptive_ifs) {
 25.3429 +        if((hw->collision_delta * hw->ifs_ratio) > 
 25.3430 +           hw->tx_packet_delta) {
 25.3431 +            if(hw->tx_packet_delta > MIN_NUM_XMITS) {
 25.3432 +                hw->in_ifs_mode = TRUE;
 25.3433 +                if(hw->current_ifs_val < hw->ifs_max_val) {
 25.3434 +                    if(hw->current_ifs_val == 0)
 25.3435 +                        hw->current_ifs_val = hw->ifs_min_val;
 25.3436 +                    else
 25.3437 +                        hw->current_ifs_val += hw->ifs_step_size;
 25.3438 +                    E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
 25.3439 +                }
 25.3440 +            }
 25.3441 +        } else {
 25.3442 +            if((hw->in_ifs_mode == TRUE) && 
 25.3443 +               (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
 25.3444 +                hw->current_ifs_val = 0;
 25.3445 +                hw->in_ifs_mode = FALSE;
 25.3446 +                E1000_WRITE_REG(hw, AIT, 0);
 25.3447 +            }
 25.3448 +        }
 25.3449 +    } else {
 25.3450 +        DEBUGOUT("Not in Adaptive IFS mode!\n");
 25.3451 +    }
 25.3452 +}
 25.3453 +
 25.3454 +/******************************************************************************
 25.3455 + * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
 25.3456 + * 
 25.3457 + * hw - Struct containing variables accessed by shared code
 25.3458 + * frame_len - The length of the frame in question
 25.3459 + * mac_addr - The Ethernet destination address of the frame in question
 25.3460 + *****************************************************************************/
 25.3461 +void
 25.3462 +e1000_tbi_adjust_stats(struct e1000_hw *hw,
 25.3463 +                       struct e1000_hw_stats *stats,
 25.3464 +                       uint32_t frame_len,
 25.3465 +                       uint8_t *mac_addr)
 25.3466 +{
 25.3467 +    uint64_t carry_bit;
 25.3468 +
 25.3469 +    /* First adjust the frame length. */
 25.3470 +    frame_len--;
 25.3471 +    /* We need to adjust the statistics counters, since the hardware
 25.3472 +     * counters overcount this packet as a CRC error and undercount
 25.3473 +     * the packet as a good packet
 25.3474 +     */
 25.3475 +    /* This packet should not be counted as a CRC error.    */
 25.3476 +    stats->crcerrs--;
 25.3477 +    /* This packet does count as a Good Packet Received.    */
 25.3478 +    stats->gprc++;
 25.3479 +
 25.3480 +    /* Adjust the Good Octets received counters             */
 25.3481 +    carry_bit = 0x80000000 & stats->gorcl;
 25.3482 +    stats->gorcl += frame_len;
 25.3483 +    /* If the high bit of Gorcl (the low 32 bits of the Good Octets
 25.3484 +     * Received Count) was one before the addition, 
 25.3485 +     * AND it is zero after, then we lost the carry out, 
 25.3486 +     * need to add one to Gorch (Good Octets Received Count High).
 25.3487 +     * This could be simplified if all environments supported 
 25.3488 +     * 64-bit integers.
 25.3489 +     */
 25.3490 +    if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
 25.3491 +        stats->gorch++;
 25.3492 +    /* Is this a broadcast or multicast?  Check broadcast first,
 25.3493 +     * since the test for a multicast frame will test positive on 
 25.3494 +     * a broadcast frame.
 25.3495 +     */
 25.3496 +    if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
 25.3497 +        /* Broadcast packet */
 25.3498 +        stats->bprc++;
 25.3499 +    else if(*mac_addr & 0x01)
 25.3500 +        /* Multicast packet */
 25.3501 +        stats->mprc++;
 25.3502 +
 25.3503 +    if(frame_len == hw->max_frame_size) {
 25.3504 +        /* In this case, the hardware has overcounted the number of
 25.3505 +         * oversize frames.
 25.3506 +         */
 25.3507 +        if(stats->roc > 0)
 25.3508 +            stats->roc--;
 25.3509 +    }
 25.3510 +
 25.3511 +    /* Adjust the bin counters when the extra byte put the frame in the
 25.3512 +     * wrong bin. Remember that the frame_len was adjusted above.
 25.3513 +     */
 25.3514 +    if(frame_len == 64) {
 25.3515 +        stats->prc64++;
 25.3516 +        stats->prc127--;
 25.3517 +    } else if(frame_len == 127) {
 25.3518 +        stats->prc127++;
 25.3519 +        stats->prc255--;
 25.3520 +    } else if(frame_len == 255) {
 25.3521 +        stats->prc255++;
 25.3522 +        stats->prc511--;
 25.3523 +    } else if(frame_len == 511) {
 25.3524 +        stats->prc511++;
 25.3525 +        stats->prc1023--;
 25.3526 +    } else if(frame_len == 1023) {
 25.3527 +        stats->prc1023++;
 25.3528 +        stats->prc1522--;
 25.3529 +    } else if(frame_len == 1522) {
 25.3530 +        stats->prc1522++;
 25.3531 +    }
 25.3532 +}
 25.3533 +
 25.3534 +/******************************************************************************
 25.3535 + * Gets the current PCI bus type, speed, and width of the hardware
 25.3536 + *
 25.3537 + * hw - Struct containing variables accessed by shared code
 25.3538 + *****************************************************************************/
 25.3539 +void
 25.3540 +e1000_get_bus_info(struct e1000_hw *hw)
 25.3541 +{
 25.3542 +    uint32_t status;
 25.3543 +
 25.3544 +    if(hw->mac_type < e1000_82543) {
 25.3545 +        hw->bus_type = e1000_bus_type_unknown;
 25.3546 +        hw->bus_speed = e1000_bus_speed_unknown;
 25.3547 +        hw->bus_width = e1000_bus_width_unknown;
 25.3548 +        return;
 25.3549 +    }
 25.3550 +
 25.3551 +    status = E1000_READ_REG(hw, STATUS);
 25.3552 +    hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
 25.3553 +                   e1000_bus_type_pcix : e1000_bus_type_pci;
 25.3554 +    if(hw->bus_type == e1000_bus_type_pci) {
 25.3555 +        hw->bus_speed = (status & E1000_STATUS_PCI66) ?
 25.3556 +                        e1000_bus_speed_66 : e1000_bus_speed_33;
 25.3557 +    } else {
 25.3558 +        switch (status & E1000_STATUS_PCIX_SPEED) {
 25.3559 +        case E1000_STATUS_PCIX_SPEED_66:
 25.3560 +            hw->bus_speed = e1000_bus_speed_66;
 25.3561 +            break;
 25.3562 +        case E1000_STATUS_PCIX_SPEED_100:
 25.3563 +            hw->bus_speed = e1000_bus_speed_100;
 25.3564 +            break;
 25.3565 +        case E1000_STATUS_PCIX_SPEED_133:
 25.3566 +            hw->bus_speed = e1000_bus_speed_133;
 25.3567 +            break;
 25.3568 +        default:
 25.3569 +            hw->bus_speed = e1000_bus_speed_reserved;
 25.3570 +            break;
 25.3571 +        }
 25.3572 +    }
 25.3573 +    hw->bus_width = (status & E1000_STATUS_BUS64) ?
 25.3574 +                    e1000_bus_width_64 : e1000_bus_width_32;
 25.3575 +}
 25.3576 +/******************************************************************************
 25.3577 + * Reads a value from one of the devices registers using port I/O (as opposed
 25.3578 + * memory mapped I/O). Only 82544 and newer devices support port I/O.
 25.3579 + *
 25.3580 + * hw - Struct containing variables accessed by shared code
 25.3581 + * offset - offset to read from
 25.3582 + *****************************************************************************/
 25.3583 +uint32_t
 25.3584 +e1000_read_reg_io(struct e1000_hw *hw,
 25.3585 +                  uint32_t offset)
 25.3586 +{
 25.3587 +    uint32_t io_addr = hw->io_base;
 25.3588 +    uint32_t io_data = hw->io_base + 4;
 25.3589 +
 25.3590 +    e1000_io_write(hw, io_addr, offset);
 25.3591 +    return e1000_io_read(hw, io_data);
 25.3592 +}
 25.3593 +
 25.3594 +/******************************************************************************
 25.3595 + * Writes a value to one of the devices registers using port I/O (as opposed to
 25.3596 + * memory mapped I/O). Only 82544 and newer devices support port I/O.
 25.3597 + *
 25.3598 + * hw - Struct containing variables accessed by shared code
 25.3599 + * offset - offset to write to
 25.3600 + * value - value to write
 25.3601 + *****************************************************************************/
 25.3602 +void
 25.3603 +e1000_write_reg_io(struct e1000_hw *hw,
 25.3604 +                   uint32_t offset,
 25.3605 +                   uint32_t value)
 25.3606 +{
 25.3607 +    uint32_t io_addr = hw->io_base;
 25.3608 +    uint32_t io_data = hw->io_base + 4;
 25.3609 +
 25.3610 +    e1000_io_write(hw, io_addr, offset);
 25.3611 +    e1000_io_write(hw, io_data, value);
 25.3612 +}
 25.3613 +
    26.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_hw.h	Tue Feb 11 16:51:47 2003 +0000
    26.3 @@ -0,0 +1,1789 @@
    26.4 +/*******************************************************************************
    26.5 +
    26.6 +  
    26.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    26.8 +  
    26.9 +  This program is free software; you can redistribute it and/or modify it 
   26.10 +  under the terms of the GNU General Public License as published by the Free 
   26.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   26.12 +  any later version.
   26.13 +  
   26.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   26.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   26.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   26.17 +  more details.
   26.18 +  
   26.19 +  You should have received a copy of the GNU General Public License along with
   26.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   26.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   26.22 +  
   26.23 +  The full GNU General Public License is included in this distribution in the
   26.24 +  file called LICENSE.
   26.25 +  
   26.26 +  Contact Information:
   26.27 +  Linux NICS <linux.nics@intel.com>
   26.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   26.29 +
   26.30 +*******************************************************************************/
   26.31 +
   26.32 +/* e1000_hw.h
   26.33 + * Structures, enums, and macros for the MAC
   26.34 + */
   26.35 +
   26.36 +#ifndef _E1000_HW_H_
   26.37 +#define _E1000_HW_H_
   26.38 +
   26.39 +#include "e1000_osdep.h"
   26.40 +
   26.41 +/* Forward declarations of structures used by the shared code */
   26.42 +struct e1000_hw;
   26.43 +struct e1000_hw_stats;
   26.44 +
   26.45 +/* Enumerated types specific to the e1000 hardware */
   26.46 +/* Media Access Controlers */
   26.47 +typedef enum {
   26.48 +    e1000_undefined = 0,
   26.49 +    e1000_82542_rev2_0,
   26.50 +    e1000_82542_rev2_1,
   26.51 +    e1000_82543,
   26.52 +    e1000_82544,
   26.53 +    e1000_82540,
   26.54 +    e1000_82545,
   26.55 +    e1000_82546,
   26.56 +    e1000_num_macs
   26.57 +} e1000_mac_type;
   26.58 +
   26.59 +/* Media Types */
   26.60 +typedef enum {
   26.61 +    e1000_media_type_copper = 0,
   26.62 +    e1000_media_type_fiber = 1,
   26.63 +    e1000_num_media_types
   26.64 +} e1000_media_type;
   26.65 +
   26.66 +typedef enum {
   26.67 +    e1000_10_half = 0,
   26.68 +    e1000_10_full = 1,
   26.69 +    e1000_100_half = 2,
   26.70 +    e1000_100_full = 3
   26.71 +} e1000_speed_duplex_type;
   26.72 +
   26.73 +/* Flow Control Settings */
   26.74 +typedef enum {
   26.75 +    e1000_fc_none = 0,
   26.76 +    e1000_fc_rx_pause = 1,
   26.77 +    e1000_fc_tx_pause = 2,
   26.78 +    e1000_fc_full = 3,
   26.79 +    e1000_fc_default = 0xFF
   26.80 +} e1000_fc_type;
   26.81 +
   26.82 +/* PCI bus types */
   26.83 +typedef enum {
   26.84 +    e1000_bus_type_unknown = 0,
   26.85 +    e1000_bus_type_pci,
   26.86 +    e1000_bus_type_pcix
   26.87 +} e1000_bus_type;
   26.88 +
   26.89 +/* PCI bus speeds */
   26.90 +typedef enum {
   26.91 +    e1000_bus_speed_unknown = 0,
   26.92 +    e1000_bus_speed_33,
   26.93 +    e1000_bus_speed_66,
   26.94 +    e1000_bus_speed_100,
   26.95 +    e1000_bus_speed_133,
   26.96 +    e1000_bus_speed_reserved
   26.97 +} e1000_bus_speed;
   26.98 +
   26.99 +/* PCI bus widths */
  26.100 +typedef enum {
  26.101 +    e1000_bus_width_unknown = 0,
  26.102 +    e1000_bus_width_32,
  26.103 +    e1000_bus_width_64
  26.104 +} e1000_bus_width;
  26.105 +
  26.106 +/* PHY status info structure and supporting enums */
  26.107 +typedef enum {
  26.108 +    e1000_cable_length_50 = 0,
  26.109 +    e1000_cable_length_50_80,
  26.110 +    e1000_cable_length_80_110,
  26.111 +    e1000_cable_length_110_140,
  26.112 +    e1000_cable_length_140,
  26.113 +    e1000_cable_length_undefined = 0xFF
  26.114 +} e1000_cable_length;
  26.115 +
  26.116 +typedef enum {
  26.117 +    e1000_10bt_ext_dist_enable_normal = 0,
  26.118 +    e1000_10bt_ext_dist_enable_lower,
  26.119 +    e1000_10bt_ext_dist_enable_undefined = 0xFF
  26.120 +} e1000_10bt_ext_dist_enable;
  26.121 +
  26.122 +typedef enum {
  26.123 +    e1000_rev_polarity_normal = 0,
  26.124 +    e1000_rev_polarity_reversed,
  26.125 +    e1000_rev_polarity_undefined = 0xFF
  26.126 +} e1000_rev_polarity;
  26.127 +
  26.128 +typedef enum {
  26.129 +    e1000_polarity_reversal_enabled = 0,
  26.130 +    e1000_polarity_reversal_disabled,
  26.131 +    e1000_polarity_reversal_undefined = 0xFF
  26.132 +} e1000_polarity_reversal;
  26.133 +
  26.134 +typedef enum {
  26.135 +    e1000_auto_x_mode_manual_mdi = 0,
  26.136 +    e1000_auto_x_mode_manual_mdix,
  26.137 +    e1000_auto_x_mode_auto1,
  26.138 +    e1000_auto_x_mode_auto2,
  26.139 +    e1000_auto_x_mode_undefined = 0xFF
  26.140 +} e1000_auto_x_mode;
  26.141 +
  26.142 +typedef enum {
  26.143 +    e1000_1000t_rx_status_not_ok = 0,
  26.144 +    e1000_1000t_rx_status_ok,
  26.145 +    e1000_1000t_rx_status_undefined = 0xFF
  26.146 +} e1000_1000t_rx_status;
  26.147 +
  26.148 +struct e1000_phy_info {
  26.149 +    e1000_cable_length cable_length;
  26.150 +    e1000_10bt_ext_dist_enable extended_10bt_distance;
  26.151 +    e1000_rev_polarity cable_polarity;
  26.152 +    e1000_polarity_reversal polarity_correction;
  26.153 +    e1000_auto_x_mode mdix_mode;
  26.154 +    e1000_1000t_rx_status local_rx;
  26.155 +    e1000_1000t_rx_status remote_rx;
  26.156 +};
  26.157 +
  26.158 +struct e1000_phy_stats {
  26.159 +    uint32_t idle_errors;
  26.160 +    uint32_t receive_errors;
  26.161 +};
  26.162 +
  26.163 +
  26.164 +
  26.165 +/* Error Codes */
  26.166 +#define E1000_SUCCESS      0
  26.167 +#define E1000_ERR_EEPROM   1
  26.168 +#define E1000_ERR_PHY      2
  26.169 +#define E1000_ERR_CONFIG   3
  26.170 +#define E1000_ERR_PARAM    4
  26.171 +#define E1000_ERR_MAC_TYPE 5
  26.172 +
  26.173 +/* Function prototypes */
  26.174 +/* Initialization */
  26.175 +void e1000_reset_hw(struct e1000_hw *hw);
  26.176 +int32_t e1000_init_hw(struct e1000_hw *hw);
  26.177 +int32_t e1000_set_mac_type(struct e1000_hw *hw);
  26.178 +
  26.179 +/* Link Configuration */
  26.180 +int32_t e1000_setup_link(struct e1000_hw *hw);
  26.181 +int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
  26.182 +void e1000_config_collision_dist(struct e1000_hw *hw);
  26.183 +int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
  26.184 +int32_t e1000_check_for_link(struct e1000_hw *hw);
  26.185 +void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
  26.186 +int32_t e1000_wait_autoneg(struct e1000_hw *hw);
  26.187 +
  26.188 +/* PHY */
  26.189 +int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
  26.190 +int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
  26.191 +void e1000_phy_hw_reset(struct e1000_hw *hw);
  26.192 +int32_t e1000_phy_reset(struct e1000_hw *hw);
  26.193 +int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
  26.194 +int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
  26.195 +int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
  26.196 +
  26.197 +/* EEPROM Functions */
  26.198 +int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t *data);
  26.199 +int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
  26.200 +int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
  26.201 +int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t data);
  26.202 +int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
  26.203 +int32_t e1000_read_mac_addr(struct e1000_hw * hw);
  26.204 +
  26.205 +/* Filters (multicast, vlan, receive) */
  26.206 +void e1000_init_rx_addrs(struct e1000_hw *hw);
  26.207 +void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad);
  26.208 +uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
  26.209 +void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
  26.210 +void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
  26.211 +void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
  26.212 +void e1000_clear_vfta(struct e1000_hw *hw);
  26.213 +
  26.214 +/* LED functions */
  26.215 +int32_t e1000_setup_led(struct e1000_hw *hw);
  26.216 +int32_t e1000_cleanup_led(struct e1000_hw *hw);
  26.217 +int32_t e1000_led_on(struct e1000_hw *hw);
  26.218 +int32_t e1000_led_off(struct e1000_hw *hw);
  26.219 +
  26.220 +/* Adaptive IFS Functions */
  26.221 +
  26.222 +/* Everything else */
  26.223 +void e1000_clear_hw_cntrs(struct e1000_hw *hw);
  26.224 +void e1000_reset_adaptive(struct e1000_hw *hw);
  26.225 +void e1000_update_adaptive(struct e1000_hw *hw);
  26.226 +void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
  26.227 +void e1000_get_bus_info(struct e1000_hw *hw);
  26.228 +void e1000_pci_set_mwi(struct e1000_hw *hw);
  26.229 +void e1000_pci_clear_mwi(struct e1000_hw *hw);
  26.230 +void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
  26.231 +void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
  26.232 +/* Port I/O is only supported on 82544 and newer */
  26.233 +uint32_t e1000_io_read(struct e1000_hw *hw, uint32_t port);
  26.234 +uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
  26.235 +void e1000_io_write(struct e1000_hw *hw, uint32_t port, uint32_t value);
  26.236 +void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
  26.237 +#define E1000_READ_REG_IO(a, reg) \
  26.238 +    e1000_read_reg_io((a), E1000_##reg)
  26.239 +#define E1000_WRITE_REG_IO(a, reg, val) \
  26.240 +    e1000_write_reg_io((a), E1000_##reg, val)
  26.241 +
  26.242 +/* PCI Device IDs */
  26.243 +#define E1000_DEV_ID_82542               0x1000
  26.244 +#define E1000_DEV_ID_82543GC_FIBER       0x1001
  26.245 +#define E1000_DEV_ID_82543GC_COPPER      0x1004
  26.246 +#define E1000_DEV_ID_82544EI_COPPER      0x1008
  26.247 +#define E1000_DEV_ID_82544EI_FIBER       0x1009
  26.248 +#define E1000_DEV_ID_82544GC_COPPER      0x100C
  26.249 +#define E1000_DEV_ID_82544GC_LOM         0x100D
  26.250 +#define E1000_DEV_ID_82540EM             0x100E
  26.251 +#define E1000_DEV_ID_82540EM_LOM         0x1015
  26.252 +#define E1000_DEV_ID_82540EP_LOM         0x1016
  26.253 +#define E1000_DEV_ID_82540EP             0x1017
  26.254 +#define E1000_DEV_ID_82540EP_LP          0x101E
  26.255 +#define E1000_DEV_ID_82545EM_COPPER      0x100F
  26.256 +#define E1000_DEV_ID_82545EM_FIBER       0x1011
  26.257 +#define E1000_DEV_ID_82546EB_COPPER      0x1010
  26.258 +#define E1000_DEV_ID_82546EB_FIBER       0x1012
  26.259 +#define NUM_DEV_IDS 16
  26.260 +
  26.261 +#define NODE_ADDRESS_SIZE 6
  26.262 +#define ETH_LENGTH_OF_ADDRESS 6
  26.263 +
  26.264 +/* MAC decode size is 128K - This is the size of BAR0 */
  26.265 +#define MAC_DECODE_SIZE (128 * 1024)
  26.266 +
  26.267 +#define E1000_82542_2_0_REV_ID 2
  26.268 +#define E1000_82542_2_1_REV_ID 3
  26.269 +
  26.270 +#define SPEED_10    10
  26.271 +#define SPEED_100   100
  26.272 +#define SPEED_1000  1000
  26.273 +#define HALF_DUPLEX 1
  26.274 +#define FULL_DUPLEX 2
  26.275 +
  26.276 +/* The sizes (in bytes) of a ethernet packet */
  26.277 +#define ENET_HEADER_SIZE             14
  26.278 +#define MAXIMUM_ETHERNET_FRAME_SIZE  1518 /* With FCS */
  26.279 +#define MINIMUM_ETHERNET_FRAME_SIZE  64   /* With FCS */
  26.280 +#define ETHERNET_FCS_SIZE            4
  26.281 +#define MAXIMUM_ETHERNET_PACKET_SIZE \
  26.282 +    (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
  26.283 +#define MINIMUM_ETHERNET_PACKET_SIZE \
  26.284 +    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
  26.285 +#define CRC_LENGTH                   ETHERNET_FCS_SIZE
  26.286 +#define MAX_JUMBO_FRAME_SIZE         0x3F00
  26.287 +
  26.288 +
  26.289 +/* 802.1q VLAN Packet Sizes */
  26.290 +#define VLAN_TAG_SIZE                     4     /* 802.3ac tag (not DMAed) */
  26.291 +
  26.292 +/* Ethertype field values */
  26.293 +#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
  26.294 +#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
  26.295 +#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
  26.296 +
  26.297 +/* Packet Header defines */
  26.298 +#define IP_PROTOCOL_TCP    6
  26.299 +#define IP_PROTOCOL_UDP    0x11
  26.300 +
  26.301 +/* This defines the bits that are set in the Interrupt Mask
  26.302 + * Set/Read Register.  Each bit is documented below:
  26.303 + *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  26.304 + *   o RXSEQ  = Receive Sequence Error 
  26.305 + */
  26.306 +#define POLL_IMS_ENABLE_MASK ( \
  26.307 +    E1000_IMS_RXDMT0 |         \
  26.308 +    E1000_IMS_RXSEQ)
  26.309 +
  26.310 +/* This defines the bits that are set in the Interrupt Mask
  26.311 + * Set/Read Register.  Each bit is documented below:
  26.312 + *   o RXT0   = Receiver Timer Interrupt (ring 0)
  26.313 + *   o TXDW   = Transmit Descriptor Written Back
  26.314 + *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  26.315 + *   o RXSEQ  = Receive Sequence Error
  26.316 + *   o LSC    = Link Status Change
  26.317 + */
  26.318 +#define IMS_ENABLE_MASK ( \
  26.319 +    E1000_IMS_RXT0   |    \
  26.320 +    E1000_IMS_TXDW   |    \
  26.321 +    E1000_IMS_RXDMT0 |    \
  26.322 +    E1000_IMS_RXSEQ  |    \
  26.323 +    E1000_IMS_LSC)
  26.324 +
  26.325 +/* The number of high/low register pairs in the RAR. The RAR (Receive Address
  26.326 + * Registers) holds the directed and multicast addresses that we monitor. We
  26.327 + * reserve one of these spots for our directed address, allowing us room for
  26.328 + * E1000_RAR_ENTRIES - 1 multicast addresses. 
  26.329 + */
  26.330 +#define E1000_RAR_ENTRIES 16
  26.331 +
  26.332 +#define MIN_NUMBER_OF_DESCRIPTORS 8
  26.333 +#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
  26.334 +
  26.335 +/* Receive Descriptor */
  26.336 +struct e1000_rx_desc {
  26.337 +    uint64_t buffer_addr; /* Address of the descriptor's data buffer */
  26.338 +    uint16_t length;     /* Length of data DMAed into data buffer */
  26.339 +    uint16_t csum;       /* Packet checksum */
  26.340 +    uint8_t status;      /* Descriptor status */
  26.341 +    uint8_t errors;      /* Descriptor Errors */
  26.342 +    uint16_t special;
  26.343 +};
  26.344 +
  26.345 +/* Receive Decriptor bit definitions */
  26.346 +#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
  26.347 +#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
  26.348 +#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
  26.349 +#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
  26.350 +#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
  26.351 +#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
  26.352 +#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
  26.353 +#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
  26.354 +#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
  26.355 +#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
  26.356 +#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
  26.357 +#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
  26.358 +#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
  26.359 +#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
  26.360 +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
  26.361 +#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
  26.362 +#define E1000_RXD_SPC_PRI_SHIFT 0x000D  /* Priority is in upper 3 of 16 */
  26.363 +#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
  26.364 +#define E1000_RXD_SPC_CFI_SHIFT 0x000C  /* CFI is bit 12 */
  26.365 +
  26.366 +/* mask to determine if packets should be dropped due to frame errors */
  26.367 +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
  26.368 +    E1000_RXD_ERR_CE  |                \
  26.369 +    E1000_RXD_ERR_SE  |                \
  26.370 +    E1000_RXD_ERR_SEQ |                \
  26.371 +    E1000_RXD_ERR_CXE |                \
  26.372 +    E1000_RXD_ERR_RXE)
  26.373 +
  26.374 +/* Transmit Descriptor */
  26.375 +struct e1000_tx_desc {
  26.376 +    uint64_t buffer_addr;       /* Address of the descriptor's data buffer */
  26.377 +    union {
  26.378 +        uint32_t data;
  26.379 +        struct {
  26.380 +            uint16_t length;    /* Data buffer length */
  26.381 +            uint8_t cso;        /* Checksum offset */
  26.382 +            uint8_t cmd;        /* Descriptor control */
  26.383 +        } flags;
  26.384 +    } lower;
  26.385 +    union {
  26.386 +        uint32_t data;
  26.387 +        struct {
  26.388 +            uint8_t status;     /* Descriptor status */
  26.389 +            uint8_t css;        /* Checksum start */
  26.390 +            uint16_t special;
  26.391 +        } fields;
  26.392 +    } upper;
  26.393 +};
  26.394 +
  26.395 +/* Transmit Descriptor bit definitions */
  26.396 +#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
  26.397 +#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
  26.398 +#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
  26.399 +#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
  26.400 +#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
  26.401 +#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
  26.402 +#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
  26.403 +#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
  26.404 +#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
  26.405 +#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
  26.406 +#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
  26.407 +#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
  26.408 +#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
  26.409 +#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
  26.410 +#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
  26.411 +#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
  26.412 +#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
  26.413 +#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
  26.414 +#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
  26.415 +#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
  26.416 +
  26.417 +/* Offload Context Descriptor */
  26.418 +struct e1000_context_desc {
  26.419 +    union {
  26.420 +        uint32_t ip_config;
  26.421 +        struct {
  26.422 +            uint8_t ipcss;      /* IP checksum start */
  26.423 +            uint8_t ipcso;      /* IP checksum offset */
  26.424 +            uint16_t ipcse;     /* IP checksum end */
  26.425 +        } ip_fields;
  26.426 +    } lower_setup;
  26.427 +    union {
  26.428 +        uint32_t tcp_config;
  26.429 +        struct {
  26.430 +            uint8_t tucss;      /* TCP checksum start */
  26.431 +            uint8_t tucso;      /* TCP checksum offset */
  26.432 +            uint16_t tucse;     /* TCP checksum end */
  26.433 +        } tcp_fields;
  26.434 +    } upper_setup;
  26.435 +    uint32_t cmd_and_length;    /* */
  26.436 +    union {
  26.437 +        uint32_t data;
  26.438 +        struct {
  26.439 +            uint8_t status;     /* Descriptor status */
  26.440 +            uint8_t hdr_len;    /* Header length */
  26.441 +            uint16_t mss;       /* Maximum segment size */
  26.442 +        } fields;
  26.443 +    } tcp_seg_setup;
  26.444 +};
  26.445 +
  26.446 +/* Offload data descriptor */
  26.447 +struct e1000_data_desc {
  26.448 +    uint64_t buffer_addr;       /* Address of the descriptor's buffer address */
  26.449 +    union {
  26.450 +        uint32_t data;
  26.451 +        struct {
  26.452 +            uint16_t length;    /* Data buffer length */
  26.453 +            uint8_t typ_len_ext;        /* */
  26.454 +            uint8_t cmd;        /* */
  26.455 +        } flags;
  26.456 +    } lower;
  26.457 +    union {
  26.458 +        uint32_t data;
  26.459 +        struct {
  26.460 +            uint8_t status;     /* Descriptor status */
  26.461 +            uint8_t popts;      /* Packet Options */
  26.462 +            uint16_t special;   /* */
  26.463 +        } fields;
  26.464 +    } upper;
  26.465 +};
  26.466 +
  26.467 +/* Filters */
  26.468 +#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
  26.469 +#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
  26.470 +#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
  26.471 +
  26.472 +
  26.473 +/* Receive Address Register */
  26.474 +struct e1000_rar {
  26.475 +    volatile uint32_t low;      /* receive address low */
  26.476 +    volatile uint32_t high;     /* receive address high */
  26.477 +};
  26.478 +
  26.479 +/* The number of entries in the Multicast Table Array (MTA). */
  26.480 +#define E1000_NUM_MTA_REGISTERS 128
  26.481 +
  26.482 +/* IPv4 Address Table Entry */
  26.483 +struct e1000_ipv4_at_entry {
  26.484 +    volatile uint32_t ipv4_addr;        /* IP Address (RW) */
  26.485 +    volatile uint32_t reserved;
  26.486 +};
  26.487 +
  26.488 +/* Four wakeup IP addresses are supported */
  26.489 +#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
  26.490 +#define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
  26.491 +#define E1000_IP6AT_SIZE                  1
  26.492 +
  26.493 +/* IPv6 Address Table Entry */
  26.494 +struct e1000_ipv6_at_entry {
  26.495 +    volatile uint8_t ipv6_addr[16];
  26.496 +};
  26.497 +
  26.498 +/* Flexible Filter Length Table Entry */
  26.499 +struct e1000_fflt_entry {
  26.500 +    volatile uint32_t length;   /* Flexible Filter Length (RW) */
  26.501 +    volatile uint32_t reserved;
  26.502 +};
  26.503 +
  26.504 +/* Flexible Filter Mask Table Entry */
  26.505 +struct e1000_ffmt_entry {
  26.506 +    volatile uint32_t mask;     /* Flexible Filter Mask (RW) */
  26.507 +    volatile uint32_t reserved;
  26.508 +};
  26.509 +
  26.510 +/* Flexible Filter Value Table Entry */
  26.511 +struct e1000_ffvt_entry {
  26.512 +    volatile uint32_t value;    /* Flexible Filter Value (RW) */
  26.513 +    volatile uint32_t reserved;
  26.514 +};
  26.515 +
  26.516 +/* Four Flexible Filters are supported */
  26.517 +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
  26.518 +
  26.519 +/* Each Flexible Filter is at most 128 (0x80) bytes in length */
  26.520 +#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
  26.521 +
  26.522 +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
  26.523 +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
  26.524 +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
  26.525 +
  26.526 +/* Register Set. (82543, 82544)
  26.527 + *
  26.528 + * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
  26.529 + * These registers are physically located on the NIC, but are mapped into the 
  26.530 + * host memory address space.
  26.531 + *
  26.532 + * RW - register is both readable and writable
  26.533 + * RO - register is read only
  26.534 + * WO - register is write only
  26.535 + * R/clr - register is read only and is cleared when read
  26.536 + * A - register array
  26.537 + */
  26.538 +#define E1000_CTRL     0x00000  /* Device Control - RW */
  26.539 +#define E1000_STATUS   0x00008  /* Device Status - RO */
  26.540 +#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
  26.541 +#define E1000_EERD     0x00014  /* EEPROM Read - RW */
  26.542 +#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
  26.543 +#define E1000_MDIC     0x00020  /* MDI Control - RW */
  26.544 +#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
  26.545 +#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
  26.546 +#define E1000_FCT      0x00030  /* Flow Control Type - RW */
  26.547 +#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
  26.548 +#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
  26.549 +#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
  26.550 +#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
  26.551 +#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
  26.552 +#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
  26.553 +#define E1000_RCTL     0x00100  /* RX Control - RW */
  26.554 +#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
  26.555 +#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
  26.556 +#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
  26.557 +#define E1000_TCTL     0x00400  /* TX Control - RW */
  26.558 +#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
  26.559 +#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
  26.560 +#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
  26.561 +#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
  26.562 +#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
  26.563 +#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
  26.564 +#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
  26.565 +#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
  26.566 +#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
  26.567 +#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
  26.568 +#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
  26.569 +#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
  26.570 +#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
  26.571 +#define E1000_RXDCTL   0x02828  /* RX Descriptor Control - RW */
  26.572 +#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
  26.573 +#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
  26.574 +#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
  26.575 +#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
  26.576 +#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
  26.577 +#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
  26.578 +#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
  26.579 +#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
  26.580 +#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
  26.581 +#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
  26.582 +#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
  26.583 +#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
  26.584 +#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
  26.585 +#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
  26.586 +#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
  26.587 +#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
  26.588 +#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
  26.589 +#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
  26.590 +#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
  26.591 +#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
  26.592 +#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
  26.593 +#define E1000_COLC     0x04028  /* Collision Count - R/clr */
  26.594 +#define E1000_DC       0x04030  /* Defer Count - R/clr */
  26.595 +#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
  26.596 +#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
  26.597 +#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
  26.598 +#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
  26.599 +#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
  26.600 +#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
  26.601 +#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
  26.602 +#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
  26.603 +#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
  26.604 +#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
  26.605 +#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
  26.606 +#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
  26.607 +#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
  26.608 +#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
  26.609 +#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
  26.610 +#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
  26.611 +#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
  26.612 +#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
  26.613 +#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
  26.614 +#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
  26.615 +#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
  26.616 +#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
  26.617 +#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
  26.618 +#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
  26.619 +#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
  26.620 +#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
  26.621 +#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
  26.622 +#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
  26.623 +#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
  26.624 +#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
  26.625 +#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
  26.626 +#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
  26.627 +#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
  26.628 +#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
  26.629 +#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
  26.630 +#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
  26.631 +#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
  26.632 +#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
  26.633 +#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
  26.634 +#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
  26.635 +#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
  26.636 +#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
  26.637 +#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
  26.638 +#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
  26.639 +#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
  26.640 +#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
  26.641 +#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
  26.642 +#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
  26.643 +#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
  26.644 +#define E1000_RA       0x05400  /* Receive Address - RW Array */
  26.645 +#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
  26.646 +#define E1000_WUC      0x05800  /* Wakeup Control - RW */
  26.647 +#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
  26.648 +#define E1000_WUS      0x05810  /* Wakeup Status - RO */
  26.649 +#define E1000_MANC     0x05820  /* Management Control - RW */
  26.650 +#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
  26.651 +#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
  26.652 +#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
  26.653 +#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
  26.654 +#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
  26.655 +#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
  26.656 +#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
  26.657 +#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
  26.658 +
  26.659 +/* Register Set (82542)
  26.660 + *
  26.661 + * Some of the 82542 registers are located at different offsets than they are
  26.662 + * in more current versions of the 8254x. Despite the difference in location,
  26.663 + * the registers function in the same manner.
  26.664 + */
  26.665 +#define E1000_82542_CTRL     E1000_CTRL
  26.666 +#define E1000_82542_STATUS   E1000_STATUS
  26.667 +#define E1000_82542_EECD     E1000_EECD
  26.668 +#define E1000_82542_EERD     E1000_EERD
  26.669 +#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
  26.670 +#define E1000_82542_MDIC     E1000_MDIC
  26.671 +#define E1000_82542_FCAL     E1000_FCAL
  26.672 +#define E1000_82542_FCAH     E1000_FCAH
  26.673 +#define E1000_82542_FCT      E1000_FCT
  26.674 +#define E1000_82542_VET      E1000_VET
  26.675 +#define E1000_82542_RA       0x00040
  26.676 +#define E1000_82542_ICR      E1000_ICR
  26.677 +#define E1000_82542_ITR      E1000_ITR
  26.678 +#define E1000_82542_ICS      E1000_ICS
  26.679 +#define E1000_82542_IMS      E1000_IMS
  26.680 +#define E1000_82542_IMC      E1000_IMC
  26.681 +#define E1000_82542_RCTL     E1000_RCTL
  26.682 +#define E1000_82542_RDTR     0x00108
  26.683 +#define E1000_82542_RDBAL    0x00110
  26.684 +#define E1000_82542_RDBAH    0x00114
  26.685 +#define E1000_82542_RDLEN    0x00118
  26.686 +#define E1000_82542_RDH      0x00120
  26.687 +#define E1000_82542_RDT      0x00128
  26.688 +#define E1000_82542_FCRTH    0x00160
  26.689 +#define E1000_82542_FCRTL    0x00168
  26.690 +#define E1000_82542_FCTTV    E1000_FCTTV
  26.691 +#define E1000_82542_TXCW     E1000_TXCW
  26.692 +#define E1000_82542_RXCW     E1000_RXCW
  26.693 +#define E1000_82542_MTA      0x00200
  26.694 +#define E1000_82542_TCTL     E1000_TCTL
  26.695 +#define E1000_82542_TIPG     E1000_TIPG
  26.696 +#define E1000_82542_TDBAL    0x00420
  26.697 +#define E1000_82542_TDBAH    0x00424
  26.698 +#define E1000_82542_TDLEN    0x00428
  26.699 +#define E1000_82542_TDH      0x00430
  26.700 +#define E1000_82542_TDT      0x00438
  26.701 +#define E1000_82542_TIDV     0x00440
  26.702 +#define E1000_82542_TBT      E1000_TBT
  26.703 +#define E1000_82542_AIT      E1000_AIT
  26.704 +#define E1000_82542_VFTA     0x00600
  26.705 +#define E1000_82542_LEDCTL   E1000_LEDCTL
  26.706 +#define E1000_82542_PBA      E1000_PBA
  26.707 +#define E1000_82542_RXDCTL   E1000_RXDCTL
  26.708 +#define E1000_82542_RADV     E1000_RADV
  26.709 +#define E1000_82542_RSRPD    E1000_RSRPD
  26.710 +#define E1000_82542_TXDMAC   E1000_TXDMAC
  26.711 +#define E1000_82542_TXDCTL   E1000_TXDCTL
  26.712 +#define E1000_82542_TADV     E1000_TADV
  26.713 +#define E1000_82542_TSPMT    E1000_TSPMT
  26.714 +#define E1000_82542_CRCERRS  E1000_CRCERRS
  26.715 +#define E1000_82542_ALGNERRC E1000_ALGNERRC
  26.716 +#define E1000_82542_SYMERRS  E1000_SYMERRS
  26.717 +#define E1000_82542_RXERRC   E1000_RXERRC
  26.718 +#define E1000_82542_MPC      E1000_MPC
  26.719 +#define E1000_82542_SCC      E1000_SCC
  26.720 +#define E1000_82542_ECOL     E1000_ECOL
  26.721 +#define E1000_82542_MCC      E1000_MCC
  26.722 +#define E1000_82542_LATECOL  E1000_LATECOL
  26.723 +#define E1000_82542_COLC     E1000_COLC
  26.724 +#define E1000_82542_DC       E1000_DC
  26.725 +#define E1000_82542_TNCRS    E1000_TNCRS
  26.726 +#define E1000_82542_SEC      E1000_SEC
  26.727 +#define E1000_82542_CEXTERR  E1000_CEXTERR
  26.728 +#define E1000_82542_RLEC     E1000_RLEC
  26.729 +#define E1000_82542_XONRXC   E1000_XONRXC
  26.730 +#define E1000_82542_XONTXC   E1000_XONTXC
  26.731 +#define E1000_82542_XOFFRXC  E1000_XOFFRXC
  26.732 +#define E1000_82542_XOFFTXC  E1000_XOFFTXC
  26.733 +#define E1000_82542_FCRUC    E1000_FCRUC
  26.734 +#define E1000_82542_PRC64    E1000_PRC64
  26.735 +#define E1000_82542_PRC127   E1000_PRC127
  26.736 +#define E1000_82542_PRC255   E1000_PRC255
  26.737 +#define E1000_82542_PRC511   E1000_PRC511
  26.738 +#define E1000_82542_PRC1023  E1000_PRC1023
  26.739 +#define E1000_82542_PRC1522  E1000_PRC1522
  26.740 +#define E1000_82542_GPRC     E1000_GPRC
  26.741 +#define E1000_82542_BPRC     E1000_BPRC
  26.742 +#define E1000_82542_MPRC     E1000_MPRC
  26.743 +#define E1000_82542_GPTC     E1000_GPTC
  26.744 +#define E1000_82542_GORCL    E1000_GORCL
  26.745 +#define E1000_82542_GORCH    E1000_GORCH
  26.746 +#define E1000_82542_GOTCL    E1000_GOTCL
  26.747 +#define E1000_82542_GOTCH    E1000_GOTCH
  26.748 +#define E1000_82542_RNBC     E1000_RNBC
  26.749 +#define E1000_82542_RUC      E1000_RUC
  26.750 +#define E1000_82542_RFC      E1000_RFC
  26.751 +#define E1000_82542_ROC      E1000_ROC
  26.752 +#define E1000_82542_RJC      E1000_RJC
  26.753 +#define E1000_82542_MGTPRC   E1000_MGTPRC
  26.754 +#define E1000_82542_MGTPDC   E1000_MGTPDC
  26.755 +#define E1000_82542_MGTPTC   E1000_MGTPTC
  26.756 +#define E1000_82542_TORL     E1000_TORL
  26.757 +#define E1000_82542_TORH     E1000_TORH
  26.758 +#define E1000_82542_TOTL     E1000_TOTL
  26.759 +#define E1000_82542_TOTH     E1000_TOTH
  26.760 +#define E1000_82542_TPR      E1000_TPR
  26.761 +#define E1000_82542_TPT      E1000_TPT
  26.762 +#define E1000_82542_PTC64    E1000_PTC64
  26.763 +#define E1000_82542_PTC127   E1000_PTC127
  26.764 +#define E1000_82542_PTC255   E1000_PTC255
  26.765 +#define E1000_82542_PTC511   E1000_PTC511
  26.766 +#define E1000_82542_PTC1023  E1000_PTC1023
  26.767 +#define E1000_82542_PTC1522  E1000_PTC1522
  26.768 +#define E1000_82542_MPTC     E1000_MPTC
  26.769 +#define E1000_82542_BPTC     E1000_BPTC
  26.770 +#define E1000_82542_TSCTC    E1000_TSCTC
  26.771 +#define E1000_82542_TSCTFC   E1000_TSCTFC
  26.772 +#define E1000_82542_RXCSUM   E1000_RXCSUM
  26.773 +#define E1000_82542_WUC      E1000_WUC
  26.774 +#define E1000_82542_WUFC     E1000_WUFC
  26.775 +#define E1000_82542_WUS      E1000_WUS
  26.776 +#define E1000_82542_MANC     E1000_MANC
  26.777 +#define E1000_82542_IPAV     E1000_IPAV
  26.778 +#define E1000_82542_IP4AT    E1000_IP4AT
  26.779 +#define E1000_82542_IP6AT    E1000_IP6AT
  26.780 +#define E1000_82542_WUPL     E1000_WUPL
  26.781 +#define E1000_82542_WUPM     E1000_WUPM
  26.782 +#define E1000_82542_FFLT     E1000_FFLT
  26.783 +#define E1000_82542_FFMT     E1000_FFMT
  26.784 +#define E1000_82542_FFVT     E1000_FFVT
  26.785 +
  26.786 +/* Statistics counters collected by the MAC */
  26.787 +struct e1000_hw_stats {
  26.788 +    uint64_t crcerrs;
  26.789 +    uint64_t algnerrc;
  26.790 +    uint64_t symerrs;
  26.791 +    uint64_t rxerrc;
  26.792 +    uint64_t mpc;
  26.793 +    uint64_t scc;
  26.794 +    uint64_t ecol;
  26.795 +    uint64_t mcc;
  26.796 +    uint64_t latecol;
  26.797 +    uint64_t colc;
  26.798 +    uint64_t dc;
  26.799 +    uint64_t tncrs;
  26.800 +    uint64_t sec;
  26.801 +    uint64_t cexterr;
  26.802 +    uint64_t rlec;
  26.803 +    uint64_t xonrxc;
  26.804 +    uint64_t xontxc;
  26.805 +    uint64_t xoffrxc;
  26.806 +    uint64_t xofftxc;
  26.807 +    uint64_t fcruc;
  26.808 +    uint64_t prc64;
  26.809 +    uint64_t prc127;
  26.810 +    uint64_t prc255;
  26.811 +    uint64_t prc511;
  26.812 +    uint64_t prc1023;
  26.813 +    uint64_t prc1522;
  26.814 +    uint64_t gprc;
  26.815 +    uint64_t bprc;
  26.816 +    uint64_t mprc;
  26.817 +    uint64_t gptc;
  26.818 +    uint64_t gorcl;
  26.819 +    uint64_t gorch;
  26.820 +    uint64_t gotcl;
  26.821 +    uint64_t gotch;
  26.822 +    uint64_t rnbc;
  26.823 +    uint64_t ruc;
  26.824 +    uint64_t rfc;
  26.825 +    uint64_t roc;
  26.826 +    uint64_t rjc;
  26.827 +    uint64_t mgprc;
  26.828 +    uint64_t mgpdc;
  26.829 +    uint64_t mgptc;
  26.830 +    uint64_t torl;
  26.831 +    uint64_t torh;
  26.832 +    uint64_t totl;
  26.833 +    uint64_t toth;
  26.834 +    uint64_t tpr;
  26.835 +    uint64_t tpt;
  26.836 +    uint64_t ptc64;
  26.837 +    uint64_t ptc127;
  26.838 +    uint64_t ptc255;
  26.839 +    uint64_t ptc511;
  26.840 +    uint64_t ptc1023;
  26.841 +    uint64_t ptc1522;
  26.842 +    uint64_t mptc;
  26.843 +    uint64_t bptc;
  26.844 +    uint64_t tsctc;
  26.845 +    uint64_t tsctfc;
  26.846 +};
  26.847 +
  26.848 +/* Structure containing variables used by the shared code (e1000_hw.c) */
  26.849 +struct e1000_hw {
  26.850 +    uint8_t *hw_addr;
  26.851 +    e1000_mac_type mac_type;
  26.852 +    e1000_media_type media_type;
  26.853 +    void *back;
  26.854 +    e1000_fc_type fc;
  26.855 +    e1000_bus_speed bus_speed;
  26.856 +    e1000_bus_width bus_width;
  26.857 +    e1000_bus_type bus_type;
  26.858 +    uint32_t io_base;
  26.859 +    uint32_t phy_id;
  26.860 +    uint32_t phy_revision;
  26.861 +    uint32_t phy_addr;
  26.862 +    uint32_t original_fc;
  26.863 +    uint32_t txcw;
  26.864 +    uint32_t autoneg_failed;
  26.865 +    uint32_t max_frame_size;
  26.866 +    uint32_t min_frame_size;
  26.867 +    uint32_t mc_filter_type;
  26.868 +    uint32_t num_mc_addrs;
  26.869 +    uint32_t collision_delta;
  26.870 +    uint32_t tx_packet_delta;
  26.871 +    uint32_t ledctl_default;
  26.872 +    uint32_t ledctl_mode1;
  26.873 +    uint32_t ledctl_mode2;
  26.874 +    uint16_t autoneg_advertised;
  26.875 +    uint16_t pci_cmd_word;
  26.876 +    uint16_t fc_high_water;
  26.877 +    uint16_t fc_low_water;
  26.878 +    uint16_t fc_pause_time;
  26.879 +    uint16_t current_ifs_val;
  26.880 +    uint16_t ifs_min_val;
  26.881 +    uint16_t ifs_max_val;
  26.882 +    uint16_t ifs_step_size;
  26.883 +    uint16_t ifs_ratio;
  26.884 +    uint16_t device_id;
  26.885 +    uint16_t vendor_id;
  26.886 +    uint16_t subsystem_id;
  26.887 +    uint16_t subsystem_vendor_id;
  26.888 +    uint8_t revision_id;
  26.889 +    uint8_t autoneg;
  26.890 +    uint8_t mdix;
  26.891 +    uint8_t forced_speed_duplex;
  26.892 +    uint8_t wait_autoneg_complete;
  26.893 +    uint8_t dma_fairness;
  26.894 +    uint8_t mac_addr[NODE_ADDRESS_SIZE];
  26.895 +    uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
  26.896 +    boolean_t disable_polarity_correction;
  26.897 +    boolean_t get_link_status;
  26.898 +    boolean_t tbi_compatibility_en;
  26.899 +    boolean_t tbi_compatibility_on;
  26.900 +    boolean_t fc_send_xon;
  26.901 +    boolean_t report_tx_early;
  26.902 +    boolean_t adaptive_ifs;
  26.903 +    boolean_t ifs_params_forced;
  26.904 +    boolean_t in_ifs_mode;
  26.905 +};
  26.906 +
  26.907 +
  26.908 +#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
  26.909 +#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
  26.910 +
  26.911 +/* Register Bit Masks */
  26.912 +/* Device Control */
  26.913 +#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
  26.914 +#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
  26.915 +#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
  26.916 +#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
  26.917 +#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
  26.918 +#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
  26.919 +#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
  26.920 +#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
  26.921 +#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
  26.922 +#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
  26.923 +#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
  26.924 +#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
  26.925 +#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
  26.926 +#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
  26.927 +#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
  26.928 +#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
  26.929 +#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
  26.930 +#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
  26.931 +#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
  26.932 +#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
  26.933 +#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
  26.934 +#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
  26.935 +#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
  26.936 +#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
  26.937 +#define E1000_CTRL_RST      0x04000000  /* Global reset */
  26.938 +#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
  26.939 +#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
  26.940 +#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
  26.941 +#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
  26.942 +#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
  26.943 +
  26.944 +/* Device Status */
  26.945 +#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
  26.946 +#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
  26.947 +#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
  26.948 +#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
  26.949 +#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
  26.950 +#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
  26.951 +#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
  26.952 +#define E1000_STATUS_SPEED_MASK 0x000000C0
  26.953 +#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
  26.954 +#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
  26.955 +#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
  26.956 +#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
  26.957 +#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
  26.958 +#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
  26.959 +#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
  26.960 +#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
  26.961 +#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
  26.962 +
  26.963 +/* Constants used to intrepret the masked PCI-X bus speed. */
  26.964 +#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
  26.965 +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
  26.966 +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
  26.967 +
  26.968 +/* EEPROM/Flash Control */
  26.969 +#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
  26.970 +#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
  26.971 +#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
  26.972 +#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
  26.973 +#define E1000_EECD_FWE_MASK  0x00000030 
  26.974 +#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
  26.975 +#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
  26.976 +#define E1000_EECD_FWE_SHIFT 4
  26.977 +#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
  26.978 +#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
  26.979 +#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
  26.980 +#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
  26.981 +
  26.982 +/* EEPROM Read */
  26.983 +#define E1000_EERD_START      0x00000001 /* Start Read */
  26.984 +#define E1000_EERD_DONE       0x00000010 /* Read Done */
  26.985 +#define E1000_EERD_ADDR_SHIFT 8
  26.986 +#define E1000_EERD_ADDR_MASK  0x0000FF00 /* Read Address */
  26.987 +#define E1000_EERD_DATA_SHIFT 16
  26.988 +#define E1000_EERD_DATA_MASK  0xFFFF0000 /* Read Data */
  26.989 +
  26.990 +/* Extended Device Control */
  26.991 +#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */ 
  26.992 +#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
  26.993 +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
  26.994 +#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
  26.995 +#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
  26.996 +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
  26.997 +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
  26.998 +#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
  26.999 +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
 26.1000 +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
 26.1001 +#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
 26.1002 +#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
 26.1003 +#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
 26.1004 +#define E1000_CTRL_EXT_SDP7_DIR  0x00000800 /* Direction of SDP7 0=in 1=out */
 26.1005 +#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
 26.1006 +#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
 26.1007 +#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
 26.1008 +#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
 26.1009 +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
 26.1010 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
 26.1011 +#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
 26.1012 +#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
 26.1013 +#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
 26.1014 +#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
 26.1015 +#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
 26.1016 +#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
 26.1017 +
 26.1018 +/* MDI Control */
 26.1019 +#define E1000_MDIC_DATA_MASK 0x0000FFFF
 26.1020 +#define E1000_MDIC_REG_MASK  0x001F0000
 26.1021 +#define E1000_MDIC_REG_SHIFT 16
 26.1022 +#define E1000_MDIC_PHY_MASK  0x03E00000
 26.1023 +#define E1000_MDIC_PHY_SHIFT 21
 26.1024 +#define E1000_MDIC_OP_WRITE  0x04000000
 26.1025 +#define E1000_MDIC_OP_READ   0x08000000
 26.1026 +#define E1000_MDIC_READY     0x10000000
 26.1027 +#define E1000_MDIC_INT_EN    0x20000000
 26.1028 +#define E1000_MDIC_ERROR     0x40000000
 26.1029 +
 26.1030 +/* LED Control */
 26.1031 +#define E1000_LEDCTL_LED0_MODE_MASK  0x0000000F
 26.1032 +#define E1000_LEDCTL_LED0_MODE_SHIFT 0
 26.1033 +#define E1000_LEDCTL_LED0_IVRT       0x00000040
 26.1034 +#define E1000_LEDCTL_LED0_BLINK      0x00000080
 26.1035 +#define E1000_LEDCTL_LED1_MODE_MASK  0x00000F00
 26.1036 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8
 26.1037 +#define E1000_LEDCTL_LED1_IVRT       0x00004000
 26.1038 +#define E1000_LEDCTL_LED1_BLINK      0x00008000
 26.1039 +#define E1000_LEDCTL_LED2_MODE_MASK  0x000F0000
 26.1040 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16
 26.1041 +#define E1000_LEDCTL_LED2_IVRT       0x00400000
 26.1042 +#define E1000_LEDCTL_LED2_BLINK      0x00800000
 26.1043 +#define E1000_LEDCTL_LED3_MODE_MASK  0x0F000000
 26.1044 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24
 26.1045 +#define E1000_LEDCTL_LED3_IVRT       0x40000000
 26.1046 +#define E1000_LEDCTL_LED3_BLINK      0x80000000
 26.1047 +
 26.1048 +#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
 26.1049 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
 26.1050 +#define E1000_LEDCTL_MODE_LINK_UP       0x2
 26.1051 +#define E1000_LEDCTL_MODE_ACTIVITY      0x3
 26.1052 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
 26.1053 +#define E1000_LEDCTL_MODE_LINK_10       0x5
 26.1054 +#define E1000_LEDCTL_MODE_LINK_100      0x6
 26.1055 +#define E1000_LEDCTL_MODE_LINK_1000     0x7
 26.1056 +#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
 26.1057 +#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
 26.1058 +#define E1000_LEDCTL_MODE_COLLISION     0xA
 26.1059 +#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
 26.1060 +#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
 26.1061 +#define E1000_LEDCTL_MODE_PAUSED        0xD
 26.1062 +#define E1000_LEDCTL_MODE_LED_ON        0xE
 26.1063 +#define E1000_LEDCTL_MODE_LED_OFF       0xF
 26.1064 +
 26.1065 +/* Receive Address */
 26.1066 +#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 26.1067 +
 26.1068 +/* Interrupt Cause Read */
 26.1069 +#define E1000_ICR_TXDW    0x00000001    /* Transmit desc written back */
 26.1070 +#define E1000_ICR_TXQE    0x00000002    /* Transmit Queue empty */
 26.1071 +#define E1000_ICR_LSC     0x00000004    /* Link Status Change */
 26.1072 +#define E1000_ICR_RXSEQ   0x00000008    /* rx sequence error */
 26.1073 +#define E1000_ICR_RXDMT0  0x00000010    /* rx desc min. threshold (0) */
 26.1074 +#define E1000_ICR_RXO     0x00000040    /* rx overrun */
 26.1075 +#define E1000_ICR_RXT0    0x00000080    /* rx timer intr (ring 0) */
 26.1076 +#define E1000_ICR_MDAC    0x00000200    /* MDIO access complete */
 26.1077 +#define E1000_ICR_RXCFG   0x00000400    /* RX /c/ ordered set */
 26.1078 +#define E1000_ICR_GPI_EN0 0x00000800    /* GP Int 0 */
 26.1079 +#define E1000_ICR_GPI_EN1 0x00001000    /* GP Int 1 */
 26.1080 +#define E1000_ICR_GPI_EN2 0x00002000    /* GP Int 2 */
 26.1081 +#define E1000_ICR_GPI_EN3 0x00004000    /* GP Int 3 */
 26.1082 +#define E1000_ICR_TXD_LOW 0x00008000
 26.1083 +#define E1000_ICR_SRPD    0x00010000
 26.1084 +
 26.1085 +/* Interrupt Cause Set */
 26.1086 +#define E1000_ICS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
 26.1087 +#define E1000_ICS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
 26.1088 +#define E1000_ICS_LSC     E1000_ICR_LSC         /* Link Status Change */
 26.1089 +#define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
 26.1090 +#define E1000_ICS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
 26.1091 +#define E1000_ICS_RXO     E1000_ICR_RXO         /* rx overrun */
 26.1092 +#define E1000_ICS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
 26.1093 +#define E1000_ICS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
 26.1094 +#define E1000_ICS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
 26.1095 +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
 26.1096 +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
 26.1097 +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
 26.1098 +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
 26.1099 +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
 26.1100 +#define E1000_ICS_SRPD    E1000_ICR_SRPD
 26.1101 +
 26.1102 +/* Interrupt Mask Set */
 26.1103 +#define E1000_IMS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
 26.1104 +#define E1000_IMS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
 26.1105 +#define E1000_IMS_LSC     E1000_ICR_LSC         /* Link Status Change */
 26.1106 +#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
 26.1107 +#define E1000_IMS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
 26.1108 +#define E1000_IMS_RXO     E1000_ICR_RXO         /* rx overrun */
 26.1109 +#define E1000_IMS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
 26.1110 +#define E1000_IMS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
 26.1111 +#define E1000_IMS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
 26.1112 +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
 26.1113 +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
 26.1114 +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
 26.1115 +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
 26.1116 +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
 26.1117 +#define E1000_IMS_SRPD    E1000_ICR_SRPD
 26.1118 +
 26.1119 +/* Interrupt Mask Clear */
 26.1120 +#define E1000_IMC_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
 26.1121 +#define E1000_IMC_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
 26.1122 +#define E1000_IMC_LSC     E1000_ICR_LSC         /* Link Status Change */
 26.1123 +#define E1000_IMC_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
 26.1124 +#define E1000_IMC_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
 26.1125 +#define E1000_IMC_RXO     E1000_ICR_RXO         /* rx overrun */
 26.1126 +#define E1000_IMC_RXT0    E1000_ICR_RXT0        /* rx timer intr */
 26.1127 +#define E1000_IMC_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
 26.1128 +#define E1000_IMC_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
 26.1129 +#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
 26.1130 +#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
 26.1131 +#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
 26.1132 +#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
 26.1133 +#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
 26.1134 +#define E1000_IMC_SRPD    E1000_ICR_SRPD
 26.1135 +
 26.1136 +/* Receive Control */
 26.1137 +#define E1000_RCTL_RST          0x00000001      /* Software reset */
 26.1138 +#define E1000_RCTL_EN           0x00000002      /* enable */
 26.1139 +#define E1000_RCTL_SBP          0x00000004      /* store bad packet */
 26.1140 +#define E1000_RCTL_UPE          0x00000008      /* unicast promiscuous enable */
 26.1141 +#define E1000_RCTL_MPE          0x00000010      /* multicast promiscuous enab */
 26.1142 +#define E1000_RCTL_LPE          0x00000020      /* long packet enable */
 26.1143 +#define E1000_RCTL_LBM_NO       0x00000000      /* no loopback mode */
 26.1144 +#define E1000_RCTL_LBM_MAC      0x00000040      /* MAC loopback mode */
 26.1145 +#define E1000_RCTL_LBM_SLP      0x00000080      /* serial link loopback mode */
 26.1146 +#define E1000_RCTL_LBM_TCVR     0x000000C0      /* tcvr loopback mode */
 26.1147 +#define E1000_RCTL_RDMTS_HALF   0x00000000      /* rx desc min threshold size */
 26.1148 +#define E1000_RCTL_RDMTS_QUAT   0x00000100      /* rx desc min threshold size */
 26.1149 +#define E1000_RCTL_RDMTS_EIGTH  0x00000200      /* rx desc min threshold size */
 26.1150 +#define E1000_RCTL_MO_SHIFT     12              /* multicast offset shift */
 26.1151 +#define E1000_RCTL_MO_0         0x00000000      /* multicast offset 11:0 */
 26.1152 +#define E1000_RCTL_MO_1         0x00001000      /* multicast offset 12:1 */
 26.1153 +#define E1000_RCTL_MO_2         0x00002000      /* multicast offset 13:2 */
 26.1154 +#define E1000_RCTL_MO_3         0x00003000      /* multicast offset 15:4 */
 26.1155 +#define E1000_RCTL_MDR          0x00004000      /* multicast desc ring 0 */
 26.1156 +#define E1000_RCTL_BAM          0x00008000      /* broadcast enable */
 26.1157 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
 26.1158 +#define E1000_RCTL_SZ_2048      0x00000000      /* rx buffer size 2048 */
 26.1159 +#define E1000_RCTL_SZ_1024      0x00010000      /* rx buffer size 1024 */
 26.1160 +#define E1000_RCTL_SZ_512       0x00020000      /* rx buffer size 512 */
 26.1161 +#define E1000_RCTL_SZ_256       0x00030000      /* rx buffer size 256 */
 26.1162 +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
 26.1163 +#define E1000_RCTL_SZ_16384     0x00010000      /* rx buffer size 16384 */
 26.1164 +#define E1000_RCTL_SZ_8192      0x00020000      /* rx buffer size 8192 */
 26.1165 +#define E1000_RCTL_SZ_4096      0x00030000      /* rx buffer size 4096 */
 26.1166 +#define E1000_RCTL_VFE          0x00040000      /* vlan filter enable */
 26.1167 +#define E1000_RCTL_CFIEN        0x00080000      /* canonical form enable */
 26.1168 +#define E1000_RCTL_CFI          0x00100000      /* canonical form indicator */
 26.1169 +#define E1000_RCTL_DPF          0x00400000      /* discard pause frames */
 26.1170 +#define E1000_RCTL_PMCF         0x00800000      /* pass MAC control frames */
 26.1171 +#define E1000_RCTL_BSEX         0x02000000      /* Buffer size extension */
 26.1172 +
 26.1173 +/* Receive Descriptor */
 26.1174 +#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
 26.1175 +#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
 26.1176 +#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
 26.1177 +#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
 26.1178 +#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
 26.1179 +
 26.1180 +/* Flow Control */
 26.1181 +#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
 26.1182 +#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
 26.1183 +#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
 26.1184 +#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 26.1185 +
 26.1186 +/* Receive Descriptor Control */
 26.1187 +#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
 26.1188 +#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
 26.1189 +#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
 26.1190 +#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
 26.1191 +
 26.1192 +/* Transmit Descriptor Control */
 26.1193 +#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
 26.1194 +#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
 26.1195 +#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
 26.1196 +#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
 26.1197 +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
 26.1198 +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
 26.1199 +
 26.1200 +/* Transmit Configuration Word */
 26.1201 +#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
 26.1202 +#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
 26.1203 +#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
 26.1204 +#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
 26.1205 +#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
 26.1206 +#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
 26.1207 +#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
 26.1208 +#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
 26.1209 +#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
 26.1210 +#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
 26.1211 +
 26.1212 +/* Receive Configuration Word */
 26.1213 +#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
 26.1214 +#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
 26.1215 +#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
 26.1216 +#define E1000_RXCW_CC    0x10000000     /* Receive config change */
 26.1217 +#define E1000_RXCW_C     0x20000000     /* Receive config */
 26.1218 +#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
 26.1219 +#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
 26.1220 +
 26.1221 +/* Transmit Control */
 26.1222 +#define E1000_TCTL_RST    0x00000001    /* software reset */
 26.1223 +#define E1000_TCTL_EN     0x00000002    /* enable tx */
 26.1224 +#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
 26.1225 +#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
 26.1226 +#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
 26.1227 +#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 26.1228 +#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
 26.1229 +#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
 26.1230 +#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 26.1231 +#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
 26.1232 +
 26.1233 +/* Receive Checksum Control */
 26.1234 +#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
 26.1235 +#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
 26.1236 +#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
 26.1237 +#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
 26.1238 +
 26.1239 +/* Definitions for power management and wakeup registers */
 26.1240 +/* Wake Up Control */
 26.1241 +#define E1000_WUC_APME       0x00000001 /* APM Enable */
 26.1242 +#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
 26.1243 +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
 26.1244 +#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
 26.1245 +
 26.1246 +/* Wake Up Filter Control */
 26.1247 +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 26.1248 +#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 26.1249 +#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 26.1250 +#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 26.1251 +#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 26.1252 +#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 26.1253 +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 26.1254 +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 26.1255 +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 26.1256 +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 26.1257 +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 26.1258 +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 26.1259 +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
 26.1260 +#define E1000_WUFC_FLX_OFFSET 16       /* Offset to the Flexible Filters bits */
 26.1261 +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
 26.1262 +
 26.1263 +/* Wake Up Status */
 26.1264 +#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
 26.1265 +#define E1000_WUS_MAG  0x00000002 /* Magic Packet Received */
 26.1266 +#define E1000_WUS_EX   0x00000004 /* Directed Exact Received */
 26.1267 +#define E1000_WUS_MC   0x00000008 /* Directed Multicast Received */
 26.1268 +#define E1000_WUS_BC   0x00000010 /* Broadcast Received */
 26.1269 +#define E1000_WUS_ARP  0x00000020 /* ARP Request Packet Received */
 26.1270 +#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
 26.1271 +#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
 26.1272 +#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
 26.1273 +#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
 26.1274 +#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
 26.1275 +#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
 26.1276 +#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
 26.1277 +
 26.1278 +/* Management Control */
 26.1279 +#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 26.1280 +#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
 26.1281 +#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
 26.1282 +#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
 26.1283 +#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
 26.1284 +#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
 26.1285 +#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
 26.1286 +#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
 26.1287 +#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
 26.1288 +#define E1000_MANC_NEIGHBOR_EN   0x00004000 /* Enable Neighbor Discovery 
 26.1289 +                                             * Filtering */
 26.1290 +#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
 26.1291 +#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 26.1292 +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
 26.1293 +#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
 26.1294 +#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
 26.1295 +#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
 26.1296 +#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
 26.1297 +#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
 26.1298 +#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
 26.1299 +
 26.1300 +#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
 26.1301 +#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
 26.1302 +
 26.1303 +/* Wake Up Packet Length */
 26.1304 +#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
 26.1305 +
 26.1306 +#define E1000_MDALIGN          4096
 26.1307 +
 26.1308 +/* EEPROM Commands */
 26.1309 +#define EEPROM_READ_OPCODE  0x6  /* EERPOM read opcode */
 26.1310 +#define EEPROM_WRITE_OPCODE 0x5  /* EERPOM write opcode */
 26.1311 +#define EEPROM_ERASE_OPCODE 0x7  /* EERPOM erase opcode */
 26.1312 +#define EEPROM_EWEN_OPCODE  0x13 /* EERPOM erase/write enable */
 26.1313 +#define EEPROM_EWDS_OPCODE  0x10 /* EERPOM erast/write disable */
 26.1314 +
 26.1315 +/* EEPROM Word Offsets */
 26.1316 +#define EEPROM_COMPAT              0x0003
 26.1317 +#define EEPROM_ID_LED_SETTINGS     0x0004
 26.1318 +#define EEPROM_INIT_CONTROL1_REG   0x000A
 26.1319 +#define EEPROM_INIT_CONTROL2_REG   0x000F
 26.1320 +#define EEPROM_FLASH_VERSION       0x0032
 26.1321 +#define EEPROM_CHECKSUM_REG        0x003F
 26.1322 +
 26.1323 +/* Word definitions for ID LED Settings */
 26.1324 +#define ID_LED_RESERVED_0000 0x0000
 26.1325 +#define ID_LED_RESERVED_FFFF 0xFFFF
 26.1326 +#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
 26.1327 +                              (ID_LED_OFF1_OFF2 << 8) | \
 26.1328 +                              (ID_LED_DEF1_DEF2 << 4) | \
 26.1329 +                              (ID_LED_DEF1_DEF2))
 26.1330 +#define ID_LED_DEF1_DEF2     0x1
 26.1331 +#define ID_LED_DEF1_ON2      0x2
 26.1332 +#define ID_LED_DEF1_OFF2     0x3
 26.1333 +#define ID_LED_ON1_DEF2      0x4
 26.1334 +#define ID_LED_ON1_ON2       0x5
 26.1335 +#define ID_LED_ON1_OFF2      0x6
 26.1336 +#define ID_LED_OFF1_DEF2     0x7
 26.1337 +#define ID_LED_OFF1_ON2      0x8
 26.1338 +#define ID_LED_OFF1_OFF2     0x9
 26.1339 +
 26.1340 +/* Mask bits for fields in Word 0x03 of the EEPROM */
 26.1341 +#define EEPROM_COMPAT_SERVER 0x0400
 26.1342 +#define EEPROM_COMPAT_CLIENT 0x0200
 26.1343 +
 26.1344 +/* Mask bits for fields in Word 0x0a of the EEPROM */
 26.1345 +#define EEPROM_WORD0A_ILOS   0x0010
 26.1346 +#define EEPROM_WORD0A_SWDPIO 0x01E0
 26.1347 +#define EEPROM_WORD0A_LRST   0x0200
 26.1348 +#define EEPROM_WORD0A_FD     0x0400
 26.1349 +#define EEPROM_WORD0A_66MHZ  0x0800
 26.1350 +
 26.1351 +/* Mask bits for fields in Word 0x0f of the EEPROM */
 26.1352 +#define EEPROM_WORD0F_PAUSE_MASK 0x3000
 26.1353 +#define EEPROM_WORD0F_PAUSE      0x1000
 26.1354 +#define EEPROM_WORD0F_ASM_DIR    0x2000
 26.1355 +#define EEPROM_WORD0F_ANE        0x0800
 26.1356 +#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
 26.1357 +
 26.1358 +/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
 26.1359 +#define EEPROM_SUM 0xBABA
 26.1360 +
 26.1361 +/* EEPROM Map defines (WORD OFFSETS)*/
 26.1362 +#define EEPROM_NODE_ADDRESS_BYTE_0 0
 26.1363 +#define EEPROM_PBA_BYTE_1          8
 26.1364 +
 26.1365 +/* EEPROM Map Sizes (Byte Counts) */
 26.1366 +#define PBA_SIZE 4
 26.1367 +
 26.1368 +/* Collision related configuration parameters */
 26.1369 +#define E1000_COLLISION_THRESHOLD       16
 26.1370 +#define E1000_CT_SHIFT                  4
 26.1371 +#define E1000_COLLISION_DISTANCE        64
 26.1372 +#define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
 26.1373 +#define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
 26.1374 +#define E1000_GB_HDX_COLLISION_DISTANCE 512
 26.1375 +#define E1000_COLD_SHIFT                12
 26.1376 +
 26.1377 +/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
 26.1378 +#define REQ_TX_DESCRIPTOR_MULTIPLE  8
 26.1379 +#define REQ_RX_DESCRIPTOR_MULTIPLE  8
 26.1380 +
 26.1381 +/* Default values for the transmit IPG register */
 26.1382 +#define DEFAULT_82542_TIPG_IPGT        10
 26.1383 +#define DEFAULT_82543_TIPG_IPGT_FIBER  9
 26.1384 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8
 26.1385 +
 26.1386 +#define E1000_TIPG_IPGT_MASK  0x000003FF
 26.1387 +#define E1000_TIPG_IPGR1_MASK 0x000FFC00
 26.1388 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000
 26.1389 +
 26.1390 +#define DEFAULT_82542_TIPG_IPGR1 2
 26.1391 +#define DEFAULT_82543_TIPG_IPGR1 8
 26.1392 +#define E1000_TIPG_IPGR1_SHIFT  10
 26.1393 +
 26.1394 +#define DEFAULT_82542_TIPG_IPGR2 10
 26.1395 +#define DEFAULT_82543_TIPG_IPGR2 6
 26.1396 +#define E1000_TIPG_IPGR2_SHIFT  20
 26.1397 +
 26.1398 +#define E1000_TXDMAC_DPP 0x00000001
 26.1399 +
 26.1400 +/* Adaptive IFS defines */
 26.1401 +#define TX_THRESHOLD_START     8
 26.1402 +#define TX_THRESHOLD_INCREMENT 10
 26.1403 +#define TX_THRESHOLD_DECREMENT 1
 26.1404 +#define TX_THRESHOLD_STOP      190
 26.1405 +#define TX_THRESHOLD_DISABLE   0
 26.1406 +#define TX_THRESHOLD_TIMER_MS  10000
 26.1407 +#define MIN_NUM_XMITS          1000
 26.1408 +#define IFS_MAX                80
 26.1409 +#define IFS_STEP               10
 26.1410 +#define IFS_MIN                40
 26.1411 +#define IFS_RATIO              4
 26.1412 +
 26.1413 +/* PBA constants */
 26.1414 +#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
 26.1415 +#define E1000_PBA_24K 0x0018
 26.1416 +#define E1000_PBA_40K 0x0028
 26.1417 +#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
 26.1418 +
 26.1419 +/* Flow Control Constants */
 26.1420 +#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 26.1421 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 26.1422 +#define FLOW_CONTROL_TYPE         0x8808
 26.1423 +
 26.1424 +/* The historical defaults for the flow control values are given below. */
 26.1425 +#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
 26.1426 +#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
 26.1427 +#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
 26.1428 +
 26.1429 +/* PCIX Config space */
 26.1430 +#define PCIX_COMMAND_REGISTER    0xE6
 26.1431 +#define PCIX_STATUS_REGISTER_LO  0xE8
 26.1432 +#define PCIX_STATUS_REGISTER_HI  0xEA
 26.1433 +
 26.1434 +#define PCIX_COMMAND_MMRBC_MASK      0x000C
 26.1435 +#define PCIX_COMMAND_MMRBC_SHIFT     0x2
 26.1436 +#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
 26.1437 +#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
 26.1438 +#define PCIX_STATUS_HI_MMRBC_4K      0x3
 26.1439 +#define PCIX_STATUS_HI_MMRBC_2K      0x2
 26.1440 +
 26.1441 +
 26.1442 +/* The number of bits that we need to shift right to move the "pause"
 26.1443 + * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
 26.1444 + * in the TXCW register 
 26.1445 + */
 26.1446 +#define PAUSE_SHIFT 5
 26.1447 +
 26.1448 +/* The number of bits that we need to shift left to move the "SWDPIO"
 26.1449 + * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
 26.1450 + * in the CTRL register 
 26.1451 + */
 26.1452 +#define SWDPIO_SHIFT 17
 26.1453 +
 26.1454 +/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
 26.1455 + * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
 26.1456 + * Extended CTRL register.
 26.1457 + * in the CTRL register 
 26.1458 + */
 26.1459 +#define SWDPIO__EXT_SHIFT 4
 26.1460 +
 26.1461 +/* The number of bits that we need to shift left to move the "ILOS"
 26.1462 + * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
 26.1463 + * in the CTRL register 
 26.1464 + */
 26.1465 +#define ILOS_SHIFT  3
 26.1466 +
 26.1467 +
 26.1468 +#define RECEIVE_BUFFER_ALIGN_SIZE  (256)
 26.1469 +
 26.1470 +/* The number of milliseconds we wait for auto-negotiation to complete */
 26.1471 +#define LINK_UP_TIMEOUT             500
 26.1472 +
 26.1473 +#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
 26.1474 +
 26.1475 +/* The carrier extension symbol, as received by the NIC. */
 26.1476 +#define CARRIER_EXTENSION   0x0F
 26.1477 +
 26.1478 +/* TBI_ACCEPT macro definition:
 26.1479 + *
 26.1480 + * This macro requires:
 26.1481 + *      adapter = a pointer to struct e1000_hw 
 26.1482 + *      status = the 8 bit status field of the RX descriptor with EOP set
 26.1483 + *      error = the 8 bit error field of the RX descriptor with EOP set
 26.1484 + *      length = the sum of all the length fields of the RX descriptors that
 26.1485 + *               make up the current frame
 26.1486 + *      last_byte = the last byte of the frame DMAed by the hardware
 26.1487 + *      max_frame_length = the maximum frame length we want to accept.
 26.1488 + *      min_frame_length = the minimum frame length we want to accept.
 26.1489 + *
 26.1490 + * This macro is a conditional that should be used in the interrupt 
 26.1491 + * handler's Rx processing routine when RxErrors have been detected.
 26.1492 + *
 26.1493 + * Typical use:
 26.1494 + *  ...
 26.1495 + *  if (TBI_ACCEPT) {
 26.1496 + *      accept_frame = TRUE;
 26.1497 + *      e1000_tbi_adjust_stats(adapter, MacAddress);
 26.1498 + *      frame_length--;
 26.1499 + *  } else {
 26.1500 + *      accept_frame = FALSE;
 26.1501 + *  }
 26.1502 + *  ...
 26.1503 + */
 26.1504 +
 26.1505 +#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
 26.1506 +    ((adapter)->tbi_compatibility_on && \
 26.1507 +     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
 26.1508 +     ((last_byte) == CARRIER_EXTENSION) && \
 26.1509 +     (((status) & E1000_RXD_STAT_VP) ? \
 26.1510 +          (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
 26.1511 +           ((length) <= ((adapter)->max_frame_size + 1))) : \
 26.1512 +          (((length) > (adapter)->min_frame_size) && \
 26.1513 +           ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
 26.1514 +
 26.1515 +
 26.1516 +/* Structures, enums, and macros for the PHY */
 26.1517 +
 26.1518 +/* Bit definitions for the Management Data IO (MDIO) and Management Data
 26.1519 + * Clock (MDC) pins in the Device Control Register.
 26.1520 + */
 26.1521 +#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
 26.1522 +#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
 26.1523 +#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
 26.1524 +#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
 26.1525 +#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
 26.1526 +#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
 26.1527 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
 26.1528 +#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
 26.1529 +
 26.1530 +/* PHY 1000 MII Register/Bit Definitions */
 26.1531 +/* PHY Registers defined by IEEE */
 26.1532 +#define PHY_CTRL         0x00 /* Control Register */
 26.1533 +#define PHY_STATUS       0x01 /* Status Regiser */
 26.1534 +#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
 26.1535 +#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
 26.1536 +#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
 26.1537 +#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
 26.1538 +#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
 26.1539 +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
 26.1540 +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
 26.1541 +#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
 26.1542 +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
 26.1543 +#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
 26.1544 +
 26.1545 +/* M88E1000 Specific Registers */
 26.1546 +#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
 26.1547 +#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
 26.1548 +#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
 26.1549 +#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
 26.1550 +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
 26.1551 +#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
 26.1552 +
 26.1553 +#define MAX_PHY_REG_ADDRESS 0x1F        /* 5 bit address bus (0-0x1F) */
 26.1554 +
 26.1555 +/* PHY Control Register */
 26.1556 +#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
 26.1557 +#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
 26.1558 +#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 26.1559 +#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 26.1560 +#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
 26.1561 +#define MII_CR_POWER_DOWN       0x0800  /* Power down */
 26.1562 +#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 26.1563 +#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
 26.1564 +#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
 26.1565 +#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
 26.1566 +
 26.1567 +/* PHY Status Register */
 26.1568 +#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
 26.1569 +#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
 26.1570 +#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
 26.1571 +#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
 26.1572 +#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
 26.1573 +#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
 26.1574 +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
 26.1575 +#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
 26.1576 +#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
 26.1577 +#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
 26.1578 +#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
 26.1579 +#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
 26.1580 +#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
 26.1581 +#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
 26.1582 +#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
 26.1583 +
 26.1584 +/* Autoneg Advertisement Register */
 26.1585 +#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
 26.1586 +#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
 26.1587 +#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
 26.1588 +#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
 26.1589 +#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
 26.1590 +#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
 26.1591 +#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
 26.1592 +#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
 26.1593 +#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
 26.1594 +#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
 26.1595 +
 26.1596 +/* Link Partner Ability Register (Base Page) */
 26.1597 +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
 26.1598 +#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
 26.1599 +#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
 26.1600 +#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
 26.1601 +#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
 26.1602 +#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
 26.1603 +#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
 26.1604 +#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
 26.1605 +#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
 26.1606 +#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
 26.1607 +#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
 26.1608 +
 26.1609 +/* Autoneg Expansion Register */
 26.1610 +#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
 26.1611 +#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
 26.1612 +#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
 26.1613 +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
 26.1614 +#define NWAY_ER_PAR_DETECT_FAULT  0x0100 /* LP is 100TX Full Duplex Capable */
 26.1615 +
 26.1616 +/* Next Page TX Register */
 26.1617 +#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
 26.1618 +#define NPTX_TOGGLE         0x0800 /* Toggles between exchanges
 26.1619 +                                    * of different NP
 26.1620 +                                    */
 26.1621 +#define NPTX_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
 26.1622 +                                    * 0 = cannot comply with msg
 26.1623 +                                    */
 26.1624 +#define NPTX_MSG_PAGE       0x2000 /* formatted(1)/unformatted(0) pg */
 26.1625 +#define NPTX_NEXT_PAGE      0x8000 /* 1 = addition NP will follow 
 26.1626 +                                    * 0 = sending last NP
 26.1627 +                                    */
 26.1628 +
 26.1629 +/* Link Partner Next Page Register */
 26.1630 +#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
 26.1631 +#define LP_RNPR_TOGGLE         0x0800 /* Toggles between exchanges
 26.1632 +                                       * of different NP
 26.1633 +                                       */
 26.1634 +#define LP_RNPR_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg 
 26.1635 +                                       * 0 = cannot comply with msg
 26.1636 +                                       */
 26.1637 +#define LP_RNPR_MSG_PAGE       0x2000  /* formatted(1)/unformatted(0) pg */
 26.1638 +#define LP_RNPR_ACKNOWLDGE     0x4000  /* 1 = ACK / 0 = NO ACK */
 26.1639 +#define LP_RNPR_NEXT_PAGE      0x8000  /* 1 = addition NP will follow
 26.1640 +                                        * 0 = sending last NP 
 26.1641 +                                        */
 26.1642 +
 26.1643 +/* 1000BASE-T Control Register */
 26.1644 +#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
 26.1645 +#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
 26.1646 +#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
 26.1647 +#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
 26.1648 +                                        /* 0=DTE device */
 26.1649 +#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
 26.1650 +                                        /* 0=Configure PHY as Slave */
 26.1651 +#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
 26.1652 +                                        /* 0=Automatic Master/Slave config */
 26.1653 +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
 26.1654 +#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
 26.1655 +#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
 26.1656 +#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
 26.1657 +#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
 26.1658 +
 26.1659 +/* 1000BASE-T Status Register */
 26.1660 +#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
 26.1661 +#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
 26.1662 +#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
 26.1663 +#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
 26.1664 +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
 26.1665 +#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
 26.1666 +#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local TX is Master, 0=Slave */
 26.1667 +#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
 26.1668 +#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
 26.1669 +#define SR_1000T_LOCAL_RX_STATUS_SHIFT  13
 26.1670 +
 26.1671 +/* Extended Status Register */
 26.1672 +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
 26.1673 +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
 26.1674 +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
 26.1675 +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
 26.1676 +
 26.1677 +#define PHY_TX_POLARITY_MASK   0x0100 /* register 10h bit 8 (polarity bit) */
 26.1678 +#define PHY_TX_NORMAL_POLARITY 0      /* register 10h bit 8 (normal polarity) */
 26.1679 +
 26.1680 +#define AUTO_POLARITY_DISABLE  0x0010 /* register 11h bit 4 */
 26.1681 +                                      /* (0=enable, 1=disable) */
 26.1682 +
 26.1683 +/* M88E1000 PHY Specific Control Register */
 26.1684 +#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
 26.1685 +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
 26.1686 +#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
 26.1687 +#define M88E1000_PSCR_CLK125_DISABLE    0x0010 /* 1=CLK125 low, 
 26.1688 +                                                * 0=CLK125 toggling
 26.1689 +                                                */
 26.1690 +#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
 26.1691 +                                               /* Manual MDI configuration */
 26.1692 +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
 26.1693 +#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,
 26.1694 +                                                *  100BASE-TX/10BASE-T: 
 26.1695 +                                                *  MDI Mode
 26.1696 +                                                */
 26.1697 +#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled 
 26.1698 +                                                * all speeds. 
 26.1699 +                                                */
 26.1700 +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 
 26.1701 +                                        /* 1=Enable Extended 10BASE-T distance
 26.1702 +                                         * (Lower 10BASE-T RX Threshold)
 26.1703 +                                         * 0=Normal 10BASE-T RX Threshold */
 26.1704 +#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
 26.1705 +                                        /* 1=5-Bit interface in 100BASE-TX
 26.1706 +                                         * 0=MII interface in 100BASE-TX */
 26.1707 +#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
 26.1708 +#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
 26.1709 +#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
 26.1710 +
 26.1711 +#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
 26.1712 +#define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
 26.1713 +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
 26.1714 +
 26.1715 +/* M88E1000 PHY Specific Status Register */
 26.1716 +#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
 26.1717 +#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
 26.1718 +#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
 26.1719 +#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
 26.1720 +                                            * 3=110-140M;4=>140M */
 26.1721 +#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
 26.1722 +#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
 26.1723 +#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
 26.1724 +#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
 26.1725 +#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
 26.1726 +#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
 26.1727 +#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
 26.1728 +#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
 26.1729 +
 26.1730 +#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
 26.1731 +#define M88E1000_PSSR_MDIX_SHIFT         6
 26.1732 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 26.1733 +
 26.1734 +/* M88E1000 Extended PHY Specific Control Register */
 26.1735 +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
 26.1736 +#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000 /* 1=Lost lock detect enabled.
 26.1737 +                                              * Will assert lost lock and bring
 26.1738 +                                              * link down if idle not seen
 26.1739 +                                              * within 1ms in 1000BASE-T 
 26.1740 +                                              */
 26.1741 +/* Number of times we will attempt to autonegotiate before downshifting if we
 26.1742 + * are the master */
 26.1743 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
 26.1744 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000    
 26.1745 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
 26.1746 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
 26.1747 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
 26.1748 +/* Number of times we will attempt to autonegotiate before downshifting if we
 26.1749 + * are the slave */
 26.1750 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
 26.1751 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
 26.1752 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 26.1753 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
 26.1754 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
 26.1755 +#define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
 26.1756 +#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
 26.1757 +#define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
 26.1758 +
 26.1759 +/* Bit definitions for valid PHY IDs. */
 26.1760 +#define M88E1000_E_PHY_ID  0x01410C50
 26.1761 +#define M88E1000_I_PHY_ID  0x01410C30
 26.1762 +#define M88E1011_I_PHY_ID  0x01410C20
 26.1763 +#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
 26.1764 +#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
 26.1765 +#define M88E1011_I_REV_4   0x04
 26.1766 +
 26.1767 +/* Miscellaneous PHY bit definitions. */
 26.1768 +#define PHY_PREAMBLE        0xFFFFFFFF
 26.1769 +#define PHY_SOF             0x01
 26.1770 +#define PHY_OP_READ         0x02
 26.1771 +#define PHY_OP_WRITE        0x01
 26.1772 +#define PHY_TURNAROUND      0x02
 26.1773 +#define PHY_PREAMBLE_SIZE   32
 26.1774 +#define MII_CR_SPEED_1000   0x0040
 26.1775 +#define MII_CR_SPEED_100    0x2000
 26.1776 +#define MII_CR_SPEED_10     0x0000
 26.1777 +#define E1000_PHY_ADDRESS   0x01
 26.1778 +#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
 26.1779 +#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
 26.1780 +#define PHY_REVISION_MASK   0xFFFFFFF0
 26.1781 +#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
 26.1782 +#define REG4_SPEED_MASK     0x01E0
 26.1783 +#define REG9_SPEED_MASK     0x0300
 26.1784 +#define ADVERTISE_10_HALF   0x0001
 26.1785 +#define ADVERTISE_10_FULL   0x0002
 26.1786 +#define ADVERTISE_100_HALF  0x0004
 26.1787 +#define ADVERTISE_100_FULL  0x0008
 26.1788 +#define ADVERTISE_1000_HALF 0x0010
 26.1789 +#define ADVERTISE_1000_FULL 0x0020
 26.1790 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
 26.1791 +
 26.1792 +#endif /* _E1000_HW_H_ */
    27.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.2 +++ b/xen-2.4.16/drivers/net/e1000/e1000_main.c	Tue Feb 11 16:51:47 2003 +0000
    27.3 @@ -0,0 +1,2284 @@
    27.4 +/*******************************************************************************
    27.5 +
    27.6 +  
    27.7 +  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
    27.8 +  
    27.9 +  This program is free software; you can redistribute it and/or modify it 
   27.10 +  under the terms of the GNU General Public License as published by the Free 
   27.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   27.12 +  any later version.
   27.13 +  
   27.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   27.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   27.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   27.17 +  more details.
   27.18 +  
   27.19 +  You should have received a copy of the GNU General Public License along with
   27.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   27.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   27.22 +  
   27.23 +  The full GNU General Public License is included in this distribution in the
   27.24 +  file called LICENSE.
   27.25 +  
   27.26 +  Contact Information:
   27.27 +  Linux NICS <linux.nics@intel.com>
   27.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   27.29 +
   27.30 +*******************************************************************************/
   27.31 +
   27.32 +#include "e1000.h"
   27.33 +
   27.34 +/* Change Log
   27.35 + *
   27.36 + * 4.4.19       11/27/02
   27.37 + *   o Feature: Added user-settable knob for interrupt throttle rate (ITR).
   27.38 + *   o Cleanup: removed large static array allocations.
   27.39 + *   o Cleanup: C99 struct initializer format.
   27.40 + *   o Bug fix: restore VLAN settings when interface is brought up.
   27.41 + *   o Bug fix: return cleanly in probe if error in detecting MAC type.
   27.42 + *   o Bug fix: Wake up on magic packet by default only if enabled in eeprom.
   27.43 + *   o Bug fix: Validate MAC address in set_mac.
   27.44 + *   o Bug fix: Throw away zero-length Tx skbs.
   27.45 + *   o Bug fix: Make ethtool EEPROM acceses work on older versions of ethtool.
   27.46 + * 
   27.47 + * 4.4.12       10/15/02
   27.48 + *   o Clean up: use members of pci_device rather than direct calls to
   27.49 + *     pci_read_config_word.
   27.50 + *   o Bug fix: changed default flow control settings.
   27.51 + *   o Clean up: ethtool file now has an inclusive list for adapters in the
   27.52 + *     Wake-On-LAN capabilities instead of an exclusive list.
   27.53 + *   o Bug fix: miscellaneous WoL bug fixes.
   27.54 + *   o Added software interrupt for clearing rx ring
   27.55 + *   o Bug fix: easier to undo "forcing" of 1000/fd using ethtool.
   27.56 + *   o Now setting netdev->mem_end in e1000_probe.
   27.57 + *   o Clean up: Moved tx_timeout from interrupt context to process context
   27.58 + *     using schedule_task.
   27.59 + * 
   27.60 + * 4.3.15       8/9/02
   27.61 + */
   27.62 +
   27.63 +char e1000_driver_name[] = "e1000";
   27.64 +char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
   27.65 +char e1000_driver_version[] = "4.4.19-k2";
   27.66 +char e1000_copyright[] = "Copyright (c) 1999-2002 Intel Corporation.";
   27.67 +
   27.68 +/* e1000_pci_tbl - PCI Device ID Table
   27.69 + *
   27.70 + * Private driver_data field (last one) stores an index into e1000_strings
   27.71 + * Wildcard entries (PCI_ANY_ID) should come last
   27.72 + * Last entry must be all 0s
   27.73 + *
   27.74 + * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
   27.75 + *   Class, Class Mask, String Index }
   27.76 + */
   27.77 +static struct pci_device_id e1000_pci_tbl[] __devinitdata = {
   27.78 +	/* Intel(R) PRO/1000 Network Connection */
   27.79 +	{0x8086, 0x1000, 0x8086, 0x1000, 0, 0, 0},
   27.80 +	{0x8086, 0x1001, 0x8086, 0x1003, 0, 0, 0},
   27.81 +	{0x8086, 0x1004, 0x8086, 0x1004, 0, 0, 0},
   27.82 +	{0x8086, 0x1008, 0x8086, 0x1107, 0, 0, 0},
   27.83 +	{0x8086, 0x1009, 0x8086, 0x1109, 0, 0, 0},
   27.84 +	{0x8086, 0x100C, 0x8086, 0x1112, 0, 0, 0},
   27.85 +	{0x8086, 0x100E, 0x8086, 0x001E, 0, 0, 0},
   27.86 +	/* Compaq Gigabit Ethernet Server Adapter */
   27.87 +	{0x8086, 0x1000, 0x0E11, PCI_ANY_ID, 0, 0, 1},
   27.88 +	{0x8086, 0x1001, 0x0E11, PCI_ANY_ID, 0, 0, 1},
   27.89 +	{0x8086, 0x1004, 0x0E11, PCI_ANY_ID, 0, 0, 1},
   27.90 +	/* IBM Mobile, Desktop & Server Adapters */
   27.91 +	{0x8086, 0x1000, 0x1014, PCI_ANY_ID, 0, 0, 2},
   27.92 +	{0x8086, 0x1001, 0x1014, PCI_ANY_ID, 0, 0, 2},
   27.93 +	{0x8086, 0x1004, 0x1014, PCI_ANY_ID, 0, 0, 2},
   27.94 +	/* Generic */
   27.95 +	{0x8086, 0x1000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   27.96 +	{0x8086, 0x1001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   27.97 +	{0x8086, 0x1004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   27.98 +	{0x8086, 0x1008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
   27.99 +	{0x8086, 0x1009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.100 +	{0x8086, 0x100C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.101 +	{0x8086, 0x100D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.102 +	{0x8086, 0x100E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.103 +	{0x8086, 0x100F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.104 +	{0x8086, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.105 +	{0x8086, 0x1010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.106 +	{0x8086, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.107 +	{0x8086, 0x1016, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.108 +	{0x8086, 0x1017, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.109 +	{0x8086, 0x101E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  27.110 +	/* required last entry */
  27.111 +	{0,}
  27.112 +};
  27.113 +
  27.114 +MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
  27.115 +
  27.116 +static char *e1000_strings[] = {
  27.117 +	"Intel(R) PRO/1000 Network Connection",
  27.118 +	"Compaq Gigabit Ethernet Server Adapter",
  27.119 +	"IBM Mobile, Desktop & Server Adapters"
  27.120 +};
  27.121 +
  27.122 +/* Local Function Prototypes */
  27.123 +
  27.124 +int e1000_up(struct e1000_adapter *adapter);
  27.125 +void e1000_down(struct e1000_adapter *adapter);
  27.126 +void e1000_reset(struct e1000_adapter *adapter);
  27.127 +
  27.128 +static int e1000_init_module(void);
  27.129 +static void e1000_exit_module(void);
  27.130 +static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  27.131 +static void e1000_remove(struct pci_dev *pdev);
  27.132 +static int e1000_sw_init(struct e1000_adapter *adapter);
  27.133 +static int e1000_open(struct net_device *netdev);
  27.134 +static int e1000_close(struct net_device *netdev);
  27.135 +static int e1000_setup_tx_resources(struct e1000_adapter *adapter);
  27.136 +static int e1000_setup_rx_resources(struct e1000_adapter *adapter);
  27.137 +static void e1000_configure_tx(struct e1000_adapter *adapter);
  27.138 +static void e1000_configure_rx(struct e1000_adapter *adapter);
  27.139 +static void e1000_setup_rctl(struct e1000_adapter *adapter);
  27.140 +static void e1000_clean_tx_ring(struct e1000_adapter *adapter);
  27.141 +static void e1000_clean_rx_ring(struct e1000_adapter *adapter);
  27.142 +static void e1000_free_tx_resources(struct e1000_adapter *adapter);
  27.143 +static void e1000_free_rx_resources(struct e1000_adapter *adapter);
  27.144 +static void e1000_set_multi(struct net_device *netdev);
  27.145 +static void e1000_update_phy_info(unsigned long data);
  27.146 +static void e1000_watchdog(unsigned long data);
  27.147 +static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  27.148 +static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
  27.149 +static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
  27.150 +static int e1000_set_mac(struct net_device *netdev, void *p);
  27.151 +static void e1000_update_stats(struct e1000_adapter *adapter);
  27.152 +static inline void e1000_irq_disable(struct e1000_adapter *adapter);
  27.153 +static inline void e1000_irq_enable(struct e1000_adapter *adapter);
  27.154 +static void e1000_intr(int irq, void *data, struct pt_regs *regs);
  27.155 +static void e1000_clean_tx_irq(struct e1000_adapter *adapter);
  27.156 +static void e1000_clean_rx_irq(struct e1000_adapter *adapter);
  27.157 +static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter);
  27.158 +static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
  27.159 +static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
  27.160 +static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
  27.161 +static inline void e1000_rx_checksum(struct e1000_adapter *adapter,
  27.162 +                                     struct e1000_rx_desc *rx_desc,
  27.163 +                                     struct sk_buff *skb);
  27.164 +static void e1000_tx_timeout(struct net_device *dev);
  27.165 +static void e1000_tx_timeout_task(struct net_device *dev);
  27.166 +
  27.167 +static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
  27.168 +static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
  27.169 +static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
  27.170 +static void e1000_restore_vlan(struct e1000_adapter *adapter);
  27.171 +
  27.172 +static int e1000_notify_reboot(struct notifier_block *, unsigned long event, void *ptr);
  27.173 +static int e1000_suspend(struct pci_dev *pdev, uint32_t state);
  27.174 +#ifdef CONFIG_PM
  27.175 +static int e1000_resume(struct pci_dev *pdev);
  27.176 +#endif
  27.177 +
  27.178 +struct notifier_block e1000_notifier_reboot = {
  27.179 +	.notifier_call	= e1000_notify_reboot,
  27.180 +	.next		= NULL,
  27.181 +	.priority	= 0
  27.182 +};
  27.183 +
  27.184 +/* Exported from other modules */
  27.185 +
  27.186 +extern void e1000_check_options(struct e1000_adapter *adapter);
  27.187 +extern int e1000_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr);
  27.188 +
  27.189 +static struct pci_driver e1000_driver = {
  27.190 +	.name     = e1000_driver_name,
  27.191 +	.id_table = e1000_pci_tbl,
  27.192 +	.probe    = e1000_probe,
  27.193 +	.remove   = __devexit_p(e1000_remove),
  27.194 +	/* Power Managment Hooks */
  27.195 +#ifdef CONFIG_PM
  27.196 +	.suspend  = e1000_suspend,
  27.197 +	.resume   = e1000_resume
  27.198 +#endif
  27.199 +};
  27.200 +
  27.201 +MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  27.202 +MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
  27.203 +MODULE_LICENSE("GPL");
  27.204 +
  27.205 +/**
  27.206 + * e1000_init_module - Driver Registration Routine
  27.207 + *
  27.208 + * e1000_init_module is the first routine called when the driver is
  27.209 + * loaded. All it does is register with the PCI subsystem.
  27.210 + **/
  27.211 +
  27.212 +static int __init
  27.213 +e1000_init_module(void)
  27.214 +{
  27.215 +	int ret;
  27.216 +
  27.217 +#if 0 /* Avoid disconcerting noise. */
  27.218 +	printk(KERN_INFO "%s - version %s\n",
  27.219 +	       e1000_driver_string, e1000_driver_version);
  27.220 +
  27.221 +	printk(KERN_INFO "%s\n", e1000_copyright);
  27.222 +#endif
  27.223 +
  27.224 +	ret = pci_module_init(&e1000_driver);
  27.225 +//	if(ret >= 0)
  27.226 +//		register_reboot_notifier(&e1000_notifier_reboot);
  27.227 +	return ret;
  27.228 +}
  27.229 +
  27.230 +module_init(e1000_init_module);
  27.231 +
  27.232 +/**
  27.233 + * e1000_exit_module - Driver Exit Cleanup Routine
  27.234 + *
  27.235 + * e1000_exit_module is called just before the driver is removed
  27.236 + * from memory.
  27.237 + **/
  27.238 +
  27.239 +static void __exit
  27.240 +e1000_exit_module(void)
  27.241 +{
  27.242 +//	unregister_reboot_notifier(&e1000_notifier_reboot);
  27.243 +	pci_unregister_driver(&e1000_driver);
  27.244 +}
  27.245 +
  27.246 +module_exit(e1000_exit_module);
  27.247 +
  27.248 +
  27.249 +int
  27.250 +e1000_up(struct e1000_adapter *adapter)
  27.251 +{
  27.252 +	struct net_device *netdev = adapter->netdev;
  27.253 +
  27.254 +	if(request_irq(netdev->irq, &e1000_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
  27.255 +	               netdev->name, netdev))
  27.256 +		return -1;
  27.257 +
  27.258 +	/* hardware has been reset, we need to reload some things */
  27.259 +
  27.260 +	e1000_set_multi(netdev);
  27.261 +	e1000_restore_vlan(adapter);
  27.262 +
  27.263 +	e1000_configure_tx(adapter);
  27.264 +	e1000_setup_rctl(adapter);
  27.265 +	e1000_configure_rx(adapter);
  27.266 +	e1000_alloc_rx_buffers(adapter);
  27.267 +
  27.268 +	mod_timer(&adapter->watchdog_timer, jiffies);
  27.269 +	e1000_irq_enable(adapter);
  27.270 +
  27.271 +	return 0;
  27.272 +}
  27.273 +
  27.274 +void
  27.275 +e1000_down(struct e1000_adapter *adapter)
  27.276 +{
  27.277 +	struct net_device *netdev = adapter->netdev;
  27.278 +
  27.279 +	e1000_irq_disable(adapter);
  27.280 +	free_irq(netdev->irq, netdev);
  27.281 +	del_timer_sync(&adapter->watchdog_timer);
  27.282 +	del_timer_sync(&adapter->phy_info_timer);
  27.283 +	adapter->link_speed = 0;
  27.284 +	adapter->link_duplex = 0;
  27.285 +	netif_carrier_off(netdev);
  27.286 +	netif_stop_queue(netdev);
  27.287 +
  27.288 +	e1000_reset(adapter);
  27.289 +	e1000_clean_tx_ring(adapter);
  27.290 +	e1000_clean_rx_ring(adapter);
  27.291 +}
  27.292 +
  27.293 +void
  27.294 +e1000_reset(struct e1000_adapter *adapter)
  27.295 +{
  27.296 +	/* Repartition Pba for greater than 9k mtu
  27.297 +	 * To take effect CTRL.RST is required.
  27.298 +	 */
  27.299 +
  27.300 +	if(adapter->rx_buffer_len > E1000_RXBUFFER_8192)
  27.301 +		E1000_WRITE_REG(&adapter->hw, PBA, E1000_JUMBO_PBA);
  27.302 +	else
  27.303 +		E1000_WRITE_REG(&adapter->hw, PBA, E1000_DEFAULT_PBA);
  27.304 +
  27.305 +	adapter->hw.fc = adapter->hw.original_fc;
  27.306 +	e1000_reset_hw(&adapter->hw);
  27.307 +printk("RESET_H/W\n");
  27.308 +	if(adapter->hw.mac_type >= e1000_82544)
  27.309 +		E1000_WRITE_REG(&adapter->hw, WUC, 0);
  27.310 +	e1000_init_hw(&adapter->hw);
  27.311 +printk("INIT H/W\n");
  27.312 +	e1000_reset_adaptive(&adapter->hw);
  27.313 +	e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
  27.314 +}
  27.315 +
  27.316 +/**
  27.317 + * e1000_probe - Device Initialization Routine
  27.318 + * @pdev: PCI device information struct
  27.319 + * @ent: entry in e1000_pci_tbl
  27.320 + *
  27.321 + * Returns 0 on success, negative on failure
  27.322 + *
  27.323 + * e1000_probe initializes an adapter identified by a pci_dev structure.
  27.324 + * The OS initialization, configuring of the adapter private structure,
  27.325 + * and a hardware reset occur.
  27.326 + **/
  27.327 +
  27.328 +static int __devinit
  27.329 +e1000_probe(struct pci_dev *pdev,
  27.330 +            const struct pci_device_id *ent)
  27.331 +{
  27.332 +	struct net_device *netdev;
  27.333 +	struct e1000_adapter *adapter;
  27.334 +	static int cards_found = 0;
  27.335 +	unsigned long mmio_start;
  27.336 +	int mmio_len;
  27.337 +	int pci_using_dac;
  27.338 +	int i;
  27.339 +	uint16_t eeprom_data;
  27.340 +
  27.341 +	if((i = pci_enable_device(pdev)))
  27.342 +		return i;
  27.343 +
  27.344 +	if(!(i = pci_set_dma_mask(pdev, PCI_DMA_64BIT))) {
  27.345 +		pci_using_dac = 1;
  27.346 +	} else {
  27.347 +		if((i = pci_set_dma_mask(pdev, PCI_DMA_32BIT))) {
  27.348 +			E1000_ERR("No usable DMA configuration, aborting\n");
  27.349 +			return i;
  27.350 +		}
  27.351 +		pci_using_dac = 0;
  27.352 +	}
  27.353 +
  27.354 +	if((i = pci_request_regions(pdev, e1000_driver_name)))
  27.355 +		return i;
  27.356 +
  27.357 +	pci_set_master(pdev);
  27.358 +
  27.359 +	netdev = alloc_etherdev(sizeof(struct e1000_adapter));
  27.360 +	if(!netdev)
  27.361 +		goto err_alloc_etherdev;
  27.362 +
  27.363 +	SET_MODULE_OWNER(netdev);
  27.364 +
  27.365 +	pci_set_drvdata(pdev, netdev);
  27.366 +	adapter = netdev->priv;
  27.367 +	adapter->netdev = netdev;
  27.368 +	adapter->pdev = pdev;
  27.369 +	adapter->hw.back = adapter;
  27.370 +
  27.371 +	mmio_start = pci_resource_start(pdev, BAR_0);
  27.372 +	mmio_len = pci_resource_len(pdev, BAR_0);
  27.373 +
  27.374 +	adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
  27.375 +	if(!adapter->hw.hw_addr)
  27.376 +		goto err_ioremap;
  27.377 +
  27.378 +	for(i = BAR_1; i <= BAR_5; i++) {
  27.379 +		if(pci_resource_len(pdev, i) == 0)
  27.380 +			continue;
  27.381 +		if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  27.382 +			adapter->hw.io_base = pci_resource_start(pdev, i);
  27.383 +			break;
  27.384 +		}
  27.385 +	}
  27.386 +
  27.387 +	netdev->open = &e1000_open;
  27.388 +	netdev->stop = &e1000_close;
  27.389 +	netdev->hard_start_xmit = &e1000_xmit_frame;
  27.390 +	netdev->get_stats = &e1000_get_stats;
  27.391 +	netdev->set_multicast_list = &e1000_set_multi;
  27.392 +	netdev->set_mac_address = &e1000_set_mac;
  27.393 +	netdev->change_mtu = &e1000_change_mtu;
  27.394 +	netdev->do_ioctl = &e1000_ioctl;
  27.395 +	netdev->tx_timeout = &e1000_tx_timeout;
  27.396 +	netdev->watchdog_timeo = HZ;
  27.397 +	netdev->vlan_rx_register = e1000_vlan_rx_register;
  27.398 +	netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
  27.399 +	netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
  27.400 +
  27.401 +	netdev->irq = pdev->irq;
  27.402 +	netdev->mem_start = mmio_start;
  27.403 +	netdev->mem_end = mmio_start + mmio_len;
  27.404 +	netdev->base_addr = adapter->hw.io_base;
  27.405 +
  27.406 +	adapter->bd_number = cards_found;
  27.407 +	adapter->id_string = e1000_strings[ent->driver_data];
  27.408 +
  27.409 +	/* setup the private structure */
  27.410 +
  27.411 +	if(e1000_sw_init(adapter))
  27.412 +		goto err_sw_init;
  27.413 +
  27.414 +	if(adapter->hw.mac_type >= e1000_82543) {
  27.415 +		netdev->features = NETIF_F_SG |
  27.416 +			           NETIF_F_HW_CSUM |
  27.417 +		       	           NETIF_F_HW_VLAN_TX |
  27.418 +		                   NETIF_F_HW_VLAN_RX |
  27.419 +				   NETIF_F_HW_VLAN_FILTER;
  27.420 +	} else {
  27.421 +		netdev->features = NETIF_F_SG;
  27.422 +	}
  27.423 +
  27.424 +	if(pci_using_dac)
  27.425 +		netdev->features |= NETIF_F_HIGHDMA;
  27.426 +
  27.427 +	/* make sure the EEPROM is good */
  27.428 +
  27.429 +	if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
  27.430 +		printk(KERN_ERR "The EEPROM Checksum Is Not Valid\n");
  27.431 +		goto err_eeprom;
  27.432 +	}
  27.433 +
  27.434 +	/* copy the MAC address out of the EEPROM */
  27.435 +
  27.436 +	e1000_read_mac_addr(&adapter->hw);
  27.437 +	memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  27.438 +
  27.439 +	if(!is_valid_ether_addr(netdev->dev_addr))
  27.440 +		goto err_eeprom;
  27.441 +
  27.442 +	e1000_read_part_num(&adapter->hw, &(adapter->part_num));
  27.443 +
  27.444 +	e1000_get_bus_info(&adapter->hw);
  27.445 +
  27.446 +	if((adapter->hw.mac_type == e1000_82544) &&
  27.447 +	   (adapter->hw.bus_type == e1000_bus_type_pcix))
  27.448 +
  27.449 +		adapter->max_data_per_txd = 4096;
  27.450 +	else
  27.451 +		adapter->max_data_per_txd = MAX_JUMBO_FRAME_SIZE;
  27.452 +
  27.453 +
  27.454 +	init_timer(&adapter->watchdog_timer);
  27.455 +	adapter->watchdog_timer.function = &e1000_watchdog;
  27.456 +	adapter->watchdog_timer.data = (unsigned long) adapter;
  27.457 +
  27.458 +	init_timer(&adapter->phy_info_timer);
  27.459 +	adapter->phy_info_timer.function = &e1000_update_phy_info;
  27.460 +	adapter->phy_info_timer.data = (unsigned long) adapter;
  27.461 +
  27.462 +	INIT_TQUEUE(&adapter->tx_timeout_task,
  27.463 +		(void (*)(void *))e1000_tx_timeout_task, netdev);
  27.464 +
  27.465 +	register_netdev(netdev);
  27.466 +	memcpy(adapter->ifname, netdev->name, IFNAMSIZ);
  27.467 +	adapter->ifname[IFNAMSIZ-1] = 0;
  27.468 +
  27.469 +	/* we're going to reset, so assume we have no link for now */
  27.470 +
  27.471 +	netif_carrier_off(netdev);
  27.472 +	netif_stop_queue(netdev);
  27.473 +
  27.474 +	printk(KERN_INFO "%s: %s\n", netdev->name, adapter->id_string);
  27.475 +	e1000_check_options(adapter);
  27.476 +printk("OPTIONS OVER\n");
  27.477 +	/* Initial Wake on LAN setting
  27.478 +	 * If APM wake is enabled in the EEPROM,
  27.479 +	 * enable the ACPI Magic Packet filter
  27.480 +	 */
  27.481 +
  27.482 +	e1000_read_eeprom(&adapter->hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data);
  27.483 +printk("EPROM OVER\n");
  27.484 +	if((adapter->hw.mac_type >= e1000_82544) &&
  27.485 +	   (eeprom_data & E1000_EEPROM_APME))
  27.486 +		adapter->wol |= E1000_WUFC_MAG;
  27.487 +
  27.488 +	/* reset the hardware with the new settings */
  27.489 +
  27.490 +	e1000_reset(adapter);
  27.491 +printk("PROBE OVER\n");
  27.492 +	cards_found++;
  27.493 +	return 0;
  27.494 +
  27.495 +err_sw_init:
  27.496 +err_eeprom:
  27.497 +	iounmap(adapter->hw.hw_addr);
  27.498 +err_ioremap:
  27.499 +	pci_release_regions(pdev);
  27.500 +	kfree(netdev);
  27.501 +err_alloc_etherdev:
  27.502 +	return -ENOMEM;
  27.503 +}
  27.504 +
  27.505 +/**
  27.506 + * e1000_remove - Device Removal Routine
  27.507 + * @pdev: PCI device information struct
  27.508 + *
  27.509 + * e1000_remove is called by the PCI subsystem to alert the driver
  27.510 + * that it should release a PCI device.  The could be caused by a
  27.511 + * Hot-Plug event, or because the driver is going to be removed from
  27.512 + * memory.
  27.513 + **/
  27.514 +
  27.515 +static void __devexit
  27.516 +e1000_remove(struct pci_dev *pdev)
  27.517 +{
  27.518 +	struct net_device *netdev = pci_get_drvdata(pdev);
  27.519 +	struct e1000_adapter *adapter = netdev->priv;
  27.520 +	uint32_t manc;
  27.521 +
  27.522 +	if(adapter->hw.mac_type >= e1000_82540) {
  27.523 +		manc = E1000_READ_REG(&adapter->hw, MANC);
  27.524 +		if(manc & E1000_MANC_SMBUS_EN) {
  27.525 +			manc |= E1000_MANC_ARP_EN;
  27.526 +			E1000_WRITE_REG(&adapter->hw, MANC, manc);
  27.527 +		}
  27.528 +	}
  27.529 +
  27.530 +	unregister_netdev(netdev);
  27.531 +
  27.532 +	e1000_phy_hw_reset(&adapter->hw);
  27.533 +
  27.534 +	iounmap(adapter->hw.hw_addr);
  27.535 +	pci_release_regions(pdev);
  27.536 +
  27.537 +	kfree(netdev);
  27.538 +}
  27.539 +
  27.540 +/**
  27.541 + * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  27.542 + * @adapter: board private structure to initialize
  27.543 + *
  27.544 + * e1000_sw_init initializes the Adapter private data structure.
  27.545 + * Fields are initialized based on PCI device information and
  27.546 + * OS network device settings (MTU size).
  27.547 + **/
  27.548 +
  27.549 +static int __devinit
  27.550 +e1000_sw_init(struct e1000_adapter *adapter)
  27.551 +{
  27.552 +	struct e1000_hw *hw = &adapter->hw;
  27.553 +	struct net_device *netdev = adapter->netdev;
  27.554 +	struct pci_dev *pdev = adapter->pdev;
  27.555 +
  27.556 +	/* PCI config space info */
  27.557 +
  27.558 +	hw->vendor_id = pdev->vendor;
  27.559 +	hw->device_id = pdev->device;
  27.560 +	hw->subsystem_vendor_id = pdev->subsystem_vendor;
  27.561 +	hw->subsystem_id = pdev->subsystem_device;
  27.562 +
  27.563 +	pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
  27.564 +
  27.565 +	pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
  27.566 +
  27.567 +	adapter->rx_buffer_len = E1000_RXBUFFER_2048;
  27.568 +	hw->max_frame_size = netdev->mtu +
  27.569 +	                         ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
  27.570 +	hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
  27.571 +
  27.572 +	/* identify the MAC */
  27.573 +
  27.574 +	if (e1000_set_mac_type(hw)) {
  27.575 +		E1000_ERR("Unknown MAC Type\n");
  27.576 +		return -1;
  27.577 +	}
  27.578 +
  27.579 +	/* flow control settings */
  27.580 +
  27.581 +	hw->fc_high_water = E1000_FC_HIGH_THRESH;
  27.582 +	hw->fc_low_water = E1000_FC_LOW_THRESH;
  27.583 +	hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  27.584 +	hw->fc_send_xon = 1;
  27.585 +
  27.586 +	/* Media type - copper or fiber */
  27.587 +
  27.588 +	if(hw->mac_type >= e1000_82543) {
  27.589 +		uint32_t status = E1000_READ_REG(hw, STATUS);
  27.590 +
  27.591 +		if(status & E1000_STATUS_TBIMODE)
  27.592 +			hw->media_type = e1000_media_type_fiber;
  27.593 +		else
  27.594 +			hw->media_type = e1000_media_type_copper;
  27.595 +	} else {
  27.596 +		hw->media_type = e1000_media_type_fiber;
  27.597 +	}
  27.598 +
  27.599 +	if(hw->mac_type < e1000_82543)
  27.600 +		hw->report_tx_early = 0;
  27.601 +	else
  27.602 +		hw->report_tx_early = 1;
  27.603 +
  27.604 +	hw->wait_autoneg_complete = FALSE;
  27.605 +	hw->tbi_compatibility_en = TRUE;
  27.606 +	hw->adaptive_ifs = TRUE;
  27.607 +
  27.608 +	/* Copper options */
  27.609 +
  27.610 +	if(hw->media_type == e1000_media_type_copper) {
  27.611 +		hw->mdix = AUTO_ALL_MODES;
  27.612 +		hw->disable_polarity_correction = FALSE;
  27.613 +	}
  27.614 +
  27.615 +	atomic_set(&adapter->irq_sem, 1);
  27.616 +	spin_lock_init(&adapter->stats_lock);
  27.617 +
  27.618 +	return 0;
  27.619 +}
  27.620 +
  27.621 +/**
  27.622 + * e1000_open - Called when a network interface is made active
  27.623 + * @netdev: network interface device structure
  27.624 + *
  27.625 + * Returns 0 on success, negative value on failure
  27.626 + *
  27.627 + * The open entry point is called when a network interface is made
  27.628 + * active by the system (IFF_UP).  At this point all resources needed
  27.629 + * for transmit and receive operations are allocated, the interrupt
  27.630 + * handler is registered with the OS, the watchdog timer is started,
  27.631 + * and the stack is notified that the interface is ready.
  27.632 + **/
  27.633 +
  27.634 +static int
  27.635 +e1000_open(struct net_device *netdev)
  27.636 +{
  27.637 +	struct e1000_adapter *adapter = netdev->priv;
  27.638 +
  27.639 +	/* allocate transmit descriptors */
  27.640 +
  27.641 +	if(e1000_setup_tx_resources(adapter))
  27.642 +		goto err_setup_tx;
  27.643 +
  27.644 +	/* allocate receive descriptors */
  27.645 +
  27.646 +	if(e1000_setup_rx_resources(adapter))
  27.647 +		goto err_setup_rx;
  27.648 +
  27.649 +	if(e1000_up(adapter))
  27.650 +		goto err_up;
  27.651 +
  27.652 +	return 0;
  27.653 +
  27.654 +err_up:
  27.655 +	e1000_free_rx_resources(adapter);
  27.656 +err_setup_rx:
  27.657 +	e1000_free_tx_resources(adapter);
  27.658 +err_setup_tx:
  27.659 +	e1000_reset(adapter);
  27.660 +
  27.661 +	return -EBUSY;
  27.662 +}
  27.663 +
  27.664 +/**
  27.665 + * e1000_close - Disables a network interface
  27.666 + * @netdev: network interface device structure
  27.667 + *
  27.668 + * Returns 0, this is not allowed to fail
  27.669 + *
  27.670 + * The close entry point is called when an interface is de-activated
  27.671 + * by the OS.  The hardware is still under the drivers control, but
  27.672 + * needs to be disabled.  A global MAC reset is issued to stop the
  27.673 + * hardware, and all transmit and receive resources are freed.
  27.674 + **/
  27.675 +
  27.676 +static int
  27.677 +e1000_close(struct net_device *netdev)
  27.678 +{
  27.679 +	struct e1000_adapter *adapter = netdev->priv;
  27.680 +
  27.681 +	e1000_down(adapter);
  27.682 +
  27.683 +	e1000_free_tx_resources(adapter);
  27.684 +	e1000_free_rx_resources(adapter);
  27.685 +
  27.686 +	return 0;
  27.687 +}
  27.688 +
  27.689 +/**
  27.690 + * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
  27.691 + * @adapter: board private structure
  27.692 + *
  27.693 + * Return 0 on success, negative on failure
  27.694 + **/
  27.695 +
  27.696 +static int
  27.697 +e1000_setup_tx_resources(struct e1000_adapter *adapter)
  27.698 +{
  27.699 +	struct e1000_desc_ring *txdr = &adapter->tx_ring;
  27.700 +	struct pci_dev *pdev = adapter->pdev;
  27.701 +	int size;
  27.702 +
  27.703 +	size = sizeof(struct e1000_buffer) * txdr->count;
  27.704 +	txdr->buffer_info = kmalloc(size, GFP_KERNEL);
  27.705 +	if(!txdr->buffer_info) {
  27.706 +		return -ENOMEM;
  27.707 +	}
  27.708 +	memset(txdr->buffer_info, 0, size);
  27.709 +
  27.710 +	/* round up to nearest 4K */
  27.711 +
  27.712 +	txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
  27.713 +	E1000_ROUNDUP(txdr->size, 4096);
  27.714 +
  27.715 +	txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
  27.716 +	if(!txdr->desc) {
  27.717 +		kfree(txdr->buffer_info);
  27.718 +		return -ENOMEM;
  27.719 +	}
  27.720 +	memset(txdr->desc, 0, txdr->size);
  27.721 +
  27.722 +	txdr->next_to_use = 0;
  27.723 +	txdr->next_to_clean = 0;
  27.724 +
  27.725 +	return 0;
  27.726 +}
  27.727 +
  27.728 +/**
  27.729 + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  27.730 + * @adapter: board private structure
  27.731 + *
  27.732 + * Configure the Tx unit of the MAC after a reset.
  27.733 + **/
  27.734 +
  27.735 +static void
  27.736 +e1000_configure_tx(struct e1000_adapter *adapter)
  27.737 +{
  27.738 +	uint64_t tdba = adapter->tx_ring.dma;
  27.739 +	uint32_t tdlen = adapter->tx_ring.count * sizeof(struct e1000_tx_desc);
  27.740 +	uint32_t tctl, tipg;
  27.741 +
  27.742 +	E1000_WRITE_REG(&adapter->hw, TDBAL, (tdba & 0x00000000ffffffffULL));
  27.743 +	E1000_WRITE_REG(&adapter->hw, TDBAH, (tdba >> 32));
  27.744 +
  27.745 +	E1000_WRITE_REG(&adapter->hw, TDLEN, tdlen);
  27.746 +
  27.747 +	/* Setup the HW Tx Head and Tail descriptor pointers */
  27.748 +
  27.749 +	E1000_WRITE_REG(&adapter->hw, TDH, 0);
  27.750 +	E1000_WRITE_REG(&adapter->hw, TDT, 0);
  27.751 +
  27.752 +	/* Set the default values for the Tx Inter Packet Gap timer */
  27.753 +
  27.754 +	switch (adapter->hw.mac_type) {
  27.755 +	case e1000_82542_rev2_0:
  27.756 +	case e1000_82542_rev2_1:
  27.757 +		tipg = DEFAULT_82542_TIPG_IPGT;
  27.758 +		tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
  27.759 +		tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
  27.760 +		break;
  27.761 +	default:
  27.762 +		if(adapter->hw.media_type == e1000_media_type_fiber)
  27.763 +			tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  27.764 +		else
  27.765 +			tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  27.766 +		tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
  27.767 +		tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
  27.768 +	}
  27.769 +	E1000_WRITE_REG(&adapter->hw, TIPG, tipg);
  27.770 +
  27.771 +	/* Set the Tx Interrupt Delay register */
  27.772 +
  27.773 +	E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay);
  27.774 +	if(adapter->hw.mac_type >= e1000_82540)
  27.775 +		E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay);
  27.776 +
  27.777 +	/* Program the Transmit Control Register */
  27.778 +
  27.779 +	tctl = E1000_READ_REG(&adapter->hw, TCTL);
  27.780 +
  27.781 +	tctl &= ~E1000_TCTL_CT;
  27.782 +	tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  27.783 +	       (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  27.784 +
  27.785 +	E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
  27.786 +
  27.787 +	e1000_config_collision_dist(&adapter->hw);
  27.788 +
  27.789 +	/* Setup Transmit Descriptor Settings for this adapter */
  27.790 +	adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE;
  27.791 +
  27.792 +	if(adapter->hw.report_tx_early == 1)
  27.793 +		adapter->txd_cmd |= E1000_TXD_CMD_RS;
  27.794 +	else
  27.795 +		adapter->txd_cmd |= E1000_TXD_CMD_RPS;
  27.796 +}
  27.797 +
  27.798 +/**
  27.799 + * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
  27.800 + * @adapter: board private structure
  27.801 + *
  27.802 + * Returns 0 on success, negative on failure
  27.803 + **/
  27.804 +
  27.805 +static int
  27.806 +e1000_setup_rx_resources(struct e1000_adapter *adapter)
  27.807 +{
  27.808 +	struct e1000_desc_ring *rxdr = &adapter->rx_ring;
  27.809 +	struct pci_dev *pdev = adapter->pdev;
  27.810 +	int size;
  27.811 +
  27.812 +	size = sizeof(struct e1000_buffer) * rxdr->count;
  27.813 +	rxdr->buffer_info = kmalloc(size, GFP_KERNEL);
  27.814 +	if(!rxdr->buffer_info) {
  27.815 +		return -ENOMEM;
  27.816 +	}
  27.817 +	memset(rxdr->buffer_info, 0, size);
  27.818 +
  27.819 +	/* Round up to nearest 4K */
  27.820 +
  27.821 +	rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
  27.822 +	E1000_ROUNDUP(rxdr->size, 4096);
  27.823 +
  27.824 +	rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
  27.825 +
  27.826 +	if(!rxdr->desc) {
  27.827 +		kfree(rxdr->buffer_info);
  27.828 +		return -ENOMEM;
  27.829 +	}
  27.830 +	memset(rxdr->desc, 0, rxdr->size);
  27.831 +
  27.832 +	rxdr->next_to_clean = 0;
  27.833 +	rxdr->next_to_use = 0;
  27.834 +
  27.835 +	return 0;
  27.836 +}
  27.837 +
  27.838 +/**
  27.839 + * e1000_setup_rctl - configure the receive control register
  27.840 + * @adapter: Board private structure
  27.841 + **/
  27.842 +
  27.843 +static void
  27.844 +e1000_setup_rctl(struct e1000_adapter *adapter)
  27.845 +{
  27.846 +	uint32_t rctl;
  27.847 +
  27.848 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
  27.849 +
  27.850 +	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  27.851 +
  27.852 +	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
  27.853 +	        E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
  27.854 +	        (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
  27.855 +
  27.856 +	if(adapter->hw.tbi_compatibility_on == 1)
  27.857 +		rctl |= E1000_RCTL_SBP;
  27.858 +	else
  27.859 +		rctl &= ~E1000_RCTL_SBP;
  27.860 +
  27.861 +	rctl &= ~(E1000_RCTL_SZ_4096);
  27.862 +	switch (adapter->rx_buffer_len) {
  27.863 +	case E1000_RXBUFFER_2048:
  27.864 +	default:
  27.865 +		rctl |= E1000_RCTL_SZ_2048;
  27.866 +		rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  27.867 +		break;
  27.868 +	case E1000_RXBUFFER_4096:
  27.869 +		rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
  27.870 +		break;
  27.871 +	case E1000_RXBUFFER_8192:
  27.872 +		rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
  27.873 +		break;
  27.874 +	case E1000_RXBUFFER_16384:
  27.875 +		rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
  27.876 +		break;
  27.877 +	}
  27.878 +
  27.879 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  27.880 +}
  27.881 +
  27.882 +/**
  27.883 + * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  27.884 + * @adapter: board private structure
  27.885 + *
  27.886 + * Configure the Rx unit of the MAC after a reset.
  27.887 + **/
  27.888 +
  27.889 +static void
  27.890 +e1000_configure_rx(struct e1000_adapter *adapter)
  27.891 +{
  27.892 +	uint64_t rdba = adapter->rx_ring.dma;
  27.893 +	uint32_t rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc);
  27.894 +	uint32_t rctl;
  27.895 +	uint32_t rxcsum;
  27.896 +
  27.897 +	/* make sure receives are disabled while setting up the descriptors */
  27.898 +
  27.899 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
  27.900 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);
  27.901 +
  27.902 +	/* set the Receive Delay Timer Register */
  27.903 +
  27.904 +	E1000_WRITE_REG(&adapter->hw, RDTR, adapter->rx_int_delay);
  27.905 +
  27.906 +	if(adapter->hw.mac_type >= e1000_82540) {
  27.907 +		E1000_WRITE_REG(&adapter->hw, RADV, adapter->rx_abs_int_delay);
  27.908 +
  27.909 +		/* Set the interrupt throttling rate.  Value is calculated
  27.910 +		 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  27.911 +#define MAX_INTS_PER_SEC        8000
  27.912 +#define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
  27.913 +		E1000_WRITE_REG(&adapter->hw, ITR, DEFAULT_ITR);
  27.914 +	}
  27.915 +
  27.916 +	/* Setup the Base and Length of the Rx Descriptor Ring */
  27.917 +
  27.918 +	E1000_WRITE_REG(&adapter->hw, RDBAL, (rdba & 0x00000000ffffffffULL));
  27.919 +	E1000_WRITE_REG(&adapter->hw, RDBAH, (rdba >> 32));
  27.920 +
  27.921 +	E1000_WRITE_REG(&adapter->hw, RDLEN, rdlen);
  27.922 +
  27.923 +	/* Setup the HW Rx Head and Tail Descriptor Pointers */
  27.924 +	E1000_WRITE_REG(&adapter->hw, RDH, 0);
  27.925 +	E1000_WRITE_REG(&adapter->hw, RDT, 0);
  27.926 +
  27.927 +	/* Enable 82543 Receive Checksum Offload for TCP and UDP */
  27.928 +	if((adapter->hw.mac_type >= e1000_82543) &&
  27.929 +	   (adapter->rx_csum == TRUE)) {
  27.930 +		rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
  27.931 +		rxcsum |= E1000_RXCSUM_TUOFL;
  27.932 +		E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum);
  27.933 +	}
  27.934 +
  27.935 +	/* Enable Receives */
  27.936 +
  27.937 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  27.938 +}
  27.939 +
  27.940 +/**
  27.941 + * e1000_free_tx_resources - Free Tx Resources
  27.942 + * @adapter: board private structure
  27.943 + *
  27.944 + * Free all transmit software resources
  27.945 + **/
  27.946 +
  27.947 +static void
  27.948 +e1000_free_tx_resources(struct e1000_adapter *adapter)
  27.949 +{
  27.950 +	struct pci_dev *pdev = adapter->pdev;
  27.951 +
  27.952 +	e1000_clean_tx_ring(adapter);
  27.953 +
  27.954 +	kfree(adapter->tx_ring.buffer_info);
  27.955 +	adapter->tx_ring.buffer_info = NULL;
  27.956 +
  27.957 +	pci_free_consistent(pdev, adapter->tx_ring.size,
  27.958 +	                    adapter->tx_ring.desc, adapter->tx_ring.dma);
  27.959 +
  27.960 +	adapter->tx_ring.desc = NULL;
  27.961 +}
  27.962 +
  27.963 +/**
  27.964 + * e1000_clean_tx_ring - Free Tx Buffers
  27.965 + * @adapter: board private structure
  27.966 + **/
  27.967 +
  27.968 +static void
  27.969 +e1000_clean_tx_ring(struct e1000_adapter *adapter)
  27.970 +{
  27.971 +	struct pci_dev *pdev = adapter->pdev;
  27.972 +	unsigned long size;
  27.973 +	int i;
  27.974 +
  27.975 +	/* Free all the Tx ring sk_buffs */
  27.976 +
  27.977 +	for(i = 0; i < adapter->tx_ring.count; i++) {
  27.978 +		if(adapter->tx_ring.buffer_info[i].skb) {
  27.979 +
  27.980 +			pci_unmap_page(pdev,
  27.981 +			               adapter->tx_ring.buffer_info[i].dma,
  27.982 +			               adapter->tx_ring.buffer_info[i].length,
  27.983 +			               PCI_DMA_TODEVICE);
  27.984 +
  27.985 +			dev_kfree_skb(adapter->tx_ring.buffer_info[i].skb);
  27.986 +
  27.987 +			adapter->tx_ring.buffer_info[i].skb = NULL;
  27.988 +		}
  27.989 +	}
  27.990 +
  27.991 +	size = sizeof(struct e1000_buffer) * adapter->tx_ring.count;
  27.992 +	memset(adapter->tx_ring.buffer_info, 0, size);
  27.993 +
  27.994 +	/* Zero out the descriptor ring */
  27.995 +
  27.996 +	memset(adapter->tx_ring.desc, 0, adapter->tx_ring.size);
  27.997 +
  27.998 +	adapter->tx_ring.next_to_use = 0;
  27.999 +	adapter->tx_ring.next_to_clean = 0;
 27.1000 +
 27.1001 +	E1000_WRITE_REG(&adapter->hw, TDH, 0);
 27.1002 +	E1000_WRITE_REG(&adapter->hw, TDT, 0);
 27.1003 +}
 27.1004 +
 27.1005 +/**
 27.1006 + * e1000_free_rx_resources - Free Rx Resources
 27.1007 + * @adapter: board private structure
 27.1008 + *
 27.1009 + * Free all receive software resources
 27.1010 + **/
 27.1011 +
 27.1012 +static void
 27.1013 +e1000_free_rx_resources(struct e1000_adapter *adapter)
 27.1014 +{
 27.1015 +	struct pci_dev *pdev = adapter->pdev;
 27.1016 +
 27.1017 +	e1000_clean_rx_ring(adapter);
 27.1018 +
 27.1019 +	kfree(adapter->rx_ring.buffer_info);
 27.1020 +	adapter->rx_ring.buffer_info = NULL;
 27.1021 +
 27.1022 +	pci_free_consistent(pdev, adapter->rx_ring.size,
 27.1023 +	                    adapter->rx_ring.desc, adapter->rx_ring.dma);
 27.1024 +
 27.1025 +	adapter->rx_ring.desc = NULL;
 27.1026 +}
 27.1027 +
 27.1028 +/**
 27.1029 + * e1000_clean_rx_ring - Free Rx Buffers
 27.1030 + * @adapter: board private structure
 27.1031 + **/
 27.1032 +
 27.1033 +static void
 27.1034 +e1000_clean_rx_ring(struct e1000_adapter *adapter)
 27.1035 +{
 27.1036 +	struct pci_dev *pdev = adapter->pdev;
 27.1037 +	unsigned long size;
 27.1038 +	int i;
 27.1039 +
 27.1040 +	/* Free all the Rx ring sk_buffs */
 27.1041 +
 27.1042 +	for(i = 0; i < adapter->rx_ring.count; i++) {
 27.1043 +		if(adapter->rx_ring.buffer_info[i].skb) {
 27.1044 +
 27.1045 +			pci_unmap_single(pdev,
 27.1046 +			                 adapter->rx_ring.buffer_info[i].dma,
 27.1047 +			                 adapter->rx_ring.buffer_info[i].length,
 27.1048 +			                 PCI_DMA_FROMDEVICE);
 27.1049 +
 27.1050 +			dev_kfree_skb(adapter->rx_ring.buffer_info[i].skb);
 27.1051 +
 27.1052 +			adapter->rx_ring.buffer_info[i].skb = NULL;
 27.1053 +		}
 27.1054 +	}
 27.1055 +
 27.1056 +	size = sizeof(struct e1000_buffer) * adapter->rx_ring.count;
 27.1057 +	memset(adapter->rx_ring.buffer_info, 0, size);
 27.1058 +
 27.1059 +	/* Zero out the descriptor ring */
 27.1060 +
 27.1061 +	memset(adapter->rx_ring.desc, 0, adapter->rx_ring.size);
 27.1062 +
 27.1063 +	adapter->rx_ring.next_to_clean = 0;
 27.1064 +	adapter->rx_ring.next_to_use = 0;
 27.1065 +
 27.1066 +	E1000_WRITE_REG(&adapter->hw, RDH, 0);
 27.1067 +	E1000_WRITE_REG(&adapter->hw, RDT, 0);
 27.1068 +}
 27.1069 +
 27.1070 +/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
 27.1071 + * and memory write and invalidate disabled for certain operations
 27.1072 + */
 27.1073 +static void
 27.1074 +e1000_enter_82542_rst(struct e1000_adapter *adapter)
 27.1075 +{
 27.1076 +	struct net_device *netdev = adapter->netdev;
 27.1077 +	uint32_t rctl;
 27.1078 +
 27.1079 +	e1000_pci_clear_mwi(&adapter->hw);
 27.1080 +
 27.1081 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
 27.1082 +	rctl |= E1000_RCTL_RST;
 27.1083 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
 27.1084 +	E1000_WRITE_FLUSH(&adapter->hw);
 27.1085 +	mdelay(5);
 27.1086 +
 27.1087 +	if(netif_running(netdev))
 27.1088 +		e1000_clean_rx_ring(adapter);
 27.1089 +}
 27.1090 +
 27.1091 +static void
 27.1092 +e1000_leave_82542_rst(struct e1000_adapter *adapter)
 27.1093 +{
 27.1094 +	struct net_device *netdev = adapter->netdev;
 27.1095 +	uint32_t rctl;
 27.1096 +
 27.1097 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
 27.1098 +	rctl &= ~E1000_RCTL_RST;
 27.1099 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
 27.1100 +	E1000_WRITE_FLUSH(&adapter->hw);
 27.1101 +	mdelay(5);
 27.1102 +
 27.1103 +	if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
 27.1104 +		e1000_pci_set_mwi(&adapter->hw);
 27.1105 +
 27.1106 +	if(netif_running(netdev)) {
 27.1107 +		e1000_configure_rx(adapter);
 27.1108 +		e1000_alloc_rx_buffers(adapter);
 27.1109 +	}
 27.1110 +}
 27.1111 +
 27.1112 +/**
 27.1113 + * e1000_set_mac - Change the Ethernet Address of the NIC
 27.1114 + * @netdev: network interface device structure
 27.1115 + * @p: pointer to an address structure
 27.1116 + *
 27.1117 + * Returns 0 on success, negative on failure
 27.1118 + **/
 27.1119 +
 27.1120 +static int
 27.1121 +e1000_set_mac(struct net_device *netdev, void *p)
 27.1122 +{
 27.1123 +	struct e1000_adapter *adapter = netdev->priv;
 27.1124 +	struct sockaddr *addr = p;
 27.1125 +
 27.1126 +	if(!is_valid_ether_addr(addr->sa_data))
 27.1127 +		return -EADDRNOTAVAIL;
 27.1128 +
 27.1129 +	/* 82542 2.0 needs to be in reset to write receive address registers */
 27.1130 +
 27.1131 +	if(adapter->hw.mac_type == e1000_82542_rev2_0)
 27.1132 +		e1000_enter_82542_rst(adapter);
 27.1133 +
 27.1134 +	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
 27.1135 +	memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
 27.1136 +
 27.1137 +	e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
 27.1138 +
 27.1139 +	if(adapter->hw.mac_type == e1000_82542_rev2_0)
 27.1140 +		e1000_leave_82542_rst(adapter);
 27.1141 +
 27.1142 +	return 0;
 27.1143 +}
 27.1144 +
 27.1145 +/**
 27.1146 + * e1000_set_multi - Multicast and Promiscuous mode set
 27.1147 + * @netdev: network interface device structure
 27.1148 + *
 27.1149 + * The set_multi entry point is called whenever the multicast address
 27.1150 + * list or the network interface flags are updated.  This routine is
 27.1151 + * resposible for configuring the hardware for proper multicast,
 27.1152 + * promiscuous mode, and all-multi behavior.
 27.1153 + **/
 27.1154 +
 27.1155 +static void
 27.1156 +e1000_set_multi(struct net_device *netdev)
 27.1157 +{
 27.1158 +	struct e1000_adapter *adapter = netdev->priv;
 27.1159 +	struct e1000_hw *hw = &adapter->hw;
 27.1160 +	struct dev_mc_list *mc_ptr;
 27.1161 +	uint32_t rctl;
 27.1162 +	uint32_t hash_value;
 27.1163 +	int i;
 27.1164 +
 27.1165 +	/* Check for Promiscuous and All Multicast modes */
 27.1166 +
 27.1167 +	rctl = E1000_READ_REG(hw, RCTL);
 27.1168 +
 27.1169 +	if(netdev->flags & IFF_PROMISC) {
 27.1170 +		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
 27.1171 +	} else if(netdev->flags & IFF_ALLMULTI) {
 27.1172 +		rctl |= E1000_RCTL_MPE;
 27.1173 +		rctl &= ~E1000_RCTL_UPE;
 27.1174 +	} else {
 27.1175 +		rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
 27.1176 +	}
 27.1177 +
 27.1178 +	E1000_WRITE_REG(hw, RCTL, rctl);
 27.1179 +
 27.1180 +	/* 82542 2.0 needs to be in reset to write receive address registers */
 27.1181 +
 27.1182 +	if(hw->mac_type == e1000_82542_rev2_0)
 27.1183 +		e1000_enter_82542_rst(adapter);
 27.1184 +
 27.1185 +	/* load the first 15 multicast address into the exact filters 1-15
 27.1186 +	 * RAR 0 is used for the station MAC adddress
 27.1187 +	 * if there are not 15 addresses, go ahead and clear the filters
 27.1188 +	 */
 27.1189 +	mc_ptr = netdev->mc_list;
 27.1190 +
 27.1191 +	for(i = 1; i < E1000_RAR_ENTRIES; i++) {
 27.1192 +		if(mc_ptr) {
 27.1193 +			e1000_rar_set(hw, mc_ptr->dmi_addr, i);
 27.1194 +			mc_ptr = mc_ptr->next;
 27.1195 +		} else {
 27.1196 +			E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
 27.1197 +			E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
 27.1198 +		}
 27.1199 +	}
 27.1200 +
 27.1201 +	/* clear the old settings from the multicast hash table */
 27.1202 +
 27.1203 +	for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
 27.1204 +		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
 27.1205 +
 27.1206 +	/* load any remaining addresses into the hash table */
 27.1207 +
 27.1208 +	for(; mc_ptr; mc_ptr = mc_ptr->next) {
 27.1209 +		hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
 27.1210 +		e1000_mta_set(hw, hash_value);
 27.1211 +	}
 27.1212 +
 27.1213 +	if(hw->mac_type == e1000_82542_rev2_0)
 27.1214 +		e1000_leave_82542_rst(adapter);
 27.1215 +}
 27.1216 +
 27.1217 +
 27.1218 +/* need to wait a few seconds after link up to get diagnostic information from the phy */
 27.1219 +
 27.1220 +static void
 27.1221 +e1000_update_phy_info(unsigned long data)
 27.1222 +{
 27.1223 +	struct e1000_adapter *adapter = (struct e1000_adapter *) data;
 27.1224 +	e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
 27.1225 +}
 27.1226 +
 27.1227 +/**
 27.1228 + * e1000_watchdog - Timer Call-back
 27.1229 + * @data: pointer to netdev cast into an unsigned long
 27.1230 + **/
 27.1231 +
 27.1232 +static void
 27.1233 +e1000_watchdog(unsigned long data)
 27.1234 +{
 27.1235 +	struct e1000_adapter *adapter = (struct e1000_adapter *) data;
 27.1236 +	struct net_device *netdev = adapter->netdev;
 27.1237 +	struct e1000_desc_ring *txdr = &adapter->tx_ring;
 27.1238 +	int i;
 27.1239 +
 27.1240 +	e1000_check_for_link(&adapter->hw);
 27.1241 +
 27.1242 +	if(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
 27.1243 +		if(!netif_carrier_ok(netdev)) {
 27.1244 +			e1000_get_speed_and_duplex(&adapter->hw,
 27.1245 +			                           &adapter->link_speed,
 27.1246 +			                           &adapter->link_duplex);
 27.1247 +
 27.1248 +			printk(KERN_INFO
 27.1249 +			       "e1000: %s NIC Link is Up %d Mbps %s\n",
 27.1250 +			       netdev->name, adapter->link_speed,
 27.1251 +			       adapter->link_duplex == FULL_DUPLEX ?
 27.1252 +			       "Full Duplex" : "Half Duplex");
 27.1253 +
 27.1254 +			netif_carrier_on(netdev);
 27.1255 +			netif_wake_queue(netdev);
 27.1256 +			mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
 27.1257 +		}
 27.1258 +	} else {
 27.1259 +		if(netif_carrier_ok(netdev)) {
 27.1260 +			adapter->link_speed = 0;
 27.1261 +			adapter->link_duplex = 0;
 27.1262 +			printk(KERN_INFO
 27.1263 +			       "e1000: %s NIC Link is Down\n",
 27.1264 +			       netdev->name);
 27.1265 +			netif_carrier_off(netdev);
 27.1266 +			netif_stop_queue(netdev);
 27.1267 +			mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
 27.1268 +		}
 27.1269 +	}
 27.1270 +
 27.1271 +	e1000_update_stats(adapter);
 27.1272 +	e1000_update_adaptive(&adapter->hw);
 27.1273 +
 27.1274 +
 27.1275 +	/* Cause software interrupt to ensure rx ring is cleaned */
 27.1276 +	E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
 27.1277 +
 27.1278 +	/* Early detection of hung controller */
 27.1279 +	i = txdr->next_to_clean;
 27.1280 +	if(txdr->buffer_info[i].dma &&
 27.1281 +	   time_after(jiffies, txdr->buffer_info[i].time_stamp + HZ) &&
 27.1282 +	   !(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF))
 27.1283 +		netif_stop_queue(netdev);
 27.1284 +
 27.1285 +	/* Reset the timer */
 27.1286 +	mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
 27.1287 +}
 27.1288 +
 27.1289 +#define E1000_TX_FLAGS_CSUM		0x00000001
 27.1290 +#define E1000_TX_FLAGS_VLAN		0x00000002
 27.1291 +#define E1000_TX_FLAGS_VLAN_MASK	0xffff0000
 27.1292 +#define E1000_TX_FLAGS_VLAN_SHIFT	16
 27.1293 +
 27.1294 +static inline boolean_t
 27.1295 +e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
 27.1296 +{
 27.1297 +	struct e1000_context_desc *context_desc;
 27.1298 +	int i;
 27.1299 +	uint8_t css, cso;
 27.1300 +
 27.1301 +	if(skb->ip_summed == CHECKSUM_HW) {
 27.1302 +		css = skb->h.raw - skb->data;
 27.1303 +		cso = (skb->h.raw + skb->csum) - skb->data;
 27.1304 +
 27.1305 +		i = adapter->tx_ring.next_to_use;
 27.1306 +		context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
 27.1307 +
 27.1308 +		context_desc->upper_setup.tcp_fields.tucss = css;
 27.1309 +		context_desc->upper_setup.tcp_fields.tucso = cso;
 27.1310 +		context_desc->upper_setup.tcp_fields.tucse = 0;
 27.1311 +		context_desc->tcp_seg_setup.data = 0;
 27.1312 +		context_desc->cmd_and_length =
 27.1313 +			cpu_to_le32(adapter->txd_cmd | E1000_TXD_CMD_DEXT);
 27.1314 +
 27.1315 +		i = (i + 1) % adapter->tx_ring.count;
 27.1316 +		adapter->tx_ring.next_to_use = i;
 27.1317 +
 27.1318 +		return TRUE;
 27.1319 +	}
 27.1320 +
 27.1321 +	return FALSE;
 27.1322 +}
 27.1323 +
 27.1324 +static inline int
 27.1325 +e1000_tx_map(struct e1000_adapter *adapter, struct sk_buff *skb)
 27.1326 +{
 27.1327 +	struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
 27.1328 +	int len, offset, size, count, i;
 27.1329 +
 27.1330 +	int f;
 27.1331 +	len = skb->len - skb->data_len;
 27.1332 +	i = (tx_ring->next_to_use + tx_ring->count - 1) % tx_ring->count;
 27.1333 +	count = 0;
 27.1334 +
 27.1335 +	offset = 0;
 27.1336 +
 27.1337 +	while(len) {
 27.1338 +		i = (i + 1) % tx_ring->count;
 27.1339 +		size = min(len, adapter->max_data_per_txd);
 27.1340 +		tx_ring->buffer_info[i].length = size;
 27.1341 +		tx_ring->buffer_info[i].dma =
 27.1342 +			pci_map_single(adapter->pdev,
 27.1343 +				skb->data + offset,
 27.1344 +				size,
 27.1345 +				PCI_DMA_TODEVICE);
 27.1346 +		tx_ring->buffer_info[i].time_stamp = jiffies;
 27.1347 +
 27.1348 +		len -= size;
 27.1349 +		offset += size;
 27.1350 +		count++;
 27.1351 +	}
 27.1352 +
 27.1353 +	for(f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
 27.1354 +		struct skb_frag_struct *frag;
 27.1355 +
 27.1356 +		frag = &skb_shinfo(skb)->frags[f];
 27.1357 +		len = frag->size;
 27.1358 +		offset = 0;
 27.1359 +
 27.1360 +		while(len) {
 27.1361 +			i = (i + 1) % tx_ring->count;
 27.1362 +			size = min(len, adapter->max_data_per_txd);
 27.1363 +			tx_ring->buffer_info[i].length = size;
 27.1364 +			tx_ring->buffer_info[i].dma =
 27.1365 +				pci_map_page(adapter->pdev,
 27.1366 +					frag->page,
 27.1367 +					frag->page_offset + offset,
 27.1368 +					size,
 27.1369 +					PCI_DMA_TODEVICE);
 27.1370 +
 27.1371 +			len -= size;
 27.1372 +			offset += size;
 27.1373 +			count++;
 27.1374 +		}
 27.1375 +	}
 27.1376 +	tx_ring->buffer_info[i].skb = skb;
 27.1377 +
 27.1378 +	return count;
 27.1379 +}
 27.1380 +
 27.1381 +static inline void
 27.1382 +e1000_tx_queue(struct e1000_adapter *adapter, int count, int tx_flags)
 27.1383 +{
 27.1384 +	struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
 27.1385 +	struct e1000_tx_desc *tx_desc = NULL;
 27.1386 +	uint32_t txd_upper, txd_lower;
 27.1387 +	int i;
 27.1388 +
 27.1389 +	txd_upper = 0;
 27.1390 +	txd_lower = adapter->txd_cmd;
 27.1391 +
 27.1392 +	if(tx_flags & E1000_TX_FLAGS_CSUM) {
 27.1393 +		txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
 27.1394 +		txd_upper |= E1000_TXD_POPTS_TXSM << 8;
 27.1395 +	}
 27.1396 +
 27.1397 +	if(tx_flags & E1000_TX_FLAGS_VLAN) {
 27.1398 +		txd_lower |= E1000_TXD_CMD_VLE;
 27.1399 +		txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
 27.1400 +	}
 27.1401 +
 27.1402 +	i = tx_ring->next_to_use;
 27.1403 +
 27.1404 +	while(count--) {
 27.1405 +		tx_desc = E1000_TX_DESC(*tx_ring, i);
 27.1406 +		tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
 27.1407 +		tx_desc->lower.data =
 27.1408 +			cpu_to_le32(txd_lower | tx_ring->buffer_info[i].length);
 27.1409 +		tx_desc->upper.data = cpu_to_le32(txd_upper);
 27.1410 +		i = (i + 1) % tx_ring->count;
 27.1411 +	}
 27.1412 +
 27.1413 +	tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP);
 27.1414 +
 27.1415 +	/* Force memory writes to complete before letting h/w
 27.1416 +	 * know there are new descriptors to fetch.  (Only
 27.1417 +	 * applicable for weak-ordered memory model archs,
 27.1418 +	 * such as IA-64). */
 27.1419 +	wmb();
 27.1420 +
 27.1421 +	tx_ring->next_to_use = i;
 27.1422 +	E1000_WRITE_REG(&adapter->hw, TDT, i);
 27.1423 +}
 27.1424 +
 27.1425 +#define TXD_USE_COUNT(S, X) (((S) / (X)) + (((S) % (X)) ? 1 : 0))
 27.1426 +
 27.1427 +static int
 27.1428 +e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
 27.1429 +{
 27.1430 +	struct e1000_adapter *adapte