ia64/xen-unstable

changeset 15145:2b14a1f22eec

[IA64] Remove unnecessary pal.h from sparse tree.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Fri May 25 09:43:21 2007 -0600 (2007-05-25)
parents 7a2b4d9cc2da
children 919d72f6dc45
files linux-2.6-xen-sparse/include/asm-ia64/pal.h
line diff
     1.1 --- a/linux-2.6-xen-sparse/include/asm-ia64/pal.h	Fri May 25 09:42:12 2007 -0600
     1.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.3 @@ -1,1685 +0,0 @@
     1.4 -#ifndef _ASM_IA64_PAL_H
     1.5 -#define _ASM_IA64_PAL_H
     1.6 -
     1.7 -/*
     1.8 - * Processor Abstraction Layer definitions.
     1.9 - *
    1.10 - * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
    1.11 - * chapter 11 IA-64 Processor Abstraction Layer
    1.12 - *
    1.13 - * Copyright (C) 1998-2001 Hewlett-Packard Co
    1.14 - *	David Mosberger-Tang <davidm@hpl.hp.com>
    1.15 - *	Stephane Eranian <eranian@hpl.hp.com>
    1.16 - * Copyright (C) 1999 VA Linux Systems
    1.17 - * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    1.18 - * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
    1.19 - *
    1.20 - * 99/10/01	davidm	Make sure we pass zero for reserved parameters.
    1.21 - * 00/03/07	davidm	Updated pal_cache_flush() to be in sync with PAL v2.6.
    1.22 - * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
    1.23 - * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
    1.24 - * 00/05/25	eranian Support for stack calls, and static physical calls
    1.25 - * 00/06/18	eranian Support for stacked physical calls
    1.26 - */
    1.27 -
    1.28 -/*
    1.29 - * Note that some of these calls use a static-register only calling
    1.30 - * convention which has nothing to do with the regular calling
    1.31 - * convention.
    1.32 - */
    1.33 -#define PAL_CACHE_FLUSH		1	/* flush i/d cache */
    1.34 -#define PAL_CACHE_INFO		2	/* get detailed i/d cache info */
    1.35 -#define PAL_CACHE_INIT		3	/* initialize i/d cache */
    1.36 -#define PAL_CACHE_SUMMARY	4	/* get summary of cache heirarchy */
    1.37 -#define PAL_MEM_ATTRIB		5	/* list supported memory attributes */
    1.38 -#define PAL_PTCE_INFO		6	/* purge TLB info */
    1.39 -#define PAL_VM_INFO		7	/* return supported virtual memory features */
    1.40 -#define PAL_VM_SUMMARY		8	/* return summary on supported vm features */
    1.41 -#define PAL_BUS_GET_FEATURES	9	/* return processor bus interface features settings */
    1.42 -#define PAL_BUS_SET_FEATURES	10	/* set processor bus features */
    1.43 -#define PAL_DEBUG_INFO		11	/* get number of debug registers */
    1.44 -#define PAL_FIXED_ADDR		12	/* get fixed component of processors's directed address */
    1.45 -#define PAL_FREQ_BASE		13	/* base frequency of the platform */
    1.46 -#define PAL_FREQ_RATIOS		14	/* ratio of processor, bus and ITC frequency */
    1.47 -#define PAL_PERF_MON_INFO	15	/* return performance monitor info */
    1.48 -#define PAL_PLATFORM_ADDR	16	/* set processor interrupt block and IO port space addr */
    1.49 -#define PAL_PROC_GET_FEATURES	17	/* get configurable processor features & settings */
    1.50 -#define PAL_PROC_SET_FEATURES	18	/* enable/disable configurable processor features */
    1.51 -#define PAL_RSE_INFO		19	/* return rse information */
    1.52 -#define PAL_VERSION		20	/* return version of PAL code */
    1.53 -#define PAL_MC_CLEAR_LOG	21	/* clear all processor log info */
    1.54 -#define PAL_MC_DRAIN		22	/* drain operations which could result in an MCA */
    1.55 -#define PAL_MC_EXPECTED		23	/* set/reset expected MCA indicator */
    1.56 -#define PAL_MC_DYNAMIC_STATE	24	/* get processor dynamic state */
    1.57 -#define PAL_MC_ERROR_INFO	25	/* get processor MCA info and static state */
    1.58 -#define PAL_MC_RESUME		26	/* Return to interrupted process */
    1.59 -#define PAL_MC_REGISTER_MEM	27	/* Register memory for PAL to use during MCAs and inits */
    1.60 -#define PAL_HALT		28	/* enter the low power HALT state */
    1.61 -#define PAL_HALT_LIGHT		29	/* enter the low power light halt state*/
    1.62 -#define PAL_COPY_INFO		30	/* returns info needed to relocate PAL */
    1.63 -#define PAL_CACHE_LINE_INIT	31	/* init tags & data of cache line */
    1.64 -#define PAL_PMI_ENTRYPOINT	32	/* register PMI memory entry points with the processor */
    1.65 -#define PAL_ENTER_IA_32_ENV	33	/* enter IA-32 system environment */
    1.66 -#define PAL_VM_PAGE_SIZE	34	/* return vm TC and page walker page sizes */
    1.67 -
    1.68 -#define PAL_MEM_FOR_TEST	37	/* get amount of memory needed for late processor test */
    1.69 -#define PAL_CACHE_PROT_INFO	38	/* get i/d cache protection info */
    1.70 -#define PAL_REGISTER_INFO	39	/* return AR and CR register information*/
    1.71 -#define PAL_SHUTDOWN		40	/* enter processor shutdown state */
    1.72 -#define PAL_PREFETCH_VISIBILITY	41	/* Make Processor Prefetches Visible */
    1.73 -#define PAL_LOGICAL_TO_PHYSICAL 42	/* returns information on logical to physical processor mapping */
    1.74 -#define PAL_CACHE_SHARED_INFO	43	/* returns information on caches shared by logical processor */
    1.75 -
    1.76 -#define PAL_COPY_PAL		256	/* relocate PAL procedures and PAL PMI */
    1.77 -#define PAL_HALT_INFO		257	/* return the low power capabilities of processor */
    1.78 -#define PAL_TEST_PROC		258	/* perform late processor self-test */
    1.79 -#define PAL_CACHE_READ		259	/* read tag & data of cacheline for diagnostic testing */
    1.80 -#define PAL_CACHE_WRITE		260	/* write tag & data of cacheline for diagnostic testing */
    1.81 -#define PAL_VM_TR_READ		261	/* read contents of translation register */
    1.82 -#define PAL_GET_PSTATE		262	/* get the current P-state */
    1.83 -#define PAL_SET_PSTATE		263	/* set the P-state */
    1.84 -
    1.85 -#ifndef __ASSEMBLY__
    1.86 -
    1.87 -#include <linux/types.h>
    1.88 -#include <asm/fpu.h>
    1.89 -
    1.90 -/*
    1.91 - * Data types needed to pass information into PAL procedures and
    1.92 - * interpret information returned by them.
    1.93 - */
    1.94 -
    1.95 -/* Return status from the PAL procedure */
    1.96 -typedef s64				pal_status_t;
    1.97 -
    1.98 -#define PAL_STATUS_SUCCESS		0	/* No error */
    1.99 -#define PAL_STATUS_UNIMPLEMENTED	(-1)	/* Unimplemented procedure */
   1.100 -#define PAL_STATUS_EINVAL		(-2)	/* Invalid argument */
   1.101 -#define PAL_STATUS_ERROR		(-3)	/* Error */
   1.102 -#define PAL_STATUS_CACHE_INIT_FAIL	(-4)	/* Could not initialize the
   1.103 -						 * specified level and type of
   1.104 -						 * cache without sideeffects
   1.105 -						 * and "restrict" was 1
   1.106 -						 */
   1.107 -
   1.108 -/* Processor cache level in the heirarchy */
   1.109 -typedef u64				pal_cache_level_t;
   1.110 -#define PAL_CACHE_LEVEL_L0		0	/* L0 */
   1.111 -#define PAL_CACHE_LEVEL_L1		1	/* L1 */
   1.112 -#define PAL_CACHE_LEVEL_L2		2	/* L2 */
   1.113 -
   1.114 -
   1.115 -/* Processor cache type at a particular level in the heirarchy */
   1.116 -
   1.117 -typedef u64				pal_cache_type_t;
   1.118 -#define PAL_CACHE_TYPE_INSTRUCTION	1	/* Instruction cache */
   1.119 -#define PAL_CACHE_TYPE_DATA		2	/* Data or unified cache */
   1.120 -#define PAL_CACHE_TYPE_INSTRUCTION_DATA	3	/* Both Data & Instruction */
   1.121 -
   1.122 -
   1.123 -#define PAL_CACHE_FLUSH_INVALIDATE	1	/* Invalidate clean lines */
   1.124 -#define PAL_CACHE_FLUSH_CHK_INTRS	2	/* check for interrupts/mc while flushing */
   1.125 -
   1.126 -/* Processor cache line size in bytes  */
   1.127 -typedef int				pal_cache_line_size_t;
   1.128 -
   1.129 -/* Processor cache line state */
   1.130 -typedef u64				pal_cache_line_state_t;
   1.131 -#define PAL_CACHE_LINE_STATE_INVALID	0	/* Invalid */
   1.132 -#define PAL_CACHE_LINE_STATE_SHARED	1	/* Shared */
   1.133 -#define PAL_CACHE_LINE_STATE_EXCLUSIVE	2	/* Exclusive */
   1.134 -#define PAL_CACHE_LINE_STATE_MODIFIED	3	/* Modified */
   1.135 -
   1.136 -typedef struct pal_freq_ratio {
   1.137 -	u32 den, num;		/* numerator & denominator */
   1.138 -} itc_ratio, proc_ratio;
   1.139 -
   1.140 -typedef	union  pal_cache_config_info_1_s {
   1.141 -	struct {
   1.142 -		u64		u		: 1,	/* 0 Unified cache ? */
   1.143 -				at		: 2,	/* 2-1 Cache mem attr*/
   1.144 -				reserved	: 5,	/* 7-3 Reserved */
   1.145 -				associativity	: 8,	/* 16-8 Associativity*/
   1.146 -				line_size	: 8,	/* 23-17 Line size */
   1.147 -				stride		: 8,	/* 31-24 Stride */
   1.148 -				store_latency	: 8,	/*39-32 Store latency*/
   1.149 -				load_latency	: 8,	/* 47-40 Load latency*/
   1.150 -				store_hints	: 8,	/* 55-48 Store hints*/
   1.151 -				load_hints	: 8;	/* 63-56 Load hints */
   1.152 -	} pcci1_bits;
   1.153 -	u64			pcci1_data;
   1.154 -} pal_cache_config_info_1_t;
   1.155 -
   1.156 -typedef	union  pal_cache_config_info_2_s {
   1.157 -	struct {
   1.158 -		u32		cache_size;		/*cache size in bytes*/
   1.159 -
   1.160 -
   1.161 -		u32		alias_boundary	: 8,	/* 39-32 aliased addr
   1.162 -							 * separation for max
   1.163 -							 * performance.
   1.164 -							 */
   1.165 -				tag_ls_bit	: 8,	/* 47-40 LSb of addr*/
   1.166 -				tag_ms_bit	: 8,	/* 55-48 MSb of addr*/
   1.167 -				reserved	: 8;	/* 63-56 Reserved */
   1.168 -	} pcci2_bits;
   1.169 -	u64			pcci2_data;
   1.170 -} pal_cache_config_info_2_t;
   1.171 -
   1.172 -
   1.173 -typedef struct pal_cache_config_info_s {
   1.174 -	pal_status_t			pcci_status;
   1.175 -	pal_cache_config_info_1_t	pcci_info_1;
   1.176 -	pal_cache_config_info_2_t	pcci_info_2;
   1.177 -	u64				pcci_reserved;
   1.178 -} pal_cache_config_info_t;
   1.179 -
   1.180 -#define pcci_ld_hints		pcci_info_1.pcci1_bits.load_hints
   1.181 -#define pcci_st_hints		pcci_info_1.pcci1_bits.store_hints
   1.182 -#define pcci_ld_latency		pcci_info_1.pcci1_bits.load_latency
   1.183 -#define pcci_st_latency		pcci_info_1.pcci1_bits.store_latency
   1.184 -#define pcci_stride		pcci_info_1.pcci1_bits.stride
   1.185 -#define pcci_line_size		pcci_info_1.pcci1_bits.line_size
   1.186 -#define pcci_assoc		pcci_info_1.pcci1_bits.associativity
   1.187 -#define pcci_cache_attr		pcci_info_1.pcci1_bits.at
   1.188 -#define pcci_unified		pcci_info_1.pcci1_bits.u
   1.189 -#define pcci_tag_msb		pcci_info_2.pcci2_bits.tag_ms_bit
   1.190 -#define pcci_tag_lsb		pcci_info_2.pcci2_bits.tag_ls_bit
   1.191 -#define pcci_alias_boundary	pcci_info_2.pcci2_bits.alias_boundary
   1.192 -#define pcci_cache_size		pcci_info_2.pcci2_bits.cache_size
   1.193 -
   1.194 -
   1.195 -
   1.196 -/* Possible values for cache attributes */
   1.197 -
   1.198 -#define PAL_CACHE_ATTR_WT		0	/* Write through cache */
   1.199 -#define PAL_CACHE_ATTR_WB		1	/* Write back cache */
   1.200 -#define PAL_CACHE_ATTR_WT_OR_WB		2	/* Either write thru or write
   1.201 -						 * back depending on TLB
   1.202 -						 * memory attributes
   1.203 -						 */
   1.204 -
   1.205 -
   1.206 -/* Possible values for cache hints */
   1.207 -
   1.208 -#define PAL_CACHE_HINT_TEMP_1		0	/* Temporal level 1 */
   1.209 -#define PAL_CACHE_HINT_NTEMP_1		1	/* Non-temporal level 1 */
   1.210 -#define PAL_CACHE_HINT_NTEMP_ALL	3	/* Non-temporal all levels */
   1.211 -
   1.212 -/* Processor cache protection  information */
   1.213 -typedef union pal_cache_protection_element_u {
   1.214 -	u32			pcpi_data;
   1.215 -	struct {
   1.216 -		u32		data_bits	: 8, /* # data bits covered by
   1.217 -						      * each unit of protection
   1.218 -						      */
   1.219 -
   1.220 -				tagprot_lsb	: 6, /* Least -do- */
   1.221 -				tagprot_msb	: 6, /* Most Sig. tag address
   1.222 -						      * bit that this
   1.223 -						      * protection covers.
   1.224 -						      */
   1.225 -				prot_bits	: 6, /* # of protection bits */
   1.226 -				method		: 4, /* Protection method */
   1.227 -				t_d		: 2; /* Indicates which part
   1.228 -						      * of the cache this
   1.229 -						      * protection encoding
   1.230 -						      * applies.
   1.231 -						      */
   1.232 -	} pcp_info;
   1.233 -} pal_cache_protection_element_t;
   1.234 -
   1.235 -#define pcpi_cache_prot_part	pcp_info.t_d
   1.236 -#define pcpi_prot_method	pcp_info.method
   1.237 -#define pcpi_prot_bits		pcp_info.prot_bits
   1.238 -#define pcpi_tagprot_msb	pcp_info.tagprot_msb
   1.239 -#define pcpi_tagprot_lsb	pcp_info.tagprot_lsb
   1.240 -#define pcpi_data_bits		pcp_info.data_bits
   1.241 -
   1.242 -/* Processor cache part encodings */
   1.243 -#define PAL_CACHE_PROT_PART_DATA	0	/* Data protection  */
   1.244 -#define PAL_CACHE_PROT_PART_TAG		1	/* Tag  protection */
   1.245 -#define PAL_CACHE_PROT_PART_TAG_DATA	2	/* Tag+data protection (tag is
   1.246 -						 * more significant )
   1.247 -						 */
   1.248 -#define PAL_CACHE_PROT_PART_DATA_TAG	3	/* Data+tag protection (data is
   1.249 -						 * more significant )
   1.250 -						 */
   1.251 -#define PAL_CACHE_PROT_PART_MAX		6
   1.252 -
   1.253 -
   1.254 -typedef struct pal_cache_protection_info_s {
   1.255 -	pal_status_t			pcpi_status;
   1.256 -	pal_cache_protection_element_t	pcp_info[PAL_CACHE_PROT_PART_MAX];
   1.257 -} pal_cache_protection_info_t;
   1.258 -
   1.259 -
   1.260 -/* Processor cache protection method encodings */
   1.261 -#define PAL_CACHE_PROT_METHOD_NONE		0	/* No protection */
   1.262 -#define PAL_CACHE_PROT_METHOD_ODD_PARITY	1	/* Odd parity */
   1.263 -#define PAL_CACHE_PROT_METHOD_EVEN_PARITY	2	/* Even parity */
   1.264 -#define PAL_CACHE_PROT_METHOD_ECC		3	/* ECC protection */
   1.265 -
   1.266 -
   1.267 -/* Processor cache line identification in the heirarchy */
   1.268 -typedef union pal_cache_line_id_u {
   1.269 -	u64			pclid_data;
   1.270 -	struct {
   1.271 -		u64		cache_type	: 8,	/* 7-0 cache type */
   1.272 -				level		: 8,	/* 15-8 level of the
   1.273 -							 * cache in the
   1.274 -							 * heirarchy.
   1.275 -							 */
   1.276 -				way		: 8,	/* 23-16 way in the set
   1.277 -							 */
   1.278 -				part		: 8,	/* 31-24 part of the
   1.279 -							 * cache
   1.280 -							 */
   1.281 -				reserved	: 32;	/* 63-32 is reserved*/
   1.282 -	} pclid_info_read;
   1.283 -	struct {
   1.284 -		u64		cache_type	: 8,	/* 7-0 cache type */
   1.285 -				level		: 8,	/* 15-8 level of the
   1.286 -							 * cache in the
   1.287 -							 * heirarchy.
   1.288 -							 */
   1.289 -				way		: 8,	/* 23-16 way in the set
   1.290 -							 */
   1.291 -				part		: 8,	/* 31-24 part of the
   1.292 -							 * cache
   1.293 -							 */
   1.294 -				mesi		: 8,	/* 39-32 cache line
   1.295 -							 * state
   1.296 -							 */
   1.297 -				start		: 8,	/* 47-40 lsb of data to
   1.298 -							 * invert
   1.299 -							 */
   1.300 -				length		: 8,	/* 55-48 #bits to
   1.301 -							 * invert
   1.302 -							 */
   1.303 -				trigger		: 8;	/* 63-56 Trigger error
   1.304 -							 * by doing a load
   1.305 -							 * after the write
   1.306 -							 */
   1.307 -
   1.308 -	} pclid_info_write;
   1.309 -} pal_cache_line_id_u_t;
   1.310 -
   1.311 -#define pclid_read_part		pclid_info_read.part
   1.312 -#define pclid_read_way		pclid_info_read.way
   1.313 -#define pclid_read_level	pclid_info_read.level
   1.314 -#define pclid_read_cache_type	pclid_info_read.cache_type
   1.315 -
   1.316 -#define pclid_write_trigger	pclid_info_write.trigger
   1.317 -#define pclid_write_length	pclid_info_write.length
   1.318 -#define pclid_write_start	pclid_info_write.start
   1.319 -#define pclid_write_mesi	pclid_info_write.mesi
   1.320 -#define pclid_write_part	pclid_info_write.part
   1.321 -#define pclid_write_way		pclid_info_write.way
   1.322 -#define pclid_write_level	pclid_info_write.level
   1.323 -#define pclid_write_cache_type	pclid_info_write.cache_type
   1.324 -
   1.325 -/* Processor cache line part encodings */
   1.326 -#define PAL_CACHE_LINE_ID_PART_DATA		0	/* Data */
   1.327 -#define PAL_CACHE_LINE_ID_PART_TAG		1	/* Tag */
   1.328 -#define PAL_CACHE_LINE_ID_PART_DATA_PROT	2	/* Data protection */
   1.329 -#define PAL_CACHE_LINE_ID_PART_TAG_PROT		3	/* Tag protection */
   1.330 -#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT	4	/* Data+tag
   1.331 -							 * protection
   1.332 -							 */
   1.333 -typedef struct pal_cache_line_info_s {
   1.334 -	pal_status_t		pcli_status;		/* Return status of the read cache line
   1.335 -							 * info call.
   1.336 -							 */
   1.337 -	u64			pcli_data;		/* 64-bit data, tag, protection bits .. */
   1.338 -	u64			pcli_data_len;		/* data length in bits */
   1.339 -	pal_cache_line_state_t	pcli_cache_line_state;	/* mesi state */
   1.340 -
   1.341 -} pal_cache_line_info_t;
   1.342 -
   1.343 -
   1.344 -/* Machine Check related crap */
   1.345 -
   1.346 -/* Pending event status bits  */
   1.347 -typedef u64					pal_mc_pending_events_t;
   1.348 -
   1.349 -#define PAL_MC_PENDING_MCA			(1 << 0)
   1.350 -#define PAL_MC_PENDING_INIT			(1 << 1)
   1.351 -
   1.352 -/* Error information type */
   1.353 -typedef u64					pal_mc_info_index_t;
   1.354 -
   1.355 -#define PAL_MC_INFO_PROCESSOR			0	/* Processor */
   1.356 -#define PAL_MC_INFO_CACHE_CHECK			1	/* Cache check */
   1.357 -#define PAL_MC_INFO_TLB_CHECK			2	/* Tlb check */
   1.358 -#define PAL_MC_INFO_BUS_CHECK			3	/* Bus check */
   1.359 -#define PAL_MC_INFO_REQ_ADDR			4	/* Requestor address */
   1.360 -#define PAL_MC_INFO_RESP_ADDR			5	/* Responder address */
   1.361 -#define PAL_MC_INFO_TARGET_ADDR			6	/* Target address */
   1.362 -#define PAL_MC_INFO_IMPL_DEP			7	/* Implementation
   1.363 -							 * dependent
   1.364 -							 */
   1.365 -
   1.366 -
   1.367 -typedef struct pal_process_state_info_s {
   1.368 -	u64		reserved1	: 2,
   1.369 -			rz		: 1,	/* PAL_CHECK processor
   1.370 -						 * rendezvous
   1.371 -						 * successful.
   1.372 -						 */
   1.373 -
   1.374 -			ra		: 1,	/* PAL_CHECK attempted
   1.375 -						 * a rendezvous.
   1.376 -						 */
   1.377 -			me		: 1,	/* Distinct multiple
   1.378 -						 * errors occurred
   1.379 -						 */
   1.380 -
   1.381 -			mn		: 1,	/* Min. state save
   1.382 -						 * area has been
   1.383 -						 * registered with PAL
   1.384 -						 */
   1.385 -
   1.386 -			sy		: 1,	/* Storage integrity
   1.387 -						 * synched
   1.388 -						 */
   1.389 -
   1.390 -
   1.391 -			co		: 1,	/* Continuable */
   1.392 -			ci		: 1,	/* MC isolated */
   1.393 -			us		: 1,	/* Uncontained storage
   1.394 -						 * damage.
   1.395 -						 */
   1.396 -
   1.397 -
   1.398 -			hd		: 1,	/* Non-essential hw
   1.399 -						 * lost (no loss of
   1.400 -						 * functionality)
   1.401 -						 * causing the
   1.402 -						 * processor to run in
   1.403 -						 * degraded mode.
   1.404 -						 */
   1.405 -
   1.406 -			tl		: 1,	/* 1 => MC occurred
   1.407 -						 * after an instr was
   1.408 -						 * executed but before
   1.409 -						 * the trap that
   1.410 -						 * resulted from instr
   1.411 -						 * execution was
   1.412 -						 * generated.
   1.413 -						 * (Trap Lost )
   1.414 -						 */
   1.415 -			mi		: 1,	/* More information available
   1.416 -						 * call PAL_MC_ERROR_INFO
   1.417 -						 */
   1.418 -			pi		: 1,	/* Precise instruction pointer */
   1.419 -			pm		: 1,	/* Precise min-state save area */
   1.420 -
   1.421 -			dy		: 1,	/* Processor dynamic
   1.422 -						 * state valid
   1.423 -						 */
   1.424 -
   1.425 -
   1.426 -			in		: 1,	/* 0 = MC, 1 = INIT */
   1.427 -			rs		: 1,	/* RSE valid */
   1.428 -			cm		: 1,	/* MC corrected */
   1.429 -			ex		: 1,	/* MC is expected */
   1.430 -			cr		: 1,	/* Control regs valid*/
   1.431 -			pc		: 1,	/* Perf cntrs valid */
   1.432 -			dr		: 1,	/* Debug regs valid */
   1.433 -			tr		: 1,	/* Translation regs
   1.434 -						 * valid
   1.435 -						 */
   1.436 -			rr		: 1,	/* Region regs valid */
   1.437 -			ar		: 1,	/* App regs valid */
   1.438 -			br		: 1,	/* Branch regs valid */
   1.439 -			pr		: 1,	/* Predicate registers
   1.440 -						 * valid
   1.441 -						 */
   1.442 -
   1.443 -			fp		: 1,	/* fp registers valid*/
   1.444 -			b1		: 1,	/* Preserved bank one
   1.445 -						 * general registers
   1.446 -						 * are valid
   1.447 -						 */
   1.448 -			b0		: 1,	/* Preserved bank zero
   1.449 -						 * general registers
   1.450 -						 * are valid
   1.451 -						 */
   1.452 -			gr		: 1,	/* General registers
   1.453 -						 * are valid
   1.454 -						 * (excl. banked regs)
   1.455 -						 */
   1.456 -			dsize		: 16,	/* size of dynamic
   1.457 -						 * state returned
   1.458 -						 * by the processor
   1.459 -						 */
   1.460 -
   1.461 -			reserved2	: 11,
   1.462 -			cc		: 1,	/* Cache check */
   1.463 -			tc		: 1,	/* TLB check */
   1.464 -			bc		: 1,	/* Bus check */
   1.465 -			rc		: 1,	/* Register file check */
   1.466 -			uc		: 1;	/* Uarch check */
   1.467 -
   1.468 -} pal_processor_state_info_t;
   1.469 -
   1.470 -typedef struct pal_cache_check_info_s {
   1.471 -	u64		op		: 4,	/* Type of cache
   1.472 -						 * operation that
   1.473 -						 * caused the machine
   1.474 -						 * check.
   1.475 -						 */
   1.476 -			level		: 2,	/* Cache level */
   1.477 -			reserved1	: 2,
   1.478 -			dl		: 1,	/* Failure in data part
   1.479 -						 * of cache line
   1.480 -						 */
   1.481 -			tl		: 1,	/* Failure in tag part
   1.482 -						 * of cache line
   1.483 -						 */
   1.484 -			dc		: 1,	/* Failure in dcache */
   1.485 -			ic		: 1,	/* Failure in icache */
   1.486 -			mesi		: 3,	/* Cache line state */
   1.487 -			mv		: 1,	/* mesi valid */
   1.488 -			way		: 5,	/* Way in which the
   1.489 -						 * error occurred
   1.490 -						 */
   1.491 -			wiv		: 1,	/* Way field valid */
   1.492 -			reserved2	: 10,
   1.493 -
   1.494 -			index		: 20,	/* Cache line index */
   1.495 -			reserved3	: 2,
   1.496 -
   1.497 -			is		: 1,	/* instruction set (1 == ia32) */
   1.498 -			iv		: 1,	/* instruction set field valid */
   1.499 -			pl		: 2,	/* privilege level */
   1.500 -			pv		: 1,	/* privilege level field valid */
   1.501 -			mcc		: 1,	/* Machine check corrected */
   1.502 -			tv		: 1,	/* Target address
   1.503 -						 * structure is valid
   1.504 -						 */
   1.505 -			rq		: 1,	/* Requester identifier
   1.506 -						 * structure is valid
   1.507 -						 */
   1.508 -			rp		: 1,	/* Responder identifier
   1.509 -						 * structure is valid
   1.510 -						 */
   1.511 -			pi		: 1;	/* Precise instruction pointer
   1.512 -						 * structure is valid
   1.513 -						 */
   1.514 -} pal_cache_check_info_t;
   1.515 -
   1.516 -typedef struct pal_tlb_check_info_s {
   1.517 -
   1.518 -	u64		tr_slot		: 8,	/* Slot# of TR where
   1.519 -						 * error occurred
   1.520 -						 */
   1.521 -			trv		: 1,	/* tr_slot field is valid */
   1.522 -			reserved1	: 1,
   1.523 -			level		: 2,	/* TLB level where failure occurred */
   1.524 -			reserved2	: 4,
   1.525 -			dtr		: 1,	/* Fail in data TR */
   1.526 -			itr		: 1,	/* Fail in inst TR */
   1.527 -			dtc		: 1,	/* Fail in data TC */
   1.528 -			itc		: 1,	/* Fail in inst. TC */
   1.529 -			op		: 4,	/* Cache operation */
   1.530 -			reserved3	: 30,
   1.531 -
   1.532 -			is		: 1,	/* instruction set (1 == ia32) */
   1.533 -			iv		: 1,	/* instruction set field valid */
   1.534 -			pl		: 2,	/* privilege level */
   1.535 -			pv		: 1,	/* privilege level field valid */
   1.536 -			mcc		: 1,	/* Machine check corrected */
   1.537 -			tv		: 1,	/* Target address
   1.538 -						 * structure is valid
   1.539 -						 */
   1.540 -			rq		: 1,	/* Requester identifier
   1.541 -						 * structure is valid
   1.542 -						 */
   1.543 -			rp		: 1,	/* Responder identifier
   1.544 -						 * structure is valid
   1.545 -						 */
   1.546 -			pi		: 1;	/* Precise instruction pointer
   1.547 -						 * structure is valid
   1.548 -						 */
   1.549 -} pal_tlb_check_info_t;
   1.550 -
   1.551 -typedef struct pal_bus_check_info_s {
   1.552 -	u64		size		: 5,	/* Xaction size */
   1.553 -			ib		: 1,	/* Internal bus error */
   1.554 -			eb		: 1,	/* External bus error */
   1.555 -			cc		: 1,	/* Error occurred
   1.556 -						 * during cache-cache
   1.557 -						 * transfer.
   1.558 -						 */
   1.559 -			type		: 8,	/* Bus xaction type*/
   1.560 -			sev		: 5,	/* Bus error severity*/
   1.561 -			hier		: 2,	/* Bus hierarchy level */
   1.562 -			reserved1	: 1,
   1.563 -			bsi		: 8,	/* Bus error status
   1.564 -						 * info
   1.565 -						 */
   1.566 -			reserved2	: 22,
   1.567 -
   1.568 -			is		: 1,	/* instruction set (1 == ia32) */
   1.569 -			iv		: 1,	/* instruction set field valid */
   1.570 -			pl		: 2,	/* privilege level */
   1.571 -			pv		: 1,	/* privilege level field valid */
   1.572 -			mcc		: 1,	/* Machine check corrected */
   1.573 -			tv		: 1,	/* Target address
   1.574 -						 * structure is valid
   1.575 -						 */
   1.576 -			rq		: 1,	/* Requester identifier
   1.577 -						 * structure is valid
   1.578 -						 */
   1.579 -			rp		: 1,	/* Responder identifier
   1.580 -						 * structure is valid
   1.581 -						 */
   1.582 -			pi		: 1;	/* Precise instruction pointer
   1.583 -						 * structure is valid
   1.584 -						 */
   1.585 -} pal_bus_check_info_t;
   1.586 -
   1.587 -typedef struct pal_reg_file_check_info_s {
   1.588 -	u64		id		: 4,	/* Register file identifier */
   1.589 -			op		: 4,	/* Type of register
   1.590 -						 * operation that
   1.591 -						 * caused the machine
   1.592 -						 * check.
   1.593 -						 */
   1.594 -			reg_num		: 7,	/* Register number */
   1.595 -			rnv		: 1,	/* reg_num valid */
   1.596 -			reserved2	: 38,
   1.597 -
   1.598 -			is		: 1,	/* instruction set (1 == ia32) */
   1.599 -			iv		: 1,	/* instruction set field valid */
   1.600 -			pl		: 2,	/* privilege level */
   1.601 -			pv		: 1,	/* privilege level field valid */
   1.602 -			mcc		: 1,	/* Machine check corrected */
   1.603 -			reserved3	: 3,
   1.604 -			pi		: 1;	/* Precise instruction pointer
   1.605 -						 * structure is valid
   1.606 -						 */
   1.607 -} pal_reg_file_check_info_t;
   1.608 -
   1.609 -typedef struct pal_uarch_check_info_s {
   1.610 -	u64		sid		: 5,	/* Structure identification */
   1.611 -			level		: 3,	/* Level of failure */
   1.612 -			array_id	: 4,	/* Array identification */
   1.613 -			op		: 4,	/* Type of
   1.614 -						 * operation that
   1.615 -						 * caused the machine
   1.616 -						 * check.
   1.617 -						 */
   1.618 -			way		: 6,	/* Way of structure */
   1.619 -			wv		: 1,	/* way valid */
   1.620 -			xv		: 1,	/* index valid */
   1.621 -			reserved1	: 8,
   1.622 -			index		: 8,	/* Index or set of the uarch
   1.623 -						 * structure that failed.
   1.624 -						 */
   1.625 -			reserved2	: 24,
   1.626 -
   1.627 -			is		: 1,	/* instruction set (1 == ia32) */
   1.628 -			iv		: 1,	/* instruction set field valid */
   1.629 -			pl		: 2,	/* privilege level */
   1.630 -			pv		: 1,	/* privilege level field valid */
   1.631 -			mcc		: 1,	/* Machine check corrected */
   1.632 -			tv		: 1,	/* Target address
   1.633 -						 * structure is valid
   1.634 -						 */
   1.635 -			rq		: 1,	/* Requester identifier
   1.636 -						 * structure is valid
   1.637 -						 */
   1.638 -			rp		: 1,	/* Responder identifier
   1.639 -						 * structure is valid
   1.640 -						 */
   1.641 -			pi		: 1;	/* Precise instruction pointer
   1.642 -						 * structure is valid
   1.643 -						 */
   1.644 -} pal_uarch_check_info_t;
   1.645 -
   1.646 -typedef union pal_mc_error_info_u {
   1.647 -	u64				pmei_data;
   1.648 -	pal_processor_state_info_t	pme_processor;
   1.649 -	pal_cache_check_info_t		pme_cache;
   1.650 -	pal_tlb_check_info_t		pme_tlb;
   1.651 -	pal_bus_check_info_t		pme_bus;
   1.652 -	pal_reg_file_check_info_t	pme_reg_file;
   1.653 -	pal_uarch_check_info_t		pme_uarch;
   1.654 -} pal_mc_error_info_t;
   1.655 -
   1.656 -#define pmci_proc_unknown_check			pme_processor.uc
   1.657 -#define pmci_proc_bus_check			pme_processor.bc
   1.658 -#define pmci_proc_tlb_check			pme_processor.tc
   1.659 -#define pmci_proc_cache_check			pme_processor.cc
   1.660 -#define pmci_proc_dynamic_state_size		pme_processor.dsize
   1.661 -#define pmci_proc_gpr_valid			pme_processor.gr
   1.662 -#define pmci_proc_preserved_bank0_gpr_valid	pme_processor.b0
   1.663 -#define pmci_proc_preserved_bank1_gpr_valid	pme_processor.b1
   1.664 -#define pmci_proc_fp_valid			pme_processor.fp
   1.665 -#define pmci_proc_predicate_regs_valid		pme_processor.pr
   1.666 -#define pmci_proc_branch_regs_valid		pme_processor.br
   1.667 -#define pmci_proc_app_regs_valid		pme_processor.ar
   1.668 -#define pmci_proc_region_regs_valid		pme_processor.rr
   1.669 -#define pmci_proc_translation_regs_valid	pme_processor.tr
   1.670 -#define pmci_proc_debug_regs_valid		pme_processor.dr
   1.671 -#define pmci_proc_perf_counters_valid		pme_processor.pc
   1.672 -#define pmci_proc_control_regs_valid		pme_processor.cr
   1.673 -#define pmci_proc_machine_check_expected	pme_processor.ex
   1.674 -#define pmci_proc_machine_check_corrected	pme_processor.cm
   1.675 -#define pmci_proc_rse_valid			pme_processor.rs
   1.676 -#define pmci_proc_machine_check_or_init		pme_processor.in
   1.677 -#define pmci_proc_dynamic_state_valid		pme_processor.dy
   1.678 -#define pmci_proc_operation			pme_processor.op
   1.679 -#define pmci_proc_trap_lost			pme_processor.tl
   1.680 -#define pmci_proc_hardware_damage		pme_processor.hd
   1.681 -#define pmci_proc_uncontained_storage_damage	pme_processor.us
   1.682 -#define pmci_proc_machine_check_isolated	pme_processor.ci
   1.683 -#define pmci_proc_continuable			pme_processor.co
   1.684 -#define pmci_proc_storage_intergrity_synced	pme_processor.sy
   1.685 -#define pmci_proc_min_state_save_area_regd	pme_processor.mn
   1.686 -#define	pmci_proc_distinct_multiple_errors	pme_processor.me
   1.687 -#define pmci_proc_pal_attempted_rendezvous	pme_processor.ra
   1.688 -#define pmci_proc_pal_rendezvous_complete	pme_processor.rz
   1.689 -
   1.690 -
   1.691 -#define pmci_cache_level			pme_cache.level
   1.692 -#define pmci_cache_line_state			pme_cache.mesi
   1.693 -#define pmci_cache_line_state_valid		pme_cache.mv
   1.694 -#define pmci_cache_line_index			pme_cache.index
   1.695 -#define pmci_cache_instr_cache_fail		pme_cache.ic
   1.696 -#define pmci_cache_data_cache_fail		pme_cache.dc
   1.697 -#define pmci_cache_line_tag_fail		pme_cache.tl
   1.698 -#define pmci_cache_line_data_fail		pme_cache.dl
   1.699 -#define pmci_cache_operation			pme_cache.op
   1.700 -#define pmci_cache_way_valid			pme_cache.wv
   1.701 -#define pmci_cache_target_address_valid		pme_cache.tv
   1.702 -#define pmci_cache_way				pme_cache.way
   1.703 -#define pmci_cache_mc				pme_cache.mc
   1.704 -
   1.705 -#define pmci_tlb_instr_translation_cache_fail	pme_tlb.itc
   1.706 -#define pmci_tlb_data_translation_cache_fail	pme_tlb.dtc
   1.707 -#define pmci_tlb_instr_translation_reg_fail	pme_tlb.itr
   1.708 -#define pmci_tlb_data_translation_reg_fail	pme_tlb.dtr
   1.709 -#define pmci_tlb_translation_reg_slot		pme_tlb.tr_slot
   1.710 -#define pmci_tlb_mc				pme_tlb.mc
   1.711 -
   1.712 -#define pmci_bus_status_info			pme_bus.bsi
   1.713 -#define pmci_bus_req_address_valid		pme_bus.rq
   1.714 -#define pmci_bus_resp_address_valid		pme_bus.rp
   1.715 -#define pmci_bus_target_address_valid		pme_bus.tv
   1.716 -#define pmci_bus_error_severity			pme_bus.sev
   1.717 -#define pmci_bus_transaction_type		pme_bus.type
   1.718 -#define pmci_bus_cache_cache_transfer		pme_bus.cc
   1.719 -#define pmci_bus_transaction_size		pme_bus.size
   1.720 -#define pmci_bus_internal_error			pme_bus.ib
   1.721 -#define pmci_bus_external_error			pme_bus.eb
   1.722 -#define pmci_bus_mc				pme_bus.mc
   1.723 -
   1.724 -/*
   1.725 - * NOTE: this min_state_save area struct only includes the 1KB
   1.726 - * architectural state save area.  The other 3 KB is scratch space
   1.727 - * for PAL.
   1.728 - */
   1.729 -
   1.730 -typedef struct pal_min_state_area_s {
   1.731 -	u64	pmsa_nat_bits;		/* nat bits for saved GRs  */
   1.732 -	u64	pmsa_gr[15];		/* GR1	- GR15		   */
   1.733 -	u64	pmsa_bank0_gr[16];	/* GR16 - GR31		   */
   1.734 -	u64	pmsa_bank1_gr[16];	/* GR16 - GR31		   */
   1.735 -	u64	pmsa_pr;		/* predicate registers	   */
   1.736 -	u64	pmsa_br0;		/* branch register 0	   */
   1.737 -	u64	pmsa_rsc;		/* ar.rsc		   */
   1.738 -	u64	pmsa_iip;		/* cr.iip		   */
   1.739 -	u64	pmsa_ipsr;		/* cr.ipsr		   */
   1.740 -	u64	pmsa_ifs;		/* cr.ifs		   */
   1.741 -	u64	pmsa_xip;		/* previous iip		   */
   1.742 -	u64	pmsa_xpsr;		/* previous psr		   */
   1.743 -	u64	pmsa_xfs;		/* previous ifs		   */
   1.744 -	u64	pmsa_br1;		/* branch register 1	   */
   1.745 -	u64	pmsa_reserved[70];	/* pal_min_state_area should total to 1KB */
   1.746 -} pal_min_state_area_t;
   1.747 -
   1.748 -
   1.749 -struct ia64_pal_retval {
   1.750 -	/*
   1.751 -	 * A zero status value indicates call completed without error.
   1.752 -	 * A negative status value indicates reason of call failure.
   1.753 -	 * A positive status value indicates success but an
   1.754 -	 * informational value should be printed (e.g., "reboot for
   1.755 -	 * change to take effect").
   1.756 -	 */
   1.757 -	s64 status;
   1.758 -	u64 v0;
   1.759 -	u64 v1;
   1.760 -	u64 v2;
   1.761 -};
   1.762 -
   1.763 -/*
   1.764 - * Note: Currently unused PAL arguments are generally labeled
   1.765 - * "reserved" so the value specified in the PAL documentation
   1.766 - * (generally 0) MUST be passed.  Reserved parameters are not optional
   1.767 - * parameters.
   1.768 - */
   1.769 -extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
   1.770 -extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
   1.771 -extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
   1.772 -extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
   1.773 -extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
   1.774 -extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
   1.775 -
   1.776 -#define PAL_CALL(iprv,a0,a1,a2,a3) do {			\
   1.777 -	struct ia64_fpreg fr[6];			\
   1.778 -	ia64_save_scratch_fpregs(fr);			\
   1.779 -	iprv = ia64_pal_call_static(a0, a1, a2, a3, 0);	\
   1.780 -	ia64_load_scratch_fpregs(fr);			\
   1.781 -} while (0)
   1.782 -
   1.783 -#define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do {		\
   1.784 -	struct ia64_fpreg fr[6];			\
   1.785 -	ia64_save_scratch_fpregs(fr);			\
   1.786 -	iprv = ia64_pal_call_static(a0, a1, a2, a3, 1);	\
   1.787 -	ia64_load_scratch_fpregs(fr);			\
   1.788 -} while (0)
   1.789 -
   1.790 -#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {		\
   1.791 -	struct ia64_fpreg fr[6];			\
   1.792 -	ia64_save_scratch_fpregs(fr);			\
   1.793 -	iprv = ia64_pal_call_stacked(a0, a1, a2, a3);	\
   1.794 -	ia64_load_scratch_fpregs(fr);			\
   1.795 -} while (0)
   1.796 -
   1.797 -#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {			\
   1.798 -	struct ia64_fpreg fr[6];				\
   1.799 -	ia64_save_scratch_fpregs(fr);				\
   1.800 -	iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);	\
   1.801 -	ia64_load_scratch_fpregs(fr);				\
   1.802 -} while (0)
   1.803 -
   1.804 -#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {		\
   1.805 -	struct ia64_fpreg fr[6];				\
   1.806 -	ia64_save_scratch_fpregs(fr);				\
   1.807 -	iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);	\
   1.808 -	ia64_load_scratch_fpregs(fr);				\
   1.809 -} while (0)
   1.810 -
   1.811 -typedef int (*ia64_pal_handler) (u64, ...);
   1.812 -extern ia64_pal_handler ia64_pal;
   1.813 -extern void ia64_pal_handler_init (void *);
   1.814 -
   1.815 -extern ia64_pal_handler ia64_pal;
   1.816 -
   1.817 -extern pal_cache_config_info_t		l0d_cache_config_info;
   1.818 -extern pal_cache_config_info_t		l0i_cache_config_info;
   1.819 -extern pal_cache_config_info_t		l1_cache_config_info;
   1.820 -extern pal_cache_config_info_t		l2_cache_config_info;
   1.821 -
   1.822 -extern pal_cache_protection_info_t	l0d_cache_protection_info;
   1.823 -extern pal_cache_protection_info_t	l0i_cache_protection_info;
   1.824 -extern pal_cache_protection_info_t	l1_cache_protection_info;
   1.825 -extern pal_cache_protection_info_t	l2_cache_protection_info;
   1.826 -
   1.827 -extern pal_cache_config_info_t		pal_cache_config_info_get(pal_cache_level_t,
   1.828 -								  pal_cache_type_t);
   1.829 -
   1.830 -extern pal_cache_protection_info_t	pal_cache_protection_info_get(pal_cache_level_t,
   1.831 -								      pal_cache_type_t);
   1.832 -
   1.833 -
   1.834 -extern void				pal_error(int);
   1.835 -
   1.836 -
   1.837 -/* Useful wrappers for the current list of pal procedures */
   1.838 -
   1.839 -typedef union pal_bus_features_u {
   1.840 -	u64	pal_bus_features_val;
   1.841 -	struct {
   1.842 -		u64	pbf_reserved1				:	29;
   1.843 -		u64	pbf_req_bus_parking			:	1;
   1.844 -		u64	pbf_bus_lock_mask			:	1;
   1.845 -		u64	pbf_enable_half_xfer_rate		:	1;
   1.846 -		u64	pbf_reserved2				:	22;
   1.847 -		u64	pbf_disable_xaction_queueing		:	1;
   1.848 -		u64	pbf_disable_resp_err_check		:	1;
   1.849 -		u64	pbf_disable_berr_check			:	1;
   1.850 -		u64	pbf_disable_bus_req_internal_err_signal	:	1;
   1.851 -		u64	pbf_disable_bus_req_berr_signal		:	1;
   1.852 -		u64	pbf_disable_bus_init_event_check	:	1;
   1.853 -		u64	pbf_disable_bus_init_event_signal	:	1;
   1.854 -		u64	pbf_disable_bus_addr_err_check		:	1;
   1.855 -		u64	pbf_disable_bus_addr_err_signal		:	1;
   1.856 -		u64	pbf_disable_bus_data_err_check		:	1;
   1.857 -	} pal_bus_features_s;
   1.858 -} pal_bus_features_u_t;
   1.859 -
   1.860 -extern void pal_bus_features_print (u64);
   1.861 -
   1.862 -/* Provide information about configurable processor bus features */
   1.863 -static inline s64
   1.864 -ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
   1.865 -			   pal_bus_features_u_t *features_status,
   1.866 -			   pal_bus_features_u_t *features_control)
   1.867 -{
   1.868 -	struct ia64_pal_retval iprv;
   1.869 -	PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
   1.870 -	if (features_avail)
   1.871 -		features_avail->pal_bus_features_val = iprv.v0;
   1.872 -	if (features_status)
   1.873 -		features_status->pal_bus_features_val = iprv.v1;
   1.874 -	if (features_control)
   1.875 -		features_control->pal_bus_features_val = iprv.v2;
   1.876 -	return iprv.status;
   1.877 -}
   1.878 -
   1.879 -/* Enables/disables specific processor bus features */
   1.880 -static inline s64
   1.881 -ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
   1.882 -{
   1.883 -	struct ia64_pal_retval iprv;
   1.884 -	PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
   1.885 -	return iprv.status;
   1.886 -}
   1.887 -
   1.888 -/* Get detailed cache information */
   1.889 -static inline s64
   1.890 -ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
   1.891 -{
   1.892 -	struct ia64_pal_retval iprv;
   1.893 -
   1.894 -	PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
   1.895 -
   1.896 -	if (iprv.status == 0) {
   1.897 -		conf->pcci_status                 = iprv.status;
   1.898 -		conf->pcci_info_1.pcci1_data      = iprv.v0;
   1.899 -		conf->pcci_info_2.pcci2_data      = iprv.v1;
   1.900 -		conf->pcci_reserved               = iprv.v2;
   1.901 -	}
   1.902 -	return iprv.status;
   1.903 -
   1.904 -}
   1.905 -
   1.906 -/* Get detailed cche protection information */
   1.907 -static inline s64
   1.908 -ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
   1.909 -{
   1.910 -	struct ia64_pal_retval iprv;
   1.911 -
   1.912 -	PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
   1.913 -
   1.914 -	if (iprv.status == 0) {
   1.915 -		prot->pcpi_status           = iprv.status;
   1.916 -		prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
   1.917 -		prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
   1.918 -		prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
   1.919 -		prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
   1.920 -		prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
   1.921 -		prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
   1.922 -	}
   1.923 -	return iprv.status;
   1.924 -}
   1.925 -
   1.926 -/*
   1.927 - * Flush the processor instruction or data caches.  *PROGRESS must be
   1.928 - * initialized to zero before calling this for the first time..
   1.929 - */
   1.930 -static inline s64
   1.931 -ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
   1.932 -{
   1.933 -	struct ia64_pal_retval iprv;
   1.934 -	PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
   1.935 -	if (vector)
   1.936 -		*vector = iprv.v0;
   1.937 -	*progress = iprv.v1;
   1.938 -	return iprv.status;
   1.939 -}
   1.940 -
   1.941 -
   1.942 -/* Initialize the processor controlled caches */
   1.943 -static inline s64
   1.944 -ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
   1.945 -{
   1.946 -	struct ia64_pal_retval iprv;
   1.947 -	PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
   1.948 -	return iprv.status;
   1.949 -}
   1.950 -
   1.951 -/* Initialize the tags and data of a data or unified cache line of
   1.952 - * processor controlled cache to known values without the availability
   1.953 - * of backing memory.
   1.954 - */
   1.955 -static inline s64
   1.956 -ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
   1.957 -{
   1.958 -	struct ia64_pal_retval iprv;
   1.959 -	PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
   1.960 -	return iprv.status;
   1.961 -}
   1.962 -
   1.963 -
   1.964 -/* Read the data and tag of a processor controlled cache line for diags */
   1.965 -static inline s64
   1.966 -ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
   1.967 -{
   1.968 -	struct ia64_pal_retval iprv;
   1.969 -	PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
   1.970 -	return iprv.status;
   1.971 -}
   1.972 -
   1.973 -/* Return summary information about the heirarchy of caches controlled by the processor */
   1.974 -static inline s64
   1.975 -ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
   1.976 -{
   1.977 -	struct ia64_pal_retval iprv;
   1.978 -	PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
   1.979 -	if (cache_levels)
   1.980 -		*cache_levels = iprv.v0;
   1.981 -	if (unique_caches)
   1.982 -		*unique_caches = iprv.v1;
   1.983 -	return iprv.status;
   1.984 -}
   1.985 -
   1.986 -/* Write the data and tag of a processor-controlled cache line for diags */
   1.987 -static inline s64
   1.988 -ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
   1.989 -{
   1.990 -	struct ia64_pal_retval iprv;
   1.991 -	PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
   1.992 -	return iprv.status;
   1.993 -}
   1.994 -
   1.995 -
   1.996 -/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
   1.997 -static inline s64
   1.998 -ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
   1.999 -		    u64 *buffer_size, u64 *buffer_align)
  1.1000 -{
  1.1001 -	struct ia64_pal_retval iprv;
  1.1002 -	PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
  1.1003 -	if (buffer_size)
  1.1004 -		*buffer_size = iprv.v0;
  1.1005 -	if (buffer_align)
  1.1006 -		*buffer_align = iprv.v1;
  1.1007 -	return iprv.status;
  1.1008 -}
  1.1009 -
  1.1010 -/* Copy relocatable PAL procedures from ROM to memory */
  1.1011 -static inline s64
  1.1012 -ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
  1.1013 -{
  1.1014 -	struct ia64_pal_retval iprv;
  1.1015 -	PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
  1.1016 -	if (pal_proc_offset)
  1.1017 -		*pal_proc_offset = iprv.v0;
  1.1018 -	return iprv.status;
  1.1019 -}
  1.1020 -
  1.1021 -/* Return the number of instruction and data debug register pairs */
  1.1022 -static inline s64
  1.1023 -ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
  1.1024 -{
  1.1025 -	struct ia64_pal_retval iprv;
  1.1026 -	PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
  1.1027 -	if (inst_regs)
  1.1028 -		*inst_regs = iprv.v0;
  1.1029 -	if (data_regs)
  1.1030 -		*data_regs = iprv.v1;
  1.1031 -
  1.1032 -	return iprv.status;
  1.1033 -}
  1.1034 -
  1.1035 -#ifdef TBD
  1.1036 -/* Switch from IA64-system environment to IA-32 system environment */
  1.1037 -static inline s64
  1.1038 -ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
  1.1039 -{
  1.1040 -	struct ia64_pal_retval iprv;
  1.1041 -	PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
  1.1042 -	return iprv.status;
  1.1043 -}
  1.1044 -#endif
  1.1045 -
  1.1046 -/* Get unique geographical address of this processor on its bus */
  1.1047 -static inline s64
  1.1048 -ia64_pal_fixed_addr (u64 *global_unique_addr)
  1.1049 -{
  1.1050 -	struct ia64_pal_retval iprv;
  1.1051 -	PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
  1.1052 -	if (global_unique_addr)
  1.1053 -		*global_unique_addr = iprv.v0;
  1.1054 -	return iprv.status;
  1.1055 -}
  1.1056 -
  1.1057 -/* Get base frequency of the platform if generated by the processor */
  1.1058 -static inline s64
  1.1059 -ia64_pal_freq_base (u64 *platform_base_freq)
  1.1060 -{
  1.1061 -	struct ia64_pal_retval iprv;
  1.1062 -	PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
  1.1063 -	if (platform_base_freq)
  1.1064 -		*platform_base_freq = iprv.v0;
  1.1065 -	return iprv.status;
  1.1066 -}
  1.1067 -
  1.1068 -/*
  1.1069 - * Get the ratios for processor frequency, bus frequency and interval timer to
  1.1070 - * to base frequency of the platform
  1.1071 - */
  1.1072 -static inline s64
  1.1073 -ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
  1.1074 -		      struct pal_freq_ratio *itc_ratio)
  1.1075 -{
  1.1076 -	struct ia64_pal_retval iprv;
  1.1077 -	PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
  1.1078 -	if (proc_ratio)
  1.1079 -		*(u64 *)proc_ratio = iprv.v0;
  1.1080 -	if (bus_ratio)
  1.1081 -		*(u64 *)bus_ratio = iprv.v1;
  1.1082 -	if (itc_ratio)
  1.1083 -		*(u64 *)itc_ratio = iprv.v2;
  1.1084 -	return iprv.status;
  1.1085 -}
  1.1086 -
  1.1087 -/* Make the processor enter HALT or one of the implementation dependent low
  1.1088 - * power states where prefetching and execution are suspended and cache and
  1.1089 - * TLB coherency is not maintained.
  1.1090 - */
  1.1091 -static inline s64
  1.1092 -ia64_pal_halt (u64 halt_state)
  1.1093 -{
  1.1094 -	struct ia64_pal_retval iprv;
  1.1095 -	PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
  1.1096 -	return iprv.status;
  1.1097 -}
  1.1098 -
  1.1099 -typedef union pal_power_mgmt_info_u {
  1.1100 -	u64			ppmi_data;
  1.1101 -	struct {
  1.1102 -	       u64		exit_latency		: 16,
  1.1103 -				entry_latency		: 16,
  1.1104 -				power_consumption	: 28,
  1.1105 -				im			: 1,
  1.1106 -				co			: 1,
  1.1107 -				reserved		: 2;
  1.1108 -	} pal_power_mgmt_info_s;
  1.1109 -} pal_power_mgmt_info_u_t;
  1.1110 -
  1.1111 -/* Return information about processor's optional power management capabilities. */
  1.1112 -static inline s64
  1.1113 -ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
  1.1114 -{
  1.1115 -	struct ia64_pal_retval iprv;
  1.1116 -	PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
  1.1117 -	return iprv.status;
  1.1118 -}
  1.1119 -
  1.1120 -/* Get the current P-state information */
  1.1121 -static inline s64
  1.1122 -ia64_pal_get_pstate (u64 *pstate_index)
  1.1123 -{
  1.1124 -	struct ia64_pal_retval iprv;
  1.1125 -	PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
  1.1126 -	*pstate_index = iprv.v0;
  1.1127 -	return iprv.status;
  1.1128 -}
  1.1129 -
  1.1130 -/* Set the P-state */
  1.1131 -static inline s64
  1.1132 -ia64_pal_set_pstate (u64 pstate_index)
  1.1133 -{
  1.1134 -	struct ia64_pal_retval iprv;
  1.1135 -	PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
  1.1136 -	return iprv.status;
  1.1137 -}
  1.1138 -
  1.1139 -/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
  1.1140 - * suspended, but cache and TLB coherency is maintained.
  1.1141 - */
  1.1142 -static inline s64
  1.1143 -ia64_pal_halt_light (void)
  1.1144 -{
  1.1145 -	struct ia64_pal_retval iprv;
  1.1146 -	PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
  1.1147 -	return iprv.status;
  1.1148 -}
  1.1149 -
  1.1150 -/* Clear all the processor error logging   registers and reset the indicator that allows
  1.1151 - * the error logging registers to be written. This procedure also checks the pending
  1.1152 - * machine check bit and pending INIT bit and reports their states.
  1.1153 - */
  1.1154 -static inline s64
  1.1155 -ia64_pal_mc_clear_log (u64 *pending_vector)
  1.1156 -{
  1.1157 -	struct ia64_pal_retval iprv;
  1.1158 -	PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
  1.1159 -	if (pending_vector)
  1.1160 -		*pending_vector = iprv.v0;
  1.1161 -	return iprv.status;
  1.1162 -}
  1.1163 -
  1.1164 -/* Ensure that all outstanding transactions in a processor are completed or that any
  1.1165 - * MCA due to thes outstanding transaction is taken.
  1.1166 - */
  1.1167 -static inline s64
  1.1168 -ia64_pal_mc_drain (void)
  1.1169 -{
  1.1170 -	struct ia64_pal_retval iprv;
  1.1171 -	PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
  1.1172 -	return iprv.status;
  1.1173 -}
  1.1174 -
  1.1175 -/* Return the machine check dynamic processor state */
  1.1176 -static inline s64
  1.1177 -ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
  1.1178 -{
  1.1179 -	struct ia64_pal_retval iprv;
  1.1180 -	PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
  1.1181 -	if (size)
  1.1182 -		*size = iprv.v0;
  1.1183 -	if (pds)
  1.1184 -		*pds = iprv.v1;
  1.1185 -	return iprv.status;
  1.1186 -}
  1.1187 -
  1.1188 -/* Return processor machine check information */
  1.1189 -static inline s64
  1.1190 -ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
  1.1191 -{
  1.1192 -	struct ia64_pal_retval iprv;
  1.1193 -	PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
  1.1194 -	if (size)
  1.1195 -		*size = iprv.v0;
  1.1196 -	if (error_info)
  1.1197 -		*error_info = iprv.v1;
  1.1198 -	return iprv.status;
  1.1199 -}
  1.1200 -
  1.1201 -/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
  1.1202 - * attempt to correct any expected machine checks.
  1.1203 - */
  1.1204 -static inline s64
  1.1205 -ia64_pal_mc_expected (u64 expected, u64 *previous)
  1.1206 -{
  1.1207 -	struct ia64_pal_retval iprv;
  1.1208 -	PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
  1.1209 -	if (previous)
  1.1210 -		*previous = iprv.v0;
  1.1211 -	return iprv.status;
  1.1212 -}
  1.1213 -
  1.1214 -/* Register a platform dependent location with PAL to which it can save
  1.1215 - * minimal processor state in the event of a machine check or initialization
  1.1216 - * event.
  1.1217 - */
  1.1218 -static inline s64
  1.1219 -ia64_pal_mc_register_mem (u64 physical_addr)
  1.1220 -{
  1.1221 -	struct ia64_pal_retval iprv;
  1.1222 -	PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
  1.1223 -	return iprv.status;
  1.1224 -}
  1.1225 -
  1.1226 -/* Restore minimal architectural processor state, set CMC interrupt if necessary
  1.1227 - * and resume execution
  1.1228 - */
  1.1229 -static inline s64
  1.1230 -ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
  1.1231 -{
  1.1232 -	struct ia64_pal_retval iprv;
  1.1233 -	PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
  1.1234 -	return iprv.status;
  1.1235 -}
  1.1236 -
  1.1237 -/* Return the memory attributes implemented by the processor */
  1.1238 -static inline s64
  1.1239 -ia64_pal_mem_attrib (u64 *mem_attrib)
  1.1240 -{
  1.1241 -	struct ia64_pal_retval iprv;
  1.1242 -	PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
  1.1243 -	if (mem_attrib)
  1.1244 -		*mem_attrib = iprv.v0 & 0xff;
  1.1245 -	return iprv.status;
  1.1246 -}
  1.1247 -
  1.1248 -/* Return the amount of memory needed for second phase of processor
  1.1249 - * self-test and the required alignment of memory.
  1.1250 - */
  1.1251 -static inline s64
  1.1252 -ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
  1.1253 -{
  1.1254 -	struct ia64_pal_retval iprv;
  1.1255 -	PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
  1.1256 -	if (bytes_needed)
  1.1257 -		*bytes_needed = iprv.v0;
  1.1258 -	if (alignment)
  1.1259 -		*alignment = iprv.v1;
  1.1260 -	return iprv.status;
  1.1261 -}
  1.1262 -
  1.1263 -typedef union pal_perf_mon_info_u {
  1.1264 -	u64			  ppmi_data;
  1.1265 -	struct {
  1.1266 -	       u64		generic		: 8,
  1.1267 -				width		: 8,
  1.1268 -				cycles		: 8,
  1.1269 -				retired		: 8,
  1.1270 -				reserved	: 32;
  1.1271 -	} pal_perf_mon_info_s;
  1.1272 -} pal_perf_mon_info_u_t;
  1.1273 -
  1.1274 -/* Return the performance monitor information about what can be counted
  1.1275 - * and how to configure the monitors to count the desired events.
  1.1276 - */
  1.1277 -static inline s64
  1.1278 -ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
  1.1279 -{
  1.1280 -	struct ia64_pal_retval iprv;
  1.1281 -	PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
  1.1282 -	if (pm_info)
  1.1283 -		pm_info->ppmi_data = iprv.v0;
  1.1284 -	return iprv.status;
  1.1285 -}
  1.1286 -
  1.1287 -/* Specifies the physical address of the processor interrupt block
  1.1288 - * and I/O port space.
  1.1289 - */
  1.1290 -static inline s64
  1.1291 -ia64_pal_platform_addr (u64 type, u64 physical_addr)
  1.1292 -{
  1.1293 -	struct ia64_pal_retval iprv;
  1.1294 -	PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
  1.1295 -	return iprv.status;
  1.1296 -}
  1.1297 -
  1.1298 -/* Set the SAL PMI entrypoint in memory */
  1.1299 -static inline s64
  1.1300 -ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
  1.1301 -{
  1.1302 -	struct ia64_pal_retval iprv;
  1.1303 -	PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
  1.1304 -	return iprv.status;
  1.1305 -}
  1.1306 -
  1.1307 -struct pal_features_s;
  1.1308 -/* Provide information about configurable processor features */
  1.1309 -static inline s64
  1.1310 -ia64_pal_proc_get_features (u64 *features_avail,
  1.1311 -			    u64 *features_status,
  1.1312 -			    u64 *features_control)
  1.1313 -{
  1.1314 -	struct ia64_pal_retval iprv;
  1.1315 -	PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
  1.1316 -	if (iprv.status == 0) {
  1.1317 -		*features_avail   = iprv.v0;
  1.1318 -		*features_status  = iprv.v1;
  1.1319 -		*features_control = iprv.v2;
  1.1320 -	}
  1.1321 -	return iprv.status;
  1.1322 -}
  1.1323 -
  1.1324 -/* Enable/disable processor dependent features */
  1.1325 -static inline s64
  1.1326 -ia64_pal_proc_set_features (u64 feature_select)
  1.1327 -{
  1.1328 -	struct ia64_pal_retval iprv;
  1.1329 -	PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
  1.1330 -	return iprv.status;
  1.1331 -}
  1.1332 -
  1.1333 -/*
  1.1334 - * Put everything in a struct so we avoid the global offset table whenever
  1.1335 - * possible.
  1.1336 - */
  1.1337 -typedef struct ia64_ptce_info_s {
  1.1338 -	u64		base;
  1.1339 -	u32		count[2];
  1.1340 -	u32		stride[2];
  1.1341 -} ia64_ptce_info_t;
  1.1342 -
  1.1343 -/* Return the information required for the architected loop used to purge
  1.1344 - * (initialize) the entire TC
  1.1345 - */
  1.1346 -static inline s64
  1.1347 -ia64_get_ptce (ia64_ptce_info_t *ptce)
  1.1348 -{
  1.1349 -	struct ia64_pal_retval iprv;
  1.1350 -
  1.1351 -	if (!ptce)
  1.1352 -		return -1;
  1.1353 -
  1.1354 -	PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
  1.1355 -	if (iprv.status == 0) {
  1.1356 -		ptce->base = iprv.v0;
  1.1357 -		ptce->count[0] = iprv.v1 >> 32;
  1.1358 -		ptce->count[1] = iprv.v1 & 0xffffffff;
  1.1359 -		ptce->stride[0] = iprv.v2 >> 32;
  1.1360 -		ptce->stride[1] = iprv.v2 & 0xffffffff;
  1.1361 -	}
  1.1362 -	return iprv.status;
  1.1363 -}
  1.1364 -
  1.1365 -/* Return info about implemented application and control registers. */
  1.1366 -static inline s64
  1.1367 -ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
  1.1368 -{
  1.1369 -	struct ia64_pal_retval iprv;
  1.1370 -	PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
  1.1371 -	if (reg_info_1)
  1.1372 -		*reg_info_1 = iprv.v0;
  1.1373 -	if (reg_info_2)
  1.1374 -		*reg_info_2 = iprv.v1;
  1.1375 -	return iprv.status;
  1.1376 -}
  1.1377 -
  1.1378 -typedef union pal_hints_u {
  1.1379 -	u64			ph_data;
  1.1380 -	struct {
  1.1381 -	       u64		si		: 1,
  1.1382 -				li		: 1,
  1.1383 -				reserved	: 62;
  1.1384 -	} pal_hints_s;
  1.1385 -} pal_hints_u_t;
  1.1386 -
  1.1387 -/* Return information about the register stack and RSE for this processor
  1.1388 - * implementation.
  1.1389 - */
  1.1390 -static inline s64
  1.1391 -ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
  1.1392 -{
  1.1393 -	struct ia64_pal_retval iprv;
  1.1394 -	PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
  1.1395 -	if (num_phys_stacked)
  1.1396 -		*num_phys_stacked = iprv.v0;
  1.1397 -	if (hints)
  1.1398 -		hints->ph_data = iprv.v1;
  1.1399 -	return iprv.status;
  1.1400 -}
  1.1401 -
  1.1402 -/* Cause the processor to enter	SHUTDOWN state, where prefetching and execution are
  1.1403 - * suspended, but cause cache and TLB coherency to be maintained.
  1.1404 - * This is usually called in IA-32 mode.
  1.1405 - */
  1.1406 -static inline s64
  1.1407 -ia64_pal_shutdown (void)
  1.1408 -{
  1.1409 -	struct ia64_pal_retval iprv;
  1.1410 -	PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
  1.1411 -	return iprv.status;
  1.1412 -}
  1.1413 -
  1.1414 -/* Perform the second phase of processor self-test. */
  1.1415 -static inline s64
  1.1416 -ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
  1.1417 -{
  1.1418 -	struct ia64_pal_retval iprv;
  1.1419 -	PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
  1.1420 -	if (self_test_state)
  1.1421 -		*self_test_state = iprv.v0;
  1.1422 -	return iprv.status;
  1.1423 -}
  1.1424 -
  1.1425 -typedef union  pal_version_u {
  1.1426 -	u64	pal_version_val;
  1.1427 -	struct {
  1.1428 -		u64	pv_pal_b_rev		:	8;
  1.1429 -		u64	pv_pal_b_model		:	8;
  1.1430 -		u64	pv_reserved1		:	8;
  1.1431 -		u64	pv_pal_vendor		:	8;
  1.1432 -		u64	pv_pal_a_rev		:	8;
  1.1433 -		u64	pv_pal_a_model		:	8;
  1.1434 -		u64	pv_reserved2		:	16;
  1.1435 -	} pal_version_s;
  1.1436 -} pal_version_u_t;
  1.1437 -
  1.1438 -
  1.1439 -/*
  1.1440 - * Return PAL version information.  While the documentation states that
  1.1441 - * PAL_VERSION can be called in either physical or virtual mode, some
  1.1442 - * implementations only allow physical calls.  We don't call it very often,
  1.1443 - * so the overhead isn't worth eliminating.
  1.1444 - */
  1.1445 -static inline s64
  1.1446 -ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
  1.1447 -{
  1.1448 -	struct ia64_pal_retval iprv;
  1.1449 -	PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
  1.1450 -	if (pal_min_version)
  1.1451 -		pal_min_version->pal_version_val = iprv.v0;
  1.1452 -
  1.1453 -	if (pal_cur_version)
  1.1454 -		pal_cur_version->pal_version_val = iprv.v1;
  1.1455 -
  1.1456 -	return iprv.status;
  1.1457 -}
  1.1458 -
  1.1459 -typedef union pal_tc_info_u {
  1.1460 -	u64			pti_val;
  1.1461 -	struct {
  1.1462 -	       u64		num_sets	:	8,
  1.1463 -				associativity	:	8,
  1.1464 -				num_entries	:	16,
  1.1465 -				pf		:	1,
  1.1466 -				unified		:	1,
  1.1467 -				reduce_tr	:	1,
  1.1468 -				reserved	:	29;
  1.1469 -	} pal_tc_info_s;
  1.1470 -} pal_tc_info_u_t;
  1.1471 -
  1.1472 -#define tc_reduce_tr		pal_tc_info_s.reduce_tr
  1.1473 -#define tc_unified		pal_tc_info_s.unified
  1.1474 -#define tc_pf			pal_tc_info_s.pf
  1.1475 -#define tc_num_entries		pal_tc_info_s.num_entries
  1.1476 -#define tc_associativity	pal_tc_info_s.associativity
  1.1477 -#define tc_num_sets		pal_tc_info_s.num_sets
  1.1478 -
  1.1479 -
  1.1480 -/* Return information about the virtual memory characteristics of the processor
  1.1481 - * implementation.
  1.1482 - */
  1.1483 -static inline s64
  1.1484 -ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
  1.1485 -{
  1.1486 -	struct ia64_pal_retval iprv;
  1.1487 -	PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
  1.1488 -	if (tc_info)
  1.1489 -		tc_info->pti_val = iprv.v0;
  1.1490 -	if (tc_pages)
  1.1491 -		*tc_pages = iprv.v1;
  1.1492 -	return iprv.status;
  1.1493 -}
  1.1494 -
  1.1495 -/* Get page size information about the virtual memory characteristics of the processor
  1.1496 - * implementation.
  1.1497 - */
  1.1498 -static inline s64
  1.1499 -ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
  1.1500 -{
  1.1501 -	struct ia64_pal_retval iprv;
  1.1502 -	PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
  1.1503 -	if (tr_pages)
  1.1504 -		*tr_pages = iprv.v0;
  1.1505 -	if (vw_pages)
  1.1506 -		*vw_pages = iprv.v1;
  1.1507 -	return iprv.status;
  1.1508 -}
  1.1509 -
  1.1510 -typedef union pal_vm_info_1_u {
  1.1511 -	u64			pvi1_val;
  1.1512 -	struct {
  1.1513 -		u64		vw		: 1,
  1.1514 -				phys_add_size	: 7,
  1.1515 -				key_size	: 8,
  1.1516 -				max_pkr		: 8,
  1.1517 -				hash_tag_id	: 8,
  1.1518 -				max_dtr_entry	: 8,
  1.1519 -				max_itr_entry	: 8,
  1.1520 -				max_unique_tcs	: 8,
  1.1521 -				num_tc_levels	: 8;
  1.1522 -	} pal_vm_info_1_s;
  1.1523 -} pal_vm_info_1_u_t;
  1.1524 -
  1.1525 -typedef union pal_vm_info_2_u {
  1.1526 -	u64			pvi2_val;
  1.1527 -	struct {
  1.1528 -		u64		impl_va_msb	: 8,
  1.1529 -				rid_size	: 8,
  1.1530 -				reserved	: 48;
  1.1531 -	} pal_vm_info_2_s;
  1.1532 -} pal_vm_info_2_u_t;
  1.1533 -
  1.1534 -/* Get summary information about the virtual memory characteristics of the processor
  1.1535 - * implementation.
  1.1536 - */
  1.1537 -static inline s64
  1.1538 -ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
  1.1539 -{
  1.1540 -	struct ia64_pal_retval iprv;
  1.1541 -	PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
  1.1542 -	if (vm_info_1)
  1.1543 -		vm_info_1->pvi1_val = iprv.v0;
  1.1544 -	if (vm_info_2)
  1.1545 -		vm_info_2->pvi2_val = iprv.v1;
  1.1546 -	return iprv.status;
  1.1547 -}
  1.1548 -
  1.1549 -typedef union pal_itr_valid_u {
  1.1550 -	u64			piv_val;
  1.1551 -	struct {
  1.1552 -	       u64		access_rights_valid	: 1,
  1.1553 -				priv_level_valid	: 1,
  1.1554 -				dirty_bit_valid		: 1,
  1.1555 -				mem_attr_valid		: 1,
  1.1556 -				reserved		: 60;
  1.1557 -	} pal_tr_valid_s;
  1.1558 -} pal_tr_valid_u_t;
  1.1559 -
  1.1560 -/* Read a translation register */
  1.1561 -static inline s64
  1.1562 -ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
  1.1563 -{
  1.1564 -	struct ia64_pal_retval iprv;
  1.1565 -	PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
  1.1566 -	if (tr_valid)
  1.1567 -		tr_valid->piv_val = iprv.v0;
  1.1568 -	return iprv.status;
  1.1569 -}
  1.1570 -
  1.1571 -/*
  1.1572 - * PAL_PREFETCH_VISIBILITY transaction types
  1.1573 - */
  1.1574 -#define PAL_VISIBILITY_VIRTUAL		0
  1.1575 -#define PAL_VISIBILITY_PHYSICAL		1
  1.1576 -
  1.1577 -/*
  1.1578 - * PAL_PREFETCH_VISIBILITY return codes
  1.1579 - */
  1.1580 -#define PAL_VISIBILITY_OK		1
  1.1581 -#define PAL_VISIBILITY_OK_REMOTE_NEEDED	0
  1.1582 -#define PAL_VISIBILITY_INVAL_ARG	-2
  1.1583 -#define PAL_VISIBILITY_ERROR		-3
  1.1584 -
  1.1585 -static inline s64
  1.1586 -ia64_pal_prefetch_visibility (s64 trans_type)
  1.1587 -{
  1.1588 -	struct ia64_pal_retval iprv;
  1.1589 -	PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
  1.1590 -	return iprv.status;
  1.1591 -}
  1.1592 -
  1.1593 -/* data structure for getting information on logical to physical mappings */
  1.1594 -typedef union pal_log_overview_u {
  1.1595 -	struct {
  1.1596 -		u64	num_log		:16,	/* Total number of logical
  1.1597 -						 * processors on this die
  1.1598 -						 */
  1.1599 -			tpc		:8,	/* Threads per core */
  1.1600 -			reserved3	:8,	/* Reserved */
  1.1601 -			cpp		:8,	/* Cores per processor */
  1.1602 -			reserved2	:8,	/* Reserved */
  1.1603 -			ppid		:8,	/* Physical processor ID */
  1.1604 -			reserved1	:8;	/* Reserved */
  1.1605 -	} overview_bits;
  1.1606 -	u64 overview_data;
  1.1607 -} pal_log_overview_t;
  1.1608 -
  1.1609 -typedef union pal_proc_n_log_info1_u{
  1.1610 -	struct {
  1.1611 -		u64	tid		:16,	/* Thread id */
  1.1612 -			reserved2	:16,	/* Reserved */
  1.1613 -			cid		:16,	/* Core id */
  1.1614 -			reserved1	:16;	/* Reserved */
  1.1615 -	} ppli1_bits;
  1.1616 -	u64	ppli1_data;
  1.1617 -} pal_proc_n_log_info1_t;
  1.1618 -
  1.1619 -typedef union pal_proc_n_log_info2_u {
  1.1620 -	struct {
  1.1621 -		u64	la		:16,	/* Logical address */
  1.1622 -			reserved	:48;	/* Reserved */
  1.1623 -	} ppli2_bits;
  1.1624 -	u64	ppli2_data;
  1.1625 -} pal_proc_n_log_info2_t;
  1.1626 -
  1.1627 -typedef struct pal_logical_to_physical_s
  1.1628 -{
  1.1629 -	pal_log_overview_t overview;
  1.1630 -	pal_proc_n_log_info1_t ppli1;
  1.1631 -	pal_proc_n_log_info2_t ppli2;
  1.1632 -} pal_logical_to_physical_t;
  1.1633 -
  1.1634 -#define overview_num_log	overview.overview_bits.num_log
  1.1635 -#define overview_tpc		overview.overview_bits.tpc
  1.1636 -#define overview_cpp		overview.overview_bits.cpp
  1.1637 -#define overview_ppid		overview.overview_bits.ppid
  1.1638 -#define log1_tid		ppli1.ppli1_bits.tid
  1.1639 -#define log1_cid		ppli1.ppli1_bits.cid
  1.1640 -#define log2_la			ppli2.ppli2_bits.la
  1.1641 -
  1.1642 -/* Get information on logical to physical processor mappings. */
  1.1643 -static inline s64
  1.1644 -ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
  1.1645 -{
  1.1646 -	struct ia64_pal_retval iprv;
  1.1647 -
  1.1648 -	PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
  1.1649 -
  1.1650 -	if (iprv.status == PAL_STATUS_SUCCESS)
  1.1651 -	{
  1.1652 -		mapping->overview.overview_data = iprv.v0;
  1.1653 -		mapping->ppli1.ppli1_data = iprv.v1;
  1.1654 -		mapping->ppli2.ppli2_data = iprv.v2;
  1.1655 -	}
  1.1656 -
  1.1657 -	return iprv.status;
  1.1658 -}
  1.1659 -
  1.1660 -typedef struct pal_cache_shared_info_s
  1.1661 -{
  1.1662 -	u64 num_shared;
  1.1663 -	pal_proc_n_log_info1_t ppli1;
  1.1664 -	pal_proc_n_log_info2_t ppli2;
  1.1665 -} pal_cache_shared_info_t;
  1.1666 -
  1.1667 -/* Get information on logical to physical processor mappings. */
  1.1668 -static inline s64
  1.1669 -ia64_pal_cache_shared_info(u64 level,
  1.1670 -		u64 type,
  1.1671 -		u64 proc_number,
  1.1672 -		pal_cache_shared_info_t *info)
  1.1673 -{
  1.1674 -	struct ia64_pal_retval iprv;
  1.1675 -
  1.1676 -	PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
  1.1677 -
  1.1678 -	if (iprv.status == PAL_STATUS_SUCCESS) {
  1.1679 -		info->num_shared = iprv.v0;
  1.1680 -		info->ppli1.ppli1_data = iprv.v1;
  1.1681 -		info->ppli2.ppli2_data = iprv.v2;
  1.1682 -	}
  1.1683 -
  1.1684 -	return iprv.status;
  1.1685 -}
  1.1686 -#endif /* __ASSEMBLY__ */
  1.1687 -
  1.1688 -#endif /* _ASM_IA64_PAL_H */