ia64/xen-unstable
changeset 8870:2b0078f771cc
Upgrade mpparse.c to linux-2.6.16-rc2 codebase.
Signed-off-by: Keir Fraser <keir@xensource.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author | kaf24@firebug.cl.cam.ac.uk |
---|---|
date | Thu Feb 16 17:37:21 2006 +0100 (2006-02-16) |
parents | 18fa851b6dc6 |
children | 0d10fac28427 |
files | xen/arch/x86/mpparse.c |
line diff
1.1 --- a/xen/arch/x86/mpparse.c Thu Feb 16 16:19:38 2006 +0000 1.2 +++ b/xen/arch/x86/mpparse.c Thu Feb 16 17:37:21 2006 +0100 1.3 @@ -37,6 +37,12 @@ 1.4 int smp_found_config; 1.5 unsigned int __initdata maxcpus = NR_CPUS; 1.6 1.7 +#ifdef CONFIG_HOTPLUG_CPU 1.8 +#define CPU_HOTPLUG_ENABLED (1) 1.9 +#else 1.10 +#define CPU_HOTPLUG_ENABLED (0) 1.11 +#endif 1.12 + 1.13 /* 1.14 * Various Linux-internal data structures created from the 1.15 * MP-table. 1.16 @@ -47,7 +53,7 @@ int mp_bus_id_to_node [MAX_MP_BUSSES]; 1.17 int mp_bus_id_to_local [MAX_MP_BUSSES]; 1.18 int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 1.19 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; 1.20 -int mp_current_pci_id; 1.21 +static int mp_current_pci_id; 1.22 1.23 /* I/O APIC entries */ 1.24 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; 1.25 @@ -63,7 +69,7 @@ int nr_ioapics; 1.26 int pic_mode; 1.27 unsigned long mp_lapic_addr; 1.28 1.29 -unsigned int def_to_bigsmp; 1.30 +unsigned int def_to_bigsmp = 0; 1.31 1.32 /* Processor that is doing the boot up */ 1.33 unsigned int boot_cpu_physical_apicid = -1U; 1.34 @@ -119,10 +125,10 @@ static int MP_valid_apicid(int apicid, i 1.35 } 1.36 #endif 1.37 1.38 -void __init MP_processor_info (struct mpc_config_processor *m) 1.39 +static void __devinit MP_processor_info (struct mpc_config_processor *m) 1.40 { 1.41 int ver, apicid; 1.42 - physid_mask_t tmp; 1.43 + physid_mask_t phys_cpu; 1.44 1.45 if (!(m->mpc_cpuflag & CPU_ENABLED)) 1.46 return; 1.47 @@ -180,48 +186,57 @@ void __init MP_processor_info (struct mp 1.48 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { 1.49 Dprintk(" Bootup CPU\n"); 1.50 boot_cpu_physical_apicid = m->mpc_apicid; 1.51 - boot_cpu_logical_apicid = apicid; 1.52 } 1.53 1.54 - if (num_processors >= NR_CPUS) { 1.55 - printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." 1.56 - " Processor ignored.\n", NR_CPUS); 1.57 - return; 1.58 - } 1.59 - 1.60 - if (num_processors >= maxcpus) { 1.61 - printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." 1.62 - " Processor ignored.\n", maxcpus); 1.63 - return; 1.64 - } 1.65 - num_processors++; 1.66 ver = m->mpc_apicver; 1.67 1.68 if (!MP_valid_apicid(apicid, ver)) { 1.69 printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n", 1.70 m->mpc_apicid, MAX_APICS); 1.71 - --num_processors; 1.72 return; 1.73 } 1.74 1.75 - tmp = apicid_to_cpu_present(apicid); 1.76 - physids_or(phys_cpu_present_map, phys_cpu_present_map, tmp); 1.77 - 1.78 /* 1.79 * Validate version 1.80 */ 1.81 if (ver == 0x0) { 1.82 - printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid); 1.83 + printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " 1.84 + "fixing up to 0x10. (tell your hw vendor)\n", 1.85 + m->mpc_apicid); 1.86 ver = 0x10; 1.87 } 1.88 apic_version[m->mpc_apicid] = ver; 1.89 - if ((num_processors > 8) && 1.90 - APIC_XAPIC(ver) && 1.91 - (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)) 1.92 - def_to_bigsmp = 1; 1.93 - else 1.94 - def_to_bigsmp = 0; 1.95 + 1.96 + phys_cpu = apicid_to_cpu_present(apicid); 1.97 + physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); 1.98 + 1.99 + if (num_processors >= NR_CPUS) { 1.100 + printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." 1.101 + " Processor ignored.\n", NR_CPUS); 1.102 + return; 1.103 + } 1.104 + 1.105 + if (num_processors >= maxcpus) { 1.106 + printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." 1.107 + " Processor ignored.\n", maxcpus); 1.108 + return; 1.109 + } 1.110 1.111 + cpu_set(num_processors, cpu_possible_map); 1.112 + num_processors++; 1.113 + 1.114 + if (CPU_HOTPLUG_ENABLED || (num_processors > 8)) { 1.115 + switch (boot_cpu_data.x86_vendor) { 1.116 + case X86_VENDOR_INTEL: 1.117 + if (!APIC_XAPIC(ver)) { 1.118 + def_to_bigsmp = 0; 1.119 + break; 1.120 + } 1.121 + /* If P4 and above fall through */ 1.122 + case X86_VENDOR_AMD: 1.123 + def_to_bigsmp = 1; 1.124 + } 1.125 + } 1.126 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid; 1.127 } 1.128 1.129 @@ -662,8 +677,6 @@ void __init get_smp_config (void) 1.130 struct intel_mp_floating *mpf = mpf_found; 1.131 1.132 /* 1.133 - * ACPI may be used to obtain the entire SMP configuration or just to 1.134 - * enumerate/configure processors (CONFIG_ACPI_BOOT). Note that 1.135 * ACPI supports both logical (e.g. Hyper-Threading) and physical 1.136 * processors, where MPS only supports physical. 1.137 */ 1.138 @@ -820,7 +833,7 @@ void __init find_smp_config (void) 1.139 ACPI-based MP Configuration 1.140 -------------------------------------------------------------------------- */ 1.141 1.142 -#ifdef CONFIG_ACPI_BOOT 1.143 +#ifdef CONFIG_ACPI 1.144 1.145 void __init mp_register_lapic_address ( 1.146 u64 address) 1.147 @@ -836,7 +849,7 @@ void __init mp_register_lapic_address ( 1.148 } 1.149 1.150 1.151 -void __init mp_register_lapic ( 1.152 +void __devinit mp_register_lapic ( 1.153 u8 id, 1.154 u8 enabled) 1.155 { 1.156 @@ -866,12 +879,12 @@ void __init mp_register_lapic ( 1.157 MP_processor_info(&processor); 1.158 } 1.159 1.160 -#if defined(CONFIG_X86_IO_APIC) && (defined(CONFIG_ACPI_INTERPRETER) || defined(CONFIG_ACPI_BOOT)) 1.161 +#ifdef CONFIG_X86_IO_APIC 1.162 1.163 #define MP_ISA_BUS 0 1.164 #define MP_MAX_IOAPIC_PIN 127 1.165 1.166 -struct mp_ioapic_routing { 1.167 +static struct mp_ioapic_routing { 1.168 int apic_id; 1.169 int gsi_base; 1.170 int gsi_end; 1.171 @@ -1067,7 +1080,7 @@ void __init mp_config_acpi_legacy_irqs ( 1.172 1.173 #define MAX_GSI_NUM 4096 1.174 1.175 -int mp_register_gsi (u32 gsi, int edge_level, int active_high_low) 1.176 +int mp_register_gsi (u32 gsi, int triggering, int polarity) 1.177 { 1.178 int ioapic = -1; 1.179 int ioapic_pin = 0; 1.180 @@ -1078,7 +1091,7 @@ int mp_register_gsi (u32 gsi, int edge_l 1.181 * represent all possible interrupts, and IRQs 1.182 * assigned to actual devices. 1.183 */ 1.184 - static int gsi_to_irq[MAX_GSI_NUM]; 1.185 + static int gsi_to_irq[MAX_GSI_NUM]; 1.186 1.187 #ifdef CONFIG_ACPI_BUS 1.188 /* Don't set up the ACPI SCI because it's already set up */ 1.189 @@ -1118,14 +1131,22 @@ int mp_register_gsi (u32 gsi, int edge_l 1.190 1.191 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); 1.192 1.193 - if (edge_level) { 1.194 + if (triggering == ACPI_LEVEL_SENSITIVE) { 1.195 /* 1.196 * For PCI devices assign IRQs in order, avoiding gaps 1.197 * due to unused I/O APIC pins. 1.198 */ 1.199 int irq = gsi; 1.200 if (gsi < MAX_GSI_NUM) { 1.201 - gsi = pci_irq++; 1.202 + if (gsi > 15) 1.203 + gsi = pci_irq++; 1.204 +#ifdef CONFIG_ACPI_BUS 1.205 + /* 1.206 + * Don't assign IRQ used by ACPI SCI 1.207 + */ 1.208 + if (gsi == acpi_fadt.sci_int) 1.209 + gsi = pci_irq++; 1.210 +#endif 1.211 gsi_to_irq[irq] = gsi; 1.212 } else { 1.213 printk(KERN_ERR "GSI %u is too high\n", gsi); 1.214 @@ -1134,10 +1155,10 @@ int mp_register_gsi (u32 gsi, int edge_l 1.215 } 1.216 1.217 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, 1.218 - edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1, 1.219 - active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1); 1.220 + triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, 1.221 + polarity == ACPI_ACTIVE_HIGH ? 0 : 1); 1.222 return gsi; 1.223 } 1.224 1.225 -#endif /*CONFIG_X86_IO_APIC && (CONFIG_ACPI_INTERPRETER || CONFIG_ACPI_BOOT)*/ 1.226 -#endif /*CONFIG_ACPI_BOOT*/ 1.227 +#endif /* CONFIG_X86_IO_APIC */ 1.228 +#endif /* CONFIG_ACPI */