ia64/xen-unstable

changeset 17001:2adf154d17c2

vmx: Clean up VPMU code a little and remove noisy printk.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 07 10:47:20 2008 +0000 (2008-02-07)
parents 199f81c4b882
children 9cac8f659a24
files xen/arch/x86/hvm/vmx/vpmu.c xen/arch/x86/hvm/vmx/vpmu_core2.c
line diff
     1.1 --- a/xen/arch/x86/hvm/vmx/vpmu.c	Thu Feb 07 10:31:48 2008 +0000
     1.2 +++ b/xen/arch/x86/hvm/vmx/vpmu.c	Thu Feb 07 10:47:20 2008 +0000
     1.3 @@ -89,8 +89,6 @@ void vpmu_initialise(struct vcpu *v)
     1.4          case 15:
     1.5          case 23:
     1.6              vpmu->arch_vpmu_ops = &core2_vpmu_ops;
     1.7 -            dprintk(XENLOG_INFO,
     1.8 -                   "Core 2 duo CPU detected for guest PMU usage.\n");
     1.9              break;
    1.10          }
    1.11      }
     2.1 --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c	Thu Feb 07 10:31:48 2008 +0000
     2.2 +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c	Thu Feb 07 10:47:20 2008 +0000
     2.3 @@ -35,60 +35,69 @@
     2.4  #include <asm/hvm/vmx/vpmu.h>
     2.5  #include <asm/hvm/vmx/vpmu_core2.h>
     2.6  
     2.7 -static int arch_pmc_cnt = 0;
     2.8 +static int arch_pmc_cnt;
     2.9  
    2.10  static int core2_get_pmc_count(void)
    2.11  {
    2.12      u32 eax, ebx, ecx, edx;
    2.13  
    2.14 -    if ( arch_pmc_cnt )
    2.15 -        return arch_pmc_cnt;
    2.16 +    if ( arch_pmc_cnt == 0 )
    2.17 +    {
    2.18 +        cpuid(0xa, &eax, &ebx, &ecx, &edx);
    2.19 +        arch_pmc_cnt = (eax & 0xff00) >> 8;
    2.20 +    }
    2.21  
    2.22 -    cpuid(0xa, &eax, &ebx, &ecx, &edx);
    2.23 -    return arch_pmc_cnt = (eax & 0xff00) >> 8;
    2.24 +    return arch_pmc_cnt;
    2.25  }
    2.26  
    2.27  static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
    2.28  {
    2.29      int i;
    2.30  
    2.31 -    for ( i=0; i < core2_counters.num; i++ )
    2.32 +    for ( i = 0; i < core2_counters.num; i++ )
    2.33 +    {
    2.34          if ( core2_counters.msr[i] == msr_index )
    2.35          {
    2.36              *type = MSR_TYPE_COUNTER;
    2.37              *index = i;
    2.38              return 1;
    2.39          }
    2.40 -    for ( i=0; i < core2_ctrls.num; i++ )
    2.41 +    }
    2.42 +    
    2.43 +    for ( i = 0; i < core2_ctrls.num; i++ )
    2.44 +    {
    2.45          if ( core2_ctrls.msr[i] == msr_index )
    2.46          {
    2.47              *type = MSR_TYPE_CTRL;
    2.48              *index = i;
    2.49              return 1;
    2.50          }
    2.51 +    }
    2.52  
    2.53 -    if ( msr_index == MSR_CORE_PERF_GLOBAL_CTRL ||
    2.54 -         msr_index == MSR_CORE_PERF_GLOBAL_STATUS ||
    2.55 -         msr_index == MSR_CORE_PERF_GLOBAL_OVF_CTRL )
    2.56 +    if ( (msr_index == MSR_CORE_PERF_GLOBAL_CTRL) ||
    2.57 +         (msr_index == MSR_CORE_PERF_GLOBAL_STATUS) ||
    2.58 +         (msr_index == MSR_CORE_PERF_GLOBAL_OVF_CTRL) )
    2.59      {
    2.60          *type = MSR_TYPE_GLOBAL;
    2.61          return 1;
    2.62      }
    2.63  
    2.64 -    if ( msr_index >= MSR_IA32_PERFCTR0 &&
    2.65 -         msr_index < MSR_IA32_PERFCTR0 + core2_get_pmc_count() )
    2.66 +    if ( (msr_index >= MSR_IA32_PERFCTR0) &&
    2.67 +         (msr_index < (MSR_IA32_PERFCTR0 + core2_get_pmc_count())) )
    2.68      {
    2.69          *type = MSR_TYPE_ARCH_COUNTER;
    2.70          *index = msr_index - MSR_IA32_PERFCTR0;
    2.71          return 1;
    2.72      }
    2.73 -    if ( msr_index >= MSR_P6_EVNTSEL0 &&
    2.74 -         msr_index < MSR_P6_EVNTSEL0 + core2_get_pmc_count() )
    2.75 +
    2.76 +    if ( (msr_index >= MSR_P6_EVNTSEL0) &&
    2.77 +         (msr_index < (MSR_P6_EVNTSEL0 + core2_get_pmc_count())) )
    2.78      {
    2.79          *type = MSR_TYPE_ARCH_CTRL;
    2.80          *index = msr_index - MSR_P6_EVNTSEL0;
    2.81          return 1;
    2.82      }
    2.83 +
    2.84      return 0;
    2.85  }
    2.86  
    2.87 @@ -97,20 +106,21 @@ static void core2_vpmu_set_msr_bitmap(ch
    2.88      int i;
    2.89  
    2.90      /* Allow Read/Write PMU Counters MSR Directly. */
    2.91 -    for ( i=0; i < core2_counters.num; i++ )
    2.92 +    for ( i = 0; i < core2_counters.num; i++ )
    2.93      {
    2.94          clear_bit(msraddr_to_bitpos(core2_counters.msr[i]), msr_bitmap);
    2.95 -        clear_bit(msraddr_to_bitpos(core2_counters.msr[i]), msr_bitmap + 0x800);
    2.96 +        clear_bit(msraddr_to_bitpos(core2_counters.msr[i]), msr_bitmap+0x800);
    2.97      }
    2.98 -    for ( i=0; i < core2_get_pmc_count(); i++ )
    2.99 +    for ( i = 0; i < core2_get_pmc_count(); i++ )
   2.100      {
   2.101          clear_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap);
   2.102 -        clear_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap + 0x800);
   2.103 +        clear_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap+0x800);
   2.104      }
   2.105 +
   2.106      /* Allow Read PMU Non-global Controls Directly. */
   2.107 -    for ( i=0; i < core2_ctrls.num; i++ )
   2.108 +    for ( i = 0; i < core2_ctrls.num; i++ )
   2.109          clear_bit(msraddr_to_bitpos(core2_ctrls.msr[i]), msr_bitmap);
   2.110 -    for ( i=0; i < core2_get_pmc_count(); i++ )
   2.111 +    for ( i = 0; i < core2_get_pmc_count(); i++ )
   2.112          clear_bit(msraddr_to_bitpos(MSR_P6_EVNTSEL0+i), msr_bitmap);
   2.113  }
   2.114  
   2.115 @@ -118,20 +128,19 @@ static void core2_vpmu_unset_msr_bitmap(
   2.116  {
   2.117      int i;
   2.118  
   2.119 -    /* Undo all the changes to msr bitmap. */
   2.120 -    for ( i=0; i < core2_counters.num; i++ )
   2.121 +    for ( i = 0; i < core2_counters.num; i++ )
   2.122      {
   2.123          set_bit(msraddr_to_bitpos(core2_counters.msr[i]), msr_bitmap);
   2.124 -        set_bit(msraddr_to_bitpos(core2_counters.msr[i]), msr_bitmap + 0x800);
   2.125 +        set_bit(msraddr_to_bitpos(core2_counters.msr[i]), msr_bitmap+0x800);
   2.126      }
   2.127 -    for ( i=0; i < core2_get_pmc_count(); i++ )
   2.128 +    for ( i = 0; i < core2_get_pmc_count(); i++ )
   2.129      {
   2.130          set_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap);
   2.131 -        set_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap + 0x800);
   2.132 +        set_bit(msraddr_to_bitpos(MSR_IA32_PERFCTR0+i), msr_bitmap+0x800);
   2.133      }
   2.134 -    for ( i=0; i < core2_ctrls.num; i++ )
   2.135 +    for ( i = 0; i < core2_ctrls.num; i++ )
   2.136          set_bit(msraddr_to_bitpos(core2_ctrls.msr[i]), msr_bitmap);
   2.137 -    for ( i=0; i < core2_get_pmc_count(); i++ )
   2.138 +    for ( i = 0; i < core2_get_pmc_count(); i++ )
   2.139          set_bit(msraddr_to_bitpos(MSR_P6_EVNTSEL0+i), msr_bitmap);
   2.140  }
   2.141  
   2.142 @@ -140,9 +149,9 @@ static inline void __core2_vpmu_save(str
   2.143      int i;
   2.144      struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
   2.145  
   2.146 -    for ( i=0; i < core2_counters.num; i++ )
   2.147 +    for ( i = 0; i < core2_counters.num; i++ )
   2.148          rdmsrl(core2_counters.msr[i], core2_vpmu_cxt->counters[i]);
   2.149 -    for ( i=0; i < core2_get_pmc_count(); i++ )
   2.150 +    for ( i = 0; i < core2_get_pmc_count(); i++ )
   2.151          rdmsrl(MSR_IA32_PERFCTR0+i, core2_vpmu_cxt->arch_msr_pair[i].counter);
   2.152      core2_vpmu_cxt->hw_lapic_lvtpc = apic_read(APIC_LVTPC);
   2.153      apic_write(APIC_LVTPC, LVTPC_HVM_PMU | APIC_LVT_MASKED);
   2.154 @@ -171,14 +180,14 @@ static inline void __core2_vpmu_load(str
   2.155      int i;
   2.156      struct core2_vpmu_context *core2_vpmu_cxt = vcpu_vpmu(v)->context;
   2.157  
   2.158 -    for ( i=0; i < core2_counters.num; i++ )
   2.159 +    for ( i = 0; i < core2_counters.num; i++ )
   2.160          wrmsrl(core2_counters.msr[i], core2_vpmu_cxt->counters[i]);
   2.161 -    for ( i=0; i < core2_get_pmc_count(); i++ )
   2.162 +    for ( i = 0; i < core2_get_pmc_count(); i++ )
   2.163          wrmsrl(MSR_IA32_PERFCTR0+i, core2_vpmu_cxt->arch_msr_pair[i].counter);
   2.164  
   2.165 -    for ( i=0; i < core2_ctrls.num; i++ )
   2.166 +    for ( i = 0; i < core2_ctrls.num; i++ )
   2.167          wrmsrl(core2_ctrls.msr[i], core2_vpmu_cxt->ctrls[i]);
   2.168 -    for ( i=0; i < core2_get_pmc_count(); i++ )
   2.169 +    for ( i = 0; i < core2_get_pmc_count(); i++ )
   2.170          wrmsrl(MSR_P6_EVNTSEL0+i, core2_vpmu_cxt->arch_msr_pair[i].control);
   2.171  
   2.172      apic_write_around(APIC_LVTPC, core2_vpmu_cxt->hw_lapic_lvtpc);
   2.173 @@ -233,9 +242,9 @@ static int core2_vpmu_alloc_resource(str
   2.174   out2:
   2.175      xfree(pmu_enable);
   2.176   out1:
   2.177 -    dprintk(XENLOG_WARNING, "Insufficient memory for PMU, PMU feature is \
   2.178 -            unavailable on domain %d vcpu %d.\n",
   2.179 -            v->vcpu_id, v->domain->domain_id);
   2.180 +    gdprintk(XENLOG_WARNING, "Insufficient memory for PMU, PMU feature is "
   2.181 +             "unavailable on domain %d vcpu %d.\n",
   2.182 +             v->vcpu_id, v->domain->domain_id);
   2.183      return 0;
   2.184  }
   2.185  
   2.186 @@ -300,17 +309,17 @@ static int core2_vpmu_do_wrmsr(struct cp
   2.187          core2_vpmu_cxt->global_ovf_status &= ~msr_content;
   2.188          return 1;
   2.189      case MSR_CORE_PERF_GLOBAL_STATUS:
   2.190 -        dprintk(XENLOG_INFO, "Can not write readonly MSR: \
   2.191 -                            MSR_PERF_GLOBAL_STATUS(0x38E)!\n");
   2.192 +        gdprintk(XENLOG_INFO, "Can not write readonly MSR: "
   2.193 +                 "MSR_PERF_GLOBAL_STATUS(0x38E)!\n");
   2.194          vmx_inject_hw_exception(current, TRAP_gp_fault, 0);
   2.195          return 1;
   2.196      case MSR_IA32_PEBS_ENABLE:
   2.197          if ( msr_content & 1 )
   2.198 -            dprintk(XENLOG_WARNING, "Guest is trying to enable PEBS, \
   2.199 -                    which is not supported.\n");
   2.200 +            gdprintk(XENLOG_WARNING, "Guest is trying to enable PEBS, "
   2.201 +                     "which is not supported.\n");
   2.202          return 1;
   2.203      case MSR_IA32_DS_AREA:
   2.204 -        dprintk(XENLOG_WARNING, "Guest setting of DTS is ignored.\n");
   2.205 +        gdprintk(XENLOG_WARNING, "Guest setting of DTS is ignored.\n");
   2.206          return 1;
   2.207      case MSR_CORE_PERF_GLOBAL_CTRL:
   2.208          global_ctrl = msr_content;
   2.209 @@ -466,4 +475,3 @@ struct arch_vpmu_ops core2_vpmu_ops = {
   2.210      .arch_vpmu_save = core2_vpmu_save,
   2.211      .arch_vpmu_load = core2_vpmu_load
   2.212  };
   2.213 -