ia64/xen-unstable

changeset 4486:2955b0140fbe

bitkeeper revision 1.1274.1.2 (4252c7d9ZNwE-cRS8KJmI-2X3Ui91A)

Merge br260@scramble.cl.cam.ac.uk:/usr/groups/xeno/BK/xen-unstable.bk
into br260.wolfson.cam.ac.uk:/share/project/xeno/xen-unstable.bk
author bren@br260.wolfson.cam.ac.uk
date Tue Apr 05 17:16:09 2005 +0000 (2005-04-05)
parents 3a76f49439ae fa593bda762e
children f0790be67b5f
files tools/xentrace/formats tools/xentrace/xentrace_format xen/common/dom0_ops.c xen/common/schedule.c xen/include/public/dom0_ops.h
line diff
     1.1 --- a/tools/xentrace/formats	Tue Apr 05 16:55:50 2005 +0000
     1.2 +++ b/tools/xentrace/formats	Tue Apr 05 17:16:09 2005 +0000
     1.3 @@ -1,35 +1,34 @@
     1.4 -0x00010000	CPU%(cpu)d %(tsc).6f sched_add_domain(0x%(3)08x)            [ dom id = 0x%(2)08x   ]
     1.5 -0x00010001	CPU%(cpu)d %(tsc).6f sched_rem_domain(0x%08(3)x)            [ dom id = 0x%(2)08x   ]
     1.6 -0x00010002	CPU%(cpu)d %(tsc).6f __wake_up(0x%(3)08x)                   [ dom id = 0x%(2)08x   ]
     1.7 -0x00010003	CPU%(cpu)d %(tsc).6f do_block()                             [ current = 0x%(2)08x  ]
     1.8 -0x00010004	CPU%(cpu)d %(tsc).6f do_yield()		                    [ current = %(2)08x    ]
     1.9 -0x00010005	CPU%(cpu)d %(tsc).6f do_set_timer_op(0x%(4)08x, 0x%(5)08x)  [ current = 0x%(3)08x  ]
    1.10 -0x00010006	CPU%(cpu)d %(tsc).6f sched_ctl(0x%(1)08x)
    1.11 -0x00010007	CPU%(cpu)d %(tsc).6f sched_adjdom(params)                   [ dom id = 0x%(2)08x   ]
    1.12 -0x00010008	CPU%(cpu)d %(tsc).6f __reschedule(0x%(3)08x)                [ dom id = 0x(2)08x    ]
    1.13 -0x00010009	CPU%(cpu)d %(tsc).6f switching to task_struct 0x%(1)08x     [ dom id = 0x%(1)x     ]
    1.14 -0x0001000A	CPU%(cpu)d %(tsc).6f s_timer_fn(unused)
    1.15 -0x0001000B	CPU%(cpu)d %(tsc).6f t_timer_fn(unused)
    1.16 -0x0001000C	CPU%(cpu)d %(tsc).6f dom_timer_fn(data)
    1.17 -0x0001000D	CPU%(cpu)d %(tsc).6f fallback_timer_fn(unused)
    1.18 +0x00010000	CPU%(cpu)d	%(tsc)d		sched_add_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.19 +0x00010001	CPU%(cpu)d	%(tsc)d		sched_rem_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.20 +0x00010002	CPU%(cpu)d	%(tsc)d		domain_sleep		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.21 +0x00010003	CPU%(cpu)d	%(tsc)d		domain_wake		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.22 +0x00010004	CPU%(cpu)d	%(tsc)d		do_yield		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.23 +0x00010005	CPU%(cpu)d	%(tsc)d		do_block		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.24 +0x00010006	CPU%(cpu)d	%(tsc)d		domain_shutdown		[ domid = 0x%(1)08x, edomid = 0x%(2)08x, reason = 0x%(3)08x ]
    1.25 +0x00010007	CPU%(cpu)d	%(tsc)d		sched_ctl
    1.26 +0x00010008	CPU%(cpu)d	%(tsc)d		sched_adjdom		[ domid = 0x%(1)08x ]
    1.27 +0x00010009	CPU%(cpu)d	%(tsc)d		__enter_scheduler	[ prev<domid:edomid> = 0x%(1)08x : 0x%(2)08x, next<domid:edomid> = 0x%(3)08x : 0x%(4)08x ]
    1.28 +0x0001000A	CPU%(cpu)d	%(tsc)d		s_timer_fn
    1.29 +0x0001000B	CPU%(cpu)d	%(tsc)d		t_timer_fn
    1.30 +0x0001000C	CPU%(cpu)d	%(tsc)d		dom_timer_fn
    1.31  
    1.32  
    1.33 -0x00020008	CPU%(cpu)d %(tsc).6f enter: dom0_create_dom ( )
    1.34 -0x00030008	CPU%(cpu)d %(tsc).6f leave: dom0_create_dom ( )
    1.35 -
    1.36 -0x00020009	CPU%(cpu)d %(tsc).6f enter: dom0_destroy_dom ( dom=0x%(2)x )
    1.37 -0x00030009	CPU%(cpu)d %(tsc).6f leave: dom0_destroy_dom ( dom=0x%(2)x ) = %(1)d
    1.38 +0x00020008	CPU%(cpu)d	%(tsc)d		enter: dom0_create_dom
    1.39 +0x00030008	CPU%(cpu)d	%(tsc)d		leave: dom0_create_dom
    1.40 +0x00020009	CPU%(cpu)d	%(tsc)d		enter: dom0_destroy_dom
    1.41 +0x00030009	CPU%(cpu)d	%(tsc)d		leave: dom0_destroy_dom
    1.42 +0x0002000A	CPU%(cpu)d	%(tsc)d		enter: dom0_start_dom
    1.43 +0x0003000A	CPU%(cpu)d	%(tsc)d		leave: dom0_start_dom
    1.44 +0x0002000B	CPU%(cpu)d	%(tsc)d		enter: dom0_stop_dom
    1.45 +0x0003000B	CPU%(cpu)d	%(tsc)d		leave: dom0_stop_dom
    1.46 +0x0002000C	CPU%(cpu)d	%(tsc)d		enter: dom0_getinfo
    1.47 +0x0003000C	CPU%(cpu)d	%(tsc)d		leave: dom0_getinfo
    1.48 +0x0002000D	CPU%(cpu)d	%(tsc)d		enter: dom0_build
    1.49 +0x0003000D	CPU%(cpu)d	%(tsc)d		leave: dom0_build
    1.50 +0x00020019	CPU%(cpu)d	%(tsc)d		enter: dom0_shadow_op
    1.51 +0x00030019	CPU%(cpu)d	%(tsc)d		leave: dom0_shadow_op
    1.52  
    1.53 -0x0002000A	CPU%(cpu)d %(tsc).6f enter: dom0_start_dom ( dom=0x%(2)x )
    1.54 -0x0003000A	CPU%(cpu)d %(tsc).6f leave: dom0_start_dom ( dom=0x%(2)x ) = %(1)d
    1.55 -0x0002000B	CPU%(cpu)d %(tsc).6f enter: dom0_stop_dom ( dom=0x%(2)x )
    1.56 -0x0003000B	CPU%(cpu)d %(tsc).6f leave: dom0_stop_dom ( dom=0x%(2)x ) = %(1)d
    1.57 -0x0002000C	CPU%(cpu)d %(tsc).6f enter: dom0_getinfo ( dom=0x%(2)x )
    1.58 -0x0003000C	CPU%(cpu)d %(tsc).6f leave: dom0_getinfo ( dom=0x%(2)x ) = %(1)d
    1.59 -0x0002000D	CPU%(cpu)d %(tsc).6f enter: dom0_build ( dom=0x%(2)x )
    1.60 -0x0003000D	CPU%(cpu)d %(tsc).6f leave: dom0_build ( dom=0x%(2)x ) = %(1)d
    1.61  
    1.62 -0x00020019	CPU%(cpu)d %(tsc).6f enter: dom0_shadow_op ( dom=0x%(2)x, %(3)d )
    1.63 -0x00030019	CPU%(cpu)d %(tsc).6f leave: dom0_shadow_op ( dom=0x%(2)x, %(3)d  ) = %(1)d
    1.64 -
    1.65 -#0x0		CPU%(cpu)d %(tsc).6f %(event)x
    1.66 +0x00040001	CPU%(cpu)d      %(tsc)d		VMX_VMEXIT		[ domid = 0x%(1)08x, eip = 0x%(2)08x, reason = 0x%(3)08x ]
    1.67 +0x00040002	CPU%(cpu)d      %(tsc)d		VMX_VECTOR		[ domid = 0x%(1)08x, eip = 0x%(2)08x, vector = 0x%(3)08x ]
    1.68 +0x00040003	CPU%(cpu)d      %(tsc)d		VMX_INT			[ domid = 0x%(1)08x, trap = 0x%(2)08x, va = 0x%(3)08x ]
    1.69 \ No newline at end of file
     2.1 --- a/tools/xentrace/xentrace_format	Tue Apr 05 16:55:50 2005 +0000
     2.2 +++ b/tools/xentrace/xentrace_format	Tue Apr 05 17:16:09 2005 +0000
     2.3 @@ -75,8 +75,6 @@ try:
     2.4  except getopt.GetoptError:
     2.5      usage()
     2.6  
     2.7 -print mhz
     2.8 -
     2.9  signal.signal(signal.SIGTERM, sighand)
    2.10  signal.signal(signal.SIGHUP,  sighand)
    2.11  signal.signal(signal.SIGINT,  sighand)
    2.12 @@ -85,8 +83,6 @@ interrupted = 0
    2.13  
    2.14  defs = read_defs(arg[0])
    2.15  
    2.16 -print defs
    2.17 -
    2.18  # structure of trace record + prepended CPU id (as output by xentrace):
    2.19  # CPU(I) TSC(Q) EVENT(L) D1(L) D2(L) D3(L) D4(L) D5(L)
    2.20  TRCREC = "IQLLLLLL"
     3.1 --- a/xen/common/dom0_ops.c	Tue Apr 05 16:55:50 2005 +0000
     3.2 +++ b/xen/common/dom0_ops.c	Tue Apr 05 17:16:09 2005 +0000
     3.3 @@ -104,10 +104,6 @@ long do_dom0_op(dom0_op_t *u_dom0_op)
     3.4      if ( op->interface_version != DOM0_INTERFACE_VERSION )
     3.5          return -EACCES;
     3.6  
     3.7 -    TRACE_5D(TRC_DOM0OP_ENTER_BASE + op->cmd, 
     3.8 -             0, op->u.dummy[0], op->u.dummy[1], 
     3.9 -             op->u.dummy[2], op->u.dummy[3] );
    3.10 -
    3.11      switch ( op->cmd )
    3.12      {
    3.13  
    3.14 @@ -471,10 +467,6 @@ long do_dom0_op(dom0_op_t *u_dom0_op)
    3.15  
    3.16      }
    3.17  
    3.18 -    TRACE_5D(TRC_DOM0OP_LEAVE_BASE + op->cmd, ret,
    3.19 -             op->u.dummy[0], op->u.dummy[1], op->u.dummy[2], op->u.dummy[3]);
    3.20 -
    3.21 -
    3.22      return ret;
    3.23  }
    3.24  
     4.1 --- a/xen/common/schedule.c	Tue Apr 05 16:55:50 2005 +0000
     4.2 +++ b/xen/common/schedule.c	Tue Apr 05 17:16:09 2005 +0000
     4.3 @@ -48,13 +48,13 @@ string_param("sched", opt_sched);
     4.4   */
     4.5  #define TRC_SCHED_DOM_ADD             0x00010000
     4.6  #define TRC_SCHED_DOM_REM             0x00010001
     4.7 -#define TRC_SCHED_WAKE                0x00010002
     4.8 -#define TRC_SCHED_BLOCK               0x00010003
     4.9 +#define TRC_SCHED_SLEEP               0x00010002
    4.10 +#define TRC_SCHED_WAKE                0x00010003
    4.11  #define TRC_SCHED_YIELD               0x00010004
    4.12 -#define TRC_SCHED_SET_TIMER           0x00010005
    4.13 -#define TRC_SCHED_CTL                 0x00010006
    4.14 -#define TRC_SCHED_ADJDOM              0x00010007
    4.15 -#define TRC_SCHED_RESCHED             0x00010008
    4.16 +#define TRC_SCHED_BLOCK               0x00010005
    4.17 +#define TRC_SCHED_SHUTDOWN            0x00010006
    4.18 +#define TRC_SCHED_CTL                 0x00010007
    4.19 +#define TRC_SCHED_ADJDOM              0x00010008
    4.20  #define TRC_SCHED_SWITCH              0x00010009
    4.21  #define TRC_SCHED_S_TIMER_FN          0x0001000A
    4.22  #define TRC_SCHED_T_TIMER_FN          0x0001000B
    4.23 @@ -186,15 +186,14 @@ void sched_add_domain(struct exec_domain
    4.24      }
    4.25  
    4.26      SCHED_OP(add_task, ed);
    4.27 -
    4.28 -    TRACE_2D(TRC_SCHED_DOM_ADD, d->id, ed);
    4.29 +    TRACE_2D(TRC_SCHED_DOM_ADD, d->id, ed->eid);
    4.30  }
    4.31  
    4.32  void sched_rem_domain(struct exec_domain *ed) 
    4.33  {
    4.34      rem_ac_timer(&ed->timer);
    4.35      SCHED_OP(rem_task, ed);
    4.36 -    TRACE_3D(TRC_SCHED_DOM_REM, ed->domain->id, ed->eid, ed);
    4.37 +    TRACE_2D(TRC_SCHED_DOM_REM, ed->domain->id, ed->eid);
    4.38  }
    4.39  
    4.40  void init_idle_task(void)
    4.41 @@ -203,19 +202,19 @@ void init_idle_task(void)
    4.42          BUG();
    4.43  }
    4.44  
    4.45 -void domain_sleep(struct exec_domain *d)
    4.46 +void domain_sleep(struct exec_domain *ed)
    4.47  {
    4.48      unsigned long flags;
    4.49  
    4.50 -    spin_lock_irqsave(&schedule_data[d->processor].schedule_lock, flags);
    4.51 +    spin_lock_irqsave(&schedule_data[ed->processor].schedule_lock, flags);
    4.52 +    if ( likely(!domain_runnable(ed)) )
    4.53 +        SCHED_OP(sleep, ed);
    4.54 +    spin_unlock_irqrestore(&schedule_data[ed->processor].schedule_lock, flags);
    4.55  
    4.56 -    if ( likely(!domain_runnable(d)) )
    4.57 -        SCHED_OP(sleep, d);
    4.58 -
    4.59 -    spin_unlock_irqrestore(&schedule_data[d->processor].schedule_lock, flags);
    4.60 +    TRACE_2D(TRC_SCHED_SLEEP, ed->domain->id, ed->eid);
    4.61   
    4.62      /* Synchronous. */
    4.63 -    while ( test_bit(EDF_RUNNING, &d->ed_flags) && !domain_runnable(d) )
    4.64 +    while ( test_bit(EDF_RUNNING, &ed->ed_flags) && !domain_runnable(ed) )
    4.65          cpu_relax();
    4.66  }
    4.67  
    4.68 @@ -224,19 +223,17 @@ void domain_wake(struct exec_domain *ed)
    4.69      unsigned long flags;
    4.70  
    4.71      spin_lock_irqsave(&schedule_data[ed->processor].schedule_lock, flags);
    4.72 -
    4.73      if ( likely(domain_runnable(ed)) )
    4.74      {
    4.75 -        TRACE_2D(TRC_SCHED_WAKE, ed->domain->id, ed);
    4.76          SCHED_OP(wake, ed);
    4.77  #ifdef WAKE_HISTO
    4.78          ed->wokenup = NOW();
    4.79  #endif
    4.80      }
    4.81 -    
    4.82      clear_bit(EDF_MIGRATED, &ed->ed_flags);
    4.83 -    
    4.84      spin_unlock_irqrestore(&schedule_data[ed->processor].schedule_lock, flags);
    4.85 +
    4.86 +    TRACE_2D(TRC_SCHED_WAKE, ed->domain->id, ed->eid);
    4.87  }
    4.88  
    4.89  /* Block the currently-executing domain until a pertinent event occurs. */
    4.90 @@ -244,8 +241,6 @@ long do_block(void)
    4.91  {
    4.92      struct exec_domain *ed = current;
    4.93  
    4.94 -    TRACE_2D(TRC_SCHED_BLOCK, ed->domain->id, ed);
    4.95 -
    4.96      ed->vcpu_info->evtchn_upcall_mask = 0;
    4.97      set_bit(EDF_BLOCKED, &ed->ed_flags);
    4.98  
    4.99 @@ -253,7 +248,10 @@ long do_block(void)
   4.100      if ( event_pending(ed) )
   4.101          clear_bit(EDF_BLOCKED, &ed->ed_flags);
   4.102      else
   4.103 +    {
   4.104 +        TRACE_2D(TRC_SCHED_BLOCK, ed->domain->id, ed->eid);
   4.105          __enter_scheduler();
   4.106 +    }
   4.107  
   4.108      return 0;
   4.109  }
   4.110 @@ -261,7 +259,7 @@ long do_block(void)
   4.111  /* Voluntarily yield the processor for this allocation. */
   4.112  static long do_yield(void)
   4.113  {
   4.114 -    TRACE_2D(TRC_SCHED_YIELD, current->domain->id, current);
   4.115 +    TRACE_2D(TRC_SCHED_YIELD, current->domain->id, current->eid);
   4.116      __enter_scheduler();
   4.117      return 0;
   4.118  }
   4.119 @@ -290,6 +288,8 @@ long do_sched_op(unsigned long op)
   4.120  
   4.121      case SCHEDOP_shutdown:
   4.122      {
   4.123 +        TRACE_3D(TRC_SCHED_SHUTDOWN, current->domain->id, current->eid,
   4.124 +                 (op >> SCHEDOP_reasonshift));
   4.125          domain_shutdown((u8)(op >> SCHEDOP_reasonshift));
   4.126          break;
   4.127      }
   4.128 @@ -322,12 +322,12 @@ int sched_id()
   4.129  
   4.130  long sched_ctl(struct sched_ctl_cmd *cmd)
   4.131  {
   4.132 -    TRACE_0D(TRC_SCHED_CTL);
   4.133 -
   4.134      if ( cmd->sched_id != ops.sched_id )
   4.135          return -EINVAL;
   4.136  
   4.137 -    return SCHED_OP(control, cmd);
   4.138 +    SCHED_OP(control, cmd);
   4.139 +    TRACE_0D(TRC_SCHED_CTL);
   4.140 +    return 0;
   4.141  }
   4.142  
   4.143  
   4.144 @@ -346,12 +346,11 @@ long sched_adjdom(struct sched_adjdom_cm
   4.145      if ( d == NULL )
   4.146          return -ESRCH;
   4.147  
   4.148 -    TRACE_1D(TRC_SCHED_ADJDOM, d->id);
   4.149 -
   4.150      spin_lock_irq(&schedule_data[d->exec_domain[0]->processor].schedule_lock);
   4.151      SCHED_OP(adjdom, d, cmd);
   4.152      spin_unlock_irq(&schedule_data[d->exec_domain[0]->processor].schedule_lock);
   4.153  
   4.154 +    TRACE_1D(TRC_SCHED_ADJDOM, d->id);
   4.155      put_domain(d);
   4.156      return 0;
   4.157  }
   4.158 @@ -423,8 +422,6 @@ static void __enter_scheduler(void)
   4.159      }
   4.160  #endif
   4.161  
   4.162 -    TRACE_2D(TRC_SCHED_SWITCH, next->domain->id, next);
   4.163 -
   4.164      prev->sleep_tick = schedule_data[cpu].tick;
   4.165  
   4.166      /* Ensure that the domain has an up-to-date time base. */
   4.167 @@ -435,6 +432,10 @@ static void __enter_scheduler(void)
   4.168              send_guest_virq(next, VIRQ_TIMER);
   4.169      }
   4.170  
   4.171 +    TRACE_4D(TRC_SCHED_SWITCH,
   4.172 +             prev->domain->id, prev->eid,
   4.173 +             next->domain->id, next->eid);
   4.174 +
   4.175      context_switch(prev, next);
   4.176  }
   4.177  
   4.178 @@ -456,7 +457,6 @@ int idle_cpu(int cpu)
   4.179  /* The scheduler timer: force a run through the scheduler */
   4.180  static void s_timer_fn(unsigned long unused)
   4.181  {
   4.182 -    TRACE_0D(TRC_SCHED_S_TIMER_FN);
   4.183      raise_softirq(SCHEDULE_SOFTIRQ);
   4.184      perfc_incrc(sched_irq);
   4.185  }
   4.186 @@ -467,8 +467,6 @@ static void t_timer_fn(unsigned long unu
   4.187      struct exec_domain *ed  = current;
   4.188      unsigned int        cpu = ed->processor;
   4.189  
   4.190 -    TRACE_0D(TRC_SCHED_T_TIMER_FN);
   4.191 -
   4.192      schedule_data[cpu].tick++;
   4.193  
   4.194      if ( !is_idle_task(ed->domain) )
   4.195 @@ -488,8 +486,6 @@ static void dom_timer_fn(unsigned long d
   4.196  {
   4.197      struct exec_domain *ed = (struct exec_domain *)data;
   4.198  
   4.199 -    TRACE_0D(TRC_SCHED_DOM_TIMER_FN);
   4.200 -    
   4.201      update_dom_time(ed);
   4.202      send_guest_virq(ed, VIRQ_TIMER);
   4.203  }
     5.1 --- a/xen/include/public/dom0_ops.h	Tue Apr 05 16:55:50 2005 +0000
     5.2 +++ b/xen/include/public/dom0_ops.h	Tue Apr 05 17:16:09 2005 +0000
     5.3 @@ -371,19 +371,19 @@ typedef struct {
     5.4          dom0_setdomaininfo_t     setdomaininfo;
     5.5          dom0_getdomaininfo_t     getdomaininfo;
     5.6          dom0_getpageframeinfo_t  getpageframeinfo;
     5.7 -	dom0_msr_t               msr;
     5.8 -	dom0_debug_t             debug;
     5.9 -	dom0_settime_t           settime;
    5.10 -	dom0_readconsole_t	 readconsole;
    5.11 -	dom0_pincpudomain_t      pincpudomain;
    5.12 +        dom0_msr_t               msr;
    5.13 +        dom0_debug_t             debug;
    5.14 +        dom0_settime_t           settime;
    5.15 +        dom0_readconsole_t	 readconsole;
    5.16 +        dom0_pincpudomain_t      pincpudomain;
    5.17          dom0_gettbufs_t          gettbufs;
    5.18          dom0_physinfo_t          physinfo;
    5.19          dom0_pcidev_access_t     pcidev_access;
    5.20          dom0_sched_id_t          sched_id;
    5.21 -	dom0_shadow_control_t    shadow_control;
    5.22 -	dom0_setdomaininitialmem_t setdomaininitialmem;
    5.23 -	dom0_setdomainmaxmem_t   setdomainmaxmem;
    5.24 -	dom0_getpageframeinfo2_t getpageframeinfo2;
    5.25 +        dom0_shadow_control_t    shadow_control;
    5.26 +        dom0_setdomaininitialmem_t setdomaininitialmem;
    5.27 +        dom0_setdomainmaxmem_t   setdomainmaxmem;
    5.28 +        dom0_getpageframeinfo2_t getpageframeinfo2;
    5.29          dom0_add_memtype_t       add_memtype;
    5.30          dom0_del_memtype_t       del_memtype;
    5.31          dom0_read_memtype_t      read_memtype;