ia64/xen-unstable

changeset 16632:2900e4dacaa7

[IA64] xenoprof: don't modify mPSR.pp. VTi case

Don't modify mPSR.pp for xenoprof. VTi domain case
xenoprof manages mPSR.pp so that mPSR.pp shouldn't be modified.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Mon Dec 17 09:56:12 2007 -0700 (2007-12-17)
parents 213a7029fdbc
children 7c98b9177b15
files xen/arch/ia64/vmx/optvfault.S xen/arch/ia64/vmx/vmx_vcpu.c xen/arch/ia64/xen/domain.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/optvfault.S	Mon Dec 17 09:51:06 2007 -0700
     1.2 +++ b/xen/arch/ia64/vmx/optvfault.S	Mon Dec 17 09:56:12 2007 -0700
     1.3 @@ -200,7 +200,12 @@ GLOBAL_ENTRY(vmx_asm_rsm)
     1.4      dep r26=r28,r26,23,1
     1.5      ;;
     1.6      ld8 r18=[r17]
     1.7 -    movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI
     1.8 +	
     1.9 +    // xenoprof
    1.10 +    // Don't change mPSR.pp.
    1.11 +    // It is manipulated by xenoprof.
    1.12 +    movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI+IA64_PSR_PP
    1.13 +
    1.14      ld1 r23=[r22]
    1.15      sub r27=-1,r26 // ~r26
    1.16      mov r24=b0
    1.17 @@ -260,6 +265,9 @@ GLOBAL_ENTRY(vmx_asm_ssm)
    1.18      ;;  //r19 vpsr
    1.19      ld8 r29=[r27]
    1.20      mov r24=b0
    1.21 +    dep r17=0,r26,IA64_PSR_PP_BIT,1 // For xenoprof
    1.22 +                                    // Don't change mPSR.pp
    1.23 +                                    // It is maintained by xenoprof.
    1.24      ;;
    1.25      add r22=IA64_VCPU_MMU_MODE_OFFSET,r21
    1.26      mov r20=cr.ipsr
    1.27 @@ -267,7 +275,7 @@ GLOBAL_ENTRY(vmx_asm_ssm)
    1.28      ;;
    1.29      ld1 r23=[r22] // mmu_mode
    1.30      st8 [r27]=r19 // vpsr
    1.31 -    or r20=r20,r26
    1.32 +    or r20=r20,r17
    1.33      ;;
    1.34      mov cr.ipsr=r20
    1.35      movl r28=IA64_PSR_DT+IA64_PSR_RT+IA64_PSR_IT
    1.36 @@ -379,6 +387,7 @@ vmx_asm_mov_to_psr_1:
    1.37      mov r20=cr.ipsr
    1.38      movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI+IA64_PSR_RT
    1.39      ;;
    1.40 +    tbit.nz p7,p0=r20,IA64_PSR_PP_BIT           // For xenoprof
    1.41      or r19=r19,r28
    1.42      dep r20=0,r20,0,32
    1.43      ;;
    1.44 @@ -386,6 +395,9 @@ vmx_asm_mov_to_psr_1:
    1.45      mov b0=r24
    1.46      ;;
    1.47      adds r27=IA64_VCPU_FP_PSR_OFFSET,r21
    1.48 +    (p7) dep r20=-1,r20,IA64_PSR_PP_BIT,1       // For xenoprof
    1.49 +                                                // Dom't change mPSR.pp
    1.50 +                                                // It is maintaned by xenoprof
    1.51      ;;
    1.52      ld8 r27=[r27]
    1.53      ;;
     2.1 --- a/xen/arch/ia64/vmx/vmx_vcpu.c	Mon Dec 17 09:51:06 2007 -0700
     2.2 +++ b/xen/arch/ia64/vmx/vmx_vcpu.c	Mon Dec 17 09:56:12 2007 -0700
     2.3 @@ -60,7 +60,12 @@ unsigned long guest_psr_index = 0;
     2.4  void
     2.5  vmx_ia64_set_dcr(VCPU *v)   
     2.6  {
     2.7 -    unsigned long dcr_bits = IA64_DEFAULT_DCR_BITS;
     2.8 +    /* xenoprof:
     2.9 +     * don't change psr.pp.
    2.10 +     * It is manipulated by xenoprof.
    2.11 +     */
    2.12 +    unsigned long dcr_bits = (IA64_DEFAULT_DCR_BITS & ~IA64_DCR_PP) |
    2.13 +        (ia64_getreg(_IA64_REG_CR_DCR) & IA64_DCR_PP);
    2.14  
    2.15      // if guest is runing on cpl > 0, set dcr.dm=1
    2.16      // if geust is runing on cpl = 0, set dcr.dm=0
    2.17 @@ -128,10 +133,16 @@ vmx_vcpu_set_psr(VCPU *vcpu, unsigned lo
    2.18       * , except for the following bits:
    2.19       *  ic/i/dt/si/rt/mc/it/bn/vm
    2.20       */
    2.21 -    mask =  IA64_PSR_IC + IA64_PSR_I + IA64_PSR_DT + IA64_PSR_SI +
    2.22 -        IA64_PSR_RT + IA64_PSR_MC + IA64_PSR_IT + IA64_PSR_BN +
    2.23 +    mask =  IA64_PSR_IC | IA64_PSR_I | IA64_PSR_DT | IA64_PSR_SI |
    2.24 +        IA64_PSR_RT | IA64_PSR_MC | IA64_PSR_IT | IA64_PSR_BN |
    2.25          IA64_PSR_VM;
    2.26  
    2.27 +    /* xenoprof:
    2.28 +     * don't change psr.pp.
    2.29 +     * It is manipulated by xenoprof.
    2.30 +     */
    2.31 +    mask |= IA64_PSR_PP;
    2.32 +
    2.33      regs->cr_ipsr = (regs->cr_ipsr & mask ) | ( value & (~mask) );
    2.34  
    2.35      if (FP_PSR(vcpu) & IA64_PSR_DFH)
     3.1 --- a/xen/arch/ia64/xen/domain.c	Mon Dec 17 09:51:06 2007 -0700
     3.2 +++ b/xen/arch/ia64/xen/domain.c	Mon Dec 17 09:56:12 2007 -0700
     3.3 @@ -231,7 +231,13 @@ void context_switch(struct vcpu *prev, s
     3.4          if (!VMX_DOMAIN(next)) {
     3.5              /* VMX domains can change the physical cr.dcr.
     3.6               * Restore default to prevent leakage. */
     3.7 -            ia64_setreg(_IA64_REG_CR_DCR, IA64_DEFAULT_DCR_BITS);
     3.8 +            uint64_t dcr = ia64_getreg(_IA64_REG_CR_DCR);
     3.9 +            /* xenoprof:
    3.10 +             * don't change psr.pp.
    3.11 +             * It is manipulated by xenoprof.
    3.12 +             */
    3.13 +            dcr = (IA64_DEFAULT_DCR_BITS & ~IA64_DCR_PP) | (dcr & IA64_DCR_PP);
    3.14 +            ia64_setreg(_IA64_REG_CR_DCR, dcr);
    3.15          }
    3.16      }
    3.17      if (VMX_DOMAIN(next))