ia64/xen-unstable

changeset 17801:268a9f8286f3

xentrace: fix tracing for 64bit guests

Xen tracing some times ago used to put values of type 'long' into the
trace buffer. This has changed to uint32_t. Some trace points log
virtual addresses, which get cropped to 32bit in this case. There were
some inline functions to handle at least PF_XEN and VMEXIT, which
caused a lot of code duplication. The attached patch fixes several
issues:
1. fix and extend tools/xentrace/formats
2. Fix xentrace_format to handle up to 7 parameters
3. create convenience macros to properly log long values
4. remove the inline functions in hvm/trace.h and replace them by macros
5. Change the CPUID trace to work correctly
6. group HVM trace points enable mechanism

I used a similar approach as in PV tracing with bit 8 indicating 64bit
pointers.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Jun 09 09:45:38 2008 +0100 (2008-06-09)
parents 5009f5d093ce
children 07ba9aeee347
files tools/xentrace/formats tools/xentrace/xentrace_format xen/arch/x86/hvm/svm/svm.c xen/arch/x86/hvm/vmx/vmx.c xen/arch/x86/trace.c xen/include/asm-x86/hvm/trace.h xen/include/public/trace.h
line diff
     1.1 --- a/tools/xentrace/formats	Mon Jun 09 09:44:21 2008 +0100
     1.2 +++ b/tools/xentrace/formats	Mon Jun 09 09:45:38 2008 +0100
     1.3 @@ -1,48 +1,67 @@
     1.4  0x00000000  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  unknown (0x%(event)016x)  [ 0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x ]
     1.5  
     1.6 -0x0001f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  lost_records        0x%(1)08x
     1.7 -0x0001f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  wrap_buffer         0x%(1)08x
     1.8 -0x0001f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  cpu_change          0x%(1)08x
     1.9 +0x0001f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  lost_records      0x%(1)08x
    1.10 +0x0001f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  wrap_buffer       0x%(1)08x
    1.11 +0x0001f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  cpu_change        0x%(1)08x
    1.12  
    1.13 -0x0002f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_add_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.14 -0x0002f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_rem_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.15 -0x0002f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_sleep		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.16 -0x0002f004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_wake		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.17 -0x0002f005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  do_yield		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.18 -0x0002f006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  do_block		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.19 -0x0002f007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_shutdown		[ domid = 0x%(1)08x, edomid = 0x%(2)08x, reason = 0x%(3)08x ]
    1.20 +0x0002f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_add_domain  [ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.21 +0x0002f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_rem_domain  [ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.22 +0x0002f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_sleep      [ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.23 +0x0002f004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_wake       [ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.24 +0x0002f005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  do_yield          [ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.25 +0x0002f006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  do_block          [ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.26 +0x0002f007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_shutdown	  [ domid = 0x%(1)08x, edomid = 0x%(2)08x, reason = 0x%(3)08x ]
    1.27  0x0002f008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_ctl
    1.28 -0x0002f009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_adjdom		[ domid = 0x%(1)08x ]
    1.29 -0x0002f00a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  __enter_scheduler	[ prev<domid:edomid> = 0x%(1)08x : 0x%(2)08x, next<domid:edomid> = 0x%(3)08x : 0x%(4)08x ]
    1.30 +0x0002f009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_adjdom      [ domid = 0x%(1)08x ]
    1.31 +0x0002f00a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  __enter_scheduler [ prev<domid:edomid> = 0x%(1)08x : 0x%(2)08x, next<domid:edomid> = 0x%(3)08x : 0x%(4)08x ]
    1.32  0x0002f00B  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  s_timer_fn
    1.33  0x0002f00c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  t_timer_fn
    1.34  0x0002f00d  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  dom_timer_fn
    1.35 +0x0002f00e  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  switch_infprev    [ old_domid = 0x%(1)08x, runtime = %(2)d ]
    1.36 +0x0002f00f  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  switch_infnext    [ new_domid = 0x%(1)08x, time = %(2)d, r_time = %(3)d ]
    1.37  
    1.38  0x00081001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY     [ dom:vcpu = 0x%(1)08x ]
    1.39  0x00081002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT      [ dom:vcpu = 0x%(1)08x, exitcode = 0x%(2)08x, rIP  = 0x%(3)08x ]
    1.40 -0x00082001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  PF_XEN      [ dom:vcpu = 0x%(1)08x, errorcode = 0x%(2)02x, virt = 0x%(3)08x ]
    1.41 -0x00082002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  PF_INJECT   [ dom:vcpu = 0x%(1)08x, virt = 0x%(2)08x, errorcode = 0x%(3)02x ]
    1.42 +0x00081102  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT      [ dom:vcpu = 0x%(1)08x, exitcode = 0x%(2)08x, rIP  = 0x%(3)016x ]
    1.43 +0x00082001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  PF_XEN      [ dom:vcpu = 0x%(1)08x, errorcode = 0x%(3)02x, virt = 0x%(2)08x ]
    1.44 +0x00082101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  PF_XEN      [ dom:vcpu = 0x%(1)08x, errorcode = 0x%(3)02x, virt = 0x%(2)016x ]
    1.45 +0x00082002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  PF_INJECT   [ dom:vcpu = 0x%(1)08x, errorcode = 0x%(2)02x, virt = 0x%(3)08x ]
    1.46 +0x00082102  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  PF_INJECT   [ dom:vcpu = 0x%(1)08x,  errorcode = 0x%(2)02x, virt = 0x%(3)016x ]
    1.47  0x00082003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  INJ_EXC     [ dom:vcpu = 0x%(1)08x, vector = 0x%(2)02x, errorcode = 0x%(3)04x ]
    1.48  0x00082004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  INJ_VIRQ    [ dom:vcpu = 0x%(1)08x, vector = 0x%(2)02x, fake = %(3)d ]
    1.49  0x00082005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  REINJ_VIRQ  [ dom:vcpu = 0x%(1)08x, vector = 0x%(2)02x ]
    1.50  0x00082006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  IO_READ     [ dom:vcpu = 0x%(1)08x, port = 0x%(2)04x, size = %(3)d ]
    1.51  0x00082007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  IO_WRITE    [ dom:vcpu = 0x%(1)08x, port = 0x%(2)04x, size = %(3)d ]
    1.52  0x00082008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  CR_READ     [ dom:vcpu = 0x%(1)08x, CR# = %(2)d, value = 0x%(3)08x ]
    1.53 +0x00082108  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  CR_READ     [ dom:vcpu = 0x%(1)08x, CR# = %(2)d, value = 0x%(3)016x ]
    1.54  0x00082009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  CR_WRITE    [ dom:vcpu = 0x%(1)08x, CR# = %(2)d, value = 0x%(3)08x ]
    1.55 +0x00082109  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  CR_WRITE    [ dom:vcpu = 0x%(1)08x, CR# = %(2)d, value = 0x%(3)016x ]
    1.56  0x0008200A  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  DR_READ     [ dom:vcpu = 0x%(1)08x ]
    1.57  0x0008200B  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  DR_WRITE    [ dom:vcpu = 0x%(1)08x ]
    1.58 -0x0008200C  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  MSR_READ    [ dom:vcpu = 0x%(1)08x, MSR# = 0x%(2)08x, value = 0x%(3)08x ]
    1.59 -0x0008200D  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  MSR_WRITE   [ dom:vcpu = 0x%(1)08x, MSR# = 0x%(2)08x, value = 0x%(3)08x ]
    1.60 -0x0008200E  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  CPUID       [ dom:vcpu = 0x%(1)08x, func = 0x%(2)08x, eax:ebx = 0x%(3)016x, ecx:edx = 0x%(4)016x ]
    1.61 +0x0008200C  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  MSR_READ    [ dom:vcpu = 0x%(1)08x, MSR# = 0x%(2)08x, value = 0x%(3)016x ]
    1.62 +0x0008200D  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  MSR_WRITE   [ dom:vcpu = 0x%(1)08x, MSR# = 0x%(2)08x, value = 0x%(3)016x ]
    1.63 +0x0008200E  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  CPUID       [ dom:vcpu = 0x%(1)08x, func = 0x%(2)08x, eax = 0x%(3)08x, ebx = 0x%(4)08x, ecx=0x%(5)08x, edx = 0x%(6)08x ]
    1.64  0x0008200F  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  INTR        [ dom:vcpu = 0x%(1)08x, vector = 0x%(2)02x ]
    1.65  0x00082010  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  NMI         [ dom:vcpu = 0x%(1)08x ]
    1.66  0x00082011  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  SMI         [ dom:vcpu = 0x%(1)08x ]
    1.67  0x00082012  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMMCALL     [ dom:vcpu = 0x%(1)08x, func = 0x%(2)08x ]
    1.68  0x00082013  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  HLT         [ dom:vcpu = 0x%(1)08x, intpending = %(2)d ]
    1.69 -0x00082014  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  INVLPG      [ dom:vcpu = 0x%(1)08x, virt = 0x%(2)08x, invlpga = %(3)d, asid = 0x%(4)02x ]
    1.70 +0x00082014  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  INVLPG      [ dom:vcpu = 0x%(1)08x, is invlpga? = %(2)d, virt = 0x%(3)08x ]
    1.71 +0x00082114  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  INVLPG      [ dom:vcpu = 0x%(1)08x, is invlpga? = %(2)d, virt = 0x%(3)016x ]
    1.72  0x00082015  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  MCE         [ dom:vcpu = 0x%(1)08x ]
    1.73  0x00082016  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  IO_ASSIST   [ dom:vcpu = 0x%(1)08x, data = 0x%(2)04x ]
    1.74  0x00082017  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  MMIO_ASSIST [ dom:vcpu = 0x%(1)08x, data = 0x%(2)04x ]
    1.75  0x00082018  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  CLTS        [ dom:vcpu = 0x%(1)08x ]
    1.76  0x00082019  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  LMSW        [ dom:vcpu = 0x%(1)08x, value = 0x%(2)08x ]
    1.77 -0x00082020  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  PF_XEN64    [ dom:vcpu = 0x%(1)08x, errorcode = 0x%(2)02x, virt = 0x%(3)08x ]
    1.78 +0x00082119  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  LMSW        [ dom:vcpu = 0x%(1)08x, value = 0x%(2)016x ]
    1.79 +
    1.80 +0x0010f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_map      [ domid = %(1)d ]
    1.81 +0x0010f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_unmap    [ domid = %(1)d ]
    1.82 +0x0010f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_transfer [ domid = %(1)d ]
    1.83 +
    1.84 +0x0020f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ eip = 0x%(1)08x, eax = 0x%(2)08x ]
    1.85 +0x0020f101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ rip = 0x%(1)016x, eax = 0x%(2)08x ]
    1.86 +0x0020f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ eip = 0x%(1)08x, trapnr:error = 0x%(2)08x ]
    1.87 +0x0020f103  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ rip = 0x%(1)016x, trapnr:error = 0x%(2)08x ]
    1.88 +0x0020f004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ eip = 0x%(1)08x, addr = 0x%(2)08x, error = 0x%(3)08x ]
    1.89 +0x0020f104  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ rip = 0x%(1)16x, addr = 0x%(3)16x, error = 0x%(5)08x ]
     2.1 --- a/tools/xentrace/xentrace_format	Mon Jun 09 09:44:21 2008 +0100
     2.2 +++ b/tools/xentrace/xentrace_format	Mon Jun 09 09:45:38 2008 +0100
     2.3 @@ -17,12 +17,12 @@ def usage():
     2.4            {event_id}{whitespace}{text format string}
     2.5  
     2.6            The textual format string may include format specifiers, such as:
     2.7 -            %(cpu)d, %(tsc)d, %(event)d, %(1)d, %(2)d, %(3)d, %(4)d, %(5)d
     2.8 +            %(cpu)d, %(tsc)d, %(event)d, %(1)d, %(2)d, %(3)d, %(4)d, ... 
     2.9            [ the 'd' format specifier outputs in decimal, alternatively 'x'
    2.10              will output in hexadecimal and 'o' will output in octal ]
    2.11  
    2.12            Which correspond to the CPU number, event ID, timestamp counter and
    2.13 -          the 5 data fields from the trace record.  There should be one such
    2.14 +          the 7 data fields from the trace record.  There should be one such
    2.15            rule for each type of event.
    2.16            
    2.17            Depending on your system and the volume of trace buffer data,
    2.18 @@ -84,7 +84,7 @@ interrupted = 0
    2.19  defs = read_defs(arg[0])
    2.20  
    2.21  # structure of trace record (as output by xentrace):
    2.22 -# HDR(I) {TSC(Q)} D1(I) D2(I) D3(I) D4(I) D5(I)
    2.23 +# HDR(I) {TSC(Q)} D1(I) D2(I) D3(I) D4(I) D5(I) D6(I) D7(I)
    2.24  #
    2.25  # HDR consists of EVENT:28:, n_data:3:, tsc_in:1:
    2.26  # EVENT means Event ID
    2.27 @@ -101,6 +101,8 @@ D2REC  = "II"
    2.28  D3REC  = "III"
    2.29  D4REC  = "IIII"
    2.30  D5REC  = "IIIII"
    2.31 +D6REC  = "IIIIII"
    2.32 +D7REC  = "IIIIIII"
    2.33  
    2.34  last_tsc = [0]
    2.35  
    2.36 @@ -121,6 +123,8 @@ while not interrupted:
    2.37          d3 = 0
    2.38          d4 = 0
    2.39          d5 = 0
    2.40 +        d6 = 0
    2.41 +        d7 = 0
    2.42  
    2.43          tsc = 0
    2.44  
    2.45 @@ -155,6 +159,16 @@ while not interrupted:
    2.46              if not line:
    2.47                  break
    2.48              (d1, d2, d3, d4, d5) = struct.unpack(D5REC, line)
    2.49 +        if n_data == 6:
    2.50 +            line = sys.stdin.read(struct.calcsize(D6REC))
    2.51 +            if not line:
    2.52 +                break
    2.53 +            (d1, d2, d3, d4, d5, d6) = struct.unpack(D6REC, line)
    2.54 +        if n_data == 7:
    2.55 +            line = sys.stdin.read(struct.calcsize(D7REC))
    2.56 +            if not line:
    2.57 +                break
    2.58 +            (d1, d2, d3, d4, d5, d6, d7) = struct.unpack(D7REC, line)
    2.59  
    2.60          # Event field is 28bit of 'uint32_t' in header, not 'long'.
    2.61          event &= 0x0fffffff
    2.62 @@ -191,7 +205,9 @@ while not interrupted:
    2.63                  '2'     : d2,
    2.64                  '3'     : d3,
    2.65                  '4'     : d4,
    2.66 -                '5'     : d5    }
    2.67 +                '5'     : d5,
    2.68 +                '6'     : d6,
    2.69 +                '7'     : d7    }
    2.70  
    2.71          try:
    2.72  
     3.1 --- a/xen/arch/x86/hvm/svm/svm.c	Mon Jun 09 09:44:21 2008 +0100
     3.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Mon Jun 09 09:45:38 2008 +0100
     3.3 @@ -757,7 +757,7 @@ static void svm_inject_exception(
     3.4      if ( trapnr == TRAP_page_fault )
     3.5      {
     3.6          vmcb->cr2 = curr->arch.hvm_vcpu.guest_cr[2] = cr2;
     3.7 -        HVMTRACE_2D(PF_INJECT, curr, curr->arch.hvm_vcpu.guest_cr[2], errcode);
     3.8 +        HVMTRACE_LONG_2D(PF_INJECT, curr, errcode, TRC_PAR_LONG(cr2));
     3.9      }
    3.10      else
    3.11      {
    3.12 @@ -914,8 +914,7 @@ static void svm_cpuid_intercept(
    3.13              __clear_bit(X86_FEATURE_APIC & 31, edx);
    3.14      }
    3.15  
    3.16 -    HVMTRACE_3D(CPUID, v, input,
    3.17 -                ((uint64_t)*eax << 32) | *ebx, ((uint64_t)*ecx << 32) | *edx);
    3.18 +    HVMTRACE_5D (CPUID, v, input, *eax, *ebx, *ecx, *edx);
    3.19  }
    3.20  
    3.21  static void svm_vmexit_do_cpuid(struct cpu_user_regs *regs)
    3.22 @@ -1014,7 +1013,7 @@ static int svm_msr_read_intercept(struct
    3.23      regs->edx = msr_content >> 32;
    3.24  
    3.25   done:
    3.26 -    hvmtrace_msr_read(v, ecx, msr_content);
    3.27 +    HVMTRACE_3D (MSR_READ, v, ecx, regs->eax, regs->edx);
    3.28      HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%x, eax=%lx, edx=%lx",
    3.29                  ecx, (unsigned long)regs->eax, (unsigned long)regs->edx);
    3.30      return X86EMUL_OKAY;
    3.31 @@ -1033,7 +1032,7 @@ static int svm_msr_write_intercept(struc
    3.32  
    3.33      msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
    3.34  
    3.35 -    hvmtrace_msr_write(v, ecx, msr_content);
    3.36 +    HVMTRACE_3D (MSR_WRITE, v, ecx, regs->eax, regs->edx);
    3.37  
    3.38      switch ( ecx )
    3.39      {
    3.40 @@ -1153,7 +1152,7 @@ static void svm_vmexit_do_invalidate_cac
    3.41  static void svm_invlpg_intercept(unsigned long vaddr)
    3.42  {
    3.43      struct vcpu *curr = current;
    3.44 -    HVMTRACE_2D(INVLPG, curr, 0, vaddr);
    3.45 +    HVMTRACE_LONG_2D(INVLPG, curr, 0, TRC_PAR_LONG(vaddr));
    3.46      paging_invlpg(curr, vaddr);
    3.47      svm_asid_g_invlpg(curr, vaddr);
    3.48  }
    3.49 @@ -1176,7 +1175,12 @@ asmlinkage void svm_vmexit_handler(struc
    3.50  
    3.51      exit_reason = vmcb->exitcode;
    3.52  
    3.53 -    hvmtrace_vmexit(v, regs->eip, exit_reason);
    3.54 +    if ( hvm_long_mode_enabled(v) )
    3.55 +        HVMTRACE_ND (VMEXIT64, 1/*cycles*/, v, 3, exit_reason,
    3.56 +            regs->eip & 0xFFFFFFFF, regs->eip >> 32, 0, 0, 0);
    3.57 +    else
    3.58 +        HVMTRACE_ND (VMEXIT, 1/*cycles*/, v, 2, exit_reason,
    3.59 +            regs->eip, 0, 0, 0, 0);
    3.60  
    3.61      if ( unlikely(exit_reason == VMEXIT_INVALID) )
    3.62      {
    3.63 @@ -1244,7 +1248,10 @@ asmlinkage void svm_vmexit_handler(struc
    3.64  
    3.65          if ( paging_fault(va, regs) )
    3.66          {
    3.67 -            HVMTRACE_2D(PF_XEN, v, va, regs->error_code);
    3.68 +            if (hvm_long_mode_enabled(v))
    3.69 +                HVMTRACE_LONG_2D(PF_XEN, v, regs->error_code, TRC_PAR_LONG(va));
    3.70 +            else
    3.71 +                HVMTRACE_2D(PF_XEN, v, regs->error_code, va);
    3.72              break;
    3.73          }
    3.74  
    3.75 @@ -1382,7 +1389,7 @@ asmlinkage void svm_vmexit_handler(struc
    3.76  
    3.77  asmlinkage void svm_trace_vmentry(void)
    3.78  {
    3.79 -    hvmtrace_vmentry(current);
    3.80 +    HVMTRACE_ND (VMENTRY, 1/*cycles*/, current, 0, 0, 0, 0, 0, 0, 0);
    3.81  }
    3.82    
    3.83  /*
     4.1 --- a/xen/arch/x86/hvm/vmx/vmx.c	Mon Jun 09 09:44:21 2008 +0100
     4.2 +++ b/xen/arch/x86/hvm/vmx/vmx.c	Mon Jun 09 09:45:38 2008 +0100
     4.3 @@ -1107,7 +1107,8 @@ static void __vmx_inject_exception(
     4.4      __vmwrite(VM_ENTRY_INTR_INFO, intr_fields);
     4.5  
     4.6      if ( trap == TRAP_page_fault )
     4.7 -        HVMTRACE_2D(PF_INJECT, v, v->arch.hvm_vcpu.guest_cr[2], error_code);
     4.8 +        HVMTRACE_LONG_2D(PF_INJECT, v, error_code,
     4.9 +            TRC_PAR_LONG(v->arch.hvm_vcpu.guest_cr[2]));
    4.10      else
    4.11          HVMTRACE_2D(INJ_EXC, v, trap, error_code);
    4.12  }
    4.13 @@ -1328,8 +1329,7 @@ static void vmx_cpuid_intercept(
    4.14              break;
    4.15      }
    4.16  
    4.17 -    HVMTRACE_3D(CPUID, current, input,
    4.18 -                ((uint64_t)*eax << 32) | *ebx, ((uint64_t)*ecx << 32) | *edx);
    4.19 +    HVMTRACE_5D (CPUID, current, input, *eax, *ebx, *ecx, *edx);
    4.20  }
    4.21  
    4.22  static void vmx_do_cpuid(struct cpu_user_regs *regs)
    4.23 @@ -1367,7 +1367,7 @@ static void vmx_dr_access(unsigned long 
    4.24  static void vmx_invlpg_intercept(unsigned long vaddr)
    4.25  {
    4.26      struct vcpu *curr = current;
    4.27 -    HVMTRACE_2D(INVLPG, curr, /*invlpga=*/ 0, vaddr);
    4.28 +    HVMTRACE_LONG_2D(INVLPG, curr, /*invlpga=*/ 0, TRC_PAR_LONG(vaddr));
    4.29      if ( paging_invlpg(curr, vaddr) )
    4.30          vpid_sync_vcpu_gva(curr, vaddr);
    4.31  }
    4.32 @@ -1418,7 +1418,7 @@ static int mov_to_cr(int gp, int cr, str
    4.33          goto exit_and_crash;
    4.34      }
    4.35  
    4.36 -    HVMTRACE_2D(CR_WRITE, v, cr, value);
    4.37 +    HVMTRACE_LONG_2D(CR_WRITE, v, cr, TRC_PAR_LONG(value));
    4.38  
    4.39      HVM_DBG_LOG(DBG_LEVEL_1, "CR%d, value = %lx", cr, value);
    4.40  
    4.41 @@ -1489,7 +1489,7 @@ static void mov_from_cr(int cr, int gp, 
    4.42          break;
    4.43      }
    4.44  
    4.45 -    HVMTRACE_2D(CR_READ, v, cr, value);
    4.46 +    HVMTRACE_LONG_2D(CR_READ, v, cr, TRC_PAR_LONG(value));
    4.47  
    4.48      HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR%d, value = %lx", cr, value);
    4.49  }
    4.50 @@ -1520,7 +1520,7 @@ static int vmx_cr_access(unsigned long e
    4.51      case VMX_CONTROL_REG_ACCESS_TYPE_LMSW:
    4.52          value = v->arch.hvm_vcpu.guest_cr[0];
    4.53          value = (value & ~0xFFFF) | ((exit_qualification >> 16) & 0xFFFF);
    4.54 -        HVMTRACE_1D(LMSW, current, value);
    4.55 +        HVMTRACE_LONG_1D(LMSW, current, value);
    4.56          return !hvm_set_cr0(value);
    4.57      default:
    4.58          BUG();
    4.59 @@ -1675,7 +1675,7 @@ static int vmx_msr_read_intercept(struct
    4.60      regs->edx = (uint32_t)(msr_content >> 32);
    4.61  
    4.62  done:
    4.63 -    hvmtrace_msr_read(v, ecx, msr_content);
    4.64 +    HVMTRACE_3D (MSR_READ, v, ecx, regs->eax, regs->edx);
    4.65      HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%x, eax=%lx, edx=%lx",
    4.66                  ecx, (unsigned long)regs->eax,
    4.67                  (unsigned long)regs->edx);
    4.68 @@ -1786,7 +1786,7 @@ static int vmx_msr_write_intercept(struc
    4.69  
    4.70      msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
    4.71  
    4.72 -    hvmtrace_msr_write(v, ecx, msr_content);
    4.73 +    HVMTRACE_3D (MSR_WRITE, v, ecx, regs->eax, regs->edx);
    4.74  
    4.75      switch ( ecx )
    4.76      {
    4.77 @@ -2020,7 +2020,12 @@ asmlinkage void vmx_vmexit_handler(struc
    4.78  
    4.79      exit_reason = __vmread(VM_EXIT_REASON);
    4.80  
    4.81 -    hvmtrace_vmexit(v, regs->eip, exit_reason);
    4.82 +    if ( hvm_long_mode_enabled(v) )
    4.83 +        HVMTRACE_ND (VMEXIT64, 1/*cycles*/, v, 3, exit_reason,
    4.84 +            regs->eip & 0xFFFFFFFF, regs->eip >> 32, 0, 0, 0);
    4.85 +    else
    4.86 +        HVMTRACE_ND (VMEXIT, 1/*cycles*/, v, 2, exit_reason,
    4.87 +            regs->eip, 0, 0, 0, 0);
    4.88  
    4.89      perfc_incra(vmexits, exit_reason);
    4.90  
    4.91 @@ -2109,7 +2114,12 @@ asmlinkage void vmx_vmexit_handler(struc
    4.92  
    4.93              if ( paging_fault(exit_qualification, regs) )
    4.94              {
    4.95 -                hvmtrace_pf_xen(v, exit_qualification, regs->error_code);
    4.96 +                if ( hvm_long_mode_enabled(v) )
    4.97 +                    HVMTRACE_LONG_2D (PF_XEN, v, regs->error_code,
    4.98 +                        TRC_PAR_LONG(exit_qualification) );
    4.99 +                else
   4.100 +                    HVMTRACE_2D (PF_XEN, v,
   4.101 +                        regs->error_code, exit_qualification );
   4.102                  break;
   4.103              }
   4.104  
   4.105 @@ -2271,7 +2281,7 @@ asmlinkage void vmx_vmexit_handler(struc
   4.106  
   4.107  asmlinkage void vmx_trace_vmentry(void)
   4.108  {
   4.109 -    hvmtrace_vmentry(current);
   4.110 +    HVMTRACE_ND (VMENTRY, 1/*cycles*/, current, 0, 0, 0, 0, 0, 0, 0);
   4.111  }
   4.112  
   4.113  /*
     5.1 --- a/xen/arch/x86/trace.c	Mon Jun 09 09:44:21 2008 +0100
     5.2 +++ b/xen/arch/x86/trace.c	Mon Jun 09 09:45:38 2008 +0100
     5.3 @@ -7,8 +7,8 @@
     5.4  #include <xen/trace.h>
     5.5  
     5.6  #ifndef __x86_64__
     5.7 -#undef TRC_PV_64_FLAG
     5.8 -#define TRC_PV_64_FLAG 0
     5.9 +#undef TRC_64_FLAG
    5.10 +#define TRC_64_FLAG 0
    5.11  #endif
    5.12  
    5.13  asmlinkage void trace_hypercall(void)
    5.14 @@ -38,7 +38,7 @@ asmlinkage void trace_hypercall(void)
    5.15          u32 event;
    5.16  
    5.17          event = TRC_PV_HYPERCALL;
    5.18 -        event |= TRC_PV_64_FLAG;
    5.19 +        event |= TRC_64_FLAG;
    5.20          d.eip = regs->eip;
    5.21          d.eax = regs->eax;
    5.22  
    5.23 @@ -84,7 +84,7 @@ void __trace_pv_trap(int trapnr, unsigne
    5.24          d.use_error_code=!!use_error_code;
    5.25                  
    5.26          event = TRC_PV_TRAP;
    5.27 -        event |= TRC_PV_64_FLAG;
    5.28 +        event |= TRC_64_FLAG;
    5.29          __trace_var(event, 1, sizeof(d), (unsigned char *)&d);
    5.30      }
    5.31  }
    5.32 @@ -119,7 +119,7 @@ void __trace_pv_page_fault(unsigned long
    5.33          d.addr = addr;
    5.34          d.error_code = error_code;
    5.35          event = TRC_PV_PAGE_FAULT;
    5.36 -        event |= TRC_PV_64_FLAG;
    5.37 +        event |= TRC_64_FLAG;
    5.38          __trace_var(event, 1, sizeof(d), (unsigned char *)&d);
    5.39      }
    5.40  }
    5.41 @@ -135,7 +135,7 @@ void __trace_trap_one_addr(unsigned even
    5.42      else
    5.43  #endif        
    5.44      {
    5.45 -        event |= TRC_PV_64_FLAG;
    5.46 +        event |= TRC_64_FLAG;
    5.47          __trace_var(event, 1, sizeof(va), (unsigned char *)&va);
    5.48      }
    5.49  }
    5.50 @@ -161,7 +161,7 @@ void __trace_trap_two_addr(unsigned even
    5.51          } __attribute__((packed)) d;
    5.52          d.va1=va1;
    5.53          d.va2=va2;
    5.54 -        event |= TRC_PV_64_FLAG;
    5.55 +        event |= TRC_64_FLAG;
    5.56          __trace_var(event, 1, sizeof(d), (unsigned char *)&d);
    5.57      }
    5.58  }
    5.59 @@ -207,7 +207,7 @@ void __trace_ptwr_emulation(unsigned lon
    5.60  
    5.61          event = ((CONFIG_PAGING_LEVELS == 3) ?
    5.62                   TRC_PV_PTWR_EMULATION_PAE : TRC_PV_PTWR_EMULATION);
    5.63 -        event |= TRC_PV_64_FLAG;
    5.64 +        event |= TRC_64_FLAG;
    5.65          __trace_var(event, 1/*tsc*/, sizeof(d), (unsigned char *)&d);
    5.66      }
    5.67  }
     6.1 --- a/xen/include/asm-x86/hvm/trace.h	Mon Jun 09 09:44:21 2008 +0100
     6.2 +++ b/xen/include/asm-x86/hvm/trace.h	Mon Jun 09 09:45:38 2008 +0100
     6.3 @@ -3,173 +3,66 @@
     6.4  
     6.5  #include <xen/trace.h>
     6.6  
     6.7 -#define DO_TRC_HVM_VMENTRY     1
     6.8 -#define DO_TRC_HVM_VMEXIT      1
     6.9 -#define DO_TRC_HVM_PF_XEN      1
    6.10 -#define DO_TRC_HVM_PF_INJECT   1
    6.11 -#define DO_TRC_HVM_INJ_EXC     1
    6.12 -#define DO_TRC_HVM_INJ_VIRQ    1
    6.13 -#define DO_TRC_HVM_REINJ_VIRQ  1
    6.14 -#define DO_TRC_HVM_IO_READ     1
    6.15 -#define DO_TRC_HVM_IO_WRITE    1
    6.16 -#define DO_TRC_HVM_CR_READ     1
    6.17 -#define DO_TRC_HVM_CR_WRITE    1
    6.18 -#define DO_TRC_HVM_DR_READ     1
    6.19 -#define DO_TRC_HVM_DR_WRITE    1
    6.20 -#define DO_TRC_HVM_MSR_READ    1
    6.21 -#define DO_TRC_HVM_MSR_WRITE   1
    6.22 -#define DO_TRC_HVM_CPUID       1
    6.23 -#define DO_TRC_HVM_INTR        1
    6.24 -#define DO_TRC_HVM_NMI         1
    6.25 -#define DO_TRC_HVM_MCE         1
    6.26 -#define DO_TRC_HVM_SMI         1
    6.27 -#define DO_TRC_HVM_VMMCALL     1
    6.28 -#define DO_TRC_HVM_HLT         1
    6.29 -#define DO_TRC_HVM_INVLPG      1
    6.30 -#define DO_TRC_HVM_IO_ASSIST   1
    6.31 -#define DO_TRC_HVM_MMIO_ASSIST 1
    6.32 -#define DO_TRC_HVM_CLTS        1
    6.33 -#define DO_TRC_HVM_LMSW        1
    6.34 +#define DEFAULT_HVM_TRACE_ON  1
    6.35 +#define DEFAULT_HVM_TRACE_OFF 0
    6.36  
    6.37 -static inline void hvmtrace_vmexit(struct vcpu *v,
    6.38 -                                   unsigned long rip,
    6.39 -                                   unsigned long exit_reason)
    6.40 -{
    6.41 -    if ( likely(!tb_init_done) )
    6.42 -        return;
    6.43 -
    6.44 -#ifdef __x86_64__
    6.45 -    if ( hvm_long_mode_enabled(v) )
    6.46 -    {
    6.47 -        struct {
    6.48 -            unsigned did:16, vid:16;
    6.49 -            unsigned exit_reason:32;
    6.50 -            u64 rip;
    6.51 -        } d;
    6.52 +#define DEFAULT_HVM_VMSWITCH   DEFAULT_HVM_TRACE_ON
    6.53 +#define DEFAULT_HVM_PF         DEFAULT_HVM_TRACE_ON
    6.54 +#define DEFAULT_HVM_INJECT     DEFAULT_HVM_TRACE_ON
    6.55 +#define DEFAULT_HVM_IO         DEFAULT_HVM_TRACE_ON
    6.56 +#define DEFAULT_HVM_REGACCESS  DEFAULT_HVM_TRACE_ON
    6.57 +#define DEFAULT_HVM_MISC       DEFAULT_HVM_TRACE_ON
    6.58 +#define DEFAULT_HVM_INTR       DEFAULT_HVM_TRACE_ON
    6.59  
    6.60 -        d.did = v->domain->domain_id;
    6.61 -        d.vid = v->vcpu_id;
    6.62 -        d.exit_reason = exit_reason;
    6.63 -        d.rip = rip;
    6.64 -        __trace_var(TRC_HVM_VMEXIT64, 1/*cycles*/, sizeof(d),
    6.65 -                    (unsigned char *)&d);
    6.66 -    }
    6.67 -    else
    6.68 -#endif
    6.69 -    {
    6.70 -        struct {
    6.71 -            unsigned did:16, vid:16;
    6.72 -            unsigned exit_reason:32;
    6.73 -            u32 eip;
    6.74 -        } d;
    6.75 -
    6.76 -        d.did = v->domain->domain_id;
    6.77 -        d.vid = v->vcpu_id;
    6.78 -        d.exit_reason = exit_reason;
    6.79 -        d.eip = rip;
    6.80 -        __trace_var(TRC_HVM_VMEXIT, 1/*cycles*/, sizeof(d),
    6.81 -                    (unsigned char *)&d);
    6.82 -    }
    6.83 -}
    6.84 +#define DO_TRC_HVM_VMENTRY     DEFAULT_HVM_VMSWITCH
    6.85 +#define DO_TRC_HVM_VMEXIT      DEFAULT_HVM_VMSWITCH
    6.86 +#define DO_TRC_HVM_VMEXIT64    DEFAULT_HVM_VMSWITCH
    6.87 +#define DO_TRC_HVM_PF_XEN      DEFAULT_HVM_PF
    6.88 +#define DO_TRC_HVM_PF_XEN64    DEFAULT_HVM_PF
    6.89 +#define DO_TRC_HVM_PF_INJECT   DEFAULT_HVM_PF
    6.90 +#define DO_TRC_HVM_PF_INJECT64 DEFAULT_HVM_PF
    6.91 +#define DO_TRC_HVM_INJ_EXC     DEFAULT_HVM_INJECT
    6.92 +#define DO_TRC_HVM_INJ_VIRQ    DEFAULT_HVM_INJECT
    6.93 +#define DO_TRC_HVM_REINJ_VIRQ  DEFAULT_HVM_INJECT
    6.94 +#define DO_TRC_HVM_IO_READ     DEFAULT_HVM_IO
    6.95 +#define DO_TRC_HVM_IO_WRITE    DEFAULT_HVM_IO
    6.96 +#define DO_TRC_HVM_CR_READ     DEFAULT_HVM_REGACCESS
    6.97 +#define DO_TRC_HVM_CR_READ64   DEFAULT_HVM_REGACCESS
    6.98 +#define DO_TRC_HVM_CR_WRITE    DEFAULT_HVM_REGACCESS
    6.99 +#define DO_TRC_HVM_CR_WRITE64  DEFAULT_HVM_REGACCESS
   6.100 +#define DO_TRC_HVM_DR_READ     DEFAULT_HVM_REGACCESS
   6.101 +#define DO_TRC_HVM_DR_WRITE    DEFAULT_HVM_REGACCESS
   6.102 +#define DO_TRC_HVM_MSR_READ    DEFAULT_HVM_REGACCESS
   6.103 +#define DO_TRC_HVM_MSR_WRITE   DEFAULT_HVM_REGACCESS
   6.104 +#define DO_TRC_HVM_CPUID       DEFAULT_HVM_MISC
   6.105 +#define DO_TRC_HVM_INTR        DEFAULT_HVM_INTR
   6.106 +#define DO_TRC_HVM_NMI         DEFAULT_HVM_INTR
   6.107 +#define DO_TRC_HVM_MCE         DEFAULT_HVM_INTR
   6.108 +#define DO_TRC_HVM_SMI         DEFAULT_HVM_INTR
   6.109 +#define DO_TRC_HVM_VMMCALL     DEFAULT_HVM_MISC
   6.110 +#define DO_TRC_HVM_HLT         DEFAULT_HVM_MISC
   6.111 +#define DO_TRC_HVM_INVLPG      DEFAULT_HVM_MISC
   6.112 +#define DO_TRC_HVM_INVLPG64    DEFAULT_HVM_MISC
   6.113 +#define DO_TRC_HVM_IO_ASSIST   DEFAULT_HVM_MISC
   6.114 +#define DO_TRC_HVM_MMIO_ASSIST DEFAULT_HVM_MISC
   6.115 +#define DO_TRC_HVM_CLTS        DEFAULT_HVM_MISC
   6.116 +#define DO_TRC_HVM_LMSW        DEFAULT_HVM_MISC
   6.117 +#define DO_TRC_HVM_LMSW64      DEFAULT_HVM_MISC
   6.118  
   6.119  
   6.120 -static inline void hvmtrace_vmentry(struct vcpu *v)
   6.121 -{
   6.122 -    struct {
   6.123 -        unsigned did:16, vid:16;
   6.124 -    } d;
   6.125 -
   6.126 -    if ( likely(!tb_init_done) )
   6.127 -        return;
   6.128 -
   6.129 -    d.did = v->domain->domain_id;
   6.130 -    d.vid = v->vcpu_id;
   6.131 -    __trace_var(TRC_HVM_VMENTRY, 1/*cycles*/, sizeof(d), (unsigned char *)&d);
   6.132 -}
   6.133 -
   6.134 -static inline void hvmtrace_msr_read(struct vcpu *v, u32 ecx, u64 msr_content)
   6.135 -{
   6.136 -    struct {
   6.137 -        unsigned did:16, vid:16;
   6.138 -        u32 ecx;
   6.139 -        u64 msr_content;
   6.140 -    } d;
   6.141 -
   6.142 -    if ( likely(!tb_init_done) )
   6.143 -        return;
   6.144 -
   6.145 -    d.did = v->domain->domain_id;
   6.146 -    d.vid = v->vcpu_id;
   6.147 -    d.ecx = ecx;
   6.148 -    d.msr_content = msr_content;
   6.149 -    __trace_var(TRC_HVM_MSR_READ, 0/*!cycles*/, sizeof(d),
   6.150 -                (unsigned char *)&d);
   6.151 -}
   6.152 -
   6.153 -static inline void hvmtrace_msr_write(struct vcpu *v, u32 ecx, u64 msr_content)
   6.154 -{
   6.155 -    struct {
   6.156 -        unsigned did:16, vid:16;
   6.157 -        u32 ecx;
   6.158 -        u64 msr_content;
   6.159 -    } d;
   6.160 -
   6.161 -    if ( likely(!tb_init_done) )
   6.162 -        return;
   6.163 +#ifdef __x86_64__
   6.164 +#define TRC_PAR_LONG(par) ((par)&0xFFFFFFFF),((par)>>32)
   6.165 +#else
   6.166 +#define TRC_PAR_LONG(par) (par)
   6.167 +#endif
   6.168  
   6.169 -    d.did = v->domain->domain_id;
   6.170 -    d.vid = v->vcpu_id;
   6.171 -    d.ecx = ecx;
   6.172 -    d.msr_content = msr_content;
   6.173 -    __trace_var(TRC_HVM_MSR_WRITE, 0/*!cycles*/,sizeof(d),
   6.174 -                (unsigned char *)&d);
   6.175 -}
   6.176 -
   6.177 -static inline void hvmtrace_pf_xen(struct vcpu *v, unsigned long va,
   6.178 -                                   u32 error_code)
   6.179 -{
   6.180 -    if ( likely(!tb_init_done) )
   6.181 -        return;
   6.182 -
   6.183 -#ifdef __x86_64__
   6.184 -    if( hvm_long_mode_enabled(v) )
   6.185 -    {
   6.186 -        struct {
   6.187 -            unsigned did:16, vid:16;
   6.188 -            u32 error_code;
   6.189 -            u64 va;
   6.190 -        } d;
   6.191 -        d.did = v->domain->domain_id;
   6.192 -        d.vid = v->vcpu_id;
   6.193 -        d.error_code = error_code;
   6.194 -        d.va = va;
   6.195 -        __trace_var(TRC_HVM_PF_XEN64, 0/*!cycles*/,sizeof(d),
   6.196 -                    (unsigned char *)&d);
   6.197 -    }
   6.198 -    else
   6.199 -#endif
   6.200 -    {
   6.201 -        struct {
   6.202 -            unsigned did:16, vid:16;
   6.203 -            u32 error_code;
   6.204 -            u32 va;
   6.205 -        } d;
   6.206 -        d.did = v->domain->domain_id;
   6.207 -        d.vid = v->vcpu_id;
   6.208 -        d.error_code = error_code;
   6.209 -        d.va = va;
   6.210 -        __trace_var(TRC_HVM_PF_XEN, 0/*!cycles*/,sizeof(d),
   6.211 -                    (unsigned char *)&d);
   6.212 -    }
   6.213 -}
   6.214 -
   6.215 -#define HVMTRACE_ND(evt, vcpu, count, d1, d2, d3, d4)                   \
   6.216 +#define HVMTRACE_ND(evt, cycles, vcpu, count, d1, d2, d3, d4, d5, d6)   \
   6.217      do {                                                                \
   6.218          if ( unlikely(tb_init_done) && DO_TRC_HVM_ ## evt )             \
   6.219          {                                                               \
   6.220              struct {                                                    \
   6.221 -                unsigned did:16, vid:16;                                \
   6.222 -                u32 d[4];                                               \
   6.223 +                u32 did:16, vid:16;                                     \
   6.224 +                u32 d[6];                                               \
   6.225              } _d;                                                       \
   6.226              _d.did=(vcpu)->domain->domain_id;                           \
   6.227              _d.vid=(vcpu)->vcpu_id;                                     \
   6.228 @@ -177,16 +70,45 @@ static inline void hvmtrace_pf_xen(struc
   6.229              _d.d[1]=(d2);                                               \
   6.230              _d.d[2]=(d3);                                               \
   6.231              _d.d[3]=(d4);                                               \
   6.232 -            __trace_var(TRC_HVM_ ## evt, 0/*!cycles*/,                  \
   6.233 +            _d.d[4]=(d5);                                               \
   6.234 +            _d.d[5]=(d6);                                               \
   6.235 +            __trace_var(TRC_HVM_ ## evt, cycles,                        \
   6.236                          sizeof(u32)*count+1, (unsigned char *)&_d);     \
   6.237          }                                                               \
   6.238      } while(0)
   6.239  
   6.240 -#define HVMTRACE_4D(evt, vcpu, d1, d2, d3, d4)   HVMTRACE_ND(evt, vcpu, 4, d1, d2, d3,  d4)
   6.241 -#define HVMTRACE_3D(evt, vcpu, d1, d2, d3)       HVMTRACE_ND(evt, vcpu, 3, d1, d2, d3,  0)
   6.242 -#define HVMTRACE_2D(evt, vcpu, d1, d2)           HVMTRACE_ND(evt, vcpu, 2, d1, d2,  0,  0)
   6.243 -#define HVMTRACE_1D(evt, vcpu, d1)               HVMTRACE_ND(evt, vcpu, 1, d1,  0,  0,  0)
   6.244 -#define HVMTRACE_0D(evt, vcpu)                   HVMTRACE_ND(evt, vcpu, 0, 0,  0,  0,  0)
   6.245 +#define HVMTRACE_6D(evt, vcpu, d1, d2, d3, d4, d5, d6)    \
   6.246 +                      HVMTRACE_ND(evt, 0, vcpu, 6, d1, d2, d3,  d4, d5, d6)
   6.247 +#define HVMTRACE_5D(evt, vcpu, d1, d2, d3, d4, d5)        \
   6.248 +                      HVMTRACE_ND(evt, 0, vcpu, 5, d1, d2, d3,  d4, d5, 0)
   6.249 +#define HVMTRACE_4D(evt, vcpu, d1, d2, d3, d4)               \
   6.250 +                      HVMTRACE_ND(evt, 0, vcpu, 4, d1, d2, d3,  d4, 0, 0)
   6.251 +#define HVMTRACE_3D(evt, vcpu, d1, d2, d3)                   \
   6.252 +                      HVMTRACE_ND(evt, 0, vcpu, 3, d1, d2, d3,  0, 0, 0)
   6.253 +#define HVMTRACE_2D(evt, vcpu, d1, d2)                       \
   6.254 +                      HVMTRACE_ND(evt, 0, vcpu, 2, d1, d2,  0,  0, 0, 0)
   6.255 +#define HVMTRACE_1D(evt, vcpu, d1)                           \
   6.256 +                      HVMTRACE_ND(evt, 0, vcpu, 1, d1,  0,  0,  0, 0, 0)
   6.257 +#define HVMTRACE_0D(evt, vcpu)                               \
   6.258 +                      HVMTRACE_ND(evt, 0, vcpu, 0, 0,  0,  0,  0, 0, 0)
   6.259 +
   6.260 +
   6.261 +
   6.262 +#ifdef __x86_64__
   6.263 +#define HVMTRACE_LONG_1D(evt, vcpu, d1)                  \
   6.264 +                   HVMTRACE_2D(evt ## 64, vcpu, (d1) & 0xFFFFFFFF, (d1) >> 32)
   6.265 +#define HVMTRACE_LONG_2D(evt,vcpu,d1,d2, ...)              \
   6.266 +                   HVMTRACE_3D(evt ## 64, vcpu, d1, d2)
   6.267 +#define HVMTRACE_LONG_3D(evt, vcpu, d1, d2, d3, ...)      \
   6.268 +                   HVMTRACE_4D(evt ## 64, vcpu, d1, d2, d3)
   6.269 +#define HVMTRACE_LONG_4D(evt, vcpu, d1, d2, d3, d4, ...)  \
   6.270 +                   HVMTRACE_5D(evt ## 64, vcpu, d1, d2, d3, d4)
   6.271 +#else
   6.272 +#define HVMTRACE_LONG_1D HVMTRACE_1D
   6.273 +#define HVMTRACE_LONG_2D HVMTRACE_2D
   6.274 +#define HVMTRACE_LONG_3D HVMTRACE_3D
   6.275 +#define HVMTRACE_LONG_4D HVMTRACE_4D
   6.276 +#endif
   6.277  
   6.278  #endif /* __ASM_X86_HVM_TRACE_H__ */
   6.279  
     7.1 --- a/xen/include/public/trace.h	Mon Jun 09 09:44:21 2008 +0100
     7.2 +++ b/xen/include/public/trace.h	Mon Jun 09 09:45:38 2008 +0100
     7.3 @@ -87,21 +87,25 @@
     7.4  #define TRC_PV_PTWR_EMULATION        (TRC_PV + 11)
     7.5  #define TRC_PV_PTWR_EMULATION_PAE    (TRC_PV + 12)
     7.6    /* Indicates that addresses in trace record are 64 bits */
     7.7 -#define TRC_PV_64_FLAG               (0x100) 
     7.8 +#define TRC_64_FLAG               (0x100) 
     7.9  
    7.10  /* trace events per subclass */
    7.11  #define TRC_HVM_VMENTRY         (TRC_HVM_ENTRYEXIT + 0x01)
    7.12  #define TRC_HVM_VMEXIT          (TRC_HVM_ENTRYEXIT + 0x02)
    7.13 -#define TRC_HVM_VMEXIT64        (TRC_HVM_ENTRYEXIT + 0x03)
    7.14 +#define TRC_HVM_VMEXIT64        (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02)
    7.15  #define TRC_HVM_PF_XEN          (TRC_HVM_HANDLER + 0x01)
    7.16 +#define TRC_HVM_PF_XEN64        (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01)
    7.17  #define TRC_HVM_PF_INJECT       (TRC_HVM_HANDLER + 0x02)
    7.18 +#define TRC_HVM_PF_INJECT64     (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02)
    7.19  #define TRC_HVM_INJ_EXC         (TRC_HVM_HANDLER + 0x03)
    7.20  #define TRC_HVM_INJ_VIRQ        (TRC_HVM_HANDLER + 0x04)
    7.21  #define TRC_HVM_REINJ_VIRQ      (TRC_HVM_HANDLER + 0x05)
    7.22  #define TRC_HVM_IO_READ         (TRC_HVM_HANDLER + 0x06)
    7.23  #define TRC_HVM_IO_WRITE        (TRC_HVM_HANDLER + 0x07)
    7.24  #define TRC_HVM_CR_READ         (TRC_HVM_HANDLER + 0x08)
    7.25 +#define TRC_HVM_CR_READ64       (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08)
    7.26  #define TRC_HVM_CR_WRITE        (TRC_HVM_HANDLER + 0x09)
    7.27 +#define TRC_HVM_CR_WRITE64      (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09)
    7.28  #define TRC_HVM_DR_READ         (TRC_HVM_HANDLER + 0x0A)
    7.29  #define TRC_HVM_DR_WRITE        (TRC_HVM_HANDLER + 0x0B)
    7.30  #define TRC_HVM_MSR_READ        (TRC_HVM_HANDLER + 0x0C)
    7.31 @@ -113,12 +117,13 @@
    7.32  #define TRC_HVM_VMMCALL         (TRC_HVM_HANDLER + 0x12)
    7.33  #define TRC_HVM_HLT             (TRC_HVM_HANDLER + 0x13)
    7.34  #define TRC_HVM_INVLPG          (TRC_HVM_HANDLER + 0x14)
    7.35 +#define TRC_HVM_INVLPG64        (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14)
    7.36  #define TRC_HVM_MCE             (TRC_HVM_HANDLER + 0x15)
    7.37  #define TRC_HVM_IO_ASSIST       (TRC_HVM_HANDLER + 0x16)
    7.38  #define TRC_HVM_MMIO_ASSIST     (TRC_HVM_HANDLER + 0x17)
    7.39  #define TRC_HVM_CLTS            (TRC_HVM_HANDLER + 0x18)
    7.40  #define TRC_HVM_LMSW            (TRC_HVM_HANDLER + 0x19)
    7.41 -#define TRC_HVM_PF_XEN64        (TRC_HVM_HANDLER + 0x20)
    7.42 +#define TRC_HVM_LMSW64          (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19)
    7.43  
    7.44  /* This structure represents a single trace buffer record. */
    7.45  struct t_rec {