ia64/xen-unstable

changeset 10139:23fe235cb6d3

[IA64] Import linux header files

Import hw_irq.h and irq.h from linux

Signed-off-by Kevin Tian <kevin.tian@intel.com>
author awilliam@xenbuild.aw
date Tue May 23 08:18:48 2006 -0600 (2006-05-23)
parents 2d08d6db792b
children d8659e39ff3c
files linux-2.6-xen-sparse/include/asm-ia64/hw_irq.h linux-2.6-xen-sparse/include/asm-ia64/irq.h
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/linux-2.6-xen-sparse/include/asm-ia64/hw_irq.h	Tue May 23 08:18:48 2006 -0600
     1.3 @@ -0,0 +1,137 @@
     1.4 +#ifndef _ASM_IA64_HW_IRQ_H
     1.5 +#define _ASM_IA64_HW_IRQ_H
     1.6 +
     1.7 +/*
     1.8 + * Copyright (C) 2001-2003 Hewlett-Packard Co
     1.9 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    1.10 + */
    1.11 +
    1.12 +#include <linux/interrupt.h>
    1.13 +#include <linux/sched.h>
    1.14 +#include <linux/types.h>
    1.15 +#include <linux/profile.h>
    1.16 +
    1.17 +#include <asm/machvec.h>
    1.18 +#include <asm/ptrace.h>
    1.19 +#include <asm/smp.h>
    1.20 +
    1.21 +typedef u8 ia64_vector;
    1.22 +
    1.23 +/*
    1.24 + * 0 special
    1.25 + *
    1.26 + * 1,3-14 are reserved from firmware
    1.27 + *
    1.28 + * 16-255 (vectored external interrupts) are available
    1.29 + *
    1.30 + * 15 spurious interrupt (see IVR)
    1.31 + *
    1.32 + * 16 lowest priority, 255 highest priority
    1.33 + *
    1.34 + * 15 classes of 16 interrupts each.
    1.35 + */
    1.36 +#define IA64_MIN_VECTORED_IRQ		 16
    1.37 +#define IA64_MAX_VECTORED_IRQ		255
    1.38 +#define IA64_NUM_VECTORS		256
    1.39 +
    1.40 +#define AUTO_ASSIGN			-1
    1.41 +
    1.42 +#define IA64_SPURIOUS_INT_VECTOR	0x0f
    1.43 +
    1.44 +/*
    1.45 + * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
    1.46 + */
    1.47 +#define IA64_CPEP_VECTOR		0x1c	/* corrected platform error polling vector */
    1.48 +#define IA64_CMCP_VECTOR		0x1d	/* corrected machine-check polling vector */
    1.49 +#define IA64_CPE_VECTOR			0x1e	/* corrected platform error interrupt vector */
    1.50 +#define IA64_CMC_VECTOR			0x1f	/* corrected machine-check interrupt vector */
    1.51 +/*
    1.52 + * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
    1.53 + */
    1.54 +#define IA64_FIRST_DEVICE_VECTOR	0x30
    1.55 +#define IA64_LAST_DEVICE_VECTOR		0xe7
    1.56 +#define IA64_NUM_DEVICE_VECTORS		(IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
    1.57 +
    1.58 +#define IA64_MCA_RENDEZ_VECTOR		0xe8	/* MCA rendez interrupt */
    1.59 +#define IA64_PERFMON_VECTOR		0xee	/* performanc monitor interrupt vector */
    1.60 +#define IA64_TIMER_VECTOR		0xef	/* use highest-prio group 15 interrupt for timer */
    1.61 +#define	IA64_MCA_WAKEUP_VECTOR		0xf0	/* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
    1.62 +#define IA64_IPI_RESCHEDULE		0xfd	/* SMP reschedule */
    1.63 +#define IA64_IPI_VECTOR			0xfe	/* inter-processor interrupt vector */
    1.64 +
    1.65 +/* Used for encoding redirected irqs */
    1.66 +
    1.67 +#define IA64_IRQ_REDIRECTED		(1 << 31)
    1.68 +
    1.69 +/* IA64 inter-cpu interrupt related definitions */
    1.70 +
    1.71 +#define IA64_IPI_DEFAULT_BASE_ADDR	0xfee00000
    1.72 +
    1.73 +/* Delivery modes for inter-cpu interrupts */
    1.74 +enum {
    1.75 +        IA64_IPI_DM_INT =       0x0,    /* pend an external interrupt */
    1.76 +        IA64_IPI_DM_PMI =       0x2,    /* pend a PMI */
    1.77 +        IA64_IPI_DM_NMI =       0x4,    /* pend an NMI (vector 2) */
    1.78 +        IA64_IPI_DM_INIT =      0x5,    /* pend an INIT interrupt */
    1.79 +        IA64_IPI_DM_EXTINT =    0x7,    /* pend an 8259-compatible interrupt. */
    1.80 +};
    1.81 +
    1.82 +extern __u8 isa_irq_to_vector_map[16];
    1.83 +#define isa_irq_to_vector(x)	isa_irq_to_vector_map[(x)]
    1.84 +
    1.85 +extern struct hw_interrupt_type irq_type_ia64_lsapic;	/* CPU-internal interrupt controller */
    1.86 +
    1.87 +extern int assign_irq_vector (int irq);	/* allocate a free vector */
    1.88 +extern void free_irq_vector (int vector);
    1.89 +extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
    1.90 +extern void register_percpu_irq (ia64_vector vec, struct irqaction *action);
    1.91 +
    1.92 +static inline void
    1.93 +hw_resend_irq (struct hw_interrupt_type *h, unsigned int vector)
    1.94 +{
    1.95 +	platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
    1.96 +}
    1.97 +
    1.98 +/*
    1.99 + * Default implementations for the irq-descriptor API:
   1.100 + */
   1.101 +
   1.102 +extern irq_desc_t irq_desc[NR_IRQS];
   1.103 +
   1.104 +#ifndef CONFIG_IA64_GENERIC
   1.105 +static inline unsigned int
   1.106 +__ia64_local_vector_to_irq (ia64_vector vec)
   1.107 +{
   1.108 +	return (unsigned int) vec;
   1.109 +}
   1.110 +#endif
   1.111 +
   1.112 +/*
   1.113 + * Next follows the irq descriptor interface.  On IA-64, each CPU supports 256 interrupt
   1.114 + * vectors.  On smaller systems, there is a one-to-one correspondence between interrupt
   1.115 + * vectors and the Linux irq numbers.  However, larger systems may have multiple interrupt
   1.116 + * domains meaning that the translation from vector number to irq number depends on the
   1.117 + * interrupt domain that a CPU belongs to.  This API abstracts such platform-dependent
   1.118 + * differences and provides a uniform means to translate between vector and irq numbers
   1.119 + * and to obtain the irq descriptor for a given irq number.
   1.120 + */
   1.121 +
   1.122 +/* Extract the IA-64 vector that corresponds to IRQ.  */
   1.123 +static inline ia64_vector
   1.124 +irq_to_vector (int irq)
   1.125 +{
   1.126 +	return (ia64_vector) irq;
   1.127 +}
   1.128 +
   1.129 +/*
   1.130 + * Convert the local IA-64 vector to the corresponding irq number.  This translation is
   1.131 + * done in the context of the interrupt domain that the currently executing CPU belongs
   1.132 + * to.
   1.133 + */
   1.134 +static inline unsigned int
   1.135 +local_vector_to_irq (ia64_vector vec)
   1.136 +{
   1.137 +	return platform_local_vector_to_irq(vec);
   1.138 +}
   1.139 +
   1.140 +#endif /* _ASM_IA64_HW_IRQ_H */
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/linux-2.6-xen-sparse/include/asm-ia64/irq.h	Tue May 23 08:18:48 2006 -0600
     2.3 @@ -0,0 +1,38 @@
     2.4 +#ifndef _ASM_IA64_IRQ_H
     2.5 +#define _ASM_IA64_IRQ_H
     2.6 +
     2.7 +/*
     2.8 + * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co
     2.9 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    2.10 + *	Stephane Eranian <eranian@hpl.hp.com>
    2.11 + *
    2.12 + * 11/24/98	S.Eranian 	updated TIMER_IRQ and irq_canonicalize
    2.13 + * 01/20/99	S.Eranian	added keyboard interrupt
    2.14 + * 02/29/00     D.Mosberger	moved most things into hw_irq.h
    2.15 + */
    2.16 +
    2.17 +#define NR_IRQS		256
    2.18 +#define NR_IRQ_VECTORS	NR_IRQS
    2.19 +
    2.20 +/*
    2.21 + * IRQ line status macro IRQ_PER_CPU is used
    2.22 + */
    2.23 +#define ARCH_HAS_IRQ_PER_CPU
    2.24 +
    2.25 +static __inline__ int
    2.26 +irq_canonicalize (int irq)
    2.27 +{
    2.28 +	/*
    2.29 +	 * We do the legacy thing here of pretending that irqs < 16
    2.30 +	 * are 8259 irqs.  This really shouldn't be necessary at all,
    2.31 +	 * but we keep it here as serial.c still uses it...
    2.32 +	 */
    2.33 +	return ((irq == 2) ? 9 : irq);
    2.34 +}
    2.35 +
    2.36 +extern void disable_irq (unsigned int);
    2.37 +extern void disable_irq_nosync (unsigned int);
    2.38 +extern void enable_irq (unsigned int);
    2.39 +extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
    2.40 +
    2.41 +#endif /* _ASM_IA64_IRQ_H */