ia64/xen-unstable
changeset 10972:23166260f6ce
[qemu patches] Update patches for changeset 10943:1de1bb6a51c5.
Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author | chris@kneesaa.uk.xensource.com |
---|---|
date | Fri Aug 04 11:34:01 2006 +0100 (2006-08-04) |
parents | 1de1bb6a51c5 |
children | baa6d08e62a0 |
files | tools/ioemu/patches/acpi-timer-support |
line diff
1.1 --- a/tools/ioemu/patches/acpi-timer-support Fri Aug 04 11:33:41 2006 +0100 1.2 +++ b/tools/ioemu/patches/acpi-timer-support Fri Aug 04 11:34:01 2006 +0100 1.3 @@ -1,116 +1,118 @@ 1.4 -diff -r 45c8b171d210 hw/piix4acpi.c 1.5 ---- a/hw/piix4acpi.c Wed Jun 28 20:33:30 2006 +0100 1.6 -+++ b/hw/piix4acpi.c Thu Jun 29 09:34:35 2006 +0100 1.7 -@@ -49,6 +49,13 @@ AcpiDeviceState *acpi_device_table; 1.8 +Index: ioemu/hw/piix4acpi.c 1.9 +=================================================================== 1.10 +--- ioemu.orig/hw/piix4acpi.c 2006-08-04 10:57:28.922994985 +0100 1.11 ++++ ioemu/hw/piix4acpi.c 2006-08-04 11:23:48.127374982 +0100 1.12 +@@ -24,31 +24,30 @@ 1.13 + */ 1.14 + 1.15 + #include "vl.h" 1.16 +-#define FREQUENCE_PMTIMER 3753425 1.17 ++#define FREQUENCE_PMTIMER 3579545 1.18 + /* acpi register bit define here */ 1.19 + 1.20 +-/* PM1_STS */ 1.21 +-#define TMROF_STS (1 << 0) 1.22 +-#define BM_STS (1 << 4) 1.23 +-#define GBL_STS (1 << 5) 1.24 +-#define PWRBTN_STS (1 << 8) 1.25 +-#define RTC_STS (1 << 10) 1.26 ++/* PM1_STS */ 1.27 ++#define TMROF_STS (1 << 0) 1.28 ++#define BM_STS (1 << 4) 1.29 ++#define GBL_STS (1 << 5) 1.30 ++#define PWRBTN_STS (1 << 8) 1.31 ++#define RTC_STS (1 << 10) 1.32 + #define PRBTNOR_STS (1 << 11) 1.33 +-#define WAK_STS (1 << 15) 1.34 +-/* PM1_EN */ 1.35 ++#define WAK_STS (1 << 15) 1.36 ++/* PM1_EN */ 1.37 + #define TMROF_EN (1 << 0) 1.38 + #define GBL_EN (1 << 5) 1.39 + #define PWRBTN_EN (1 << 8) 1.40 +-#define RTC_EN (1 << 10) 1.41 +-/* PM1_CNT */ 1.42 ++#define RTC_EN (1 << 10) 1.43 ++/* PM1_CNT */ 1.44 + #define SCI_EN (1 << 0) 1.45 + #define GBL_RLS (1 << 2) 1.46 +-#define SLP_EN (1 << 13) 1.47 ++#define SLP_EN (1 << 13) 1.48 + 1.49 + typedef struct AcpiDeviceState AcpiDeviceState; 1.50 AcpiDeviceState *acpi_device_table; 1.51 1.52 - /* Bits of PM1a register define here */ 1.53 -+typedef struct PMTState { 1.54 -+ uint32_t count; 1.55 -+ int irq; 1.56 -+ uint64_t next_pm_time; 1.57 -+ QEMUTimer *pm_timer; 1.58 -+}PMTState; 1.59 -+ 1.60 +-/* Bits of PM1a register define here */ 1.61 typedef struct PM1Event_BLK { 1.62 uint16_t pm1_status; /* pm1a_EVT_BLK */ 1.63 uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */ 1.64 -@@ -63,13 +70,80 @@ typedef struct PCIAcpiState { 1.65 +@@ -61,17 +60,11 @@ 1.66 + uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */ 1.67 + uint16_t pm1_control; /* pm1a_ECNT_BLK */ 1.68 uint32_t pm1_timer; /* pmtmr_BLK */ 1.69 ++ uint64_t old_vmck_ticks /* using vm_clock counter */ 1.70 } PCIAcpiState; 1.71 1.72 -+static PMTState *pmtimer_state; 1.73 static PCIAcpiState *acpi_state; 1.74 -+ 1.75 -+static void pmtimer_save(QEMUFile *f, void *opaque) 1.76 -+{ 1.77 -+ PMTState *s = opaque; 1.78 -+ 1.79 -+ qemu_put_be32s(f, &s->count); 1.80 -+ qemu_put_be32s(f, &s->irq); 1.81 -+ qemu_put_be64s(f, &s->next_pm_time); 1.82 -+ qemu_put_timer(f, s->pm_timer); 1.83 -+} 1.84 -+ 1.85 -+static int pmtimer_load(QEMUFile *f, void *opaque, int version_id) 1.86 -+{ 1.87 -+ PMTState *s = opaque; 1.88 -+ 1.89 -+ if (version_id != 1) 1.90 -+ return -EINVAL; 1.91 -+ qemu_get_be32s(f, &s->count); 1.92 -+ qemu_get_be32s(f, &s->irq); 1.93 -+ qemu_get_be64s(f, &s->next_pm_time); 1.94 -+ qemu_get_timer(f, s->pm_timer); 1.95 -+ return 0; 1.96 -+} 1.97 1.98 - static inline void acpi_set_irq(PCIAcpiState *s) 1.99 +-static inline void acpi_set_irq(PCIAcpiState *s) 1.100 +-{ 1.101 +-/* no real SCI event need for now, so comment the following line out */ 1.102 +-/* pic_set_irq(s->irq, 1); */ 1.103 +- printf("acpi_set_irq: s->irq %x \n",s->irq); 1.104 +-} 1.105 +- 1.106 + static void acpi_reset(PCIAcpiState *s) 1.107 { 1.108 - /* no real SCI event need for now, so comment the following line out */ 1.109 - /* pic_set_irq(s->irq, 1); */ 1.110 - printf("acpi_set_irq: s->irq %x \n",s->irq); 1.111 -+} 1.112 -+ 1.113 -+static void pm_timer_update(void *opaque) 1.114 -+{ 1.115 -+ PMTState *s = opaque; 1.116 -+ s->next_pm_time = qemu_get_clock(vm_clock) + 1.117 -+ muldiv64(1, ticks_per_sec,FREQUENCE_PMTIMER); 1.118 -+ qemu_mod_timer(s->pm_timer, s->next_pm_time); 1.119 -+ acpi_state->pm1_timer ++; 1.120 -+ 1.121 -+ /* If pm timer is zero then reset it to zero. */ 1.122 -+ if (acpi_state->pm1_timer >= 0x1000000) { 1.123 -+/* printf("pm_timerupdate: timer overflow: %x \n", acpi_state->pm1_timer); */ 1.124 -+ 1.125 -+ acpi_state->pm1_timer = 0; 1.126 -+ acpi_state->pm1_status = acpi_state->pm1_status | TMROF_STS; 1.127 -+ /* If TMROF_EN is set then send the irq. */ 1.128 -+ if ((acpi_state->pm1_enable & TMROF_EN) == TMROF_EN) { 1.129 -+ acpi_set_irq(acpi_state); 1.130 -+ acpi_state->pm1_enable = 0x00; /* only need one time...*/ 1.131 -+ } 1.132 -+ } 1.133 -+ s->count = acpi_state->pm1_timer; 1.134 -+} 1.135 -+ 1.136 -+static PMTState *pmtimer_init(void) 1.137 -+{ 1.138 -+ PMTState *s; 1.139 -+ 1.140 -+ s = qemu_mallocz(sizeof(PMTState)); 1.141 -+ if (!s) 1.142 -+ return NULL; 1.143 -+ 1.144 -+ /* s->irq = irq; */ 1.145 -+ 1.146 -+ s->pm_timer = qemu_new_timer(vm_clock, pm_timer_update, s); 1.147 -+ 1.148 -+ s->count = 0; 1.149 -+ s->next_pm_time = qemu_get_clock(vm_clock) + muldiv64(1, ticks_per_sec,FREQUENCE_PMTIMER) + 1; 1.150 -+ qemu_mod_timer(s->pm_timer, s->next_pm_time); 1.151 -+ 1.152 -+ register_savevm("pm timer", 1, 1, pmtimer_save, pmtimer_load, s); 1.153 -+ return s; 1.154 + uint8_t *pci_conf; 1.155 +@@ -84,6 +77,7 @@ 1.156 + s->pm1_enable = 0x00; /* TMROF_EN should cleared */ 1.157 + s->pm1_control = SCI_EN; /* SCI_EN */ 1.158 + s->pm1_timer = 0; 1.159 ++ s->old_vmck_ticks = qemu_get_clock(vm_clock); 1.160 } 1.161 1.162 - static void acpi_reset(PCIAcpiState *s) 1.163 -@@ -288,13 +362,15 @@ static void acpiPm1Event_writel(void *op 1.164 + /*byte access */ 1.165 +@@ -95,8 +89,8 @@ 1.166 + s->pm1_status = s->pm1_status&!TMROF_STS; 1.167 + 1.168 + if ((val&GBL_STS)==GBL_STS) 1.169 +- s->pm1_status = s->pm1_status&!GBL_STS; 1.170 +- 1.171 ++ s->pm1_status = s->pm1_status&!GBL_STS; 1.172 ++ 1.173 + /* printf("acpiPm1Status_writeb \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */ 1.174 + } 1.175 + 1.176 +@@ -115,7 +109,7 @@ 1.177 + { 1.178 + PCIAcpiState *s = opaque; 1.179 + 1.180 +- s->pm1_status = (val<<8)||(s->pm1_status); 1.181 ++ s->pm1_status = (val<<8)||(s->pm1_status); 1.182 + /* printf("acpiPm1StatusP1_writeb \n addr %x val:%x\n", addr, val); */ 1.183 + } 1.184 + 1.185 +@@ -220,7 +214,7 @@ 1.186 + s->pm1_status = s->pm1_status&!TMROF_STS; 1.187 + 1.188 + if ((val&GBL_STS)==GBL_STS) 1.189 +- s->pm1_status = s->pm1_status&!GBL_STS; 1.190 ++ s->pm1_status = s->pm1_status&!GBL_STS; 1.191 + 1.192 + /* printf("acpiPm1Status_writew \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */ 1.193 + } 1.194 +@@ -288,13 +282,15 @@ 1.195 1.196 } 1.197 1.198 -static void acpiPm1Event_readl(void *opaque, uint32_t addr) 1.199 --{ 1.200 -- PCIAcpiState *s = opaque; 1.201 -- uint32_t val; 1.202 -- 1.203 ++static uint32_t acpiPm1Event_readl(void *opaque, uint32_t addr) 1.204 + { 1.205 + PCIAcpiState *s = opaque; 1.206 + uint32_t val; 1.207 + 1.208 - val=s->pm1_status|(s->pm1_enable<<16); 1.209 -+static uint32_t acpiPm1Event_readl(void *opaque, uint32_t addr) 1.210 -+{ 1.211 -+ PCIAcpiState *s = opaque; 1.212 -+ uint32_t val; 1.213 -+ 1.214 + val = s->pm1_status|(s->pm1_enable<<16); 1.215 /* printf("acpiPm1Event_readl \n addr %x val:%x\n", addr, val); */ 1.216 + 1.217 @@ -118,11 +120,76 @@ diff -r 45c8b171d210 hw/piix4acpi.c 1.218 } 1.219 1.220 static void acpiPm1Timer_writel(void *opaque, uint32_t addr, uint32_t val) 1.221 -@@ -384,5 +460,7 @@ void pci_piix4_acpi_init(PCIBus *bus) 1.222 +@@ -302,17 +298,21 @@ 1.223 + PCIAcpiState *s = opaque; 1.224 + 1.225 + s->pm1_timer = val; 1.226 +-/* printf("acpiPm1Timer_writel \n addr %x val:%x\n", addr, val); */ 1.227 ++ s->old_vmck_ticks = qemu_get_clock(vm_clock) + 1.228 ++ muldiv64(val, FREQUENCE_PMTIMER, ticks_per_sec); 1.229 + } 1.230 + 1.231 + static uint32_t acpiPm1Timer_readl(void *opaque, uint32_t addr) 1.232 + { 1.233 + PCIAcpiState *s = opaque; 1.234 +- uint32_t val; 1.235 ++ int64_t current_vmck_ticks = qemu_get_clock(vm_clock); 1.236 ++ int64_t vmck_ticks_delta = current_vmck_ticks - s->old_vmck_ticks; 1.237 + 1.238 +- val = s->pm1_timer; 1.239 +-/* printf("acpiPm1Timer_readl \n addr %x val:%x\n", addr, val); */ 1.240 +- return val; 1.241 ++ if (s->old_vmck_ticks) 1.242 ++ s->pm1_timer += muldiv64(vmck_ticks_delta, FREQUENCE_PMTIMER, 1.243 ++ ticks_per_sec); 1.244 ++ s->old_vmck_ticks = current_vmck_ticks; 1.245 ++ return s->pm1_timer; 1.246 + } 1.247 + 1.248 + static void acpi_map(PCIDevice *pci_dev, int region_num, 1.249 +@@ -320,7 +320,7 @@ 1.250 + { 1.251 + PCIAcpiState *d = (PCIAcpiState *)pci_dev; 1.252 + 1.253 +- printf("register acpi io \n"); 1.254 ++ printf("register acpi io\n"); 1.255 + 1.256 + /* Byte access */ 1.257 + register_ioport_write(addr, 1, 1, acpiPm1Status_writeb, d); 1.258 +@@ -336,14 +336,14 @@ 1.259 + register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d); 1.260 + register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d); 1.261 + register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d); 1.262 +- register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d); 1.263 ++ register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d); 1.264 + 1.265 + /* Word access */ 1.266 + register_ioport_write(addr, 2, 2, acpiPm1Status_writew, d); 1.267 + register_ioport_read(addr, 2, 2, acpiPm1Status_readw, d); 1.268 + 1.269 + register_ioport_write(addr + 2, 2, 2, acpiPm1Enable_writew, d); 1.270 +- register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d); 1.271 ++ register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d); 1.272 + 1.273 + register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d); 1.274 + register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d); 1.275 +@@ -351,11 +351,10 @@ 1.276 + /* DWord access */ 1.277 + register_ioport_write(addr, 4, 4, acpiPm1Event_writel, d); 1.278 + register_ioport_read(addr, 4, 4, acpiPm1Event_readl, d); 1.279 +- 1.280 ++ 1.281 + register_ioport_write(addr + 8, 4, 4, acpiPm1Timer_writel, d); 1.282 + register_ioport_read(addr + 8, 4, 4, acpiPm1Timer_readl, d); 1.283 + } 1.284 +- 1.285 + 1.286 + /* PIIX4 acpi pci configuration space, func 3 */ 1.287 + void pci_piix4_acpi_init(PCIBus *bus) 1.288 +@@ -384,5 +383,5 @@ 1.289 pci_register_io_region((PCIDevice *)d, 4, 0x10, 1.290 PCI_ADDRESS_SPACE_IO, acpi_map); 1.291 1.292 -+ pmtimer_state = pmtimer_init(); 1.293 -+ 1.294 - acpi_reset (d); 1.295 +- acpi_reset (d); 1.296 ++ acpi_reset(d); 1.297 }