ia64/xen-unstable

changeset 5374:22e42640bcff

bitkeeper revision 1.1691.1.8 (42a6fb21d3oJwpLmOxa2jKHRJ-8fJg)

First phase of removing IRQ numbers from Xen (transitioning to
IRQ addressing by 'legacy ISA IRQ', 'interrupt vector', and
'I/O APIC address + pin' as appropriate). Overall plan is to move
I/O APIC parsing and setup out of Xen (so we start DOM0 in virtual wire
mode).
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Jun 08 14:05:21 2005 +0000 (2005-06-08)
parents bf014cae2dad
children be46d7ecf186
files xen/arch/ia64/irq.c xen/arch/x86/i8259.c xen/arch/x86/io_apic.c xen/arch/x86/irq.c xen/arch/x86/physdev.c xen/arch/x86/smpboot.c xen/include/asm-x86/hardirq.h xen/include/asm-x86/irq.h xen/include/xen/irq.h
line diff
     1.1 --- a/xen/arch/ia64/irq.c	Wed Jun 08 11:39:13 2005 +0000
     1.2 +++ b/xen/arch/ia64/irq.c	Wed Jun 08 14:05:21 2005 +0000
     1.3 @@ -1471,28 +1471,6 @@ int pirq_guest_unbind(struct domain *d, 
     1.4      return 0;
     1.5  }
     1.6  
     1.7 -int pirq_guest_bindable(int irq, int will_share)
     1.8 -{
     1.9 -    irq_desc_t         *desc = &irq_desc[irq];
    1.10 -    irq_guest_action_t *action;
    1.11 -    unsigned long       flags;
    1.12 -    int                 okay;
    1.13 -
    1.14 -    spin_lock_irqsave(&desc->lock, flags);
    1.15 -
    1.16 -    action = (irq_guest_action_t *)desc->action;
    1.17 -
    1.18 -    /*
    1.19 -     * To be bindable the IRQ must either be not currently bound (1), or
    1.20 -     * it must be shareable (2) and not at its share limit (3).
    1.21 -     */
    1.22 -    okay = ((!(desc->status & IRQ_GUEST) && (action == NULL)) || /* 1 */
    1.23 -            (action->shareable && will_share &&                  /* 2 */
    1.24 -             (action->nr_guests != IRQ_MAX_GUESTS)));            /* 3 */
    1.25 -
    1.26 -    spin_unlock_irqrestore(&desc->lock, flags);
    1.27 -    return okay;
    1.28 -}
    1.29  #endif
    1.30  
    1.31  #ifdef XEN
     2.1 --- a/xen/arch/x86/i8259.c	Wed Jun 08 11:39:13 2005 +0000
     2.2 +++ b/xen/arch/x86/i8259.c	Wed Jun 08 14:05:21 2005 +0000
     2.3 @@ -43,28 +43,10 @@ BUILD_COMMON_IRQ()
     2.4  	BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
     2.5  	BI(x,c) BI(x,d) BI(x,e) BI(x,f)
     2.6  
     2.7 -/*
     2.8 - * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
     2.9 - * (these are usually mapped to vectors 0x20-0x2f)
    2.10 - */
    2.11 -BUILD_16_IRQS(0x0)
    2.12 -
    2.13 -#ifdef CONFIG_X86_IO_APIC
    2.14 -/*
    2.15 - * The IO-APIC gives us many more interrupt sources. Most of these 
    2.16 - * are unused but an SMP system is supposed to have enough memory ...
    2.17 - * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
    2.18 - * across the spectrum, so we really want to be prepared to get all
    2.19 - * of these. Plus, more powerful systems might have more than 64
    2.20 - * IO-APIC registers.
    2.21 - *
    2.22 - * (these are usually mapped into the 0x20-0xff vector range)
    2.23 - */
    2.24 -BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
    2.25 +BUILD_16_IRQS(0x0) BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
    2.26  BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
    2.27  BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
    2.28 -BUILD_16_IRQS(0xc)
    2.29 -#endif
    2.30 +BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
    2.31  
    2.32  #undef BUILD_16_IRQS
    2.33  #undef BI
    2.34 @@ -101,15 +83,11 @@ BUILD_SMP_INTERRUPT(spurious_interrupt,S
    2.35  	IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
    2.36  	IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
    2.37  
    2.38 -    void (*interrupt[NR_IRQS])(void) = {
    2.39 -	IRQLIST_16(0x0),
    2.40 -
    2.41 -#ifdef CONFIG_X86_IO_APIC
    2.42 -        IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
    2.43 +    static void (*interrupt[])(void) = {
    2.44 +	IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
    2.45  	IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
    2.46  	IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
    2.47 -	IRQLIST_16(0xc)
    2.48 -#endif
    2.49 +	IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
    2.50      };
    2.51  
    2.52  #undef IRQ
    2.53 @@ -128,7 +106,7 @@ spinlock_t i8259A_lock = SPIN_LOCK_UNLOC
    2.54  
    2.55  static void end_8259A_irq (unsigned int irq)
    2.56  {
    2.57 -    if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
    2.58 +    if (!(irq_desc[irq_to_vector(irq)].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
    2.59          enable_8259A_irq(irq);
    2.60  }
    2.61  
    2.62 @@ -225,7 +203,7 @@ void make_8259A_irq(unsigned int irq)
    2.63  {
    2.64      disable_irq_nosync(irq);
    2.65      io_apic_irqs &= ~(1<<irq);
    2.66 -    irq_desc[irq].handler = &i8259A_irq_type;
    2.67 +    irq_desc[irq_to_vector(irq)].handler = &i8259A_irq_type;
    2.68      enable_irq(irq);
    2.69  }
    2.70  
    2.71 @@ -384,11 +362,17 @@ void __init init_IRQ(void)
    2.72      for ( i = 0; i < NR_IRQS; i++ )
    2.73      {
    2.74          irq_desc[i].status  = IRQ_DISABLED;
    2.75 -        irq_desc[i].handler = (i<16) ? &i8259A_irq_type : &no_irq_type;
    2.76 +        irq_desc[i].handler = &no_irq_type;
    2.77          irq_desc[i].action  = NULL;
    2.78          irq_desc[i].depth   = 1;
    2.79          spin_lock_init(&irq_desc[i].lock);
    2.80 -        set_intr_gate(FIRST_EXTERNAL_VECTOR+i, interrupt[i]);
    2.81 +        set_intr_gate(i, interrupt[i]);
    2.82 +    }
    2.83 +
    2.84 +    for ( i = 0; i < 16; i++ )
    2.85 +    {
    2.86 +        vector_irq[LEGACY_VECTOR(i)] = i;
    2.87 +        irq_desc[LEGACY_VECTOR(i)].handler = &i8259A_irq_type;
    2.88      }
    2.89  
    2.90      /*
    2.91 @@ -397,7 +381,6 @@ void __init init_IRQ(void)
    2.92       */
    2.93      irq_vector[0] = FIRST_DEVICE_VECTOR;
    2.94      vector_irq[FIRST_DEVICE_VECTOR] = 0;
    2.95 -    set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
    2.96  
    2.97      /* Various IPI functions. */
    2.98      set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
     3.1 --- a/xen/arch/x86/io_apic.c	Wed Jun 08 11:39:13 2005 +0000
     3.2 +++ b/xen/arch/x86/io_apic.c	Wed Jun 08 14:05:21 2005 +0000
     3.3 @@ -65,12 +65,14 @@ static struct irq_pin_list {
     3.4  } irq_2_pin[PIN_MAP_SIZE];
     3.5  
     3.6  int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
     3.7 +#if 0
     3.8  #ifdef CONFIG_PCI_MSI
     3.9  #define vector_to_irq(vector) 	\
    3.10  	(platform_legacy_irq(vector) ? vector : vector_irq[vector])
    3.11  #else
    3.12  #define vector_to_irq(vector)	(vector)
    3.13  #endif
    3.14 +#endif
    3.15  
    3.16  /*
    3.17   * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
    3.18 @@ -657,21 +659,11 @@ static struct hw_interrupt_type ioapic_e
    3.19  
    3.20  static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
    3.21  {
    3.22 -	if (use_pci_vector() && !platform_legacy_irq(irq)) {
    3.23 -		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
    3.24 -				trigger == IOAPIC_LEVEL)
    3.25 -			irq_desc[vector].handler = &ioapic_level_type;
    3.26 -		else
    3.27 -			irq_desc[vector].handler = &ioapic_edge_type;
    3.28 -		set_intr_gate(vector, interrupt[vector]);
    3.29 -	} else	{
    3.30 -		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
    3.31 -				trigger == IOAPIC_LEVEL)
    3.32 -			irq_desc[irq].handler = &ioapic_level_type;
    3.33 -		else
    3.34 -			irq_desc[irq].handler = &ioapic_edge_type;
    3.35 -		set_intr_gate(vector, interrupt[irq]);
    3.36 -	}
    3.37 +	if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
    3.38 +		trigger == IOAPIC_LEVEL)
    3.39 +		irq_desc[vector].handler = &ioapic_level_type;
    3.40 +	else
    3.41 +		irq_desc[vector].handler = &ioapic_edge_type;
    3.42  }
    3.43  
    3.44  void __init setup_IO_APIC_irqs(void)
    3.45 @@ -781,7 +773,7 @@ void __init setup_ExtINT_IRQ0_pin(unsign
    3.46  	 * The timer IRQ doesn't have to know that behind the
    3.47  	 * scene we have a 8259A-master in AEOI mode ...
    3.48  	 */
    3.49 -	irq_desc[0].handler = &ioapic_edge_type;
    3.50 +	irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
    3.51  
    3.52  	/*
    3.53  	 * Add it to the IO-APIC irq-routing table:
    3.54 @@ -1176,7 +1168,7 @@ static unsigned int startup_edge_ioapic_
    3.55   */
    3.56  static void ack_edge_ioapic_irq(unsigned int irq)
    3.57  {
    3.58 -	if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
    3.59 +	if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
    3.60  					== (IRQ_PENDING | IRQ_DISABLED))
    3.61  		mask_IO_APIC_irq(irq);
    3.62  	ack_APIC_irq();
    3.63 @@ -1354,11 +1346,13 @@ static inline void init_IO_APIC_traps(vo
    3.64  	 */
    3.65  	for (irq = 0; irq < NR_IRQS ; irq++) {
    3.66  		int tmp = irq;
    3.67 +#if 0
    3.68  		if (use_pci_vector()) {
    3.69  			if (!platform_legacy_irq(tmp))
    3.70  				if ((tmp = vector_to_irq(tmp)) == -1)
    3.71  					continue;
    3.72  		}
    3.73 +#endif
    3.74  		if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
    3.75  			/*
    3.76  			 * Hmm.. We don't have an entry for this,
    3.77 @@ -1367,9 +1361,6 @@ static inline void init_IO_APIC_traps(vo
    3.78  			 */
    3.79  			if (irq < 16)
    3.80  				make_8259A_irq(irq);
    3.81 -			else
    3.82 -				/* Strange. Oh, well.. */
    3.83 -				irq_desc[irq].handler = &no_irq_type;
    3.84  		}
    3.85  	}
    3.86  }
    3.87 @@ -1485,7 +1476,10 @@ static inline void check_timer(void)
    3.88  	 */
    3.89  	disable_8259A_irq(0);
    3.90  	vector = assign_irq_vector(0);
    3.91 -	set_intr_gate(vector, interrupt[0]);
    3.92 +
    3.93 +        irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
    3.94 +        irq_desc[IO_APIC_VECTOR(0)].depth  = 0;
    3.95 +        irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
    3.96  
    3.97  	/*
    3.98  	 * Subtle, code in do_timer_interrupt() expects an AEOI
    3.99 @@ -1546,7 +1540,7 @@ static inline void check_timer(void)
   3.100  	printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
   3.101  
   3.102  	disable_8259A_irq(0);
   3.103 -	irq_desc[0].handler = &lapic_irq_type;
   3.104 +	irq_desc[vector].handler = &lapic_irq_type;
   3.105  	apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);	/* Fixed mode */
   3.106  	enable_8259A_irq(0);
   3.107  
   3.108 @@ -1834,7 +1828,7 @@ int ioapic_guest_write(int apicid, int a
   3.109              return 0;
   3.110  
   3.111          /* Set the correct irq-handling type. */
   3.112 -        irq_desc[irq].handler = rte.trigger ? 
   3.113 +        irq_desc[IO_APIC_VECTOR(irq)].handler = rte.trigger ? 
   3.114              &ioapic_level_type: &ioapic_edge_type;
   3.115  
   3.116          /* Record the pin<->irq mapping. */
     4.1 --- a/xen/arch/x86/irq.c	Wed Jun 08 11:39:13 2005 +0000
     4.2 +++ b/xen/arch/x86/irq.c	Wed Jun 08 14:05:21 2005 +0000
     4.3 @@ -16,7 +16,7 @@
     4.4  
     4.5  irq_desc_t irq_desc[NR_IRQS];
     4.6  
     4.7 -static void __do_IRQ_guest(int irq);
     4.8 +static void __do_IRQ_guest(int vector);
     4.9  
    4.10  void no_action(int cpl, void *dev_id, struct cpu_user_regs *regs) { }
    4.11  
    4.12 @@ -46,7 +46,8 @@ atomic_t irq_err_count;
    4.13  
    4.14  inline void disable_irq_nosync(unsigned int irq)
    4.15  {
    4.16 -    irq_desc_t   *desc = &irq_desc[irq];
    4.17 +    unsigned int  vector = irq_to_vector(irq);
    4.18 +    irq_desc_t   *desc = &irq_desc[vector];
    4.19      unsigned long flags;
    4.20  
    4.21      spin_lock_irqsave(&desc->lock, flags);
    4.22 @@ -60,15 +61,10 @@ inline void disable_irq_nosync(unsigned 
    4.23      spin_unlock_irqrestore(&desc->lock, flags);
    4.24  }
    4.25  
    4.26 -void disable_irq(unsigned int irq)
    4.27 -{
    4.28 -    disable_irq_nosync(irq);
    4.29 -    do { smp_mb(); } while ( irq_desc[irq].status & IRQ_INPROGRESS );
    4.30 -}
    4.31 -
    4.32  void enable_irq(unsigned int irq)
    4.33  {
    4.34 -    irq_desc_t   *desc = &irq_desc[irq];
    4.35 +    unsigned int  vector = irq_to_vector(irq);
    4.36 +    irq_desc_t   *desc = &irq_desc[vector];
    4.37      unsigned long flags;
    4.38  
    4.39      spin_lock_irqsave(&desc->lock, flags);
    4.40 @@ -77,10 +73,7 @@ void enable_irq(unsigned int irq)
    4.41      {
    4.42          desc->status &= ~IRQ_DISABLED;
    4.43          if ( (desc->status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING )
    4.44 -        {
    4.45              desc->status |= IRQ_REPLAY;
    4.46 -            hw_resend_irq(desc->handler,irq);
    4.47 -        }
    4.48          desc->handler->enable(irq);
    4.49      }
    4.50  
    4.51 @@ -88,9 +81,10 @@ void enable_irq(unsigned int irq)
    4.52  }
    4.53  
    4.54  asmlinkage void do_IRQ(struct cpu_user_regs *regs)
    4.55 -{       
    4.56 -    unsigned int      irq = regs->entry_vector;
    4.57 -    irq_desc_t       *desc = &irq_desc[irq];
    4.58 +{
    4.59 +    unsigned int      vector = regs->entry_vector;
    4.60 +    unsigned int      irq = vector_to_irq(vector);
    4.61 +    irq_desc_t       *desc = &irq_desc[vector];
    4.62      struct irqaction *action;
    4.63  
    4.64      perfc_incrc(irqs);
    4.65 @@ -100,7 +94,7 @@ asmlinkage void do_IRQ(struct cpu_user_r
    4.66  
    4.67      if ( likely(desc->status & IRQ_GUEST) )
    4.68      {
    4.69 -        __do_IRQ_guest(irq);
    4.70 +        __do_IRQ_guest(vector);
    4.71          spin_unlock(&desc->lock);
    4.72          return;
    4.73      }
    4.74 @@ -121,11 +115,11 @@ asmlinkage void do_IRQ(struct cpu_user_r
    4.75      while ( desc->status & IRQ_PENDING )
    4.76      {
    4.77          desc->status &= ~IRQ_PENDING;
    4.78 -        irq_enter(smp_processor_id(), irq);
    4.79 +        irq_enter(smp_processor_id());
    4.80          spin_unlock_irq(&desc->lock);
    4.81          action->handler(irq, action->dev_id, regs);
    4.82          spin_lock_irq(&desc->lock);
    4.83 -        irq_exit(smp_processor_id(), irq);
    4.84 +        irq_exit(smp_processor_id());
    4.85      }
    4.86  
    4.87      desc->status &= ~IRQ_INPROGRESS;
    4.88 @@ -137,7 +131,8 @@ asmlinkage void do_IRQ(struct cpu_user_r
    4.89  
    4.90  void free_irq(unsigned int irq)
    4.91  {
    4.92 -    irq_desc_t   *desc = &irq_desc[irq];
    4.93 +    unsigned int  vector = irq_to_vector(irq);
    4.94 +    irq_desc_t   *desc = &irq_desc[vector];
    4.95      unsigned long flags;
    4.96  
    4.97      spin_lock_irqsave(&desc->lock,flags);
    4.98 @@ -148,12 +143,13 @@ void free_irq(unsigned int irq)
    4.99      spin_unlock_irqrestore(&desc->lock,flags);
   4.100  
   4.101      /* Wait to make sure it's not being used on another CPU */
   4.102 -    do { smp_mb(); } while ( irq_desc[irq].status & IRQ_INPROGRESS );
   4.103 +    do { smp_mb(); } while ( desc->status & IRQ_INPROGRESS );
   4.104  }
   4.105  
   4.106  int setup_irq(unsigned int irq, struct irqaction *new)
   4.107  {
   4.108 -    irq_desc_t   *desc = &irq_desc[irq];
   4.109 +    unsigned int  vector = irq_to_vector(irq);
   4.110 +    irq_desc_t   *desc = &irq_desc[vector];
   4.111      unsigned long flags;
   4.112   
   4.113      spin_lock_irqsave(&desc->lock,flags);
   4.114 @@ -187,9 +183,10 @@ typedef struct {
   4.115      struct domain *guest[IRQ_MAX_GUESTS];
   4.116  } irq_guest_action_t;
   4.117  
   4.118 -static void __do_IRQ_guest(int irq)
   4.119 +static void __do_IRQ_guest(int vector)
   4.120  {
   4.121 -    irq_desc_t         *desc = &irq_desc[irq];
   4.122 +    unsigned int        irq = vector_to_irq(vector);
   4.123 +    irq_desc_t         *desc = &irq_desc[vector];
   4.124      irq_guest_action_t *action = (irq_guest_action_t *)desc->action;
   4.125      struct domain      *d;
   4.126      int                 i;
   4.127 @@ -218,7 +215,7 @@ int pirq_guest_unmask(struct domain *d)
   4.128              j = find_first_set_bit(m);
   4.129              m &= ~(1 << j);
   4.130              pirq = (i << 5) + j;
   4.131 -            desc = &irq_desc[pirq];
   4.132 +            desc = &irq_desc[irq_to_vector(pirq)];
   4.133              spin_lock_irq(&desc->lock);
   4.134              if ( !test_bit(d->pirq_to_evtchn[pirq], &s->evtchn_mask[0]) &&
   4.135                   test_and_clear_bit(pirq, &d->pirq_mask) &&
   4.136 @@ -233,8 +230,9 @@ int pirq_guest_unmask(struct domain *d)
   4.137  
   4.138  int pirq_guest_bind(struct vcpu *v, int irq, int will_share)
   4.139  {
   4.140 +    unsigned int        vector = irq_to_vector(irq);
   4.141      struct domain      *d = v->domain;
   4.142 -    irq_desc_t         *desc = &irq_desc[irq];
   4.143 +    irq_desc_t         *desc = &irq_desc[vector];
   4.144      irq_guest_action_t *action;
   4.145      unsigned long       flags;
   4.146      int                 rc = 0;
   4.147 @@ -243,6 +241,9 @@ int pirq_guest_bind(struct vcpu *v, int 
   4.148      if ( !IS_CAPABLE_PHYSDEV(d) )
   4.149          return -EPERM;
   4.150  
   4.151 +    if ( vector == 0 )
   4.152 +        return -EBUSY;
   4.153 +
   4.154      spin_lock_irqsave(&desc->lock, flags);
   4.155  
   4.156      action = (irq_guest_action_t *)desc->action;
   4.157 @@ -303,11 +304,14 @@ int pirq_guest_bind(struct vcpu *v, int 
   4.158  
   4.159  int pirq_guest_unbind(struct domain *d, int irq)
   4.160  {
   4.161 -    irq_desc_t         *desc = &irq_desc[irq];
   4.162 +    unsigned int        vector = irq_to_vector(irq);
   4.163 +    irq_desc_t         *desc = &irq_desc[vector];
   4.164      irq_guest_action_t *action;
   4.165      unsigned long       flags;
   4.166      int                 i;
   4.167  
   4.168 +    BUG_ON(vector == 0);
   4.169 +
   4.170      spin_lock_irqsave(&desc->lock, flags);
   4.171  
   4.172      action = (irq_guest_action_t *)desc->action;
   4.173 @@ -337,26 +341,3 @@ int pirq_guest_unbind(struct domain *d, 
   4.174      spin_unlock_irqrestore(&desc->lock, flags);    
   4.175      return 0;
   4.176  }
   4.177 -
   4.178 -int pirq_guest_bindable(int irq, int will_share)
   4.179 -{
   4.180 -    irq_desc_t         *desc = &irq_desc[irq];
   4.181 -    irq_guest_action_t *action;
   4.182 -    unsigned long       flags;
   4.183 -    int                 okay;
   4.184 -
   4.185 -    spin_lock_irqsave(&desc->lock, flags);
   4.186 -
   4.187 -    action = (irq_guest_action_t *)desc->action;
   4.188 -
   4.189 -    /*
   4.190 -     * To be bindable the IRQ must either be not currently bound (1), or
   4.191 -     * it must be shareable (2) and not at its share limit (3).
   4.192 -     */
   4.193 -    okay = ((!(desc->status & IRQ_GUEST) && (action == NULL)) || /* 1 */
   4.194 -            (action->shareable && will_share &&                  /* 2 */
   4.195 -             (action->nr_guests != IRQ_MAX_GUESTS)));            /* 3 */
   4.196 -
   4.197 -    spin_unlock_irqrestore(&desc->lock, flags);
   4.198 -    return okay;
   4.199 -}
     5.1 --- a/xen/arch/x86/physdev.c	Wed Jun 08 11:39:13 2005 +0000
     5.2 +++ b/xen/arch/x86/physdev.c	Wed Jun 08 14:05:21 2005 +0000
     5.3 @@ -60,7 +60,7 @@ long do_physdev_op(physdev_op_t *uop)
     5.4              break;
     5.5          op.u.irq_status_query.flags = 0;
     5.6          /* Edge-triggered interrupts don't need an explicit unmask downcall. */
     5.7 -        if ( strstr(irq_desc[irq].handler->typename, "edge") == NULL )
     5.8 +        if ( strstr(irq_desc[irq_to_vector(irq)].handler->typename, "edge") == NULL )
     5.9              op.u.irq_status_query.flags |= PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY;
    5.10          ret = 0;
    5.11          break;
    5.12 @@ -89,7 +89,6 @@ long do_physdev_op(physdev_op_t *uop)
    5.13              return -EINVAL;
    5.14          
    5.15          op.u.irq_op.vector = assign_irq_vector(irq);
    5.16 -        set_intr_gate(op.u.irq_op.vector, interrupt[irq]);
    5.17          ret = 0;
    5.18          break;
    5.19  
     6.1 --- a/xen/arch/x86/smpboot.c	Wed Jun 08 11:39:13 2005 +0000
     6.2 +++ b/xen/arch/x86/smpboot.c	Wed Jun 08 14:05:21 2005 +0000
     6.3 @@ -1178,12 +1178,6 @@ void __init smp_cpus_done(unsigned int m
     6.4  void __init smp_intr_init(void)
     6.5  {
     6.6  	/*
     6.7 -	 * IRQ0 must be given a fixed assignment and initialized,
     6.8 -	 * because it's used before the IO-APIC is set up.
     6.9 -	 */
    6.10 -	set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
    6.11 -
    6.12 -	/*
    6.13  	 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
    6.14  	 * IPI, driven by wakeup.
    6.15  	 */
     7.1 --- a/xen/include/asm-x86/hardirq.h	Wed Jun 08 11:39:13 2005 +0000
     7.2 +++ b/xen/include/asm-x86/hardirq.h	Wed Jun 08 14:05:21 2005 +0000
     7.3 @@ -15,7 +15,7 @@ typedef struct {
     7.4  
     7.5  #define in_irq() (local_irq_count(smp_processor_id()) != 0)
     7.6  
     7.7 -#define irq_enter(cpu, irq)	(local_irq_count(cpu)++)
     7.8 -#define irq_exit(cpu, irq)	(local_irq_count(cpu)--)
     7.9 +#define irq_enter(cpu)	(local_irq_count(cpu)++)
    7.10 +#define irq_exit(cpu)	(local_irq_count(cpu)--)
    7.11  
    7.12  #endif /* __ASM_HARDIRQ_H */
     8.1 --- a/xen/include/asm-x86/irq.h	Wed Jun 08 11:39:13 2005 +0000
     8.2 +++ b/xen/include/asm-x86/irq.h	Wed Jun 08 14:05:21 2005 +0000
     8.3 @@ -8,17 +8,20 @@
     8.4  #include <asm/asm_defns.h>
     8.5  #include <irq_vectors.h>
     8.6  
     8.7 -extern void disable_irq(unsigned int);
     8.8 +#define IO_APIC_IRQ(irq)    (((irq) >= 16) || ((1<<(irq)) & io_apic_irqs))
     8.9 +#define IO_APIC_VECTOR(irq) (irq_vector[irq])
    8.10 +#define LEGACY_VECTOR(irq)  ((irq) + FIRST_EXTERNAL_VECTOR)
    8.11 +#define irq_to_vector(irq)  \
    8.12 +    (IO_APIC_IRQ(irq) ? IO_APIC_VECTOR(irq) : LEGACY_VECTOR(irq))
    8.13 +#define vector_to_irq(vec)  (vector_irq[vec])
    8.14 +
    8.15  extern void disable_irq_nosync(unsigned int);
    8.16  extern void enable_irq(unsigned int);
    8.17  
    8.18  extern int vector_irq[NR_VECTORS];
    8.19  extern u8 irq_vector[NR_IRQ_VECTORS];
    8.20 -#define IO_APIC_VECTOR(irq)     irq_vector[irq]
    8.21  #define AUTO_ASSIGN             -1
    8.22  
    8.23 -extern void (*interrupt[NR_IRQS])(void);
    8.24 -
    8.25  #define platform_legacy_irq(irq)	((irq) < 16)
    8.26  
    8.27  void disable_8259A_irq(unsigned int irq);
    8.28 @@ -40,12 +43,4 @@ extern unsigned long io_apic_irqs;
    8.29  extern atomic_t irq_err_count;
    8.30  extern atomic_t irq_mis_count;
    8.31  
    8.32 -#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs))
    8.33 -
    8.34 -static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
    8.35 -{
    8.36 -    if (IO_APIC_IRQ(i))
    8.37 -        send_IPI_self(IO_APIC_VECTOR(i));
    8.38 -}
    8.39 -
    8.40  #endif /* _ASM_HW_IRQ_H */
     9.1 --- a/xen/include/xen/irq.h	Wed Jun 08 11:39:13 2005 +0000
     9.2 +++ b/xen/include/xen/irq.h	Wed Jun 08 14:05:21 2005 +0000
     9.3 @@ -71,6 +71,5 @@ struct vcpu;
     9.4  extern int pirq_guest_unmask(struct domain *p);
     9.5  extern int pirq_guest_bind(struct vcpu *p, int irq, int will_share);
     9.6  extern int pirq_guest_unbind(struct domain *p, int irq);
     9.7 -extern int pirq_guest_bindable(int irq, int will_share);
     9.8  
     9.9  #endif /* __XEN_IRQ_H__ */