ia64/xen-unstable

changeset 4786:214e5c4b003d

bitkeeper revision 1.1389.9.2 (427bdfb3_b3KQR-vZHyKEmWLaNwEJQ)

First implementation of hyperprivops (no fast assembly yet)
Signed-off by: Dan Magenheimer <dan.magenheimer@hp.com>
author djm@kirby.fc.hp.com
date Fri May 06 21:20:51 2005 +0000 (2005-05-06)
parents 674bf85fff9a
children e24efdd35ac2
files xen/arch/ia64/asm-offsets.c xen/arch/ia64/ivt.S xen/arch/ia64/privop.c xen/arch/ia64/process.c xen/arch/ia64/vcpu.c
line diff
     1.1 --- a/xen/arch/ia64/asm-offsets.c	Fri May 06 17:02:01 2005 +0000
     1.2 +++ b/xen/arch/ia64/asm-offsets.c	Fri May 06 21:20:51 2005 +0000
     1.3 @@ -8,6 +8,7 @@
     1.4  #include <xen/sched.h>
     1.5  #include <asm/processor.h>
     1.6  #include <asm/ptrace.h>
     1.7 +#include <public/xen.h>
     1.8  
     1.9  #define task_struct exec_domain
    1.10  
    1.11 @@ -37,6 +38,9 @@ void foo(void)
    1.12  
    1.13  	BLANK();
    1.14  
    1.15 +	DEFINE(XSI_PSR_IC_OFS, offsetof(vcpu_info_t, arch.interrupt_collection_enabled));
    1.16 +	DEFINE(XSI_PSR_IC, (SHAREDINFO_ADDR+offsetof(vcpu_info_t, arch.interrupt_collection_enabled)));
    1.17 +	DEFINE(XSI_PSR_I_OFS, offsetof(vcpu_info_t, arch.interrupt_delivery_enabled));
    1.18  	//DEFINE(IA64_TASK_BLOCKED_OFFSET,offsetof (struct task_struct, blocked));
    1.19  	//DEFINE(IA64_TASK_CLEAR_CHILD_TID_OFFSET,offsetof (struct task_struct, clear_child_tid));
    1.20  	//DEFINE(IA64_TASK_GROUP_LEADER_OFFSET, offsetof (struct task_struct, group_leader));
     2.1 --- a/xen/arch/ia64/ivt.S	Fri May 06 17:02:01 2005 +0000
     2.2 +++ b/xen/arch/ia64/ivt.S	Fri May 06 21:20:51 2005 +0000
     2.3 @@ -778,10 +778,22 @@ ENTRY(break_fault)
     2.4  	mov r17=cr.iim
     2.5  	mov r31=pr
     2.6  	;;
     2.7 +	movl r18=XSI_PSR_IC
     2.8 +	;;
     2.9 +	ld8 r19=[r18]
    2.10 +	;;
    2.11  	cmp.eq p7,p0=r0,r17			// is this a psuedo-cover?
    2.12 -	// FIXME: may also need to check slot==2?
    2.13  (p7)	br.sptk.many dispatch_privop_fault
    2.14 +	;;
    2.15 +	cmp.ne p7,p0=r0,r19
    2.16 +(p7)	br.sptk.many dispatch_break_fault
    2.17 +	// If we get to here, we have a hyperprivop
    2.18 +	// For now, hyperprivops are handled through the break mechanism
    2.19 +	// Later, they will be fast hand-coded assembly with psr.ic off
    2.20 +	// which means no calls, no use of r1-r15 and no memory accesses
    2.21 +	// except to pinned addresses!
    2.22  	br.sptk.many dispatch_break_fault
    2.23 +	;;
    2.24  #endif
    2.25  	mov r16=IA64_KR(CURRENT)		// r16 = current task; 12 cycle read lat.
    2.26  	mov r17=cr.iim
     3.1 --- a/xen/arch/ia64/privop.c	Fri May 06 17:02:01 2005 +0000
     3.2 +++ b/xen/arch/ia64/privop.c	Fri May 06 21:20:51 2005 +0000
     3.3 @@ -758,6 +758,38 @@ priv_emulate(VCPU *vcpu, REGS *regs, UIN
     3.4  }
     3.5  
     3.6  
     3.7 +// FIXME: Move these to include/public/arch-ia64?
     3.8 +#define HYPERPRIVOP_RFI			1
     3.9 +#define HYPERPRIVOP_RSM_DT		2
    3.10 +#define HYPERPRIVOP_SSM_DT		3
    3.11 +#define HYPERPRIVOP_COVER		4
    3.12 +
    3.13 +/* hyperprivops are generally executed in assembly (with physical psr.ic off)
    3.14 + * so this code is primarily used for debugging them */
    3.15 +int
    3.16 +ia64_hyperprivop(unsigned long iim)
    3.17 +{
    3.18 +	struct exec_domain *ed = (struct domain *) current;
    3.19 +
    3.20 +// FIXME: Add instrumentation for these
    3.21 +	switch(iim) {
    3.22 +	    case HYPERPRIVOP_RFI:
    3.23 +		(void)vcpu_rfi(ed);
    3.24 +		return 0;	// don't update iip
    3.25 +	    case HYPERPRIVOP_RSM_DT:
    3.26 +		(void)vcpu_reset_psr_dt(ed);
    3.27 +		return 1;
    3.28 +	    case HYPERPRIVOP_SSM_DT:
    3.29 +		(void)vcpu_set_psr_dt(ed);
    3.30 +		return 1;
    3.31 +	    case HYPERPRIVOP_COVER:
    3.32 +		(void)vcpu_cover(ed);
    3.33 +		return 1;
    3.34 +	}
    3.35 +	return 0;
    3.36 +}
    3.37 +
    3.38 +
    3.39  /**************************************************************************
    3.40  Privileged operation instrumentation routines
    3.41  **************************************************************************/
     4.1 --- a/xen/arch/ia64/process.c	Fri May 06 17:02:01 2005 +0000
     4.2 +++ b/xen/arch/ia64/process.c	Fri May 06 21:20:51 2005 +0000
     4.3 @@ -722,6 +722,10 @@ ia64_handle_break (unsigned long ifa, st
     4.4  		if (ia64_hypercall(regs))
     4.5  			vcpu_increment_iip(current);
     4.6  	}
     4.7 +	else if (!PSCB(ed,interrupt_collection_enabled)) {
     4.8 +		if (ia64_hyperprivop(iim))
     4.9 +			vcpu_increment_iip(current);
    4.10 +	}
    4.11  	else reflect_interruption(ifa,isr,iim,regs,IA64_BREAK_VECTOR);
    4.12  }
    4.13  
     5.1 --- a/xen/arch/ia64/vcpu.c	Fri May 06 17:02:01 2005 +0000
     5.2 +++ b/xen/arch/ia64/vcpu.c	Fri May 06 21:20:51 2005 +0000
     5.3 @@ -120,6 +120,12 @@ void vcpu_set_metaphysical_mode(VCPU *vc
     5.4  	}
     5.5  }
     5.6  
     5.7 +IA64FAULT vcpu_reset_psr_dt(VCPU *vcpu)
     5.8 +{
     5.9 +	vcpu_set_metaphysical_mode(vcpu,TRUE);
    5.10 +	return IA64_NO_FAULT;
    5.11 +}
    5.12 +
    5.13  IA64FAULT vcpu_reset_psr_sm(VCPU *vcpu, UINT64 imm24)
    5.14  {
    5.15  	struct ia64_psr psr, imm, *ipsr;
    5.16 @@ -154,6 +160,12 @@ IA64FAULT vcpu_reset_psr_sm(VCPU *vcpu, 
    5.17  extern UINT64 vcpu_check_pending_interrupts(VCPU *vcpu);
    5.18  #define SPURIOUS_VECTOR 0xf
    5.19  
    5.20 +IA64FAULT vcpu_set_psr_dt(VCPU *vcpu)
    5.21 +{
    5.22 +	vcpu_set_metaphysical_mode(vcpu,FALSE);
    5.23 +	return IA64_NO_FAULT;
    5.24 +}
    5.25 +
    5.26  IA64FAULT vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm24)
    5.27  {
    5.28  	struct ia64_psr psr, imm, *ipsr;