ia64/xen-unstable

changeset 16631:213a7029fdbc

[IA64] xenoprof: don't modify mPSR.pp. PV case

Don't change mPSR.pp for xenoprof for PV domain case.
xenoprof manages mPSR.pp so that mPSR.pp shouldn't be modified.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Mon Dec 17 09:51:06 2007 -0700 (2007-12-17)
parents 57eec263d48b
children 2900e4dacaa7
files xen/arch/ia64/xen/hyperprivop.S xen/arch/ia64/xen/vcpu.c
line diff
     1.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Mon Dec 17 09:45:53 2007 -0700
     1.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Mon Dec 17 09:51:06 2007 -0700
     1.3 @@ -1099,14 +1099,21 @@ just_do_rfi:
     1.4  	// force on psr.ic, i, dt, rt, it, bn
     1.5  	movl r20=(IA64_PSR_I|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT| \
     1.6  	          IA64_PSR_IT|IA64_PSR_BN)
     1.7 +	// keep cr.ipsr.pp and set vPSR.pp = vIPSR.pp
     1.8 +	mov r22=cr.ipsr
     1.9  	;;
    1.10  	or r21=r21,r20
    1.11 +	tbit.z p10,p11 = r22, IA64_PSR_PP_BIT
    1.12  	;;
    1.13  	adds r20=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
    1.14  	tbit.z p8,p9 = r21, IA64_PSR_DFH_BIT
    1.15 +	adds r23=XSI_VPSR_PP_OFS-XSI_PSR_IC_OFS,r18
    1.16  	;;
    1.17  	(p9) mov r27=1;;
    1.18  	(p9) st1 [r20]=r27
    1.19 +	dep r21=r22,r21,IA64_PSR_PP_BIT,1
    1.20 +	(p10) st1 [r23]=r0
    1.21 +	(p11) st1 [r23]=r27
    1.22  	;;
    1.23  	(p8) st1 [r20]=r0
    1.24  	(p8) adds r20=XSI_HPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
    1.25 @@ -1484,20 +1491,20 @@ ENTRY(hyper_get_psr)
    1.26  	movl r8=0xffffffff | IA64_PSR_MC | IA64_PSR_IT;;
    1.27  	// only return PSR{36:35,31:0}
    1.28  	and r8=r8,r24
    1.29 -	// set vpsr.ic
    1.30 +	// get vpsr.ic
    1.31  	ld4 r21=[r18];;
    1.32  	dep r8=r21,r8,IA64_PSR_IC_BIT,1
    1.33 -	// set vpsr.pp
    1.34 +	// get vpsr.pp
    1.35  	adds r20=XSI_VPSR_PP_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.36  	ld1 r21=[r20];;
    1.37  	dep r8=r21,r8,IA64_PSR_PP_BIT,1
    1.38 -	// set vpsr.dt
    1.39 +	// get vpsr.dt
    1.40  	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.41  	ld4 r21=[r20];;
    1.42  	cmp.ne p6,p0=r21,r0
    1.43  	;;
    1.44  (p6)	dep.z r8=r8,IA64_PSR_DT_BIT,1
    1.45 -	// set vpsr.i
    1.46 +	// get vpsr.i
    1.47  	adds r20=XSI_PSR_I_ADDR_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.48  	ld8 r20=[r20];;
    1.49  	ld1 r21=[r20];;
    1.50 @@ -1505,7 +1512,7 @@ ENTRY(hyper_get_psr)
    1.51  	;;
    1.52  (p8)	dep r8=-1,r8,IA64_PSR_I_BIT,1
    1.53  (p9)	dep r8=0,r8,IA64_PSR_I_BIT,1
    1.54 -	// set vpsr.dfh
    1.55 +	// get vpsr.dfh
    1.56  	adds r20=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
    1.57  	ld1 r21=[r20];;
    1.58  	dep r8=r21,r8,IA64_PSR_DFH_BIT,1
     2.1 --- a/xen/arch/ia64/xen/vcpu.c	Mon Dec 17 09:45:53 2007 -0700
     2.2 +++ b/xen/arch/ia64/xen/vcpu.c	Mon Dec 17 09:51:06 2007 -0700
     2.3 @@ -329,8 +329,11 @@ IA64FAULT vcpu_reset_psr_sm(VCPU * vcpu,
     2.4  	if (imm.dfl)
     2.5  		ipsr->dfl = 0;
     2.6  	if (imm.pp) {
     2.7 -		ipsr->pp = 1;
     2.8 -		psr.pp = 1;	// priv perf ctrs always enabled
     2.9 +		// xenoprof:
    2.10 +		// Don't change psr.pp and ipsr->pp 
    2.11 +		// They are manipulated by xenoprof
    2.12 +		// psr.pp = 1;
    2.13 +		// ipsr->pp = 1;
    2.14  		PSCB(vcpu, vpsr_pp) = 0; // but fool the domain if it gets psr
    2.15  	}
    2.16  	if (imm.up) {
    2.17 @@ -391,8 +394,11 @@ IA64FAULT vcpu_set_psr_sm(VCPU * vcpu, u
    2.18  	if (imm.dfl)
    2.19  		ipsr->dfl = 1;
    2.20  	if (imm.pp) {
    2.21 -		ipsr->pp = 1;
    2.22 -		psr.pp = 1;
    2.23 +		// xenoprof:
    2.24 +		// Don't change psr.pp and ipsr->pp 
    2.25 +		// They are manipulated by xenoprof
    2.26 +		// psr.pp = 1;
    2.27 +		// ipsr->pp = 1;
    2.28  		PSCB(vcpu, vpsr_pp) = 1;
    2.29  	}
    2.30  	if (imm.sp) {
    2.31 @@ -462,10 +468,16 @@ IA64FAULT vcpu_set_psr_l(VCPU * vcpu, u6
    2.32  	if (newpsr.dfl)
    2.33  		ipsr->dfl = 1;
    2.34  	if (newpsr.pp) {
    2.35 -		ipsr->pp = 1;
    2.36 +		// xenoprof:
    2.37 +		// Don't change ipsr->pp 
    2.38 +		// It is manipulated by xenoprof
    2.39 +		// ipsr->pp = 1;
    2.40  		PSCB(vcpu, vpsr_pp) = 1;
    2.41  	} else {
    2.42 -		ipsr->pp = 1;
    2.43 +		// xenoprof:
    2.44 +		// Don't change ipsr->pp 
    2.45 +		// It is manipulated by xenoprof
    2.46 +		// ipsr->pp = 1;
    2.47  		PSCB(vcpu, vpsr_pp) = 0;
    2.48  	}
    2.49  	if (newpsr.up)
    2.50 @@ -517,7 +529,15 @@ IA64FAULT vcpu_set_psr(VCPU * vcpu, u64 
    2.51  	newpsr.val |= IA64_PSR_DI;
    2.52  
    2.53  	newpsr.val |= IA64_PSR_I  | IA64_PSR_IC | IA64_PSR_DT | IA64_PSR_RT |
    2.54 -		      IA64_PSR_IT | IA64_PSR_BN | IA64_PSR_DI | IA64_PSR_PP;
    2.55 +		      IA64_PSR_IT | IA64_PSR_BN | IA64_PSR_DI;
    2.56 +	/*
    2.57 +	 * xenoprof:
    2.58 +	 * keep psr.pp unchanged for xenoprof.
    2.59 +	 */
    2.60 +	if (regs->cr_ipsr & IA64_PSR_PP)
    2.61 +		newpsr.val |= IA64_PSR_PP;
    2.62 +	else
    2.63 +		newpsr.val &= ~IA64_PSR_PP;
    2.64  
    2.65  	vpsr.val = val;
    2.66